diff --git a/config/kernel/linux-mvebu-edge.config b/config/kernel/linux-mvebu-edge.config index 07c98f29e4..426399e5d7 100644 --- a/config/kernel/linux-mvebu-edge.config +++ b/config/kernel/linux-mvebu-edge.config @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm 5.17.15 Kernel Configuration +# Linux/arm 6.1.3 Kernel Configuration # CONFIG_CC_VERSION_TEXT="arm-linux-gnueabihf-gcc (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36)) 8.3.0" CONFIG_CC_IS_GCC=y @@ -13,9 +13,9 @@ CONFIG_LD_VERSION=23200 CONFIG_LLD_VERSION=0 CONFIG_CC_CAN_LINK=y CONFIG_CC_CAN_LINK_STATIC=y -CONFIG_CC_HAS_ASM_GOTO=y CONFIG_CC_HAS_ASM_INLINE=y CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y +CONFIG_PAHOLE_VERSION=122 CONFIG_IRQ_WORK=y CONFIG_BUILDTIME_TABLE_SORT=y CONFIG_THREAD_INFO_IN_TASK=y @@ -41,7 +41,6 @@ CONFIG_KERNEL_GZIP=y # CONFIG_KERNEL_LZ4 is not set CONFIG_DEFAULT_INIT="" CONFIG_DEFAULT_HOSTNAME="(none)" -CONFIG_SWAP=y CONFIG_SYSVIPC=y CONFIG_SYSVIPC_SYSCTL=y CONFIG_POSIX_MQUEUE=y @@ -78,6 +77,8 @@ CONFIG_GENERIC_IRQ_MULTI_HANDLER=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_ARCH_HAS_TICK_BROADCAST=y CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_CONTEXT_TRACKING=y +CONFIG_CONTEXT_TRACKING_IDLE=y # # Timers subsystem @@ -133,8 +134,9 @@ CONFIG_RCU_EXPERT=y CONFIG_SRCU=y CONFIG_TREE_SRCU=y CONFIG_TASKS_RCU_GENERIC=y -CONFIG_TASKS_RCU=y -CONFIG_TASKS_RUDE_RCU=y +# CONFIG_FORCE_TASKS_RCU is not set +# CONFIG_FORCE_TASKS_RUDE_RCU is not set +# CONFIG_FORCE_TASKS_TRACE_RCU is not set CONFIG_TASKS_TRACE_RCU=y CONFIG_RCU_STALL_COMMON=y CONFIG_RCU_NEED_SEGCBLIST=y @@ -161,10 +163,11 @@ CONFIG_GENERIC_SCHED_CLOCK=y # end of Scheduler features CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" +CONFIG_GCC12_NO_ARRAY_BOUNDS=y CONFIG_CGROUPS=y CONFIG_PAGE_COUNTER=y +# CONFIG_CGROUP_FAVOR_DYNMODS is not set CONFIG_MEMCG=y -CONFIG_MEMCG_SWAP=y CONFIG_MEMCG_KMEM=y CONFIG_BLK_CGROUP=y CONFIG_CGROUP_WRITEBACK=y @@ -204,6 +207,7 @@ CONFIG_RD_LZO=y CONFIG_RD_LZ4=y CONFIG_RD_ZSTD=y # CONFIG_BOOT_CONFIG is not set +CONFIG_INITRAMFS_PRESERVE_MTIME=y CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_LD_ORPHAN_WARN=y @@ -233,7 +237,6 @@ CONFIG_MEMBARRIER=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_ALL is not set CONFIG_KALLSYMS_BASE_RELATIVE=y -# CONFIG_USERFAULTFD is not set CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y CONFIG_RSEQ=y # CONFIG_EMBEDDED is not set @@ -247,22 +250,12 @@ CONFIG_PERF_EVENTS=y # CONFIG_DEBUG_PERF_USE_VMALLOC is not set # end of Kernel Performance Events And Counters -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_SLUB_DEBUG=y -# CONFIG_COMPAT_BRK is not set -# CONFIG_SLAB is not set -CONFIG_SLUB=y -CONFIG_SLAB_MERGE_DEFAULT=y -CONFIG_SLAB_FREELIST_RANDOM=y -CONFIG_SLAB_FREELIST_HARDENED=y -# CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set -CONFIG_SLUB_CPU_PARTIAL=y CONFIG_SYSTEM_DATA_VERIFICATION=y # CONFIG_PROFILING is not set # end of General setup CONFIG_ARM=y -CONFIG_ARM_HAS_SG_CHAIN=y +CONFIG_ARM_HAS_GROUP_RELOCS=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y CONFIG_HAVE_PROC_CPU=y CONFIG_STACKTRACE_SUPPORT=y @@ -282,19 +275,9 @@ CONFIG_MMU=y CONFIG_ARCH_MMAP_RND_BITS_MIN=8 CONFIG_ARCH_MMAP_RND_BITS_MAX=16 CONFIG_ARCH_MULTIPLATFORM=y -# CONFIG_ARCH_EP93XX is not set -# CONFIG_ARCH_FOOTBRIDGE is not set -# CONFIG_ARCH_IOP32X is not set -# CONFIG_ARCH_IXP4XX is not set -# CONFIG_ARCH_DOVE is not set -# CONFIG_ARCH_PXA is not set -# CONFIG_ARCH_RPC is not set -# CONFIG_ARCH_SA1100 is not set -# CONFIG_ARCH_S3C24XX is not set -# CONFIG_ARCH_OMAP1 is not set # -# Multiple platform selection +# Platform selection # # @@ -303,9 +286,10 @@ CONFIG_ARCH_MULTIPLATFORM=y # CONFIG_ARCH_MULTI_V6 is not set CONFIG_ARCH_MULTI_V7=y CONFIG_ARCH_MULTI_V6_V7=y -# end of Multiple platform selection +# end of Platform selection # CONFIG_ARCH_VIRT is not set +# CONFIG_ARCH_AIROHA is not set # CONFIG_ARCH_ACTIONS is not set # CONFIG_ARCH_ALPINE is not set # CONFIG_ARCH_ARTPEC is not set @@ -314,9 +298,11 @@ CONFIG_ARCH_MULTI_V6_V7=y # CONFIG_ARCH_BCM is not set # CONFIG_ARCH_BERLIN is not set # CONFIG_ARCH_DIGICOLOR is not set +# CONFIG_ARCH_DOVE is not set # CONFIG_ARCH_EXYNOS is not set # CONFIG_ARCH_HIGHBANK is not set # CONFIG_ARCH_HISI is not set +# CONFIG_ARCH_HPE is not set # CONFIG_ARCH_MXC is not set # CONFIG_ARCH_KEYSTONE is not set # CONFIG_ARCH_MEDIATEK is not set @@ -349,7 +335,6 @@ CONFIG_MACH_DOVE=y # CONFIG_ARCH_QCOM is not set # CONFIG_ARCH_RDA is not set # CONFIG_ARCH_REALTEK is not set -# CONFIG_ARCH_REALVIEW is not set # CONFIG_ARCH_ROCKCHIP is not set # CONFIG_ARCH_S5PV210 is not set # CONFIG_ARCH_RENESAS is not set @@ -357,10 +342,12 @@ CONFIG_MACH_DOVE=y # CONFIG_PLAT_SPEAR is not set # CONFIG_ARCH_STI is not set # CONFIG_ARCH_STM32 is not set +# CONFIG_ARCH_SUNPLUS is not set # CONFIG_ARCH_SUNXI is not set # CONFIG_ARCH_TEGRA is not set # CONFIG_ARCH_UNIPHIER is not set # CONFIG_ARCH_U8500 is not set +# CONFIG_ARCH_REALVIEW is not set # CONFIG_ARCH_VEXPRESS is not set # CONFIG_ARCH_WM8850 is not set # CONFIG_ARCH_ZYNQ is not set @@ -393,6 +380,7 @@ CONFIG_ARM_THUMB=y CONFIG_ARM_THUMBEE=y CONFIG_ARM_VIRT_EXT=y CONFIG_SWP_EMULATE=y +CONFIG_CPU_LITTLE_ENDIAN=y # CONFIG_CPU_BIG_ENDIAN is not set # CONFIG_CPU_ICACHE_DISABLE is not set # CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND is not set @@ -418,7 +406,6 @@ CONFIG_ARM_L1_CACHE_SHIFT_6=y CONFIG_ARM_L1_CACHE_SHIFT=6 CONFIG_ARM_DMA_MEM_BUFFERABLE=y CONFIG_ARM_HEAVY_MB=y -CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y CONFIG_DEBUG_ALIGN_RODATA=y CONFIG_IWMMXT=y CONFIG_PJ4B_ERRATA_4742=y @@ -428,6 +415,7 @@ CONFIG_ARM_ERRATA_720789=y # CONFIG_ARM_ERRATA_754322 is not set # CONFIG_ARM_ERRATA_754327 is not set # CONFIG_ARM_ERRATA_764369 is not set +CONFIG_ARM_ERRATA_764319=y # CONFIG_ARM_ERRATA_775420 is not set # CONFIG_ARM_ERRATA_798181 is not set # CONFIG_ARM_ERRATA_773022 is not set @@ -453,6 +441,7 @@ CONFIG_HAVE_SMP=y CONFIG_SMP=y CONFIG_SMP_ON_UP=y CONFIG_CURRENT_POINTER_IN_TPIDRURO=y +CONFIG_IRQSTACKS=y CONFIG_ARM_CPU_TOPOLOGY=y CONFIG_SCHED_MC=y # CONFIG_SCHED_SMT is not set @@ -489,9 +478,8 @@ CONFIG_HIGHMEM=y CONFIG_HIGHPTE=y CONFIG_CPU_SW_DOMAIN_PAN=y CONFIG_HW_PERF_EVENTS=y -CONFIG_ARCH_WANT_GENERAL_HUGETLB=y CONFIG_ARM_MODULE_PLTS=y -CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_ARCH_FORCE_MAX_ORDER=11 CONFIG_ALIGNMENT_TRAP=y # CONFIG_UACCESS_WITH_MEMCPY is not set # CONFIG_PARAVIRT is not set @@ -505,6 +493,7 @@ CONFIG_ALIGNMENT_TRAP=y # CONFIG_USE_OF=y CONFIG_ATAGS=y +# CONFIG_UNUSED_BOARD_FILES is not set # CONFIG_DEPRECATED_PARAM_STRUCT is not set CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 @@ -591,6 +580,7 @@ CONFIG_SUSPEND_FREEZER=y CONFIG_PM_SLEEP=y CONFIG_PM_SLEEP_SMP=y # CONFIG_PM_AUTOSLEEP is not set +# CONFIG_PM_USERSPACE_AUTOSLEEP is not set # CONFIG_PM_WAKELOCKS is not set CONFIG_PM=y # CONFIG_PM_DEBUG is not set @@ -607,25 +597,6 @@ CONFIG_ARM_CPU_SUSPEND=y CONFIG_ARCH_HIBERNATION_POSSIBLE=y # end of Power management options -CONFIG_ARM_CRYPTO=y -CONFIG_CRYPTO_SHA1_ARM=m -CONFIG_CRYPTO_SHA1_ARM_NEON=m -CONFIG_CRYPTO_SHA1_ARM_CE=m -CONFIG_CRYPTO_SHA2_ARM_CE=m -CONFIG_CRYPTO_SHA256_ARM=m -CONFIG_CRYPTO_SHA512_ARM=m -CONFIG_CRYPTO_BLAKE2S_ARM=m -CONFIG_CRYPTO_BLAKE2B_NEON=m -CONFIG_CRYPTO_AES_ARM=m -CONFIG_CRYPTO_AES_ARM_BS=m -CONFIG_CRYPTO_AES_ARM_CE=m -CONFIG_CRYPTO_GHASH_ARM_CE=m -CONFIG_CRYPTO_CRCT10DIF_ARM_CE=m -CONFIG_CRYPTO_CRC32_ARM_CE=m -CONFIG_CRYPTO_CHACHA20_NEON=m -CONFIG_CRYPTO_POLY1305_ARM=m -CONFIG_CRYPTO_NHPOLY1305_NEON=m -CONFIG_CRYPTO_CURVE25519_NEON=m CONFIG_AS_VFP_VMRS_FPINST=y # @@ -667,11 +638,14 @@ CONFIG_HAVE_STACKPROTECTOR=y CONFIG_STACKPROTECTOR=y CONFIG_STACKPROTECTOR_STRONG=y CONFIG_LTO_NONE=y -CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_CONTEXT_TRACKING_USER=y CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y CONFIG_HAVE_MOD_ARCH_SPECIFIC=y CONFIG_MODULES_USE_ELF_REL=y +CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y +CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK=y +CONFIG_SOFTIRQ_ON_OWN_STACK=y CONFIG_ARCH_HAS_ELF_RANDOMIZE=y CONFIG_HAVE_ARCH_MMAP_RND_BITS=y CONFIG_HAVE_EXIT_THREAD=y @@ -683,13 +657,14 @@ CONFIG_CLONE_BACKWARDS=y CONFIG_OLD_SIGSUSPEND3=y CONFIG_OLD_SIGACTION=y CONFIG_COMPAT_32BIT_TIME=y +CONFIG_HAVE_ARCH_VMAP_STACK=y +CONFIG_VMAP_STACK=y CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y CONFIG_STRICT_KERNEL_RWX=y CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y CONFIG_STRICT_MODULE_RWX=y -CONFIG_ARCH_HAS_PHYS_TO_DMA=y # CONFIG_LOCK_EVENT_COUNTS is not set CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y CONFIG_HAVE_ARCH_PFN_VALID=y @@ -704,7 +679,6 @@ CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y CONFIG_HAVE_GCC_PLUGINS=y CONFIG_GCC_PLUGINS=y # CONFIG_GCC_PLUGIN_LATENT_ENTROPY is not set -# CONFIG_GCC_PLUGIN_RANDSTRUCT is not set # end of General architecture-dependent options CONFIG_RT_MUTEXES=y @@ -714,6 +688,7 @@ CONFIG_MODULES=y # CONFIG_MODULE_FORCE_LOAD is not set CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_FORCE_UNLOAD=y +# CONFIG_MODULE_UNLOAD_TAINT_TRACKING is not set # CONFIG_MODVERSIONS is not set # CONFIG_MODULE_SRCVERSION_ALL is not set CONFIG_MODULE_SIG=y @@ -734,6 +709,7 @@ CONFIG_MODULE_COMPRESS_XZ=y CONFIG_MODPROBE_PATH="/sbin/modprobe" CONFIG_MODULES_TREE_LOOKUP=y CONFIG_BLOCK=y +CONFIG_BLOCK_LEGACY_AUTOLOAD=y CONFIG_BLK_CGROUP_RWSTAT=y CONFIG_BLK_DEV_BSG_COMMON=y CONFIG_BLK_ICQ=y @@ -764,6 +740,7 @@ CONFIG_BLK_MQ_PCI=y CONFIG_BLK_MQ_VIRTIO=y CONFIG_BLK_PM=y CONFIG_BLOCK_HOLDER_DEPRECATED=y +CONFIG_BLK_MQ_STACKING=y # # IO Schedulers @@ -802,7 +779,6 @@ CONFIG_BINFMT_FLAT=y CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y # CONFIG_BINFMT_FLAT_OLD is not set CONFIG_BINFMT_ZFLAT=y -CONFIG_BINFMT_SHARED_FLAT=y CONFIG_BINFMT_MISC=m CONFIG_COREDUMP=y # end of Executable file formats @@ -810,29 +786,10 @@ CONFIG_COREDUMP=y # # Memory Management options # -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_FLATMEM_MANUAL=y -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_MEMORY_ISOLATION=y -CONFIG_SPLIT_PTLOCK_CPUS=4 -CONFIG_MEMORY_BALLOON=y -CONFIG_BALLOON_COMPACTION=y -CONFIG_COMPACTION=y -CONFIG_PAGE_REPORTING=y -CONFIG_MIGRATION=y -CONFIG_CONTIG_ALLOC=y -CONFIG_BOUNCE=y -CONFIG_KSM=y -CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 -CONFIG_FRONTSWAP=y -CONFIG_CMA=y -# CONFIG_CMA_DEBUG is not set -# CONFIG_CMA_DEBUGFS is not set -# CONFIG_CMA_SYSFS is not set -CONFIG_CMA_AREAS=7 +CONFIG_ZPOOL=y +CONFIG_SWAP=y CONFIG_ZSWAP=y +CONFIG_ZSWAP_DEFAULT_ON=y # CONFIG_ZSWAP_COMPRESSOR_DEFAULT_DEFLATE is not set # CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZO is not set # CONFIG_ZSWAP_COMPRESSOR_DEFAULT_842 is not set @@ -844,20 +801,61 @@ CONFIG_ZSWAP_COMPRESSOR_DEFAULT="zstd" CONFIG_ZSWAP_ZPOOL_DEFAULT_Z3FOLD=y # CONFIG_ZSWAP_ZPOOL_DEFAULT_ZSMALLOC is not set CONFIG_ZSWAP_ZPOOL_DEFAULT="z3fold" -CONFIG_ZSWAP_DEFAULT_ON=y -CONFIG_ZPOOL=y CONFIG_ZBUD=y CONFIG_Z3FOLD=y CONFIG_ZSMALLOC=m # CONFIG_ZSMALLOC_STAT is not set + +# +# SLAB allocator options +# +# CONFIG_SLAB is not set +CONFIG_SLUB=y +CONFIG_SLAB_MERGE_DEFAULT=y +CONFIG_SLAB_FREELIST_RANDOM=y +CONFIG_SLAB_FREELIST_HARDENED=y +# CONFIG_SLUB_STATS is not set +CONFIG_SLUB_CPU_PARTIAL=y +# end of SLAB allocator options + +# CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set +# CONFIG_COMPAT_BRK is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_MEMORY_ISOLATION=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_MEMORY_BALLOON=y +CONFIG_BALLOON_COMPACTION=y +CONFIG_COMPACTION=y +CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 +CONFIG_PAGE_REPORTING=y +CONFIG_MIGRATION=y +CONFIG_CONTIG_ALLOC=y +CONFIG_BOUNCE=y +CONFIG_KSM=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +CONFIG_FRONTSWAP=y +CONFIG_CMA=y +# CONFIG_CMA_DEBUG is not set +# CONFIG_CMA_DEBUGFS is not set +# CONFIG_CMA_SYSFS is not set +CONFIG_CMA_AREAS=7 CONFIG_GENERIC_EARLY_IOREMAP=y CONFIG_PAGE_IDLE_FLAG=y CONFIG_IDLE_PAGE_TRACKING=y +CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y +CONFIG_VM_EVENT_COUNTERS=y # CONFIG_PERCPU_STATS is not set # CONFIG_GUP_TEST is not set CONFIG_KMAP_LOCAL=y CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y # CONFIG_ANON_VMA_NAME is not set +# CONFIG_USERFAULTFD is not set +# CONFIG_LRU_GEN is not set # # Data Access Monitoring @@ -931,6 +929,7 @@ CONFIG_INET_ESP=m CONFIG_INET_ESP_OFFLOAD=m # CONFIG_INET_ESPINTCP is not set CONFIG_INET_IPCOMP=m +CONFIG_INET_TABLE_PERTURB_ORDER=16 CONFIG_INET_XFRM_TUNNEL=m CONFIG_INET_TUNNEL=m CONFIG_INET_DIAG=m @@ -1085,6 +1084,7 @@ CONFIG_NFT_FIB_NETDEV=m CONFIG_NFT_REJECT_NETDEV=m CONFIG_NF_FLOW_TABLE_INET=m CONFIG_NF_FLOW_TABLE=m +# CONFIG_NF_FLOW_TABLE_PROCFS is not set CONFIG_NETFILTER_XTABLES=m # @@ -1418,6 +1418,7 @@ CONFIG_NET_DSA_TAG_OCELOT_8021Q=m CONFIG_NET_DSA_TAG_QCA=m CONFIG_NET_DSA_TAG_RTL4_A=m CONFIG_NET_DSA_TAG_RTL8_4=m +CONFIG_NET_DSA_TAG_RZN1_A5PSW=m CONFIG_NET_DSA_TAG_LAN9303=m CONFIG_NET_DSA_TAG_SJA1105=m CONFIG_NET_DSA_TAG_TRAILER=m @@ -1425,7 +1426,6 @@ CONFIG_NET_DSA_TAG_XRS700X=m CONFIG_VLAN_8021Q=m CONFIG_VLAN_8021Q_GVRP=y CONFIG_VLAN_8021Q_MVRP=y -# CONFIG_DECNET is not set CONFIG_LLC=m # CONFIG_LLC2 is not set CONFIG_ATALK=m @@ -1638,68 +1638,6 @@ CONFIG_CAN_BCM=m CONFIG_CAN_GW=m CONFIG_CAN_J1939=m CONFIG_CAN_ISOTP=m - -# -# CAN Device Drivers -# -CONFIG_CAN_VCAN=m -CONFIG_CAN_VXCAN=m -CONFIG_CAN_SLCAN=m -CONFIG_CAN_DEV=m -CONFIG_CAN_CALC_BITTIMING=y -CONFIG_CAN_FLEXCAN=m -CONFIG_CAN_GRCAN=m -CONFIG_CAN_KVASER_PCIEFD=m -CONFIG_CAN_TI_HECC=m -CONFIG_CAN_C_CAN=m -CONFIG_CAN_C_CAN_PLATFORM=m -CONFIG_CAN_C_CAN_PCI=m -CONFIG_CAN_CC770=m -CONFIG_CAN_CC770_ISA=m -CONFIG_CAN_CC770_PLATFORM=m -# CONFIG_CAN_IFI_CANFD is not set -CONFIG_CAN_M_CAN=m -CONFIG_CAN_M_CAN_PCI=m -CONFIG_CAN_M_CAN_PLATFORM=m -CONFIG_CAN_M_CAN_TCAN4X5X=m -CONFIG_CAN_PEAK_PCIEFD=m -CONFIG_CAN_SJA1000=m -CONFIG_CAN_EMS_PCI=m -CONFIG_CAN_F81601=m -CONFIG_CAN_KVASER_PCI=m -CONFIG_CAN_PEAK_PCI=m -CONFIG_CAN_PEAK_PCIEC=y -CONFIG_CAN_PLX_PCI=m -CONFIG_CAN_SJA1000_ISA=m -CONFIG_CAN_SJA1000_PLATFORM=m -CONFIG_CAN_SOFTING=m - -# -# CAN SPI interfaces -# -CONFIG_CAN_HI311X=m -CONFIG_CAN_MCP251X=m -CONFIG_CAN_MCP251XFD=m -# CONFIG_CAN_MCP251XFD_SANITY is not set -# end of CAN SPI interfaces - -# -# CAN USB interfaces -# -CONFIG_CAN_8DEV_USB=m -CONFIG_CAN_EMS_USB=m -CONFIG_CAN_ESD_USB2=m -CONFIG_CAN_ETAS_ES58X=m -CONFIG_CAN_GS_USB=m -CONFIG_CAN_KVASER_USB=m -CONFIG_CAN_MCBA_USB=m -CONFIG_CAN_PEAK_USB=m -CONFIG_CAN_UCAN=m -# end of CAN USB interfaces - -# CONFIG_CAN_DEBUG_DEVICES is not set -# end of CAN Device Drivers - CONFIG_BT=m CONFIG_BT_BREDR=y CONFIG_BT_RFCOMM=m @@ -1863,6 +1801,7 @@ CONFIG_NET_SELFTESTS=y CONFIG_NET_SOCK_MSG=y CONFIG_NET_DEVLINK=y CONFIG_PAGE_POOL=y +CONFIG_PAGE_POOL_STATS=y CONFIG_FAILOVER=m CONFIG_ETHTOOL_NETLINK=y @@ -1886,10 +1825,13 @@ CONFIG_PCI_MSI_IRQ_DOMAIN=y CONFIG_PCI_QUIRKS=y CONFIG_PCI_DEBUG=y # CONFIG_PCI_STUB is not set +CONFIG_PCI_DOE=y CONFIG_PCI_BRIDGE_EMUL=y # CONFIG_PCI_IOV is not set # CONFIG_PCI_PRI is not set # CONFIG_PCI_PASID is not set +CONFIG_VGA_ARB=y +CONFIG_VGA_ARB_MAX_GPUS=16 # CONFIG_HOTPLUG_PCI is not set # @@ -1938,8 +1880,11 @@ CONFIG_PCI_MVEBU=y # end of PCI switch controller drivers CONFIG_CXL_BUS=m -CONFIG_CXL_MEM=m +CONFIG_CXL_PCI=m # CONFIG_CXL_MEM_RAW_COMMANDS is not set +CONFIG_CXL_MEM=m +CONFIG_CXL_PORT=m +CONFIG_CXL_SUSPEND=y # CONFIG_PCCARD is not set CONFIG_RAPIDIO=m CONFIG_RAPIDIO_DISC_TIMEOUT=30 @@ -1961,6 +1906,7 @@ CONFIG_RAPIDIO_DISC_TIMEOUT=30 # # Generic Driver Options # +CONFIG_AUXILIARY_BUS=y CONFIG_UEVENT_HELPER=y CONFIG_UEVENT_HELPER_PATH="" CONFIG_DEVTMPFS=y @@ -1974,11 +1920,13 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y # CONFIG_FW_LOADER=y CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_FW_LOADER_SYSFS=y CONFIG_EXTRA_FIRMWARE="" CONFIG_FW_LOADER_USER_HELPER=y CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y # CONFIG_FW_LOADER_COMPRESS is not set CONFIG_FW_CACHE=y +# CONFIG_FW_UPLOAD is not set # end of Firmware loader CONFIG_WANT_DEV_COREDUMP=y @@ -2014,6 +1962,7 @@ CONFIG_MVEBU_MBUS=y CONFIG_MHI_BUS=m # CONFIG_MHI_BUS_DEBUG is not set CONFIG_MHI_BUS_PCI_GENERIC=m +CONFIG_MHI_BUS_EP=m # end of Bus devices # CONFIG_CONNECTOR is not set @@ -2026,14 +1975,18 @@ CONFIG_MHI_BUS_PCI_GENERIC=m # ARM System Control and Management Interface Protocol # CONFIG_ARM_SCMI_PROTOCOL=m +CONFIG_ARM_SCMI_HAVE_TRANSPORT=y +CONFIG_ARM_SCMI_HAVE_SHMEM=y +CONFIG_ARM_SCMI_HAVE_MSG=y +CONFIG_ARM_SCMI_TRANSPORT_OPTEE=y # CONFIG_ARM_SCMI_TRANSPORT_VIRTIO is not set CONFIG_ARM_SCMI_POWER_DOMAIN=m +CONFIG_ARM_SCMI_POWER_CONTROL=m # end of ARM System Control and Management Interface Protocol # CONFIG_FW_CFG_SYSFS is not set # CONFIG_TRUSTED_FOUNDATIONS is not set # CONFIG_GOOGLE_FIRMWARE is not set -# CONFIG_EFI_DISABLE_RUNTIME is not set CONFIG_HAVE_ARM_SMCCC=y # @@ -2142,6 +2095,10 @@ CONFIG_MTD_NAND_CAFE=m CONFIG_MTD_NAND_ORION=m CONFIG_MTD_NAND_MARVELL=m CONFIG_MTD_NAND_BRCMNAND=m +CONFIG_MTD_NAND_BRCMNAND_BCM63XX=m +CONFIG_MTD_NAND_BRCMNAND_BCMBCA=m +CONFIG_MTD_NAND_BRCMNAND_BRCMSTB=m +CONFIG_MTD_NAND_BRCMNAND_IPROC=m # CONFIG_MTD_NAND_MXIC is not set CONFIG_MTD_NAND_GPIO=m CONFIG_MTD_NAND_PLATFORM=m @@ -2168,6 +2125,7 @@ CONFIG_MTD_NAND_ECC=y CONFIG_MTD_NAND_ECC_SW_HAMMING=y # CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC is not set # CONFIG_MTD_NAND_ECC_SW_BCH is not set +# CONFIG_MTD_NAND_ECC_MXIC is not set # end of ECC engine support # end of NAND @@ -2220,7 +2178,6 @@ CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 # CONFIG_BLK_DEV_DRBD is not set # CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_SX8 is not set CONFIG_BLK_DEV_RAM=m CONFIG_BLK_DEV_RAM_COUNT=8 CONFIG_BLK_DEV_RAM_SIZE=4096 @@ -2228,6 +2185,7 @@ CONFIG_BLK_DEV_RAM_SIZE=4096 CONFIG_ATA_OVER_ETH=m CONFIG_VIRTIO_BLK=m CONFIG_BLK_DEV_RBD=m +CONFIG_BLK_DEV_UBLK=m # # NVME Support @@ -2235,10 +2193,12 @@ CONFIG_BLK_DEV_RBD=m CONFIG_NVME_CORE=y CONFIG_BLK_DEV_NVME=y # CONFIG_NVME_MULTIPATH is not set +# CONFIG_NVME_VERBOSE_ERRORS is not set # CONFIG_NVME_HWMON is not set CONFIG_NVME_FABRICS=m # CONFIG_NVME_FC is not set CONFIG_NVME_TCP=m +# CONFIG_NVME_AUTH is not set # CONFIG_NVME_TARGET is not set # end of NVME Support @@ -2268,6 +2228,8 @@ CONFIG_DW_XDATA_PCIE=m # CONFIG_XILINX_SDFEC is not set CONFIG_MISC_RTSX=m CONFIG_HISI_HIKEY_USB=m +CONFIG_OPEN_DICE=m +CONFIG_VCPU_STALL_DETECTOR=m # CONFIG_C2PORT is not set # @@ -2303,6 +2265,7 @@ CONFIG_MISC_RTSX_USB=m CONFIG_HABANA_AI=m CONFIG_UACCE=m # CONFIG_PVPANIC is not set +CONFIG_GP_PCI1XXXX=m # end of Misc devices # @@ -2334,7 +2297,7 @@ CONFIG_BLK_DEV_BSG=y # CONFIG_SCSI_SPI_ATTRS is not set # CONFIG_SCSI_FC_ATTRS is not set CONFIG_SCSI_ISCSI_ATTRS=m -# CONFIG_SCSI_SAS_ATTRS is not set +CONFIG_SCSI_SAS_ATTRS=m # CONFIG_SCSI_SAS_LIBSAS is not set # CONFIG_SCSI_SRP_ATTRS is not set # end of SCSI Transports @@ -2367,8 +2330,9 @@ CONFIG_ISCSI_BOOT_SYSFS=m # CONFIG_SCSI_MPT2SAS is not set CONFIG_SCSI_MPI3MR=m # CONFIG_SCSI_SMARTPQI is not set -# CONFIG_SCSI_UFSHCD is not set # CONFIG_SCSI_HPTIOP is not set +CONFIG_SCSI_BUSLOGIC=m +# CONFIG_SCSI_FLASHPOINT is not set CONFIG_SCSI_MYRB=m CONFIG_SCSI_MYRS=m # CONFIG_SCSI_SNIC is not set @@ -2397,8 +2361,6 @@ CONFIG_ATA=y CONFIG_SATA_HOST=y CONFIG_ATA_VERBOSE_ERROR=y CONFIG_ATA_FORCE=y -CONFIG_ARCH_WANT_LIBATA_LEDS=y -CONFIG_ATA_LEDS=y CONFIG_SATA_PMP=y # @@ -2407,6 +2369,7 @@ CONFIG_SATA_PMP=y CONFIG_SATA_AHCI=y CONFIG_SATA_MOBILE_LPM_POLICY=0 CONFIG_SATA_AHCI_PLATFORM=y +CONFIG_AHCI_DWC=m # CONFIG_AHCI_CEVA is not set CONFIG_AHCI_MVEBU=y # CONFIG_AHCI_QORIQ is not set @@ -2483,6 +2446,8 @@ CONFIG_SATA_MV=y # CONFIG_PATA_MPIIX is not set # CONFIG_PATA_NS87410 is not set # CONFIG_PATA_OPTI is not set +CONFIG_PATA_PLATFORM=m +CONFIG_PATA_OF_PLATFORM=m # CONFIG_PATA_RZ1000 is not set # @@ -2619,20 +2584,25 @@ CONFIG_NET_DSA_HIRSCHMANN_HELLCREEK=m CONFIG_NET_DSA_LANTIQ_GSWIP=m # CONFIG_NET_DSA_MT7530 is not set CONFIG_NET_DSA_MV88E6060=m -# CONFIG_NET_DSA_MICROCHIP_KSZ9477 is not set -# CONFIG_NET_DSA_MICROCHIP_KSZ8795 is not set +CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON=m +CONFIG_NET_DSA_MICROCHIP_KSZ9477_I2C=m +CONFIG_NET_DSA_MICROCHIP_KSZ_SPI=m +CONFIG_NET_DSA_MICROCHIP_KSZ8863_SMI=m CONFIG_NET_DSA_MV88E6XXX=m # CONFIG_NET_DSA_MV88E6XXX_PTP is not set CONFIG_NET_DSA_MSCC_SEVILLE=m # CONFIG_NET_DSA_AR9331 is not set +# CONFIG_NET_DSA_QCA8K is not set CONFIG_NET_DSA_SJA1105=m # CONFIG_NET_DSA_SJA1105_PTP is not set CONFIG_NET_DSA_XRS700X=m CONFIG_NET_DSA_XRS700X_I2C=m CONFIG_NET_DSA_XRS700X_MDIO=m -# CONFIG_NET_DSA_QCA8K is not set CONFIG_NET_DSA_REALTEK=m +CONFIG_NET_DSA_REALTEK_MDIO=m CONFIG_NET_DSA_REALTEK_SMI=m +CONFIG_NET_DSA_REALTEK_RTL8365MB=m +CONFIG_NET_DSA_REALTEK_RTL8366RB=m # CONFIG_NET_DSA_SMSC_LAN9303_I2C is not set # CONFIG_NET_DSA_SMSC_LAN9303_MDIO is not set CONFIG_NET_DSA_VITESSE_VSC73XX=m @@ -2641,6 +2611,7 @@ CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM=m # end of Distributed Switch Architecture drivers CONFIG_ETHERNET=y +CONFIG_MDIO=m # CONFIG_NET_VENDOR_3COM is not set # CONFIG_NET_VENDOR_ADAPTEC is not set # CONFIG_NET_VENDOR_AGERE is not set @@ -2663,7 +2634,9 @@ CONFIG_NET_VENDOR_CADENCE=y # CONFIG_NET_VENDOR_CISCO is not set CONFIG_NET_VENDOR_CORTINA=y CONFIG_GEMINI_ETHERNET=m +CONFIG_NET_VENDOR_DAVICOM=y # CONFIG_DM9000 is not set +CONFIG_DM9051=m # CONFIG_DNET is not set # CONFIG_NET_VENDOR_DEC is not set # CONFIG_NET_VENDOR_DLINK is not set @@ -2672,11 +2645,20 @@ CONFIG_NET_VENDOR_ENGLEDER=y # CONFIG_TSNEP is not set # CONFIG_NET_VENDOR_EZCHIP is not set # CONFIG_NET_VENDOR_FARADAY is not set +CONFIG_NET_VENDOR_FUNGIBLE=y +CONFIG_FUN_CORE=m +CONFIG_FUN_ETH=m CONFIG_NET_VENDOR_GOOGLE=y +CONFIG_GVE=m # CONFIG_NET_VENDOR_HISILICON is not set CONFIG_NET_VENDOR_HUAWEI=y # CONFIG_NET_VENDOR_INTEL is not set +CONFIG_NET_VENDOR_WANGXUN=y +CONFIG_NGBE=m +CONFIG_TXGBE=m # CONFIG_JME is not set +CONFIG_NET_VENDOR_ADI=y +CONFIG_ADIN1110=m CONFIG_NET_VENDOR_LITEX=y CONFIG_LITEX_LITEETH=m CONFIG_NET_VENDOR_MARVELL=y @@ -2704,7 +2686,6 @@ CONFIG_NI_XGE_MANAGEMENT_ENET=m # CONFIG_NET_VENDOR_NATSEMI is not set CONFIG_NET_VENDOR_NETERION=y # CONFIG_S2IO is not set -# CONFIG_VXGE is not set # CONFIG_NET_VENDOR_NETRONOME is not set # CONFIG_NET_VENDOR_NVIDIA is not set # CONFIG_NET_VENDOR_OKI is not set @@ -2762,6 +2743,7 @@ CONFIG_SFP=m # # CONFIG_AMD_PHY is not set # CONFIG_ADIN_PHY is not set +CONFIG_ADIN1100_PHY=m # CONFIG_AQUANTIA_PHY is not set CONFIG_AX88796B_PHY=m # CONFIG_BROADCOM_PHY is not set @@ -2802,16 +2784,81 @@ CONFIG_TERANETICS_PHY=m CONFIG_DP83848_PHY=m # CONFIG_DP83867_PHY is not set # CONFIG_DP83869_PHY is not set +CONFIG_DP83TD510_PHY=m CONFIG_VITESSE_PHY=m # CONFIG_XILINX_GMII2RGMII is not set # CONFIG_MICREL_KS8995MA is not set +# CONFIG_PSE_CONTROLLER is not set +CONFIG_CAN_DEV=m +CONFIG_CAN_VCAN=m +CONFIG_CAN_VXCAN=m +CONFIG_CAN_NETLINK=y +CONFIG_CAN_CALC_BITTIMING=y +CONFIG_CAN_RX_OFFLOAD=y +CONFIG_CAN_CAN327=m +CONFIG_CAN_FLEXCAN=m +CONFIG_CAN_GRCAN=m +CONFIG_CAN_KVASER_PCIEFD=m +CONFIG_CAN_SLCAN=m +CONFIG_CAN_TI_HECC=m +CONFIG_CAN_C_CAN=m +CONFIG_CAN_C_CAN_PLATFORM=m +CONFIG_CAN_C_CAN_PCI=m +CONFIG_CAN_CC770=m +CONFIG_CAN_CC770_ISA=m +CONFIG_CAN_CC770_PLATFORM=m +CONFIG_CAN_CTUCANFD=m +CONFIG_CAN_CTUCANFD_PCI=m +CONFIG_CAN_CTUCANFD_PLATFORM=m +# CONFIG_CAN_IFI_CANFD is not set +CONFIG_CAN_M_CAN=m +CONFIG_CAN_M_CAN_PCI=m +CONFIG_CAN_M_CAN_PLATFORM=m +CONFIG_CAN_M_CAN_TCAN4X5X=m +CONFIG_CAN_PEAK_PCIEFD=m +CONFIG_CAN_SJA1000=m +CONFIG_CAN_EMS_PCI=m +CONFIG_CAN_F81601=m +CONFIG_CAN_KVASER_PCI=m +CONFIG_CAN_PEAK_PCI=m +CONFIG_CAN_PEAK_PCIEC=y +CONFIG_CAN_PLX_PCI=m +CONFIG_CAN_SJA1000_ISA=m +CONFIG_CAN_SJA1000_PLATFORM=m +CONFIG_CAN_SOFTING=m + +# +# CAN SPI interfaces +# +CONFIG_CAN_HI311X=m +CONFIG_CAN_MCP251X=m +CONFIG_CAN_MCP251XFD=m +# CONFIG_CAN_MCP251XFD_SANITY is not set +# end of CAN SPI interfaces + +# +# CAN USB interfaces +# +CONFIG_CAN_8DEV_USB=m +CONFIG_CAN_EMS_USB=m +CONFIG_CAN_ESD_USB=m +CONFIG_CAN_ETAS_ES58X=m +CONFIG_CAN_GS_USB=m +CONFIG_CAN_KVASER_USB=m +CONFIG_CAN_MCBA_USB=m +CONFIG_CAN_PEAK_USB=m +CONFIG_CAN_UCAN=m +# end of CAN USB interfaces + +# CONFIG_CAN_DEBUG_DEVICES is not set CONFIG_MDIO_DEVICE=y CONFIG_MDIO_BUS=y CONFIG_FWNODE_MDIO=y CONFIG_OF_MDIO=y CONFIG_MDIO_DEVRES=y -# CONFIG_MDIO_BITBANG is not set +CONFIG_MDIO_BITBANG=m # CONFIG_MDIO_BCM_UNIMAC is not set +CONFIG_MDIO_GPIO=m # CONFIG_MDIO_HISI_FEMAC is not set CONFIG_MDIO_I2C=m # CONFIG_MDIO_MVUSB is not set @@ -2895,7 +2942,7 @@ CONFIG_USB_SIERRA_NET=m # CONFIG_USB_VL600 is not set # CONFIG_USB_NET_CH9200 is not set CONFIG_USB_NET_AQC111=m -# CONFIG_USB_RTL8153_ECM is not set +CONFIG_USB_RTL8153_ECM=m CONFIG_WLAN=y # CONFIG_WLAN_VENDOR_ADMTEK is not set CONFIG_ATH_COMMON=m @@ -3052,9 +3099,12 @@ CONFIG_MT76x2U=m CONFIG_MT7921_COMMON=m CONFIG_MT7921E=m CONFIG_MT7921S=m +CONFIG_MT7921U=m CONFIG_WLAN_VENDOR_MICROCHIP=y # CONFIG_WILC1000_SDIO is not set # CONFIG_WILC1000_SPI is not set +CONFIG_WLAN_VENDOR_PURELIFI=y +CONFIG_PLFXLC=m CONFIG_WLAN_VENDOR_RALINK=y CONFIG_RT2X00=m CONFIG_RT2400PCI=m @@ -3123,6 +3173,8 @@ CONFIG_RTW88_8723DE=m # CONFIG_RTW89 is not set CONFIG_WLAN_VENDOR_RSI=y # CONFIG_RSI_91X is not set +CONFIG_WLAN_VENDOR_SILABS=y +# CONFIG_WFX is not set CONFIG_WLAN_VENDOR_ST=y # CONFIG_CW1200 is not set CONFIG_WLAN_VENDOR_TI=y @@ -3153,7 +3205,6 @@ CONFIG_VIRT_WIFI=m CONFIG_IEEE802154_DRIVERS=m CONFIG_IEEE802154_FAKELB=m CONFIG_IEEE802154_AT86RF230=m -# CONFIG_IEEE802154_AT86RF230_DEBUGFS is not set CONFIG_IEEE802154_MRF24J40=m CONFIG_IEEE802154_CC2520=m CONFIG_IEEE802154_ATUSB=m @@ -3171,6 +3222,8 @@ CONFIG_WWAN_DEBUGFS=y CONFIG_WWAN_HWSIM=m CONFIG_MHI_WWAN_CTRL=m CONFIG_MHI_WWAN_MBIM=m +CONFIG_IOSM=m +CONFIG_MTK_T7XX=m # end of Wireless WAN # CONFIG_VMXNET3 is not set @@ -3186,6 +3239,7 @@ CONFIG_INPUT_LEDS=m CONFIG_INPUT_FF_MEMLESS=m # CONFIG_INPUT_SPARSEKMAP is not set CONFIG_INPUT_MATRIXKMAP=m +CONFIG_INPUT_VIVALDIFMAP=y # # Userland interfaces @@ -3223,6 +3277,7 @@ CONFIG_KEYBOARD_GPIO=y # CONFIG_KEYBOARD_MPR121 is not set # CONFIG_KEYBOARD_NEWTON is not set # CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_PINEPHONE is not set # CONFIG_KEYBOARD_SAMSUNG is not set # CONFIG_KEYBOARD_STOWAWAY is not set # CONFIG_KEYBOARD_SUNKBD is not set @@ -3291,6 +3346,7 @@ CONFIG_JOYSTICK_WALKERA0701=m # CONFIG_JOYSTICK_PXRC is not set CONFIG_JOYSTICK_QWIIC=m # CONFIG_JOYSTICK_FSIA6B is not set +# CONFIG_JOYSTICK_SENSEHAT is not set # CONFIG_INPUT_TABLET is not set # CONFIG_INPUT_TOUCHSCREEN is not set # CONFIG_INPUT_MISC is not set @@ -3345,7 +3401,6 @@ CONFIG_SERIAL_8250_NR_UARTS=4 CONFIG_SERIAL_8250_RUNTIME_UARTS=4 CONFIG_SERIAL_8250_EXTENDED=y CONFIG_SERIAL_8250_MANY_PORTS=y -# CONFIG_SERIAL_8250_ASPEED_VUART is not set CONFIG_SERIAL_8250_SHARE_IRQ=y CONFIG_SERIAL_8250_DETECT_IRQ=y CONFIG_SERIAL_8250_RSA=y @@ -3369,7 +3424,6 @@ CONFIG_SERIAL_CORE_CONSOLE=y CONFIG_SERIAL_SIFIVE=m # CONFIG_SERIAL_SCCNXP is not set # CONFIG_SERIAL_SC16IS7XX is not set -# CONFIG_SERIAL_BCM63XX is not set # CONFIG_SERIAL_ALTERA_JTAGUART is not set # CONFIG_SERIAL_ALTERA_UART is not set # CONFIG_SERIAL_XILINX_PS_UART is not set @@ -3419,6 +3473,7 @@ CONFIG_DEVPORT=y CONFIG_XILLYBUS_CLASS=m # CONFIG_XILLYBUS is not set CONFIG_XILLYUSB=m +CONFIG_RANDOM_TRUST_CPU=y # CONFIG_RANDOM_TRUST_BOOTLOADER is not set # end of Character devices @@ -3457,6 +3512,7 @@ CONFIG_I2C_ALGOBIT=m # # PC SMBus host controller drivers # +CONFIG_I2C_CCGX_UCSI=m # CONFIG_I2C_ALI1535 is not set # CONFIG_I2C_ALI1563 is not set # CONFIG_I2C_ALI15X3 is not set @@ -3495,6 +3551,7 @@ CONFIG_I2C_MV64XXX=y # CONFIG_I2C_DIOLAN_U2C is not set CONFIG_I2C_CP2615=m CONFIG_I2C_PARPORT=m +CONFIG_I2C_PCI1XXXX=m # CONFIG_I2C_ROBOTFUZZ_OSIF is not set # CONFIG_I2C_TAOS_EVM is not set # CONFIG_I2C_TINY_USB is not set @@ -3540,6 +3597,8 @@ CONFIG_SPI_CADENCE_XSPI=m # CONFIG_SPI_GPIO is not set CONFIG_SPI_LM70_LLP=m # CONFIG_SPI_FSL_SPI is not set +CONFIG_SPI_MICROCHIP_CORE=m +CONFIG_SPI_MICROCHIP_CORE_QSPI=m # CONFIG_SPI_OC_TINY is not set CONFIG_SPI_ORION=y # CONFIG_SPI_PXA2XX is not set @@ -3602,6 +3661,7 @@ CONFIG_PINMUX=y CONFIG_PINCONF=y CONFIG_GENERIC_PINCONF=y # CONFIG_DEBUG_PINCTRL is not set +CONFIG_PINCTRL_CY8C95X0=m # CONFIG_PINCTRL_MCP23S08 is not set # CONFIG_PINCTRL_MICROCHIP_SGPIO is not set # CONFIG_PINCTRL_OCELOT is not set @@ -3647,7 +3707,6 @@ CONFIG_GPIO_GENERIC_PLATFORM=y # CONFIG_GPIO_MB86S7X is not set # CONFIG_GPIO_MPC8XXX is not set CONFIG_GPIO_MVEBU=y -# CONFIG_GPIO_SAMA5D2_PIOBU is not set # CONFIG_GPIO_SIFIVE is not set CONFIG_GPIO_SYSCON=y # CONFIG_GPIO_XILINX is not set @@ -3658,7 +3717,6 @@ CONFIG_GPIO_SYSCON=y # # I2C GPIO expanders # -CONFIG_GPIO_ADP5588=m # CONFIG_GPIO_ADNP is not set # CONFIG_GPIO_GW_PLD is not set # CONFIG_GPIO_MAX7300 is not set @@ -3771,6 +3829,7 @@ CONFIG_POWER_SUPPLY=y CONFIG_POWER_SUPPLY_HWMON=y CONFIG_PDA_POWER=m CONFIG_GENERIC_ADC_BATTERY=m +CONFIG_IP5XXX_POWER=m CONFIG_TEST_POWER=m CONFIG_CHARGER_ADP5061=m # CONFIG_BATTERY_CW2015 is not set @@ -3778,6 +3837,7 @@ CONFIG_BATTERY_DS2760=m CONFIG_BATTERY_DS2780=m CONFIG_BATTERY_DS2781=m CONFIG_BATTERY_DS2782=m +# CONFIG_BATTERY_SAMSUNG_SDI is not set CONFIG_BATTERY_SBS=m CONFIG_CHARGER_SBS=m CONFIG_MANAGER_SBS=m @@ -3798,6 +3858,7 @@ CONFIG_CHARGER_LTC4162L=m CONFIG_CHARGER_DETECTOR_MAX14656=m CONFIG_CHARGER_MAX77650=m CONFIG_CHARGER_MAX77976=m +# CONFIG_CHARGER_MT6370 is not set CONFIG_CHARGER_BQ2415X=m CONFIG_CHARGER_BQ24190=m CONFIG_CHARGER_BQ24257=m @@ -3813,6 +3874,7 @@ CONFIG_BATTERY_RT5033=m CONFIG_CHARGER_RT9455=m CONFIG_CHARGER_UCS1002=m # CONFIG_CHARGER_BD99954 is not set +CONFIG_BATTERY_UG3105=m CONFIG_HWMON=y CONFIG_HWMON_VID=m # CONFIG_HWMON_DEBUG_CHIP is not set @@ -3823,7 +3885,6 @@ CONFIG_HWMON_VID=m CONFIG_SENSORS_AD7314=m CONFIG_SENSORS_AD7414=m CONFIG_SENSORS_AD7418=m -CONFIG_SENSORS_ADM1021=m CONFIG_SENSORS_ADM1025=m CONFIG_SENSORS_ADM1026=m CONFIG_SENSORS_ADM1029=m @@ -3843,7 +3904,6 @@ CONFIG_SENSORS_AS370=m CONFIG_SENSORS_ASC7621=m # CONFIG_SENSORS_AXI_FAN_CONTROL is not set CONFIG_SENSORS_ARM_SCMI=m -CONFIG_SENSORS_ASPEED=m CONFIG_SENSORS_ATXP1=m # CONFIG_SENSORS_CORSAIR_CPRO is not set CONFIG_SENSORS_CORSAIR_PSU=m @@ -3885,10 +3945,10 @@ CONFIG_SENSORS_MAX1668=m CONFIG_SENSORS_MAX197=m CONFIG_SENSORS_MAX31722=m # CONFIG_SENSORS_MAX31730 is not set +CONFIG_SENSORS_MAX31760=m CONFIG_SENSORS_MAX6620=m CONFIG_SENSORS_MAX6621=m CONFIG_SENSORS_MAX6639=m -CONFIG_SENSORS_MAX6642=m CONFIG_SENSORS_MAX6650=m CONFIG_SENSORS_MAX6697=m CONFIG_SENSORS_MAX31790=m @@ -3917,7 +3977,9 @@ CONFIG_SENSORS_PC87360=m CONFIG_SENSORS_PC87427=m CONFIG_SENSORS_NTC_THERMISTOR=m CONFIG_SENSORS_NCT6683=m +CONFIG_SENSORS_NCT6775_CORE=m CONFIG_SENSORS_NCT6775=m +CONFIG_SENSORS_NCT6775_I2C=m CONFIG_SENSORS_NCT7802=m CONFIG_SENSORS_NCT7904=m CONFIG_SENSORS_NPCM7XX=m @@ -3944,6 +4006,8 @@ CONFIG_SENSORS_IR38064=m # CONFIG_SENSORS_IRPS5401 is not set CONFIG_SENSORS_ISL68137=m CONFIG_SENSORS_LM25066=m +# CONFIG_SENSORS_LM25066_REGULATOR is not set +CONFIG_SENSORS_LT7182S=m # CONFIG_SENSORS_LTC2978 is not set CONFIG_SENSORS_LTC3815=m CONFIG_SENSORS_MAX15301=m @@ -3958,14 +4022,18 @@ CONFIG_SENSORS_MP2888=m CONFIG_SENSORS_MP2975=m CONFIG_SENSORS_MP5023=m CONFIG_SENSORS_PIM4328=m +CONFIG_SENSORS_PLI1209BC=m +# CONFIG_SENSORS_PLI1209BC_REGULATOR is not set CONFIG_SENSORS_PM6764TR=m CONFIG_SENSORS_PXE1610=m CONFIG_SENSORS_Q54SJ108A2=m CONFIG_SENSORS_STPDDC60=m CONFIG_SENSORS_TPS40422=m CONFIG_SENSORS_TPS53679=m +CONFIG_SENSORS_TPS546D24=m CONFIG_SENSORS_UCD9000=m CONFIG_SENSORS_UCD9200=m +CONFIG_SENSORS_XDPE152=m # CONFIG_SENSORS_XDPE122 is not set CONFIG_SENSORS_ZL6100=m CONFIG_SENSORS_PWM_FAN=m @@ -3977,9 +4045,11 @@ CONFIG_SENSORS_SHT3x=m CONFIG_SENSORS_SHT4x=m CONFIG_SENSORS_SHTC1=m CONFIG_SENSORS_SIS5595=m +# CONFIG_SENSORS_SY7636A is not set CONFIG_SENSORS_DME1737=m CONFIG_SENSORS_EMC1403=m CONFIG_SENSORS_EMC2103=m +CONFIG_SENSORS_EMC2305=m CONFIG_SENSORS_EMC6W201=m CONFIG_SENSORS_SMSC47M1=m CONFIG_SENSORS_SMSC47M192=m @@ -4004,6 +4074,7 @@ CONFIG_SENSORS_TMP103=m CONFIG_SENSORS_TMP108=m CONFIG_SENSORS_TMP401=m CONFIG_SENSORS_TMP421=m +# CONFIG_SENSORS_TMP464 is not set # CONFIG_SENSORS_TMP513 is not set CONFIG_SENSORS_VIA686A=m CONFIG_SENSORS_VT1211=m @@ -4073,6 +4144,7 @@ CONFIG_ARMADA_37XX_WATCHDOG=m # CONFIG_DW_WATCHDOG is not set CONFIG_ORION_WATCHDOG=m # CONFIG_MAX63XX_WATCHDOG is not set +# CONFIG_MAX77620_WATCHDOG is not set # CONFIG_ARM_SMC_WATCHDOG is not set CONFIG_STPMIC1_WATCHDOG=m # CONFIG_ALIM7101_WDT is not set @@ -4156,14 +4228,17 @@ CONFIG_MFD_CORE=m CONFIG_MFD_MAX77650=m # CONFIG_MFD_MAX77686 is not set # CONFIG_MFD_MAX77693 is not set +CONFIG_MFD_MAX77714=m # CONFIG_MFD_MAX77843 is not set # CONFIG_MFD_MAX8907 is not set # CONFIG_MFD_MAX8925 is not set # CONFIG_MFD_MAX8997 is not set # CONFIG_MFD_MAX8998 is not set # CONFIG_MFD_MT6360 is not set +CONFIG_MFD_MT6370=m # CONFIG_MFD_MT6397 is not set # CONFIG_MFD_MENF21BMC is not set +CONFIG_MFD_OCELOT=m # CONFIG_EZX_PCAP is not set # CONFIG_MFD_CPCAP is not set # CONFIG_MFD_VIPERBOARD is not set @@ -4171,14 +4246,17 @@ CONFIG_MFD_NTXEC=m # CONFIG_MFD_RETU is not set # CONFIG_MFD_PCF50633 is not set # CONFIG_MFD_PM8XXX is not set +CONFIG_MFD_SY7636A=m # CONFIG_MFD_RDC321X is not set CONFIG_MFD_RT4831=m # CONFIG_MFD_RT5033 is not set +CONFIG_MFD_RT5120=m # CONFIG_MFD_RC5T583 is not set # CONFIG_MFD_RK808 is not set # CONFIG_MFD_RN5T618 is not set # CONFIG_MFD_SEC_CORE is not set # CONFIG_MFD_SI476X_CORE is not set +CONFIG_MFD_SIMPLE_MFD_I2C=m # CONFIG_MFD_SM501 is not set # CONFIG_MFD_SKY81452 is not set # CONFIG_MFD_STMPE is not set @@ -4274,6 +4352,7 @@ CONFIG_REGULATOR_MCP16502=m # CONFIG_REGULATOR_MP886X is not set # CONFIG_REGULATOR_MPQ7920 is not set # CONFIG_REGULATOR_MT6311 is not set +CONFIG_REGULATOR_MT6370=m # CONFIG_REGULATOR_PCA9450 is not set CONFIG_REGULATOR_PF8X00=m # CONFIG_REGULATOR_PFUZE100 is not set @@ -4285,6 +4364,9 @@ CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY=m CONFIG_REGULATOR_ROHM=m CONFIG_REGULATOR_RT4801=m CONFIG_REGULATOR_RT4831=m +CONFIG_REGULATOR_RT5120=m +CONFIG_REGULATOR_RT5190A=m +CONFIG_REGULATOR_RT5759=m CONFIG_REGULATOR_RT6160=m CONFIG_REGULATOR_RT6245=m CONFIG_REGULATOR_RTQ2134=m @@ -4292,11 +4374,13 @@ CONFIG_REGULATOR_RTMV20=m CONFIG_REGULATOR_RTQ6752=m # CONFIG_REGULATOR_SLG51000 is not set CONFIG_REGULATOR_STPMIC1=m +CONFIG_REGULATOR_SY7636A=m # CONFIG_REGULATOR_SY8106A is not set # CONFIG_REGULATOR_SY8824X is not set # CONFIG_REGULATOR_SY8827N is not set # CONFIG_REGULATOR_TPS51632 is not set # CONFIG_REGULATOR_TPS62360 is not set +CONFIG_REGULATOR_TPS6286X=m # CONFIG_REGULATOR_TPS65023 is not set # CONFIG_REGULATOR_TPS6507X is not set # CONFIG_REGULATOR_TPS65132 is not set @@ -4336,7 +4420,6 @@ CONFIG_DVB_CORE=m # # Video4Linux options # -CONFIG_VIDEO_V4L2=m CONFIG_VIDEO_V4L2_I2C=y CONFIG_VIDEO_V4L2_SUBDEV_API=y # CONFIG_VIDEO_ADV_DEBUG is not set @@ -4344,8 +4427,6 @@ CONFIG_VIDEO_V4L2_SUBDEV_API=y CONFIG_VIDEO_TUNER=m CONFIG_V4L2_FWNODE=m CONFIG_V4L2_ASYNC=m -CONFIG_VIDEOBUF_GEN=m -CONFIG_VIDEOBUF_VMALLOC=m # end of Video4Linux options # @@ -4372,17 +4453,16 @@ CONFIG_DVB_MAX_ADAPTERS=16 # # Drivers filtered as selected at 'Filter media drivers' # + +# +# Media drivers +# CONFIG_MEDIA_USB_SUPPORT=y # # Webcam devices # -CONFIG_USB_VIDEO_CLASS=m -CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y CONFIG_USB_GSPCA=m -CONFIG_USB_M5602=m -CONFIG_USB_STV06XX=m -CONFIG_USB_GL860=m CONFIG_USB_GSPCA_BENQ=m CONFIG_USB_GSPCA_CONEX=m CONFIG_USB_GSPCA_CPIA1=m @@ -4407,13 +4487,13 @@ CONFIG_USB_GSPCA_SN9C2028=m CONFIG_USB_GSPCA_SN9C20X=m CONFIG_USB_GSPCA_SONIXB=m CONFIG_USB_GSPCA_SONIXJ=m +CONFIG_USB_GSPCA_SPCA1528=m CONFIG_USB_GSPCA_SPCA500=m CONFIG_USB_GSPCA_SPCA501=m CONFIG_USB_GSPCA_SPCA505=m CONFIG_USB_GSPCA_SPCA506=m CONFIG_USB_GSPCA_SPCA508=m CONFIG_USB_GSPCA_SPCA561=m -CONFIG_USB_GSPCA_SPCA1528=m CONFIG_USB_GSPCA_SQ905=m CONFIG_USB_GSPCA_SQ905C=m CONFIG_USB_GSPCA_SQ930X=m @@ -4429,29 +4509,31 @@ CONFIG_USB_GSPCA_VC032X=m CONFIG_USB_GSPCA_VICAM=m CONFIG_USB_GSPCA_XIRLINK_CIT=m CONFIG_USB_GSPCA_ZC3XX=m +CONFIG_USB_GL860=m +CONFIG_USB_M5602=m +CONFIG_USB_STV06XX=m CONFIG_USB_PWC=m # CONFIG_USB_PWC_DEBUG is not set CONFIG_USB_PWC_INPUT_EVDEV=y -CONFIG_VIDEO_CPIA2=m -CONFIG_USB_ZR364XX=m -CONFIG_USB_STKWEBCAM=m CONFIG_USB_S2255=m CONFIG_VIDEO_USBTV=m +CONFIG_USB_VIDEO_CLASS=m +CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y # # Analog TV USB devices # -CONFIG_VIDEO_PVRUSB2=m -CONFIG_VIDEO_PVRUSB2_SYSFS=y -CONFIG_VIDEO_PVRUSB2_DVB=y -# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set -CONFIG_VIDEO_HDPVR=m -CONFIG_VIDEO_STK1160_COMMON=m -CONFIG_VIDEO_STK1160=m CONFIG_VIDEO_GO7007=m CONFIG_VIDEO_GO7007_USB=m CONFIG_VIDEO_GO7007_LOADER=m CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m +CONFIG_VIDEO_HDPVR=m +CONFIG_VIDEO_PVRUSB2=m +CONFIG_VIDEO_PVRUSB2_SYSFS=y +CONFIG_VIDEO_PVRUSB2_DVB=y +# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set +CONFIG_VIDEO_STK1160_COMMON=m +CONFIG_VIDEO_STK1160=m # # Analog/digital TV USB devices @@ -4465,6 +4547,8 @@ CONFIG_VIDEO_CX231XX_DVB=m # # Digital TV USB devices # +# CONFIG_DVB_AS102 is not set +# CONFIG_DVB_B2C2_FLEXCOP_USB is not set CONFIG_DVB_USB_V2=m CONFIG_DVB_USB_AF9015=m CONFIG_DVB_USB_AF9035=m @@ -4472,17 +4556,15 @@ CONFIG_DVB_USB_ANYSEE=m CONFIG_DVB_USB_AU6610=m CONFIG_DVB_USB_AZ6007=m CONFIG_DVB_USB_CE6230=m +CONFIG_DVB_USB_DVBSKY=m CONFIG_DVB_USB_EC168=m CONFIG_DVB_USB_GL861=m CONFIG_DVB_USB_MXL111SF=m CONFIG_DVB_USB_RTL28XXU=m -CONFIG_DVB_USB_DVBSKY=m CONFIG_DVB_USB_ZD1301=m +# CONFIG_SMS_USB_DRV is not set # CONFIG_DVB_TTUSB_BUDGET is not set # CONFIG_DVB_TTUSB_DEC is not set -# CONFIG_SMS_USB_DRV is not set -# CONFIG_DVB_B2C2_FLEXCOP_USB is not set -# CONFIG_DVB_AS102 is not set # # Webcam, TV (analog/digital) USB devices @@ -4499,24 +4581,24 @@ CONFIG_USB_AIRSPY=m CONFIG_USB_HACKRF=m CONFIG_USB_MSI2500=m # CONFIG_MEDIA_PCI_SUPPORT is not set -CONFIG_RADIO_ADAPTERS=y -# CONFIG_RADIO_SI470X is not set -# CONFIG_RADIO_SI4713 is not set -# CONFIG_USB_MR800 is not set -# CONFIG_USB_DSBR is not set +CONFIG_RADIO_ADAPTERS=m # CONFIG_RADIO_MAXIRADIO is not set +# CONFIG_RADIO_SAA7706H is not set # CONFIG_RADIO_SHARK is not set # CONFIG_RADIO_SHARK2 is not set -# CONFIG_USB_KEENE is not set -# CONFIG_USB_RAREMONO is not set -# CONFIG_USB_MA901 is not set +# CONFIG_RADIO_SI4713 is not set # CONFIG_RADIO_TEA5764 is not set -# CONFIG_RADIO_SAA7706H is not set # CONFIG_RADIO_TEF6862 is not set # CONFIG_RADIO_WL1273 is not set +# CONFIG_USB_DSBR is not set +# CONFIG_USB_KEENE is not set +# CONFIG_USB_MA901 is not set +# CONFIG_USB_MR800 is not set +# CONFIG_USB_RAREMONO is not set +# CONFIG_RADIO_SI470X is not set +CONFIG_CYPRESS_FIRMWARE=m CONFIG_VIDEO_CX2341X=m CONFIG_VIDEO_TVEEPROM=m -CONFIG_CYPRESS_FIRMWARE=m CONFIG_VIDEOBUF2_CORE=m CONFIG_VIDEOBUF2_V4L2=m CONFIG_VIDEOBUF2_MEMOPS=m @@ -4530,31 +4612,14 @@ CONFIG_MEDIA_HIDE_ANCILLARY_SUBDRV=y # CONFIG_MEDIA_ATTACH=y -# -# audio, video and radio I2C drivers auto-selected by 'Autoselect ancillary drivers' -# -CONFIG_VIDEO_MSP3400=m -CONFIG_VIDEO_CS53L32A=m -CONFIG_VIDEO_UDA1342=m -CONFIG_VIDEO_WM8775=m -CONFIG_VIDEO_SONY_BTF_MPX=m -CONFIG_VIDEO_SAA711X=m -CONFIG_VIDEO_TVP5150=m -CONFIG_VIDEO_TW2804=m -CONFIG_VIDEO_TW9903=m -CONFIG_VIDEO_TW9906=m - -# -# Video and audio decoders -# -CONFIG_VIDEO_CX25840=m - # # Camera sensor devices # CONFIG_VIDEO_CCS_PLL=m +# CONFIG_VIDEO_AR0521 is not set # CONFIG_VIDEO_HI556 is not set CONFIG_VIDEO_HI846=m +CONFIG_VIDEO_HI847=m CONFIG_VIDEO_IMX208=m # CONFIG_VIDEO_IMX214 is not set # CONFIG_VIDEO_IMX219 is not set @@ -4566,33 +4631,7 @@ CONFIG_VIDEO_IMX334=m CONFIG_VIDEO_IMX335=m # CONFIG_VIDEO_IMX355 is not set CONFIG_VIDEO_IMX412=m -CONFIG_VIDEO_OV02A10=m -CONFIG_VIDEO_OV2640=m -# CONFIG_VIDEO_OV2659 is not set -# CONFIG_VIDEO_OV2680 is not set -# CONFIG_VIDEO_OV2685 is not set -# CONFIG_VIDEO_OV5640 is not set -# CONFIG_VIDEO_OV5645 is not set -# CONFIG_VIDEO_OV5647 is not set -CONFIG_VIDEO_OV5648=m -# CONFIG_VIDEO_OV6650 is not set -# CONFIG_VIDEO_OV5670 is not set -# CONFIG_VIDEO_OV5675 is not set -CONFIG_VIDEO_OV5693=m -# CONFIG_VIDEO_OV5695 is not set -# CONFIG_VIDEO_OV7251 is not set -# CONFIG_VIDEO_OV772X is not set -CONFIG_VIDEO_OV7640=m -# CONFIG_VIDEO_OV7670 is not set -# CONFIG_VIDEO_OV7740 is not set -# CONFIG_VIDEO_OV8856 is not set -CONFIG_VIDEO_OV8865=m -CONFIG_VIDEO_OV9282=m -# CONFIG_VIDEO_OV9640 is not set -# CONFIG_VIDEO_OV9650 is not set -# CONFIG_VIDEO_OV13858 is not set -CONFIG_VIDEO_OV13B10=m -# CONFIG_VIDEO_VS6624 is not set +CONFIG_VIDEO_MAX9271_LIB=m # CONFIG_VIDEO_MT9M001 is not set # CONFIG_VIDEO_MT9M032 is not set # CONFIG_VIDEO_MT9M111 is not set @@ -4602,20 +4641,48 @@ CONFIG_VIDEO_OV13B10=m CONFIG_VIDEO_MT9V011=m # CONFIG_VIDEO_MT9V032 is not set # CONFIG_VIDEO_MT9V111 is not set -# CONFIG_VIDEO_SR030PC30 is not set # CONFIG_VIDEO_NOON010PC30 is not set -# CONFIG_VIDEO_M5MOLS is not set -CONFIG_VIDEO_MAX9271_LIB=m +CONFIG_VIDEO_OG01A1B=m +CONFIG_VIDEO_OV02A10=m +CONFIG_VIDEO_OV08D10=m +# CONFIG_VIDEO_OV13858 is not set +CONFIG_VIDEO_OV13B10=m +CONFIG_VIDEO_OV2640=m +# CONFIG_VIDEO_OV2659 is not set +# CONFIG_VIDEO_OV2680 is not set +# CONFIG_VIDEO_OV2685 is not set +# CONFIG_VIDEO_OV5640 is not set +# CONFIG_VIDEO_OV5645 is not set +# CONFIG_VIDEO_OV5647 is not set +CONFIG_VIDEO_OV5648=m +# CONFIG_VIDEO_OV5670 is not set +# CONFIG_VIDEO_OV5675 is not set +CONFIG_VIDEO_OV5693=m +# CONFIG_VIDEO_OV5695 is not set +# CONFIG_VIDEO_OV6650 is not set +# CONFIG_VIDEO_OV7251 is not set +CONFIG_VIDEO_OV7640=m +# CONFIG_VIDEO_OV7670 is not set +# CONFIG_VIDEO_OV772X is not set +# CONFIG_VIDEO_OV7740 is not set +# CONFIG_VIDEO_OV8856 is not set +CONFIG_VIDEO_OV8865=m +CONFIG_VIDEO_OV9282=m +# CONFIG_VIDEO_OV9640 is not set +# CONFIG_VIDEO_OV9650 is not set # CONFIG_VIDEO_RDACM20 is not set CONFIG_VIDEO_RDACM21=m # CONFIG_VIDEO_RJ54N1 is not set -# CONFIG_VIDEO_S5K6AA is not set -# CONFIG_VIDEO_S5K6A3 is not set +# CONFIG_VIDEO_S5C73M3 is not set # CONFIG_VIDEO_S5K4ECGX is not set # CONFIG_VIDEO_S5K5BAF is not set +# CONFIG_VIDEO_S5K6A3 is not set +# CONFIG_VIDEO_S5K6AA is not set +# CONFIG_VIDEO_SR030PC30 is not set +# CONFIG_VIDEO_VS6624 is not set CONFIG_VIDEO_CCS=m # CONFIG_VIDEO_ET8EK8 is not set -# CONFIG_VIDEO_S5C73M3 is not set +# CONFIG_VIDEO_M5MOLS is not set # end of Camera sensor devices # @@ -4636,6 +4703,25 @@ CONFIG_VIDEO_CCS=m # CONFIG_VIDEO_LM3646 is not set # end of Flash devices +# +# audio, video and radio I2C drivers auto-selected by 'Autoselect ancillary drivers' +# +CONFIG_VIDEO_CS53L32A=m +CONFIG_VIDEO_MSP3400=m +CONFIG_VIDEO_SONY_BTF_MPX=m +CONFIG_VIDEO_UDA1342=m +CONFIG_VIDEO_WM8775=m +CONFIG_VIDEO_SAA711X=m +CONFIG_VIDEO_TVP5150=m +CONFIG_VIDEO_TW2804=m +CONFIG_VIDEO_TW9903=m +CONFIG_VIDEO_TW9906=m + +# +# Video and audio decoders +# +CONFIG_VIDEO_CX25840=m + # # SPI I2C drivers auto-selected by 'Autoselect ancillary drivers' # @@ -4644,6 +4730,7 @@ CONFIG_VIDEO_CCS=m # Media SPI Adapters # CONFIG_CXD2880_SPI_DRV=m +CONFIG_VIDEO_GS1662=m # end of Media SPI Adapters CONFIG_MEDIA_TUNER=m @@ -4651,36 +4738,36 @@ CONFIG_MEDIA_TUNER=m # # Tuner drivers auto-selected by 'Autoselect ancillary drivers' # -CONFIG_MEDIA_TUNER_SIMPLE=m -CONFIG_MEDIA_TUNER_TDA8290=m -CONFIG_MEDIA_TUNER_TDA827X=m -CONFIG_MEDIA_TUNER_TDA18271=m -CONFIG_MEDIA_TUNER_TDA9887=m -CONFIG_MEDIA_TUNER_TEA5761=m -CONFIG_MEDIA_TUNER_TEA5767=m -CONFIG_MEDIA_TUNER_MSI001=m -CONFIG_MEDIA_TUNER_MT20XX=m -CONFIG_MEDIA_TUNER_MT2060=m -CONFIG_MEDIA_TUNER_MT2063=m -CONFIG_MEDIA_TUNER_QT1010=m -CONFIG_MEDIA_TUNER_XC2028=m -CONFIG_MEDIA_TUNER_XC5000=m -CONFIG_MEDIA_TUNER_XC4000=m -CONFIG_MEDIA_TUNER_MXL5005S=m -CONFIG_MEDIA_TUNER_MXL5007T=m -CONFIG_MEDIA_TUNER_MC44S803=m -CONFIG_MEDIA_TUNER_TDA18218=m +CONFIG_MEDIA_TUNER_E4000=m CONFIG_MEDIA_TUNER_FC0011=m CONFIG_MEDIA_TUNER_FC0012=m CONFIG_MEDIA_TUNER_FC0013=m -CONFIG_MEDIA_TUNER_TDA18212=m -CONFIG_MEDIA_TUNER_E4000=m CONFIG_MEDIA_TUNER_FC2580=m -CONFIG_MEDIA_TUNER_TUA9001=m -CONFIG_MEDIA_TUNER_SI2157=m CONFIG_MEDIA_TUNER_IT913X=m -CONFIG_MEDIA_TUNER_R820T=m +CONFIG_MEDIA_TUNER_MC44S803=m +CONFIG_MEDIA_TUNER_MSI001=m +CONFIG_MEDIA_TUNER_MT2060=m +CONFIG_MEDIA_TUNER_MT2063=m +CONFIG_MEDIA_TUNER_MT20XX=m +CONFIG_MEDIA_TUNER_MXL5005S=m +CONFIG_MEDIA_TUNER_MXL5007T=m CONFIG_MEDIA_TUNER_QM1D1C0042=m +CONFIG_MEDIA_TUNER_QT1010=m +CONFIG_MEDIA_TUNER_R820T=m +CONFIG_MEDIA_TUNER_SI2157=m +CONFIG_MEDIA_TUNER_SIMPLE=m +CONFIG_MEDIA_TUNER_TDA18212=m +CONFIG_MEDIA_TUNER_TDA18218=m +CONFIG_MEDIA_TUNER_TDA18271=m +CONFIG_MEDIA_TUNER_TDA827X=m +CONFIG_MEDIA_TUNER_TDA8290=m +CONFIG_MEDIA_TUNER_TDA9887=m +CONFIG_MEDIA_TUNER_TEA5761=m +CONFIG_MEDIA_TUNER_TEA5767=m +CONFIG_MEDIA_TUNER_TUA9001=m +CONFIG_MEDIA_TUNER_XC2028=m +CONFIG_MEDIA_TUNER_XC4000=m +CONFIG_MEDIA_TUNER_XC5000=m # # DVB Frontend drivers auto-selected by 'Autoselect ancillary drivers' @@ -4695,36 +4782,36 @@ CONFIG_DVB_M88DS3103=m # Multistandard (cable + terrestrial) frontends # CONFIG_DVB_DRXK=m -CONFIG_DVB_TDA18271C2DD=m -CONFIG_DVB_SI2165=m CONFIG_DVB_MN88472=m CONFIG_DVB_MN88473=m +CONFIG_DVB_SI2165=m +CONFIG_DVB_TDA18271C2DD=m # # DVB-S (satellite) frontends # -CONFIG_DVB_STV6110=m -CONFIG_DVB_STV0900=m CONFIG_DVB_CX24116=m -CONFIG_DVB_TS2020=m +CONFIG_DVB_STV0900=m +CONFIG_DVB_STV6110=m CONFIG_DVB_TDA10071=m +CONFIG_DVB_TS2020=m # # DVB-T (terrestrial) frontends # -CONFIG_DVB_DRXD=m -CONFIG_DVB_MT352=m -CONFIG_DVB_ZL10353=m -CONFIG_DVB_TDA10048=m CONFIG_DVB_AF9013=m -CONFIG_DVB_EC100=m CONFIG_DVB_CXD2820R=m CONFIG_DVB_CXD2841ER=m +CONFIG_DVB_DRXD=m +CONFIG_DVB_EC100=m +CONFIG_DVB_MT352=m CONFIG_DVB_RTL2830=m CONFIG_DVB_RTL2832=m CONFIG_DVB_RTL2832_SDR=m CONFIG_DVB_SI2168=m +CONFIG_DVB_TDA10048=m CONFIG_DVB_ZD1301_DEMOD=m +CONFIG_DVB_ZL10353=m # # DVB-C (cable) frontends @@ -4734,22 +4821,22 @@ CONFIG_DVB_TDA10023=m # # ATSC (North American/Korean Terrestrial/Cable DTV) frontends # -CONFIG_DVB_LGDT330X=m -CONFIG_DVB_LGDT3305=m -CONFIG_DVB_LGDT3306A=m -CONFIG_DVB_LG2160=m -CONFIG_DVB_S5H1409=m CONFIG_DVB_AU8522=m CONFIG_DVB_AU8522_DTV=m CONFIG_DVB_AU8522_V4L=m -CONFIG_DVB_S5H1411=m +CONFIG_DVB_LG2160=m +CONFIG_DVB_LGDT3305=m +CONFIG_DVB_LGDT3306A=m +CONFIG_DVB_LGDT330X=m CONFIG_DVB_MXL692=m +CONFIG_DVB_S5H1409=m +CONFIG_DVB_S5H1411=m # # ISDB-T (terrestrial) frontends # -CONFIG_DVB_S921=m CONFIG_DVB_MB86A20S=m +CONFIG_DVB_S921=m # # ISDB-S (satellite) & ISDB-T (terrestrial) frontends @@ -4764,10 +4851,10 @@ CONFIG_DVB_PLL=m # # SEC control devices for DVB-S # -CONFIG_DVB_DRX39XYJ=m -CONFIG_DVB_ISL6423=m CONFIG_DVB_A8293=m CONFIG_DVB_AF9033=m +CONFIG_DVB_ISL6423=m +CONFIG_DVB_DRX39XYJ=m # # Common Interface (EN50221) controller drivers @@ -4778,8 +4865,6 @@ CONFIG_DVB_SP2=m # # Graphics support # -CONFIG_VGA_ARB=y -CONFIG_VGA_ARB_MAX_GPUS=16 # CONFIG_IMX_IPUV3_CORE is not set # CONFIG_DRM is not set @@ -4813,6 +4898,7 @@ CONFIG_LCD_OTM3225A=m CONFIG_BACKLIGHT_CLASS_DEVICE=m CONFIG_BACKLIGHT_KTD253=m CONFIG_BACKLIGHT_PWM=m +CONFIG_BACKLIGHT_MT6370=m # CONFIG_BACKLIGHT_QCOM_WLED is not set CONFIG_BACKLIGHT_RT4831=m CONFIG_BACKLIGHT_ADP8860=m @@ -4851,7 +4937,9 @@ CONFIG_SND_PCM_TIMER=y CONFIG_SND_PROC_FS=y # CONFIG_SND_VERBOSE_PROCFS is not set # CONFIG_SND_VERBOSE_PRINTK is not set +CONFIG_SND_CTL_FAST_LOOKUP=y # CONFIG_SND_DEBUG is not set +# CONFIG_SND_CTL_INPUT_VALIDATION is not set CONFIG_SND_SEQUENCER=m CONFIG_SND_SEQ_DUMMY=m CONFIG_SND_SEQ_MIDI_EVENT=m @@ -4864,6 +4952,7 @@ CONFIG_SND_VIRMIDI=m CONFIG_SND_MTPAV=m CONFIG_SND_MTS64=m # CONFIG_SND_SERIAL_U16550 is not set +CONFIG_SND_SERIAL_GENERIC=m # CONFIG_SND_MPU401 is not set CONFIG_SND_PORTMAN2X4=m # CONFIG_SND_PCI is not set @@ -4934,6 +5023,7 @@ CONFIG_HID_FT260=m # CONFIG_HID_GFRM is not set # CONFIG_HID_GLORIOUS is not set # CONFIG_HID_HOLTEK is not set +CONFIG_HID_VIVALDI_COMMON=m CONFIG_HID_VIVALDI=m # CONFIG_HID_GT683R is not set # CONFIG_HID_KEYTOUCH is not set @@ -4941,6 +5031,7 @@ CONFIG_HID_VIVALDI=m # CONFIG_HID_UCLOGIC is not set # CONFIG_HID_WALTOP is not set CONFIG_HID_VIEWSONIC=m +CONFIG_HID_VRC2=m CONFIG_HID_XIAOMI=m CONFIG_HID_GYRATION=m CONFIG_HID_ICADE=m @@ -4956,6 +5047,7 @@ CONFIG_HID_LETSKETCH=m # CONFIG_HID_MAGICMOUSE is not set CONFIG_HID_MALTRON=m # CONFIG_HID_MAYFLASH is not set +# CONFIG_HID_MEGAWORLD_FF is not set CONFIG_HID_REDRAGON=y # CONFIG_HID_MICROSOFT is not set # CONFIG_HID_MONTEREY is not set @@ -4970,12 +5062,15 @@ CONFIG_HID_NINTENDO=m # CONFIG_HID_PETALYNX is not set # CONFIG_HID_PICOLCD is not set # CONFIG_HID_PLANTRONICS is not set +# CONFIG_HID_PXRC is not set +# CONFIG_HID_RAZER is not set # CONFIG_HID_PRIMAX is not set # CONFIG_HID_RETRODE is not set CONFIG_HID_ROCCAT=m CONFIG_HID_SAITEK=m CONFIG_HID_SAMSUNG=m CONFIG_HID_SEMITEK=m +# CONFIG_HID_SIGMAMICRO is not set CONFIG_HID_SONY=m CONFIG_SONY_FF=y CONFIG_HID_SPEEDLINK=m @@ -4987,6 +5082,7 @@ CONFIG_HID_SPEEDLINK=m # CONFIG_HID_SMARTJOYPLUS is not set # CONFIG_HID_TIVO is not set # CONFIG_HID_TOPSEED is not set +# CONFIG_HID_TOPRE is not set # CONFIG_HID_THINGM is not set # CONFIG_HID_THRUSTMASTER is not set # CONFIG_HID_UDRAW_PS3 is not set @@ -5013,6 +5109,7 @@ CONFIG_USB_HIDDEV=y # I2C HID support # CONFIG_I2C_HID_OF=m +CONFIG_I2C_HID_OF_ELAN=m CONFIG_I2C_HID_OF_GOODIX=m # end of I2C HID support @@ -5215,6 +5312,7 @@ CONFIG_USB_HSIC_USB3503=y # CONFIG_USB_HSIC_USB4604 is not set # CONFIG_USB_LINK_LAYER_TEST is not set # CONFIG_USB_CHAOSKEY is not set +# CONFIG_USB_ONBOARD_HUB is not set CONFIG_USB_ATM=m # CONFIG_USB_SPEEDTOUCH is not set # CONFIG_USB_CXACRU is not set @@ -5252,7 +5350,6 @@ CONFIG_MMC_SDHCI_IO_ACCESSORS=y # CONFIG_MMC_SDHCI_PCI is not set CONFIG_MMC_SDHCI_PLTFM=y # CONFIG_MMC_SDHCI_OF_ARASAN is not set -# CONFIG_MMC_SDHCI_OF_ASPEED is not set # CONFIG_MMC_SDHCI_OF_AT91 is not set CONFIG_MMC_SDHCI_OF_DWCMSHC=m # CONFIG_MMC_SDHCI_CADENCE is not set @@ -5279,6 +5376,8 @@ CONFIG_MMC_CQHCI=m # CONFIG_MMC_SDHCI_XENON is not set # CONFIG_MMC_SDHCI_OMAP is not set CONFIG_MMC_SDHCI_AM654=m +# CONFIG_MMC_LITEX is not set +# CONFIG_SCSI_UFSHCD is not set # CONFIG_MEMSTICK is not set CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y @@ -5336,6 +5435,10 @@ CONFIG_LEDS_LM3697=m # Flash and Torch LED drivers # +# +# RGB LED drivers +# + # # LED Triggers # @@ -5402,6 +5505,8 @@ CONFIG_RTC_DRV_ABEOZ9=m # CONFIG_RTC_DRV_DS1672 is not set # CONFIG_RTC_DRV_HYM8563 is not set # CONFIG_RTC_DRV_MAX6900 is not set +CONFIG_RTC_DRV_MAX77686=m +CONFIG_RTC_DRV_NCT3018Y=m # CONFIG_RTC_DRV_RS5C372 is not set # CONFIG_RTC_DRV_ISL1208 is not set # CONFIG_RTC_DRV_ISL12022 is not set @@ -5470,6 +5575,7 @@ CONFIG_RTC_DRV_RX6110=m # CONFIG_RTC_DRV_BQ4802 is not set # CONFIG_RTC_DRV_RP5C01 is not set # CONFIG_RTC_DRV_V3020 is not set +CONFIG_RTC_DRV_OPTEE=m # CONFIG_RTC_DRV_ZYNQMP is not set CONFIG_RTC_DRV_NTXEC=m @@ -5562,6 +5668,7 @@ CONFIG_VFIO_PLATFORM_AMDXGBE_RESET=m CONFIG_VFIO_MDEV=m CONFIG_IRQ_BYPASS_MANAGER=m # CONFIG_VIRT_DRIVERS is not set +CONFIG_VIRTIO_ANCHOR=y CONFIG_VIRTIO=m CONFIG_VIRTIO_MENU=y # CONFIG_VIRTIO_PCI is not set @@ -5614,7 +5721,6 @@ CONFIG_R8188EU=m # Analog to digital converters # # CONFIG_AD7816 is not set -# CONFIG_AD7280 is not set # end of Analog to digital converters # @@ -5623,12 +5729,6 @@ CONFIG_R8188EU=m # CONFIG_ADT7316 is not set # end of Analog digital bi-direction converters -# -# Capacitance to digital converters -# -# CONFIG_AD7746 is not set -# end of Capacitance to digital converters - # # Direct Digital Synthesis # @@ -5656,17 +5756,8 @@ CONFIG_AD9834=m # end of IIO staging drivers # CONFIG_STAGING_MEDIA is not set - -# -# Android -# -# end of Android - # CONFIG_STAGING_BOARD is not set # CONFIG_LTE_GDM724X is not set -# CONFIG_GS_FPGABOOT is not set -# CONFIG_UNISYSSPAR is not set -CONFIG_COMMON_CLK_XLNX_CLKWZRD=m # CONFIG_MOST_COMPONENTS is not set # CONFIG_KS7010 is not set # CONFIG_PI433 is not set @@ -5676,7 +5767,7 @@ CONFIG_HMS_ANYBUSS_BUS=m CONFIG_ARCX_ANYBUS_CONTROLLER=m CONFIG_HMS_PROFINET=m # CONFIG_QLGE is not set -# CONFIG_WFX is not set +# CONFIG_VME_BUS is not set # CONFIG_GOLDFISH is not set # CONFIG_CHROME_PLATFORMS is not set # CONFIG_MELLANOX_PLATFORM is not set @@ -5702,10 +5793,11 @@ CONFIG_COMMON_CLK_SCMI=m # CONFIG_COMMON_CLK_CDCE706 is not set # CONFIG_COMMON_CLK_CDCE925 is not set # CONFIG_COMMON_CLK_CS2000_CP is not set -# CONFIG_COMMON_CLK_LAN966X is not set CONFIG_COMMON_CLK_AXI_CLKGEN=m # CONFIG_COMMON_CLK_PWM is not set +CONFIG_COMMON_CLK_RS9_PCIE=m # CONFIG_COMMON_CLK_VC5 is not set +CONFIG_COMMON_CLK_VC7=m CONFIG_COMMON_CLK_BD718XX=m # CONFIG_COMMON_CLK_FIXED_MMIO is not set CONFIG_MVEBU_CLK_COMMON=y @@ -5720,6 +5812,7 @@ CONFIG_ARMADA_XP_CLK=y CONFIG_ARMADA_AP_CPU_CLK=y CONFIG_DOVE_CLK=y # CONFIG_XILINX_VCU is not set +CONFIG_COMMON_CLK_XLNX_CLKWZRD=m # CONFIG_HWSPINLOCK is not set # @@ -5776,6 +5869,11 @@ CONFIG_SOC_BRCMSTB=y # CONFIG_FSL_RCPM is not set # end of NXP/Freescale QorIQ SoC drivers +# +# fujitsu SoC drivers +# +# end of fujitsu SoC drivers + # # i.MX SoC drivers # @@ -5816,7 +5914,6 @@ CONFIG_EXTCON_PTN5150=m # CONFIG_EXTCON_RT8973A is not set # CONFIG_EXTCON_SM5502 is not set CONFIG_EXTCON_USB_GPIO=m -CONFIG_EXTCON_USBC_TUSB320=m CONFIG_MEMORY=y CONFIG_MVEBU_DEVBUS=y CONFIG_IIO=m @@ -5848,6 +5945,9 @@ CONFIG_ADXL345_SPI=m CONFIG_ADXL355=m CONFIG_ADXL355_I2C=m CONFIG_ADXL355_SPI=m +CONFIG_ADXL367=m +CONFIG_ADXL367_SPI=m +CONFIG_ADXL367_I2C=m CONFIG_ADXL372=m CONFIG_ADXL372_SPI=m CONFIG_ADXL372_I2C=m @@ -5883,6 +5983,7 @@ CONFIG_MMA8452=m CONFIG_MMA9551_CORE=m CONFIG_MMA9551=m CONFIG_MMA9553=m +# CONFIG_MSA311 is not set CONFIG_MXC4005=m CONFIG_MXC6255=m CONFIG_SCA3000=m @@ -5899,6 +6000,7 @@ CONFIG_AD_SIGMA_DELTA=m CONFIG_AD7124=m # CONFIG_AD7192 is not set CONFIG_AD7266=m +# CONFIG_AD7280 is not set CONFIG_AD7291=m # CONFIG_AD7292 is not set CONFIG_AD7298=m @@ -5928,6 +6030,7 @@ CONFIG_LTC2497=m # CONFIG_MAX1027 is not set CONFIG_MAX11100=m CONFIG_MAX1118=m +# CONFIG_MAX11205 is not set # CONFIG_MAX1241 is not set # CONFIG_MAX1363 is not set # CONFIG_MAX9611 is not set @@ -5935,6 +6038,7 @@ CONFIG_MAX1118=m # CONFIG_MCP3422 is not set CONFIG_MCP3911=m # CONFIG_NAU7802 is not set +# CONFIG_RICHTEK_RTQ6056 is not set # CONFIG_SD_ADC_MODULATOR is not set CONFIG_TI_ADC081C=m CONFIG_TI_ADC0832=m @@ -5971,6 +6075,7 @@ CONFIG_AD74413R=m # Amplifiers # # CONFIG_AD8366 is not set +# CONFIG_ADA4250 is not set # CONFIG_HMC425 is not set # end of Amplifiers @@ -5978,6 +6083,7 @@ CONFIG_AD74413R=m # Capacitance to digital converters # # CONFIG_AD7150 is not set +# CONFIG_AD7746 is not set # end of Capacitance to digital converters # @@ -6039,6 +6145,7 @@ CONFIG_IIO_ST_SENSORS_CORE=m # CONFIG_AD5593R is not set # CONFIG_AD5504 is not set # CONFIG_AD5624R_SPI is not set +# CONFIG_LTC2688 is not set CONFIG_AD5686=m CONFIG_AD5686_SPI=m CONFIG_AD5696_I2C=m @@ -6094,6 +6201,7 @@ CONFIG_TI_DAC7612=m # CONFIG_ADF4350 is not set CONFIG_ADF4371=m CONFIG_ADMV1013=m +# CONFIG_ADMV4420 is not set CONFIG_ADRF6780=m # end of Phase-Locked Loop (PLL) frequency synthesizers # end of Frequency Synthesizers DDS/PLL @@ -6152,6 +6260,8 @@ CONFIG_SI7020=m # CONFIG_ADIS16480 is not set # CONFIG_BMI160_I2C is not set # CONFIG_BMI160_SPI is not set +# CONFIG_BOSCH_BNO055_SERIAL is not set +# CONFIG_BOSCH_BNO055_I2C is not set # CONFIG_FXOS8700_I2C is not set # CONFIG_FXOS8700_SPI is not set # CONFIG_KMX61 is not set @@ -6193,6 +6303,7 @@ CONFIG_ISL29125=m CONFIG_JSA1212=m CONFIG_RPR0521=m CONFIG_LTR501=m +# CONFIG_LTRF216A is not set CONFIG_LV0104CS=m CONFIG_MAX44000=m CONFIG_MAX44009=m @@ -6327,6 +6438,8 @@ CONFIG_MB1232=m # CONFIG_RFD77402 is not set # CONFIG_SRF04 is not set # CONFIG_SX9310 is not set +# CONFIG_SX9324 is not set +# CONFIG_SX9360 is not set # CONFIG_SX9500 is not set CONFIG_SRF08=m # CONFIG_VCNL3020 is not set @@ -6357,15 +6470,16 @@ CONFIG_MAX31865=m # end of Temperature sensors # CONFIG_NTB is not set -# CONFIG_VME_BUS is not set CONFIG_PWM=y CONFIG_PWM_SYSFS=y # CONFIG_PWM_DEBUG is not set CONFIG_PWM_ATMEL_TCB=m +CONFIG_PWM_CLK=m CONFIG_PWM_DWC=m # CONFIG_PWM_FSL_FTM is not set CONFIG_PWM_NTXEC=m # CONFIG_PWM_PCA9685 is not set +CONFIG_PWM_XILINX=m # # IRQ chip support @@ -6376,6 +6490,7 @@ CONFIG_ARM_GIC_MAX_NR=1 CONFIG_ARMADA_370_XP_IRQ=y # CONFIG_AL_FIC is not set CONFIG_ORION_IRQCHIP=y +# CONFIG_XILINX_INTC is not set # end of IRQ chip support # CONFIG_IPACK_BUS is not set @@ -6385,7 +6500,6 @@ CONFIG_ORION_IRQCHIP=y # PHY Subsystem # CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PHY_MIPI_DPHY=y CONFIG_PHY_CAN_TRANSCEIVER=m # @@ -6396,10 +6510,8 @@ CONFIG_PHY_CAN_TRANSCEIVER=m # CONFIG_PHY_CADENCE_TORRENT is not set # CONFIG_PHY_CADENCE_DPHY is not set +# CONFIG_PHY_CADENCE_DPHY_RX is not set # CONFIG_PHY_CADENCE_SALVO is not set -CONFIG_PHY_FSL_IMX8MQ_USB=m -CONFIG_PHY_MIXEL_MIPI_DPHY=m -CONFIG_PHY_FSL_IMX8M_PCIE=m CONFIG_ARMADA375_USBCLUSTER_PHY=y CONFIG_PHY_MVEBU_A3700_COMPHY=m CONFIG_PHY_MVEBU_A3700_UTMI=m @@ -6434,13 +6546,14 @@ CONFIG_RAS=y # # Android # -# CONFIG_ANDROID is not set +# CONFIG_ANDROID_BINDER_IPC is not set # end of Android CONFIG_DAX=m CONFIG_NVMEM=y CONFIG_NVMEM_SYSFS=y CONFIG_NVMEM_RMEM=m +# CONFIG_NVMEM_U_BOOT_ENV is not set # # HW tracing support @@ -6463,14 +6576,7 @@ CONFIG_FSI=m # CONFIG_FSI_SCOM is not set # CONFIG_FSI_SBEFIFO is not set CONFIG_TEE=m - -# -# TEE drivers -# CONFIG_OPTEE=m -CONFIG_OPTEE_SHM_NUM_PRIV_PAGES=1 -# end of TEE drivers - CONFIG_MULTIPLEXER=m # @@ -6495,6 +6601,8 @@ CONFIG_MOST=m # CONFIG_MOST_USB_HDM is not set CONFIG_MOST_CDEV=m CONFIG_MOST_SND=m +# CONFIG_PECI is not set +# CONFIG_HTE is not set # end of Device Drivers # @@ -6566,6 +6674,7 @@ CONFIG_F2FS_FS_LZ4=y CONFIG_F2FS_FS_LZ4HC=y CONFIG_F2FS_FS_ZSTD=y CONFIG_F2FS_IOSTAT=y +# CONFIG_F2FS_UNFAIR_RWSEM is not set # CONFIG_ZONEFS_FS is not set CONFIG_FS_POSIX_ACL=y CONFIG_EXPORTFS=y @@ -6611,6 +6720,7 @@ CONFIG_FSCACHE_STATS=y CONFIG_CACHEFILES=m # CONFIG_CACHEFILES_DEBUG is not set # CONFIG_CACHEFILES_ERROR_INJECTION is not set +# CONFIG_CACHEFILES_ONDEMAND is not set # end of Caches # @@ -6789,7 +6899,6 @@ CONFIG_NFS_DISABLE_UDP_SUPPORT=y # CONFIG_NFS_V4_2_READ_PLUS is not set CONFIG_NFSD=m CONFIG_NFSD_V2_ACL=y -CONFIG_NFSD_V3=y CONFIG_NFSD_V3_ACL=y CONFIG_NFSD_V4=y CONFIG_NFSD_PNFS=y @@ -6892,6 +7001,7 @@ CONFIG_NLS_MAC_ROMANIAN=m CONFIG_NLS_MAC_TURKISH=m CONFIG_NLS_UTF8=m CONFIG_DLM=m +# CONFIG_DLM_DEPRECATED_API is not set # CONFIG_DLM_DEBUG is not set CONFIG_UNICODE=y # CONFIG_UNICODE_NORMALIZATION_SELFTEST is not set @@ -6904,7 +7014,9 @@ CONFIG_IO_WQ=y CONFIG_KEYS=y CONFIG_KEYS_REQUEST_CACHE=y CONFIG_PERSISTENT_KEYRINGS=y +# CONFIG_TRUSTED_KEYS is not set CONFIG_ENCRYPTED_KEYS=y +# CONFIG_USER_DECRYPTED_DATA is not set CONFIG_KEY_DH_OPERATIONS=y # CONFIG_SECURITY_DMESG_RESTRICT is not set CONFIG_SECURITY=y @@ -6937,9 +7049,12 @@ CONFIG_SECURITY_TOMOYO_POLICY_LOADER="/sbin/tomoyo-init" CONFIG_SECURITY_TOMOYO_ACTIVATION_TRIGGER="/sbin/init" # CONFIG_SECURITY_TOMOYO_INSECURE_BUILTIN_SETTING is not set CONFIG_SECURITY_APPARMOR=y +# CONFIG_SECURITY_APPARMOR_DEBUG is not set +CONFIG_SECURITY_APPARMOR_INTROSPECT_POLICY=y CONFIG_SECURITY_APPARMOR_HASH=y CONFIG_SECURITY_APPARMOR_HASH_DEFAULT=y -# CONFIG_SECURITY_APPARMOR_DEBUG is not set +CONFIG_SECURITY_APPARMOR_EXPORT_BINARY=y +CONFIG_SECURITY_APPARMOR_PARANOID_LOAD=y # CONFIG_SECURITY_LOADPIN is not set CONFIG_SECURITY_YAMA=y CONFIG_SECURITY_SAFESETID=y @@ -6979,6 +7094,10 @@ CONFIG_INIT_STACK_NONE=y CONFIG_INIT_ON_ALLOC_DEFAULT_ON=y # CONFIG_INIT_ON_FREE_DEFAULT_ON is not set # end of Memory initialization + +CONFIG_RANDSTRUCT_NONE=y +# CONFIG_RANDSTRUCT_FULL is not set +# CONFIG_RANDSTRUCT_PERFORMANCE is not set # end of Kernel hardening options # end of Security options @@ -7022,85 +7141,29 @@ CONFIG_CRYPTO_AUTHENC=m CONFIG_CRYPTO_TEST=m CONFIG_CRYPTO_SIMD=m CONFIG_CRYPTO_ENGINE=m +# end of Crypto core or helper # # Public-key cryptography # CONFIG_CRYPTO_RSA=y CONFIG_CRYPTO_DH=y +# CONFIG_CRYPTO_DH_RFC7919_GROUPS is not set CONFIG_CRYPTO_ECC=m CONFIG_CRYPTO_ECDH=m CONFIG_CRYPTO_ECDSA=m CONFIG_CRYPTO_ECRDSA=m CONFIG_CRYPTO_SM2=m # CONFIG_CRYPTO_CURVE25519 is not set +# end of Public-key cryptography # -# Authenticated Encryption with Associated Data -# -CONFIG_CRYPTO_CCM=m -CONFIG_CRYPTO_GCM=y -CONFIG_CRYPTO_CHACHA20POLY1305=m -CONFIG_CRYPTO_AEGIS128=m -CONFIG_CRYPTO_AEGIS128_SIMD=y -CONFIG_CRYPTO_SEQIV=y -CONFIG_CRYPTO_ECHAINIV=m - -# -# Block modes -# -CONFIG_CRYPTO_CBC=y -CONFIG_CRYPTO_CFB=m -CONFIG_CRYPTO_CTR=y -CONFIG_CRYPTO_CTS=y -CONFIG_CRYPTO_ECB=y -CONFIG_CRYPTO_LRW=m -CONFIG_CRYPTO_OFB=m -CONFIG_CRYPTO_PCBC=m -CONFIG_CRYPTO_XTS=y -CONFIG_CRYPTO_KEYWRAP=m -CONFIG_CRYPTO_NHPOLY1305=m -CONFIG_CRYPTO_ADIANTUM=m -CONFIG_CRYPTO_ESSIV=m - -# -# Hash modes -# -CONFIG_CRYPTO_CMAC=m -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_XCBC=m -CONFIG_CRYPTO_VMAC=m - -# -# Digest -# -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_CRC32=y -CONFIG_CRYPTO_XXHASH=y -CONFIG_CRYPTO_BLAKE2B=y -# CONFIG_CRYPTO_BLAKE2S is not set -CONFIG_CRYPTO_CRCT10DIF=y -CONFIG_CRYPTO_GHASH=y -CONFIG_CRYPTO_POLY1305=m -CONFIG_CRYPTO_MD4=m -CONFIG_CRYPTO_MD5=y -CONFIG_CRYPTO_MICHAEL_MIC=m -CONFIG_CRYPTO_RMD160=m -CONFIG_CRYPTO_SHA1=y -CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_SHA512=y -CONFIG_CRYPTO_SHA3=m -CONFIG_CRYPTO_SM3=m -CONFIG_CRYPTO_STREEBOG=m -CONFIG_CRYPTO_WP512=m - -# -# Ciphers +# Block ciphers # CONFIG_CRYPTO_AES=y CONFIG_CRYPTO_AES_TI=m CONFIG_CRYPTO_ANUBIS=m -CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_ARIA=m CONFIG_CRYPTO_BLOWFISH=m CONFIG_CRYPTO_BLOWFISH_COMMON=m CONFIG_CRYPTO_CAMELLIA=m @@ -7110,13 +7173,83 @@ CONFIG_CRYPTO_CAST6=m CONFIG_CRYPTO_DES=m CONFIG_CRYPTO_FCRYPT=m CONFIG_CRYPTO_KHAZAD=m -CONFIG_CRYPTO_CHACHA20=m CONFIG_CRYPTO_SEED=m CONFIG_CRYPTO_SERPENT=m CONFIG_CRYPTO_SM4=m +CONFIG_CRYPTO_SM4_GENERIC=m CONFIG_CRYPTO_TEA=m CONFIG_CRYPTO_TWOFISH=m CONFIG_CRYPTO_TWOFISH_COMMON=m +# end of Block ciphers + +# +# Length-preserving ciphers and modes +# +CONFIG_CRYPTO_ADIANTUM=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_CHACHA20=m +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CFB=m +CONFIG_CRYPTO_CTR=y +CONFIG_CRYPTO_CTS=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_HCTR2=m +CONFIG_CRYPTO_KEYWRAP=m +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_OFB=m +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_XCTR=m +CONFIG_CRYPTO_XTS=y +CONFIG_CRYPTO_NHPOLY1305=m +# end of Length-preserving ciphers and modes + +# +# AEAD (authenticated encryption with associated data) ciphers +# +CONFIG_CRYPTO_AEGIS128=m +CONFIG_CRYPTO_AEGIS128_SIMD=y +CONFIG_CRYPTO_CHACHA20POLY1305=m +CONFIG_CRYPTO_CCM=m +CONFIG_CRYPTO_GCM=y +CONFIG_CRYPTO_SEQIV=y +CONFIG_CRYPTO_ECHAINIV=m +CONFIG_CRYPTO_ESSIV=m +# end of AEAD (authenticated encryption with associated data) ciphers + +# +# Hashes, digests, and MACs +# +CONFIG_CRYPTO_BLAKE2B=y +CONFIG_CRYPTO_CMAC=m +CONFIG_CRYPTO_GHASH=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_POLYVAL=m +CONFIG_CRYPTO_POLY1305=m +CONFIG_CRYPTO_RMD160=m +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_SHA3=m +CONFIG_CRYPTO_SM3=m +CONFIG_CRYPTO_SM3_GENERIC=m +CONFIG_CRYPTO_STREEBOG=m +CONFIG_CRYPTO_VMAC=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_XXHASH=y +# end of Hashes, digests, and MACs + +# +# CRCs (cyclic redundancy checks) +# +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_CRC32=y +CONFIG_CRYPTO_CRCT10DIF=y +CONFIG_CRYPTO_CRC64_ROCKSOFT=y +# end of CRCs (cyclic redundancy checks) # # Compression @@ -7127,9 +7260,10 @@ CONFIG_CRYPTO_842=y CONFIG_CRYPTO_LZ4=m CONFIG_CRYPTO_LZ4HC=m CONFIG_CRYPTO_ZSTD=y +# end of Compression # -# Random Number Generation +# Random number generation # CONFIG_CRYPTO_ANSI_CPRNG=m CONFIG_CRYPTO_DRBG_MENU=y @@ -7139,6 +7273,11 @@ CONFIG_CRYPTO_DRBG_CTR=y CONFIG_CRYPTO_DRBG=y CONFIG_CRYPTO_JITTERENTROPY=y CONFIG_CRYPTO_KDF800108_CTR=y +# end of Random number generation + +# +# Userspace interface +# CONFIG_CRYPTO_USER_API=m CONFIG_CRYPTO_USER_API_HASH=m CONFIG_CRYPTO_USER_API_SKCIPHER=m @@ -7147,13 +7286,46 @@ CONFIG_CRYPTO_USER_API_RNG=m CONFIG_CRYPTO_USER_API_AEAD=m CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y CONFIG_CRYPTO_STATS=y +# end of Userspace interface + CONFIG_CRYPTO_HASH_INFO=y + +# +# Accelerated Cryptographic Algorithms for CPU (arm) +# +CONFIG_CRYPTO_CURVE25519_NEON=m +CONFIG_CRYPTO_GHASH_ARM_CE=m +CONFIG_CRYPTO_NHPOLY1305_NEON=m +CONFIG_CRYPTO_POLY1305_ARM=m +CONFIG_CRYPTO_BLAKE2S_ARM=y +CONFIG_CRYPTO_BLAKE2B_NEON=m +CONFIG_CRYPTO_SHA1_ARM=m +CONFIG_CRYPTO_SHA1_ARM_NEON=m +CONFIG_CRYPTO_SHA1_ARM_CE=m +CONFIG_CRYPTO_SHA2_ARM_CE=m +CONFIG_CRYPTO_SHA256_ARM=m +CONFIG_CRYPTO_SHA512_ARM=m +CONFIG_CRYPTO_AES_ARM=m +CONFIG_CRYPTO_AES_ARM_BS=m +CONFIG_CRYPTO_AES_ARM_CE=m +CONFIG_CRYPTO_CHACHA20_NEON=m +CONFIG_CRYPTO_CRC32_ARM_CE=m +CONFIG_CRYPTO_CRCT10DIF_ARM_CE=m +# end of Accelerated Cryptographic Algorithms for CPU (arm) + CONFIG_CRYPTO_HW=y CONFIG_CRYPTO_DEV_HIFN_795X=m # CONFIG_CRYPTO_DEV_HIFN_795X_RNG is not set CONFIG_CRYPTO_DEV_ATMEL_I2C=m CONFIG_CRYPTO_DEV_ATMEL_ECC=m CONFIG_CRYPTO_DEV_ATMEL_SHA204A=m +# CONFIG_CRYPTO_DEV_QAT_DH895xCC is not set +# CONFIG_CRYPTO_DEV_QAT_C3XXX is not set +# CONFIG_CRYPTO_DEV_QAT_C62X is not set +# CONFIG_CRYPTO_DEV_QAT_4XXX is not set +# CONFIG_CRYPTO_DEV_QAT_DH895xCCVF is not set +# CONFIG_CRYPTO_DEV_QAT_C3XXXVF is not set +# CONFIG_CRYPTO_DEV_QAT_C62XVF is not set CONFIG_CRYPTO_DEV_MARVELL=m CONFIG_CRYPTO_DEV_MARVELL_CESA=m CONFIG_CRYPTO_DEV_VIRTIO=m @@ -7167,6 +7339,7 @@ CONFIG_PKCS8_PRIVATE_KEY_PARSER=m CONFIG_PKCS7_MESSAGE_PARSER=y CONFIG_PKCS7_TEST_KEY=m CONFIG_SIGNED_PE_FILE_VERIFICATION=y +# CONFIG_FIPS_SIGNATURE_SELFTEST is not set # # Certificates for signature checking @@ -7182,6 +7355,7 @@ CONFIG_SECONDARY_TRUSTED_KEYRING=y CONFIG_SYSTEM_BLACKLIST_KEYRING=y CONFIG_SYSTEM_BLACKLIST_HASH_LIST="" # CONFIG_SYSTEM_REVOCATION_LIST is not set +# CONFIG_SYSTEM_BLACKLIST_AUTH_UPDATE is not set # end of Certificates for signature checking CONFIG_BINARY_PRINTF=y @@ -7207,6 +7381,7 @@ CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y # # Crypto library routines # +CONFIG_CRYPTO_LIB_UTILS=y CONFIG_CRYPTO_LIB_AES=y CONFIG_CRYPTO_LIB_ARC4=m CONFIG_CRYPTO_ARCH_HAVE_LIB_BLAKE2S=y @@ -7222,13 +7397,14 @@ CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=m CONFIG_CRYPTO_LIB_POLY1305_GENERIC=m CONFIG_CRYPTO_LIB_POLY1305=m CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m +CONFIG_CRYPTO_LIB_SHA1=y CONFIG_CRYPTO_LIB_SHA256=y -CONFIG_CRYPTO_LIB_SM4=m # end of Crypto library routines CONFIG_CRC_CCITT=y CONFIG_CRC16=y CONFIG_CRC_T10DIF=y +CONFIG_CRC64_ROCKSOFT=y CONFIG_CRC_ITU_T=m CONFIG_CRC32=y # CONFIG_CRC32_SELFTEST is not set @@ -7236,7 +7412,7 @@ CONFIG_CRC32_SLICEBY8=y # CONFIG_CRC32_SLICEBY4 is not set # CONFIG_CRC32_SARWATE is not set # CONFIG_CRC32_BIT is not set -CONFIG_CRC64=m +CONFIG_CRC64=y CONFIG_CRC4=m CONFIG_CRC7=m CONFIG_LIBCRC32C=y @@ -7253,6 +7429,7 @@ CONFIG_LZO_DECOMPRESS=y CONFIG_LZ4_COMPRESS=y CONFIG_LZ4HC_COMPRESS=y CONFIG_LZ4_DECOMPRESS=y +CONFIG_ZSTD_COMMON=y CONFIG_ZSTD_COMPRESS=y CONFIG_ZSTD_DECOMPRESS=y CONFIG_XZ_DEC=y @@ -7282,6 +7459,8 @@ CONFIG_TEXTSEARCH=y CONFIG_TEXTSEARCH_KMP=m CONFIG_TEXTSEARCH_BM=m CONFIG_TEXTSEARCH_FSM=m +CONFIG_INTERVAL_TREE=y +CONFIG_XARRAY_MULTI=y CONFIG_ASSOCIATIVE_ARRAY=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT_MAP=y @@ -7291,8 +7470,9 @@ CONFIG_NEED_DMA_MAP_STATE=y CONFIG_DMA_DECLARE_COHERENT=y CONFIG_ARCH_HAS_SETUP_DMA_OPS=y CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y +CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y +CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y CONFIG_DMA_NONCOHERENT_MMAP=y -CONFIG_DMA_REMAP=y CONFIG_DMA_CMA=y # CONFIG_DMA_PERNUMA_CMA is not set @@ -7308,6 +7488,7 @@ CONFIG_CMA_ALIGNMENT=8 # CONFIG_DMA_API_DEBUG is not set # CONFIG_DMA_MAP_BENCHMARK is not set CONFIG_SGL_ALLOC=y +# CONFIG_FORCE_NR_CPUS is not set CONFIG_CPU_RMAP=y CONFIG_DQL=y CONFIG_GLOB=y @@ -7321,12 +7502,12 @@ CONFIG_LIBFDT=y CONFIG_OID_REGISTRY=y CONFIG_SG_POOL=y CONFIG_STACKDEPOT=y -CONFIG_STACK_HASH_ORDER=20 CONFIG_REF_TRACKER=y CONFIG_SBITMAP=y # end of Library routines CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y +CONFIG_POLYNOMIAL=m # # Kernel hacking @@ -7348,10 +7529,17 @@ CONFIG_SYMBOLIC_ERRNAME=y CONFIG_DEBUG_BUGVERBOSE=y # end of printk and dmesg options +CONFIG_DEBUG_KERNEL=y +CONFIG_DEBUG_MISC=y + # # Compile-time checks and compiler options # -# CONFIG_DEBUG_INFO is not set +CONFIG_AS_HAS_NON_CONST_LEB128=y +CONFIG_DEBUG_INFO_NONE=y +# CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT is not set +# CONFIG_DEBUG_INFO_DWARF4 is not set +# CONFIG_DEBUG_INFO_DWARF5 is not set CONFIG_FRAME_WARN=1024 # CONFIG_STRIP_ASM_SYMS is not set # CONFIG_READABLE_ASM is not set @@ -7377,14 +7565,12 @@ CONFIG_HAVE_ARCH_KGDB=y # CONFIG_UBSAN is not set # end of Generic Kernel Debugging Instruments -CONFIG_DEBUG_KERNEL=y -CONFIG_DEBUG_MISC=y - # # Networking Debugging # # CONFIG_NET_DEV_REFCNT_TRACKER is not set # CONFIG_NET_NS_REFCNT_TRACKER is not set +# CONFIG_DEBUG_NET is not set # end of Networking Debugging # @@ -7392,13 +7578,14 @@ CONFIG_DEBUG_MISC=y # CONFIG_PAGE_EXTENSION=y # CONFIG_DEBUG_PAGEALLOC is not set +CONFIG_SLUB_DEBUG=y +# CONFIG_SLUB_DEBUG_ON is not set # CONFIG_PAGE_OWNER is not set # CONFIG_PAGE_POISONING is not set # CONFIG_DEBUG_RODATA_TEST is not set # CONFIG_DEBUG_WX is not set # CONFIG_DEBUG_OBJECTS is not set -# CONFIG_SLUB_DEBUG_ON is not set -# CONFIG_SLUB_STATS is not set +# CONFIG_SHRINKER_DEBUG is not set CONFIG_HAVE_DEBUG_KMEMLEAK=y # CONFIG_DEBUG_KMEMLEAK is not set # CONFIG_DEBUG_STACK_USAGE is not set @@ -7411,6 +7598,7 @@ CONFIG_DEBUG_MEMORY_INIT=y # CONFIG_DEBUG_KMAP_LOCAL is not set # CONFIG_DEBUG_HIGHMEM is not set CONFIG_HAVE_ARCH_KASAN=y +CONFIG_HAVE_ARCH_KASAN_VMALLOC=y CONFIG_CC_HAS_KASAN_GENERIC=y CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y # CONFIG_KASAN is not set @@ -7430,7 +7618,6 @@ CONFIG_PANIC_TIMEOUT=0 CONFIG_DETECT_HUNG_TASK=y CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120 # CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set -CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 # CONFIG_WQ_WATCHDOG is not set # CONFIG_TEST_LOCKUP is not set # end of Debug Oops, Lockups and Hangs @@ -7477,6 +7664,7 @@ CONFIG_STACKTRACE=y # CONFIG_DEBUG_SG is not set # CONFIG_DEBUG_NOTIFIERS is not set # CONFIG_BUG_ON_DATA_CORRUPTION is not set +# CONFIG_DEBUG_MAPLE_TREE is not set # end of Debug kernel data structures # CONFIG_DEBUG_CREDENTIALS is not set @@ -7489,6 +7677,7 @@ CONFIG_RCU_SCALE_TEST=m # CONFIG_RCU_TORTURE_TEST is not set # CONFIG_RCU_REF_SCALE_TEST is not set CONFIG_RCU_CPU_STALL_TIMEOUT=21 +CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=0 CONFIG_RCU_TRACE=y # CONFIG_RCU_EQS_DEBUG is not set # end of RCU Debugging @@ -7497,6 +7686,7 @@ CONFIG_RCU_TRACE=y # CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set # CONFIG_LATENCYTOP is not set CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y CONFIG_HAVE_DYNAMIC_FTRACE=y CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y @@ -7532,7 +7722,6 @@ CONFIG_DEBUG_UART_VIRT=0xfec12000 CONFIG_DEBUG_UART_8250_SHIFT=2 # CONFIG_DEBUG_UART_8250_WORD is not set # CONFIG_DEBUG_UART_8250_PALMCHIP is not set -CONFIG_DEBUG_UNCOMPRESS=y CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" CONFIG_EARLY_PRINTK=y CONFIG_ARM_KPROBES_TEST=m @@ -7571,7 +7760,7 @@ CONFIG_TEST_SCANF=m # CONFIG_TEST_BITMAP is not set # CONFIG_TEST_UUID is not set CONFIG_TEST_XARRAY=m -# CONFIG_TEST_OVERFLOW is not set +# CONFIG_TEST_MAPLE_TREE is not set # CONFIG_TEST_RHASHTABLE is not set CONFIG_TEST_SIPHASH=m # CONFIG_TEST_IDA is not set @@ -7586,12 +7775,17 @@ CONFIG_TEST_BLACKHOLE_DEV=m # CONFIG_TEST_SYSCTL is not set # CONFIG_TEST_UDELAY is not set # CONFIG_TEST_STATIC_KEYS is not set +# CONFIG_TEST_DYNAMIC_DEBUG is not set # CONFIG_TEST_KMOD is not set CONFIG_TEST_MEMCAT_P=m -CONFIG_TEST_STACKINIT=m # CONFIG_TEST_MEMINIT is not set # CONFIG_TEST_FREE_PAGES is not set CONFIG_ARCH_USE_MEMTEST=y # CONFIG_MEMTEST is not set # end of Kernel Testing and Coverage + +# +# Rust hacking +# +# end of Rust hacking # end of Kernel hacking diff --git a/config/sources/families/mvebu.conf b/config/sources/families/mvebu.conf index b809018e2a..f9cfba853d 100644 --- a/config/sources/families/mvebu.conf +++ b/config/sources/families/mvebu.conf @@ -18,7 +18,7 @@ case $BRANCH in edge) - KERNELBRANCH='branch:linux-5.17.y' + KERNELBRANCH='branch:linux-6.1.y' LINUXCONFIG='linux-mvebu-edge' KERNELPATCHDIR="mvebu-edge" diff --git a/patch/kernel/archive/mvebu-6.1/0001-cpuidle-mvebu-indicate-failure-to-enter-deeper-sleep.patch b/patch/kernel/archive/mvebu-6.1/0001-cpuidle-mvebu-indicate-failure-to-enter-deeper-sleep.patch new file mode 100644 index 0000000000..da5c35ff04 --- /dev/null +++ b/patch/kernel/archive/mvebu-6.1/0001-cpuidle-mvebu-indicate-failure-to-enter-deeper-sleep.patch @@ -0,0 +1,43 @@ +From: Russell King +Subject: [PATCH 01/30] cpuidle: mvebu: indicate failure to enter deeper sleep + states +MIME-Version: 1.0 +Content-Disposition: inline +Content-Transfer-Encoding: 8bit +Content-Type: text/plain; charset="utf-8" + +The cpuidle ->enter method expects the return value to be the sleep +state we entered. Returning negative numbers or other codes is not +permissible since coupled CPU idle was merged. + +At least some of the mvebu_v7_cpu_suspend() implementations return the +value from cpu_suspend(), which returns zero if the CPU vectors back +into the kernel via cpu_resume() (the success case), or the non-zero +return value of the suspend actor, or one (failure cases). + +We do not want to be returning the failure case value back to CPU idle +as that indicates that we successfully entered one of the deeper idle +states. Always return zero instead, indicating that we slept for the +shortest amount of time. + +Signed-off-by: Russell King +--- + drivers/cpuidle/cpuidle-mvebu-v7.c | 6 +++++- + 1 file changed, 5 insertions(+), 1 deletion(-) + +--- a/drivers/cpuidle/cpuidle-mvebu-v7.c ++++ b/drivers/cpuidle/cpuidle-mvebu-v7.c +@@ -39,8 +39,12 @@ static int mvebu_v7_enter_idle(struct cp + ret = mvebu_v7_cpu_suspend(deepidle); + cpu_pm_exit(); + ++ /* ++ * If we failed to enter the desired state, indicate that we ++ * slept lightly. ++ */ + if (ret) +- return ret; ++ return 0; + + return index; + } diff --git a/patch/kernel/archive/mvebu-6.1/09-pci-link-retraining.patch b/patch/kernel/archive/mvebu-6.1/09-pci-link-retraining.patch new file mode 100644 index 0000000000..d3cf9df1cd --- /dev/null +++ b/patch/kernel/archive/mvebu-6.1/09-pci-link-retraining.patch @@ -0,0 +1,219 @@ +Subject: [PATCH v3] PCI: Disallow retraining link for Atheros chips on non-Gen1 PCIe bridges +Atheros AR9xxx and QCA9xxx chips have behaviour issues not only after a +bus reset, but also after doing retrain link, if PCIe bridge is not in +GEN1 mode (at 2.5 GT/s speed): + +- QCA9880 and QCA9890 chips throw a Link Down event and completely + disappear from the bus and their config space is not accessible + afterwards. + +- QCA9377 chip throws a Link Down event followed by Link Up event, the + config space is accessible and PCI device ID is correct. But trying to + access chip's I/O space causes Uncorrected (Non-Fatal) AER error, + followed by Synchronous external abort 96000210 and Segmentation fault + of insmod while loading ath10k_pci.ko module. + +- AR9390 chip throws a Link Down event followed by Link Up event, config + space is accessible, but contains nonsense values. PCI device ID is + 0xABCD which indicates HW bug that chip itself was not able to read + values from internal EEPROM/OTP. + +- AR9287 chip throws also Link Down and Link Up events, also has + accessible config space containing correct values. But ath9k driver + fails to initialize card from this state as it is unable to access HW + registers. This also indicates that the chip iself is not able to read + values from internal EEPROM/OTP. + +These issues related to PCI device ID 0xABCD and to reading internal +EEPROM/OTP were previously discussed at ath9k-devel mailing list in +following thread: + + https://www.mail-archive.com/ath9k-devel@lists.ath9k.org/msg07529.html + +After experiments we've come up with a solution: it seems that Retrain +link can be called only when using GEN1 PCIe bridge or when PCIe bridge +link speed is forced to 2.5 GT/s. Applying this workaround fixes all +mentioned cards. + +This issue was reproduced with more cards: +- Compex WLE900VX (QCA9880 based / device ID 0x003c) +- QCNFA435 (QCA9377 based / device ID 0x0042) +- Compex WLE200NX (AR9287 based / device ID 0x002e) +- "noname" card (QCA9890 based / device ID 0x003c) +- Wistron NKR-DNXAH1 (AR9390 based / device ID 0x0030) +on Armada 385 with pci-mvebu.c driver and also on Armada 3720 with +pci-aardvark.c driver. + +To workaround this issue, this change introduces a new PCI quirk called +PCI_DEV_FLAGS_NO_RETRAIN_LINK_WHEN_NOT_GEN1, which is enabled for all +Atheros chips with PCI_DEV_FLAGS_NO_BUS_RESET quirk, and also for Atheros +chip AR9287. + +When this quirk is set, kernel disallows triggering PCI_EXP_LNKCTL_RL +bit in config space of PCIe Bridge in the case when PCIe Bridge is +capable of higher speed than 2.5 GT/s and this higher speed is already +allowed. When PCIe Bridge has accessible LNKCTL2 register, we try to +force target link speed to 2.5 GT/s. After this change it is possible +to trigger PCI_EXP_LNKCTL_RL bit without issues. + +Currently only PCIe ASPM kernel code triggers this PCI_EXP_LNKCTL_RL bit, +so quirk check is added only into pcie/aspm.c file. + +Signed-off-by: Pali Rohár +Reported-by: Toke Høiland-Jørgensen +Tested-by: Toke Høiland-Jørgensen +Tested-by: Marek Behún +BugLink: https://lore.kernel.org/linux-pci/87h7l8axqp.fsf@toke.dk/ +BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=84821 +BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=192441 +BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=209833 +Cc: stable@vger.kernel.org # c80851f6ce63a ("PCI: Add PCI_EXP_LNKCTL2_TLS* macros") + +--- +Changes since v1: +* Move whole quirk code into pcie_downgrade_link_to_gen1() function +* Reformat to 80 chars per line where possible +* Add quirk also for cards with AR9287 chip (PCI ID 0x002e) +* Extend commit message description and add information about 0xABCD + +Changes since v2: +* Add quirk also for Atheros QCA9377 chip +--- + drivers/pci/pcie/aspm.c | 44 +++++++++++++++++++++++++++++++++++++++++ + drivers/pci/quirks.c | 39 ++++++++++++++++++++++++++++-------- + include/linux/pci.h | 2 ++ + 3 files changed, 77 insertions(+), 8 deletions(-) + +diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c +index ac0557a305af..729b0389562b 100644 +--- a/drivers/pci/pcie/aspm.c ++++ b/drivers/pci/pcie/aspm.c +@@ -192,12 +192,56 @@ static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist) + link->clkpm_disable = blacklist ? 1 : 0; + } + ++static int pcie_downgrade_link_to_gen1(struct pci_dev *parent) ++{ ++ u16 reg16; ++ u32 reg32; ++ int ret; ++ ++ /* Check if link is capable of higher speed than 2.5 GT/s */ ++ pcie_capability_read_dword(parent, PCI_EXP_LNKCAP, ®32); ++ if ((reg32 & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB) ++ return 0; ++ ++ /* Check if link speed can be downgraded to 2.5 GT/s */ ++ pcie_capability_read_dword(parent, PCI_EXP_LNKCAP2, ®32); ++ if (!(reg32 & PCI_EXP_LNKCAP2_SLS_2_5GB)) { ++ pci_err(parent, "ASPM: Bridge does not support changing Link Speed to 2.5 GT/s\n"); ++ return -EOPNOTSUPP; ++ } ++ ++ /* Force link speed to 2.5 GT/s */ ++ ret = pcie_capability_clear_and_set_word(parent, PCI_EXP_LNKCTL2, ++ PCI_EXP_LNKCTL2_TLS, ++ PCI_EXP_LNKCTL2_TLS_2_5GT); ++ if (!ret) { ++ /* Verify that new value was really set */ ++ pcie_capability_read_word(parent, PCI_EXP_LNKCTL2, ®16); ++ if ((reg16 & PCI_EXP_LNKCTL2_TLS) != PCI_EXP_LNKCTL2_TLS_2_5GT) ++ ret = -EINVAL; ++ } ++ ++ if (ret) { ++ pci_err(parent, "ASPM: Changing Target Link Speed to 2.5 GT/s failed: %d\n", ret); ++ return ret; ++ } ++ ++ pci_info(parent, "ASPM: Target Link Speed changed to 2.5 GT/s due to quirk\n"); ++ return 0; ++} ++ + static bool pcie_retrain_link(struct pcie_link_state *link) + { + struct pci_dev *parent = link->pdev; + unsigned long end_jiffies; + u16 reg16; + ++ if ((link->downstream->dev_flags & PCI_DEV_FLAGS_NO_RETRAIN_LINK_WHEN_NOT_GEN1) && ++ pcie_downgrade_link_to_gen1(parent)) { ++ pci_err(parent, "ASPM: Retrain Link at higher speed is disallowed by quirk\n"); ++ return false; ++ } ++ + pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16); + reg16 |= PCI_EXP_LNKCTL_RL; + pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16); +diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c +index 5d2acebc3..91d675e0d 100644 +--- a/drivers/pci/quirks.c ++++ b/drivers/pci/quirks.c +@@ -3572,19 +3572,46 @@ static void quirk_nvidia_no_bus_reset(struct pci_dev *dev) + DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, + quirk_nvidia_no_bus_reset); + ++ ++static void quirk_no_bus_reset_and_no_retrain_link(struct pci_dev *dev) ++{ ++ dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET | ++ PCI_DEV_FLAGS_NO_RETRAIN_LINK_WHEN_NOT_GEN1; ++} ++ + /* + * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset. ++ * Atheros AR9xxx and QCA9xxx chips do not behave after a bus reset and also ++ * after retrain link when PCIe bridge is not in GEN1 mode at 2.5 GT/s speed. + * The device will throw a Link Down error on AER-capable systems and + * regardless of AER, config space of the device is never accessible again + * and typically causes the system to hang or reset when access is attempted. ++ * Or if config space is accessible again then it contains only dummy values ++ * like fixed PCI device ID 0xABCD or values not initialized at all. ++ * Retrain link can be called only when using GEN1 PCIe bridge or when ++ * PCIe bridge has forced link speed to 2.5 GT/s via PCI_EXP_LNKCTL2 register. ++ * To reset these cards it is required to do PCIe Warm Reset via PERST# pin. + * https://lore.kernel.org/r/20140923210318.498dacbd@dualc.maya.org/ ++ * https://lore.kernel.org/r/87h7l8axqp.fsf@toke.dk/ ++ * https://www.mail-archive.com/ath9k-devel@lists.ath9k.org/msg07529.html + */ +-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset); +-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset); +-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset); +-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset); +-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034, quirk_no_bus_reset); +-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003e, quirk_no_bus_reset); ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x002e, ++ quirk_no_bus_reset_and_no_retrain_link); ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, ++ quirk_no_bus_reset_and_no_retrain_link); ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, ++ quirk_no_bus_reset_and_no_retrain_link); ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, ++ quirk_no_bus_reset_and_no_retrain_link); ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034, ++ quirk_no_bus_reset_and_no_retrain_link); ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003e, ++ quirk_no_bus_reset_and_no_retrain_link); ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, ++ quirk_no_bus_reset_and_no_retrain_link); ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0042, ++ quirk_no_bus_reset_and_no_retrain_link); ++ + + /* + * Root port on some Cavium CN8xxx chips do not successfully complete a bus +diff --git a/include/linux/pci.h b/include/linux/pci.h +index 86c799c97b77..fdbf7254e4ab 100644 +--- a/include/linux/pci.h ++++ b/include/linux/pci.h +@@ -227,6 +227,8 @@ enum pci_dev_flags { + PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11), + /* Device does honor MSI masking despite saying otherwise */ + PCI_DEV_FLAGS_HAS_MSI_MASKING = (__force pci_dev_flags_t) (1 << 12), ++ /* Don't Retrain Link for device when bridge is not in GEN1 mode */ ++ PCI_DEV_FLAGS_NO_RETRAIN_LINK_WHEN_NOT_GEN1 = (__force pci_dev_flags_t) (1 << 12), + }; + + enum pci_irq_reroute_variant { +-- +2.20.1 diff --git a/patch/kernel/archive/mvebu-6.1/10-mvebu-clearfog-pcie-updates.patch b/patch/kernel/archive/mvebu-6.1/10-mvebu-clearfog-pcie-updates.patch new file mode 100644 index 0000000000..d3dbb2bcf9 --- /dev/null +++ b/patch/kernel/archive/mvebu-6.1/10-mvebu-clearfog-pcie-updates.patch @@ -0,0 +1,196 @@ +From 4d73779886194072ecbfea4e0232d10232b5709f Mon Sep 17 00:00:00 2001 +From: Russell King +Date: Tue, 29 Nov 2016 10:13:46 +0000 +Subject: mvebu/clearfog pcie updates + +Signed-off-by: Russell King +--- + drivers/pci/controller/pci-mvebu.c | 76 ++++++++++++++++++++++++++++++++++++++ + drivers/pci/pci-bridge-emul.c | 2 + + drivers/pci/pcie/aspm.c | 6 +++ + drivers/pci/pcie/portdrv_core.c | 2 + + 4 files changed, 86 insertions(+) + +diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c +index c1ffdb06c971..dba5baa2c1ed 100644 +--- a/drivers/pci/controller/pci-mvebu.c ++++ b/drivers/pci/controller/pci-mvebu.c +@@ -59,6 +59,12 @@ + #define PCIE_INT_INTX(i) BIT(24+i) + #define PCIE_INT_PM_PME BIT(28) + #define PCIE_INT_ALL_MASK GENMASK(31, 0) ++#define PCIE_MASK_ERR_COR BIT(18) ++#define PCIE_MASK_ERR_NONFATAL BIT(17) ++#define PCIE_MASK_ERR_FATAL BIT(16) ++#define PCIE_MASK_FERR_DET BIT(10) ++#define PCIE_MASK_NFERR_DET BIT(9) ++#define PCIE_MASK_CORERR_DET BIT(8) + #define PCIE_CTRL_OFF 0x1a00 + #define PCIE_CTRL_X1_MODE 0x0001 + #define PCIE_CTRL_RC_MODE BIT(1) +@@ -618,6 +624,54 @@ mvebu_pci_bridge_emul_base_conf_read(struct pci_bridge_emul *bridge, + return PCI_BRIDGE_EMUL_HANDLED; + } + ++static void mvebu_pcie_handle_irq_change(struct mvebu_pcie_port *port) ++{ ++ u32 reg, old; ++ u16 devctl, rtctl; ++ ++ /* ++ * Errors from downstream devices: ++ * bridge control register SERR: enables reception of errors ++ * Errors from this device, or received errors: ++ * command SERR: enables ERR_NONFATAL and ERR_FATAL messages ++ * => when enabled, these conditions also flag SERR in status register ++ * devctl CERE: enables ERR_CORR messages ++ * devctl NFERE: enables ERR_NONFATAL messages ++ * devctl FERE: enables ERR_FATAL messages ++ * Enabled messages then have three paths: ++ * 1. rtctl: enables system error indication ++ * 2. root error status register updated ++ * 3. root error command register: forwarding via MSI ++ */ ++ old = mvebu_readl(port, PCIE_INT_UNMASK_OFF); ++ reg = old & ~(PCIE_INT_PM_PME | PCIE_MASK_FERR_DET | ++ PCIE_MASK_NFERR_DET | PCIE_MASK_CORERR_DET | ++ PCIE_MASK_ERR_COR | PCIE_MASK_ERR_NONFATAL | ++ PCIE_MASK_ERR_FATAL); ++ ++ devctl = port->bridge.pcie_conf.devctl; ++ if (devctl & PCI_EXP_DEVCTL_FERE) ++ reg |= PCIE_MASK_FERR_DET | PCIE_MASK_ERR_FATAL; ++ if (devctl & PCI_EXP_DEVCTL_NFERE) ++ reg |= PCIE_MASK_NFERR_DET | PCIE_MASK_ERR_NONFATAL; ++ if (devctl & PCI_EXP_DEVCTL_CERE) ++ reg |= PCIE_MASK_CORERR_DET | PCIE_MASK_ERR_COR; ++ if (port->bridge.conf.command & PCI_COMMAND_SERR) ++ reg |= PCIE_MASK_FERR_DET | PCIE_MASK_NFERR_DET | ++ PCIE_MASK_ERR_FATAL | PCIE_MASK_ERR_NONFATAL; ++ ++ if (!(port->bridge.conf.bridgectrl & PCI_BRIDGE_CTL_SERR)) ++ reg &= ~(PCIE_MASK_ERR_COR | PCIE_MASK_ERR_NONFATAL | ++ PCIE_MASK_ERR_FATAL); ++ ++ rtctl = port->bridge.pcie_conf.rootctl; ++ if (rtctl & PCI_EXP_RTCTL_PMEIE) ++ reg |= PCIE_INT_PM_PME; ++ ++ if (old != reg) ++ mvebu_writel(port, reg, PCIE_INT_UNMASK_OFF); ++} ++ + static pci_bridge_emul_read_status_t + mvebu_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge, + int reg, u32 *value) +@@ -734,6 +788,9 @@ mvebu_pci_bridge_emul_base_conf_write(struct pci_bridge_emul *bridge, + switch (reg) { + case PCI_COMMAND: + mvebu_writel(port, new, PCIE_CMD_OFF); ++ ++ if ((old ^ new) & PCI_COMMAND_SERR) ++ mvebu_pcie_handle_irq_change(port); + break; + + case PCI_IO_BASE: +@@ -775,6 +832,8 @@ mvebu_pci_bridge_emul_base_conf_write(struct pci_bridge_emul *bridge, + break; + + case PCI_INTERRUPT_LINE: ++ if (((old ^ new) >> 16) & PCI_BRIDGE_CTL_SERR) ++ mvebu_pcie_handle_irq_change(port); + if (mask & (PCI_BRIDGE_CTL_BUS_RESET << 16)) { + u32 ctrl = mvebu_readl(port, PCIE_CTRL_OFF); + if (new & (PCI_BRIDGE_CTL_BUS_RESET << 16)) +@@ -798,7 +857,18 @@ mvebu_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge, + + switch (reg) { + case PCI_EXP_DEVCTL: ++ /* ++ * Armada370 data says these bits must always ++ * be zero when in root complex mode. ++ */ ++ new &= ~(PCI_EXP_DEVCTL_URRE | PCI_EXP_DEVCTL_FERE | ++ PCI_EXP_DEVCTL_NFERE | PCI_EXP_DEVCTL_CERE); ++ + mvebu_writel(port, new, PCIE_CAP_PCIEXP + PCI_EXP_DEVCTL); ++ ++ if ((new ^ old) & (PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_NFERE | ++ PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_URRE)) ++ mvebu_pcie_handle_irq_change(port); + break; + + case PCI_EXP_LNKCTL: +@@ -849,6 +919,12 @@ mvebu_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge, + + default: + break; ++ ++ case PCI_EXP_RTCTL: ++ if ((new ^ old) & (PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE | ++ PCI_EXP_RTCTL_SEFEE | PCI_EXP_RTCTL_PMEIE)) ++ mvebu_pcie_handle_irq_change(port); ++ break; + } + } + +diff --git a/drivers/pci/pci-bridge-emul.c b/drivers/pci/pci-bridge-emul.c +index 8e429766838c..33868afb5d05 100644 +--- a/drivers/pci/pci-bridge-emul.c ++++ b/drivers/pci/pci-bridge-emul.c +@@ -161,6 +161,7 @@ struct pci_bridge_reg_behavior pci_regs_behavior[PCI_STD_HEADER_SIZEOF / 4] = { + .rw = (GENMASK(7, 0) | + ((PCI_BRIDGE_CTL_PARITY | + PCI_BRIDGE_CTL_SERR | ++ /* NOTE: PCIe does not allow ISA, VGA, MASTER_ABORT */ + PCI_BRIDGE_CTL_ISA | + PCI_BRIDGE_CTL_VGA | + PCI_BRIDGE_CTL_MASTER_ABORT | +@@ -359,6 +360,7 @@ int pci_bridge_emul_init(struct pci_bridge_emul *bridge, + bridge->conf.header_type = PCI_HEADER_TYPE_BRIDGE; + bridge->conf.cache_line_size = 0x10; + bridge->conf.status = cpu_to_le16(PCI_STATUS_CAP_LIST); ++ bridge->conf.bridgectrl = cpu_to_le16(PCI_BRIDGE_CTL_SERR); + bridge->pci_regs_behavior = kmemdup(pci_regs_behavior, + sizeof(pci_regs_behavior), + GFP_KERNEL); +diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c +index a96b7424c9bc..72888e25c0d8 100644 +--- a/drivers/pci/pcie/aspm.c ++++ b/drivers/pci/pcie/aspm.c +@@ -586,6 +586,12 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) + pcie_capability_read_dword(child, PCI_EXP_LNKCAP, &child_lnkcap); + pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &parent_lnkctl); + pcie_capability_read_word(child, PCI_EXP_LNKCTL, &child_lnkctl); ++dev_info(&parent->dev, "up support %x enabled %x\n", ++ (parent_lnkcap & PCI_EXP_LNKCAP_ASPMS) >> 10, ++ !!(parent_lnkctl & PCI_EXP_LNKCTL_ASPMC)); ++dev_info(&parent->dev, "dn support %x enabled %x\n", ++ (child_lnkcap & PCI_EXP_LNKCAP_ASPMS) >> 10, ++ !!(child_lnkctl & PCI_EXP_LNKCTL_ASPMC)); + + /* + * Setup L0s state +diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c +index 604feeb84ee4..09f1ec9f5acb 100644 +--- a/drivers/pci/pcie/portdrv_core.c ++++ b/drivers/pci/pcie/portdrv_core.c +@@ -327,6 +327,7 @@ int pcie_port_device_register(struct pci_dev *dev) + + /* Get and check PCI Express port services */ + capabilities = get_port_device_capability(dev); ++dev_info(&dev->dev, "PCIe capabilities: 0x%x\n", capabilities); + if (!capabilities) + return 0; + +@@ -339,6 +340,7 @@ int pcie_port_device_register(struct pci_dev *dev) + * if that is to be used. + */ + status = pcie_init_service_irqs(dev, irqs, capabilities); ++dev_info(&dev->dev, "init_service_irqs: %d\n", status); + if (status) { + capabilities &= PCIE_PORT_SERVICE_HP; + if (!capabilities) +-- +cgit + diff --git a/patch/kernel/archive/mvebu-6.1/11-implement-slot-capabilities-SSPL.patch b/patch/kernel/archive/mvebu-6.1/11-implement-slot-capabilities-SSPL.patch new file mode 100644 index 0000000000..e61243b7ae --- /dev/null +++ b/patch/kernel/archive/mvebu-6.1/11-implement-slot-capabilities-SSPL.patch @@ -0,0 +1,57 @@ +From e6a83c8b624052022b8212beabee6e4c40c6d8b2 Mon Sep 17 00:00:00 2001 +From: Russell King +Date: Tue, 29 Nov 2016 10:13:48 +0000 +Subject: implement slot capabilities (SSPL) + +--- + drivers/pci/controller/pci-mvebu.c | 20 ++++++++++++++++++++ + 1 file changed, 20 insertions(+) + +diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c +index dba5baa2c1ed..c817cc5b2206 100644 +--- a/drivers/pci/controller/pci-mvebu.c ++++ b/drivers/pci/controller/pci-mvebu.c +@@ -78,6 +78,7 @@ + #define PCIE_SSPL_VALUE_MASK GENMASK(7, 0) + #define PCIE_SSPL_SCALE_SHIFT 8 + #define PCIE_SSPL_SCALE_MASK GENMASK(9, 8) ++#define PCIE_SSPL_MSGEN BIT(14) + #define PCIE_SSPL_ENABLE BIT(16) + #define PCIE_RC_RTSTA 0x1a14 + #define PCIE_DEBUG_CTRL 0x1a60 +@@ -705,6 +706,14 @@ mvebu_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge, + (PCI_EXP_LNKSTA_DLLLA << 16) : 0); + break; + ++ case PCI_EXP_SLTCAP: ++ { ++ u32 tmp = mvebu_readl(port, PCIE_SSPL_OFF); ++ *value = FIELD_GET(PCIE_SSPL_SCALE_MASK, tmp) << 15 | ++ FIELD_GET(PCIE_SSPL_VALUE_MASK, tmp) << 7; ++ break; ++ } ++ + case PCI_EXP_SLTCTL: { + u16 slotctl = le16_to_cpu(bridge->pcie_conf.slotctl); + u16 slotsta = le16_to_cpu(bridge->pcie_conf.slotsta); +@@ -882,6 +891,17 @@ mvebu_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge, + mvebu_writel(port, new, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL); + break; + ++ case PCI_EXP_SLTCAP: ++ { ++ u32 sspl = FIELD_PREP(PCIE_SSPL_VALUE_MASK, ++ FIELD_GET(PCI_EXP_SLTCAP_SPLV, new)) | ++ FIELD_PREP(PCIE_SSPL_SCALE_MASK, ++ FIELD_GET(PCI_EXP_SLTCAP_SPLS, new)) | ++ PCIE_SSPL_MSGEN; ++ mvebu_writel(port, sspl, PCIE_SSPL_OFF); ++ break; ++ } ++ + case PCI_EXP_SLTCTL: + /* + * Allow to change PCIE_SSPL_ENABLE bit only when slot power +-- +cgit + diff --git a/patch/kernel/archive/mvebu-6.1/12-net-dsa-mv88e6xxx.patch b/patch/kernel/archive/mvebu-6.1/12-net-dsa-mv88e6xxx.patch new file mode 100644 index 0000000000..26d0a41070 --- /dev/null +++ b/patch/kernel/archive/mvebu-6.1/12-net-dsa-mv88e6xxx.patch @@ -0,0 +1,1323 @@ +From 6dda089c4f2e277136eff3c370f514f6b1ccbe21 Mon Sep 17 00:00:00 2001 +From: Vivien Didelot +Date: Thu, 22 Oct 2015 14:31:23 -0400 +Subject: net: dsa: mv88e6xxx: add debugfs interface + +Add a debugfs directory named mv88e6xxx.X where X is the DSA switch +index. Mount the debugfs file system with: + + # mount -t debugfs none /sys/kernel/debug + +Signed-off-by: Vivien Didelot +[Modified by rmk for current kernels.] +Signed-off-by: Russell King +--- + drivers/net/dsa/mv88e6xxx/chip.c | 7 + + drivers/net/dsa/mv88e6xxx/chip.h | 2 + + drivers/net/dsa/mv88e6xxx/mv88e6xxx_debugfs.c | 1099 +++++++++++++++++++++++++ + 3 files changed, 1108 insertions(+) + create mode 100644 drivers/net/dsa/mv88e6xxx/mv88e6xxx_debugfs.c + +diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c +index 0b49d243e00b..6fde0e0fec5e 100644 +--- a/drivers/net/dsa/mv88e6xxx/chip.c ++++ b/drivers/net/dsa/mv88e6xxx/chip.c +@@ -3638,8 +3638,13 @@ static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip) + return mv88e6xxx_software_reset(chip); + } + ++#include "mv88e6xxx_debugfs.c" ++ + static void mv88e6xxx_teardown(struct dsa_switch *ds) + { ++ struct mv88e6xxx_chip *chip = ds->priv; ++ ++ mv88e6xxx_remove_debugfs(chip); + mv88e6xxx_teardown_devlink_params(ds); + dsa_devlink_resources_unregister(ds); + mv88e6xxx_teardown_devlink_regions_global(ds); +@@ -3774,6 +3779,8 @@ static int mv88e6xxx_setup(struct dsa_switch *ds) + if (err) + goto unlock; + ++ mv88e6xxx_init_debugfs(chip); ++ + unlock: + mv88e6xxx_reg_unlock(chip); + +diff --git a/drivers/net/dsa/mv88e6xxx/chip.h b/drivers/net/dsa/mv88e6xxx/chip.h +index 5e03cfe50156..b5be8a5719e1 100644 +--- a/drivers/net/dsa/mv88e6xxx/chip.h ++++ b/drivers/net/dsa/mv88e6xxx/chip.h +@@ -410,6 +410,8 @@ struct mv88e6xxx_chip { + + /* Bridge MST to SID mappings */ + struct list_head msts; ++ ++ struct dentry *dbgfs; + }; + + struct mv88e6xxx_bus_ops { +diff --git a/drivers/net/dsa/mv88e6xxx/mv88e6xxx_debugfs.c b/drivers/net/dsa/mv88e6xxx/mv88e6xxx_debugfs.c +new file mode 100644 +index 000000000000..931e769fe9ce +--- /dev/null ++++ b/drivers/net/dsa/mv88e6xxx/mv88e6xxx_debugfs.c +@@ -0,0 +1,1099 @@ ++#include ++#include ++ ++#define GLOBAL2_PVT_ADDR 0x0b ++#define GLOBAL2_PVT_ADDR_BUSY BIT(15) ++#define GLOBAL2_PVT_ADDR_OP_INIT_ONES ((0x01 << 12) | GLOBAL2_PVT_ADDR_BUSY) ++#define GLOBAL2_PVT_ADDR_OP_WRITE_PVLAN ((0x03 << 12) | GLOBAL2_PVT_ADDR_BUSY) ++#define GLOBAL2_PVT_ADDR_OP_READ ((0x04 << 12) | GLOBAL2_PVT_ADDR_BUSY) ++#define GLOBAL2_PVT_DATA 0x0c ++ ++#define ADDR_GLOBAL2 0x1c ++ ++static int mv88e6xxx_serdes_read(struct mv88e6xxx_chip *chip, int reg, u16 *val) ++{ ++ return mv88e6xxx_phy_page_read(chip, MV88E6352_ADDR_SERDES, ++ MV88E6352_SERDES_PAGE_FIBER, ++ reg, val); ++} ++ ++static int mv88e6xxx_serdes_write(struct mv88e6xxx_chip *chip, int reg, u16 val) ++{ ++ return mv88e6xxx_phy_page_write(chip, MV88E6352_ADDR_SERDES, ++ MV88E6352_SERDES_PAGE_FIBER, ++ reg, val); ++} ++ ++static int _mv88e6xxx_pvt_wait(struct mv88e6xxx_chip *chip) ++{ ++ return mv88e6xxx_wait_mask(chip, ADDR_GLOBAL2, GLOBAL2_PVT_ADDR, ++ GLOBAL2_PVT_ADDR_BUSY, 0); ++} ++ ++static int _mv88e6xxx_pvt_cmd(struct mv88e6xxx_chip *chip, int src_dev, ++ int src_port, u16 op) ++{ ++ u16 reg = op; ++ int err; ++ ++ /* 9-bit Cross-chip PVT pointer: with GLOBAL2_MISC_5_BIT_PORT cleared, ++ * source device is 5-bit, source port is 4-bit. ++ */ ++ reg |= (src_dev & 0x1f) << 4; ++ reg |= (src_port & 0xf); ++ ++ err = mv88e6xxx_g2_write(chip, GLOBAL2_PVT_ADDR, reg); ++ if (err) ++ return err; ++ ++ return _mv88e6xxx_pvt_wait(chip); ++} ++ ++static int _mv88e6xxx_pvt_read(struct mv88e6xxx_chip *chip, int src_dev, ++ int src_port, u16 *data) ++{ ++ int ret; ++ ++ ret = _mv88e6xxx_pvt_wait(chip); ++ if (ret < 0) ++ return ret; ++ ++ ret = _mv88e6xxx_pvt_cmd(chip, src_dev, src_port, ++ GLOBAL2_PVT_ADDR_OP_READ); ++ if (ret < 0) ++ return ret; ++ ++ return mv88e6xxx_g2_read(chip, GLOBAL2_PVT_DATA, data); ++} ++ ++static int _mv88e6xxx_pvt_write(struct mv88e6xxx_chip *chip, int src_dev, ++ int src_port, u16 data) ++{ ++ int err; ++ ++ err = _mv88e6xxx_pvt_wait(chip); ++ if (err) ++ return err; ++ ++ err = mv88e6xxx_g2_write(chip, GLOBAL2_PVT_DATA, data); ++ if (err) ++ return err; ++ ++ return _mv88e6xxx_pvt_cmd(chip, src_dev, src_port, ++ GLOBAL2_PVT_ADDR_OP_WRITE_PVLAN); ++} ++ ++static int mv88e6xxx_regs_show(struct seq_file *s, void *p) ++{ ++ struct mv88e6xxx_chip *chip = s->private; ++ int port, reg, ret; ++ u16 data; ++ ++ seq_puts(s, " GLOBAL GLOBAL2 SERDES "); ++ for (port = 0; port < mv88e6xxx_num_ports(chip); port++) ++ seq_printf(s, " %2d ", port); ++ seq_puts(s, "\n"); ++ ++ mutex_lock(&chip->reg_lock); ++ ++ for (reg = 0; reg < 32; reg++) { ++ seq_printf(s, "%2x:", reg); ++ ++ ret = mv88e6xxx_g1_read(chip, reg, &data); ++ if (ret < 0) ++ goto unlock; ++ seq_printf(s, " %4x ", data); ++ ++ ret = mv88e6xxx_g2_read(chip, reg, &data); ++ if (ret < 0) ++ goto unlock; ++ seq_printf(s, " %4x ", data); ++ ++ if (reg != MV88E6XXX_PHY_PAGE) { ++ ret = mv88e6xxx_serdes_read(chip, reg, &data); ++ if (ret < 0) ++ goto unlock; ++ } else { ++ data = 0; ++ } ++ seq_printf(s, " %4x ", data); ++ ++ /* Port regs 0x1a-0x1f are reserved in 6185 family */ ++ if (chip->info->family == MV88E6XXX_FAMILY_6185 && reg > 25) { ++ for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) ++ seq_printf(s, "%4c ", '-'); ++ seq_puts(s, "\n"); ++ continue; ++ } ++ ++ for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) { ++ ret = mv88e6xxx_port_read(chip, port, reg, &data); ++ if (ret < 0) ++ goto unlock; ++ ++ seq_printf(s, "%4x ", data); ++ } ++ ++ seq_puts(s, "\n"); ++ } ++ ++ ret = 0; ++unlock: ++ mutex_unlock(&chip->reg_lock); ++ ++ return ret; ++} ++ ++static ssize_t mv88e6xxx_regs_write(struct file *file, const char __user *buf, ++ size_t count, loff_t *ppos) ++{ ++ struct seq_file *s = file->private_data; ++ struct mv88e6xxx_chip *chip = s->private; ++ char cmd[32], name[32] = { 0 }; ++ unsigned int port, reg, val; ++ int ret; ++ ++ if (count > sizeof(name) - 1) ++ return -EINVAL; ++ ++ if (copy_from_user(cmd, buf, sizeof(cmd))) ++ return -EFAULT; ++ ++ ret = sscanf(cmd, "%s %x %x", name, ®, &val); ++ if (ret != 3) ++ return -EINVAL; ++ ++ if (reg > 0x1f || val > 0xffff) ++ return -ERANGE; ++ ++ mutex_lock(&chip->reg_lock); ++ ++ if (strcasecmp(name, "GLOBAL") == 0) ++ ret = mv88e6xxx_g1_write(chip, reg, val); ++ else if (strcasecmp(name, "GLOBAL2") == 0) ++ ret = mv88e6xxx_g2_write(chip, reg, val); ++ else if (strcasecmp(name, "SERDES") == 0) ++ ret = mv88e6xxx_serdes_write(chip, reg, val); ++ else if (kstrtouint(name, 10, &port) == 0 && port < mv88e6xxx_num_ports(chip)) ++ ret = mv88e6xxx_port_write(chip, port, reg, val); ++ else ++ ret = -EINVAL; ++ ++ mutex_unlock(&chip->reg_lock); ++ ++ return ret < 0 ? ret : count; ++} ++ ++static int mv88e6xxx_regs_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, mv88e6xxx_regs_show, inode->i_private); ++} ++ ++static const struct file_operations mv88e6xxx_regs_fops = { ++ .open = mv88e6xxx_regs_open, ++ .read = seq_read, ++ .write = mv88e6xxx_regs_write, ++ .llseek = no_llseek, ++ .release = single_release, ++ .owner = THIS_MODULE, ++}; ++ ++static int mv88e6xxx_name_show(struct seq_file *s, void *p) ++{ ++ struct mv88e6xxx_chip *chip = s->private; ++ struct dsa_switch *ds = chip->ds; ++ struct dsa_switch_tree *dst = ds->dst; ++ struct dsa_port *dp; ++ int i; ++ ++ if (!ds->cd) ++ return 0; ++ ++ seq_puts(s, " Port Name\n"); ++ ++ list_for_each_entry(dp, &dst->ports, list) { ++ if (dp->ds != ds) ++ continue; ++ ++ i = dp->index; ++ if (!ds->cd->port_names[i]) ++ continue; ++ ++ seq_printf(s, "%4d %s", i, ds->cd->port_names[i]); ++ ++ if (dp->slave) ++ seq_printf(s, " (%s)", netdev_name(dp->slave)); ++ ++ seq_puts(s, "\n"); ++ } ++ ++ return 0; ++} ++ ++static int mv88e6xxx_name_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, mv88e6xxx_name_show, inode->i_private); ++} ++ ++static const struct file_operations mv88e6xxx_name_fops = { ++ .open = mv88e6xxx_name_open, ++ .read = seq_read, ++ .llseek = no_llseek, ++ .release = single_release, ++ .owner = THIS_MODULE, ++}; ++ ++static int mv88e6xxx_atu_show(struct seq_file *s, void *p) ++{ ++ struct mv88e6xxx_chip *chip = s->private; ++ struct mv88e6xxx_atu_entry addr; ++ const char *state; ++ int fid, i, err; ++ ++ seq_puts(s, " FID MAC Addr State Trunk? DPV/Trunk ID\n"); ++ ++ for (fid = 0; fid < mv88e6xxx_num_databases(chip); ++fid) { ++ addr.state = 0; ++ eth_broadcast_addr(addr.mac); ++ ++ do { ++ mutex_lock(&chip->reg_lock); ++ err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); ++ mutex_unlock(&chip->reg_lock); ++ if (err) ++ return err; ++ ++ if (addr.state == 0) ++ break; ++ ++ /* print ATU entry */ ++ seq_printf(s, "%4d %pM", fid, addr.mac); ++ ++ if (is_multicast_ether_addr(addr.mac)) { ++ switch (addr.state) { ++ case MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_PO: ++ state = "MC_STATIC_PO"; ++ break; ++ case MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_DA_MGMT_PO: ++ state = "MC_STATIC_MGMT_PO"; ++ break; ++ case MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_AVB_NRL_PO: ++ state = "MC_STATIC_NRL_PO"; ++ break; ++ case MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY_PO: ++ state = "MC_STATIC_POLICY_PO"; ++ break; ++ case MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC: ++ state = "MC_STATIC"; ++ break; ++ case MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_DA_MGMT: ++ state = "MC_STATIC_MGMT"; ++ break; ++ case MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_AVB_NRL: ++ state = "MC_STATIC_NRL"; ++ break; ++ case MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY: ++ state = "MC_STATIC_POLICY"; ++ break; ++ case 0xb: case 0xa: case 0x9: case 0x8: ++ /* Reserved for future use */ ++ case 0x3: case 0x2: case 0x1: ++ /* Reserved for future use */ ++ case MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED: ++ default: ++ state = "???"; ++ break; ++ } ++ } else { ++ switch (addr.state) { ++ case MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_PO: ++ state = "UC_STATIC_PO"; ++ break; ++ case MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC: ++ state = "UC_STATIC"; ++ break; ++ case MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_DA_MGMT_PO: ++ state = "UC_STATIC_MGMT_PO"; ++ break; ++ case MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_DA_MGMT: ++ state = "UC_STATIC_MGMT"; ++ break; ++ case MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_AVB_NRL_PO: ++ state = "UC_STATIC_NRL_PO"; ++ break; ++ case MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_AVB_NRL: ++ state = "UC_STATIC_NRL"; ++ break; ++ case MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY_PO: ++ state = "UC_STATIC_POLICY_PO"; ++ break; ++ case MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY: ++ state = "UC_STATIC_POLICY"; ++ break; ++ case MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_7_NEWEST: ++ state = "Age 7 (newest)"; ++ break; ++ case MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_6: ++ state = "Age 6"; ++ break; ++ case MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_5: ++ state = "Age 5"; ++ break; ++ case MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_4: ++ state = "Age 4"; ++ break; ++ case MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_3: ++ state = "Age 3"; ++ break; ++ case MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_2: ++ state = "Age 2"; ++ break; ++ case MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_1_OLDEST: ++ state = "Age 1 (oldest)"; ++ break; ++ case MV88E6XXX_G1_ATU_DATA_STATE_UC_UNUSED: ++ default: ++ state = "???"; ++ break; ++ } ++ } ++ ++ seq_printf(s, " %19s", state); ++ ++ if (addr.trunk) { ++ seq_printf(s, " y %d", ++ addr.portvec); ++ } else { ++ seq_puts(s, " n "); ++ for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) ++ seq_printf(s, " %c", ++ addr.portvec & BIT(i) ? ++ 48 + i : '-'); ++ } ++ ++ seq_puts(s, "\n"); ++ } while (!is_broadcast_ether_addr(addr.mac)); ++ } ++ ++ return 0; ++} ++ ++static ssize_t mv88e6xxx_atu_write(struct file *file, const char __user *buf, ++ size_t count, loff_t *ppos) ++{ ++ struct seq_file *s = file->private_data; ++ struct mv88e6xxx_chip *chip = s->private; ++ char cmd[64]; ++ unsigned int fid; ++ int ret; ++ ++ if (copy_from_user(cmd, buf, sizeof(cmd))) ++ return -EFAULT; ++ ++ ret = sscanf(cmd, "%u", &fid); ++ if (ret != 1) ++ return -EINVAL; ++ ++ if (fid >= mv88e6xxx_num_databases(chip)) ++ return -ERANGE; ++ ++ mutex_lock(&chip->reg_lock); ++ ret = mv88e6xxx_g1_atu_flush(chip, fid, true); ++ mutex_unlock(&chip->reg_lock); ++ ++ return ret < 0 ? ret : count; ++} ++ ++static int mv88e6xxx_atu_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, mv88e6xxx_atu_show, inode->i_private); ++} ++ ++static const struct file_operations mv88e6xxx_atu_fops = { ++ .open = mv88e6xxx_atu_open, ++ .read = seq_read, ++ .write = mv88e6xxx_atu_write, ++ .llseek = no_llseek, ++ .release = single_release, ++ .owner = THIS_MODULE, ++}; ++ ++static int mv88e6xxx_default_vid_show(struct seq_file *s, void *p) ++{ ++ struct mv88e6xxx_chip *chip = s->private; ++ u16 pvid; ++ int i, err; ++ ++ seq_puts(s, " Port DefaultVID\n"); ++ ++ mutex_lock(&chip->reg_lock); ++ ++ for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { ++ err = mv88e6xxx_port_get_pvid(chip, i, &pvid); ++ if (err) ++ break; ++ ++ seq_printf(s, "%4d %d\n", i, pvid); ++ } ++ ++ mutex_unlock(&chip->reg_lock); ++ ++ return err; ++} ++ ++static ssize_t mv88e6xxx_default_vid_write(struct file *file, ++ const char __user *buf, size_t count, ++ loff_t *ppos) ++{ ++ struct seq_file *s = file->private_data; ++ struct mv88e6xxx_chip *chip = s->private; ++ char cmd[32]; ++ unsigned int port, pvid; ++ int ret; ++ ++ if (copy_from_user(cmd, buf, sizeof(cmd))) ++ return -EFAULT; ++ ++ ret = sscanf(cmd, "%u %u", &port, &pvid); ++ if (ret != 2) ++ return -EINVAL; ++ ++ if (port >= mv88e6xxx_num_ports(chip) || pvid > 0xfff) ++ return -ERANGE; ++ ++ mutex_lock(&chip->reg_lock); ++ ret = mv88e6xxx_port_set_pvid(chip, port, pvid); ++ mutex_unlock(&chip->reg_lock); ++ ++ return ret < 0 ? ret : count; ++} ++ ++static int mv88e6xxx_default_vid_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, mv88e6xxx_default_vid_show, inode->i_private); ++} ++ ++static const struct file_operations mv88e6xxx_default_vid_fops = { ++ .open = mv88e6xxx_default_vid_open, ++ .read = seq_read, ++ .write = mv88e6xxx_default_vid_write, ++ .llseek = no_llseek, ++ .release = single_release, ++ .owner = THIS_MODULE, ++}; ++ ++static int mv88e6xxx_fid_show(struct seq_file *s, void *p) ++{ ++ struct mv88e6xxx_chip *chip = s->private; ++ u16 fid; ++ int i, err; ++ ++ seq_puts(s, " Port FID\n"); ++ ++ mutex_lock(&chip->reg_lock); ++ ++ for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { ++ err = mv88e6xxx_port_get_fid(chip, i, &fid); ++ if (err) ++ break; ++ ++ seq_printf(s, "%4d %d\n", i, fid); ++ } ++ ++ mutex_unlock(&chip->reg_lock); ++ ++ return err; ++} ++ ++static int mv88e6xxx_fid_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, mv88e6xxx_fid_show, inode->i_private); ++} ++ ++static const struct file_operations mv88e6xxx_fid_fops = { ++ .open = mv88e6xxx_fid_open, ++ .read = seq_read, ++ .llseek = no_llseek, ++ .release = single_release, ++ .owner = THIS_MODULE, ++}; ++ ++static const char * const mv88e6xxx_port_state_names[] = { ++ [MV88E6XXX_PORT_CTL0_STATE_DISABLED] = "Disabled", ++ [MV88E6XXX_PORT_CTL0_STATE_BLOCKING] = "Blocking/Listening", ++ [MV88E6XXX_PORT_CTL0_STATE_LEARNING] = "Learning", ++ [MV88E6XXX_PORT_CTL0_STATE_FORWARDING] = "Forwarding", ++}; ++ ++static int mv88e6xxx_state_show(struct seq_file *s, void *p) ++{ ++ struct mv88e6xxx_chip *chip = s->private; ++ int i, ret; ++ u16 data; ++ ++ /* header */ ++ seq_puts(s, " Port Mode\n"); ++ ++ mutex_lock(&chip->reg_lock); ++ ++ /* One line per input port */ ++ for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { ++ seq_printf(s, "%4d ", i); ++ ++ ret = mv88e6xxx_port_read(chip, i, MV88E6XXX_PORT_CTL0, &data); ++ if (ret < 0) ++ goto unlock; ++ ++ data &= MV88E6XXX_PORT_CTL0_STATE_MASK; ++ seq_printf(s, " %s\n", mv88e6xxx_port_state_names[data]); ++ ret = 0; ++ } ++ ++unlock: ++ mutex_unlock(&chip->reg_lock); ++ ++ return ret; ++} ++ ++static int mv88e6xxx_state_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, mv88e6xxx_state_show, inode->i_private); ++} ++ ++static const struct file_operations mv88e6xxx_state_fops = { ++ .open = mv88e6xxx_state_open, ++ .read = seq_read, ++ .llseek = no_llseek, ++ .release = single_release, ++ .owner = THIS_MODULE, ++}; ++ ++static const char * const mv88e6xxx_port_8021q_mode_names[] = { ++ [MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED] = "Disabled", ++ [MV88E6XXX_PORT_CTL2_8021Q_MODE_FALLBACK] = "Fallback", ++ [MV88E6XXX_PORT_CTL2_8021Q_MODE_CHECK] = "Check", ++ [MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE] = "Secure", ++}; ++ ++static int mv88e6xxx_8021q_mode_show(struct seq_file *s, void *p) ++{ ++ struct mv88e6xxx_chip *chip = s->private; ++ int i, ret; ++ u16 data; ++ ++ /* header */ ++ seq_puts(s, " Port Mode\n"); ++ ++ mutex_lock(&chip->reg_lock); ++ ++ /* One line per input port */ ++ for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { ++ seq_printf(s, "%4d ", i); ++ ++ ret = mv88e6xxx_port_read(chip, i, MV88E6XXX_PORT_CTL2, &data); ++ if (ret < 0) ++ goto unlock; ++ ++ data &= MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK; ++ seq_printf(s, " %s\n", mv88e6xxx_port_8021q_mode_names[data]); ++ ret = 0; ++ } ++ ++unlock: ++ mutex_unlock(&chip->reg_lock); ++ ++ return ret; ++} ++ ++static int mv88e6xxx_8021q_mode_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, mv88e6xxx_8021q_mode_show, inode->i_private); ++} ++ ++static const struct file_operations mv88e6xxx_8021q_mode_fops = { ++ .open = mv88e6xxx_8021q_mode_open, ++ .read = seq_read, ++ .llseek = no_llseek, ++ .release = single_release, ++ .owner = THIS_MODULE, ++}; ++ ++static int mv88e6xxx_vlan_table_show(struct seq_file *s, void *p) ++{ ++ struct mv88e6xxx_chip *chip = s->private; ++ int i, j, ret; ++ u16 data; ++ ++ /* header */ ++ seq_puts(s, " Port"); ++ for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) ++ seq_printf(s, " %2d", i); ++ seq_puts(s, "\n"); ++ ++ mutex_lock(&chip->reg_lock); ++ ++ /* One line per input port */ ++ for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { ++ seq_printf(s, "%4d ", i); ++ ++ ret = mv88e6xxx_port_read(chip, i, MV88E6XXX_PORT_BASE_VLAN, &data); ++ if (ret < 0) ++ goto unlock; ++ ++ /* One column per output port */ ++ for (j = 0; j < mv88e6xxx_num_ports(chip); ++j) ++ seq_printf(s, " %c", data & BIT(j) ? '*' : '-'); ++ seq_puts(s, "\n"); ++ } ++ ++ ret = 0; ++unlock: ++ mutex_unlock(&chip->reg_lock); ++ ++ return ret; ++} ++ ++static int mv88e6xxx_vlan_table_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, mv88e6xxx_vlan_table_show, inode->i_private); ++} ++ ++static const struct file_operations mv88e6xxx_vlan_table_fops = { ++ .open = mv88e6xxx_vlan_table_open, ++ .read = seq_read, ++ .llseek = no_llseek, ++ .release = single_release, ++ .owner = THIS_MODULE, ++}; ++ ++static int mv88e6xxx_pvt_show(struct seq_file *s, void *p) ++{ ++ struct mv88e6xxx_chip *chip = s->private; ++ struct dsa_switch_tree *dst = chip->ds->dst; ++ int port, src_dev, src_port; ++ u16 pvlan; ++ int err = 0; ++ ++ if (chip->info->family == MV88E6XXX_FAMILY_6185) ++ return -ENODEV; ++ ++ /* header */ ++ seq_puts(s, " Dev Port PVLAN"); ++ for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) ++ seq_printf(s, " %2d", port); ++ seq_puts(s, "\n"); ++ ++ mutex_lock(&chip->reg_lock); ++ ++ /* One line per external port */ ++ for (src_dev = 0; src_dev < DSA_MAX_SWITCHES; ++src_dev) { ++ if (!dst->ds[src_dev]) ++ break; ++ ++ if (src_dev == chip->ds->index) ++ continue; ++ ++ seq_puts(s, "\n"); ++ for (src_port = 0; src_port < 16; ++src_port) { ++ if (src_port >= DSA_MAX_PORTS) ++ break; ++ ++ err = _mv88e6xxx_pvt_read(chip, src_dev, src_port, ++ &pvlan); ++ if (err) ++ goto unlock; ++ ++ seq_printf(s, " %d %2d %03hhx ", src_dev, src_port, ++ pvlan); ++ ++ /* One column per internal output port */ ++ for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) ++ seq_printf(s, " %c", ++ pvlan & BIT(port) ? '*' : '-'); ++ seq_puts(s, "\n"); ++ } ++ } ++ ++unlock: ++ mutex_unlock(&chip->reg_lock); ++ ++ return err; ++} ++ ++static ssize_t mv88e6xxx_pvt_write(struct file *file, const char __user *buf, ++ size_t count, loff_t *ppos) ++{ ++ struct seq_file *s = file->private_data; ++ struct mv88e6xxx_chip *chip = s->private; ++ const u16 mask = (1 << mv88e6xxx_num_ports(chip)) - 1; ++ char cmd[32]; ++ unsigned int src_dev, src_port, pvlan; ++ int ret; ++ ++ if (copy_from_user(cmd, buf, sizeof(cmd))) ++ return -EFAULT; ++ ++ if (sscanf(cmd, "%d %d %x", &src_dev, &src_port, &pvlan) != 3) ++ return -EINVAL; ++ ++ if (src_dev >= 32 || src_port >= 16 || pvlan & ~mask) ++ return -ERANGE; ++ ++ mutex_lock(&chip->reg_lock); ++ ret = _mv88e6xxx_pvt_write(chip, src_dev, src_port, pvlan); ++ mutex_unlock(&chip->reg_lock); ++ ++ return ret < 0 ? ret : count; ++} ++ ++static int mv88e6xxx_pvt_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, mv88e6xxx_pvt_show, inode->i_private); ++} ++ ++static const struct file_operations mv88e6xxx_pvt_fops = { ++ .open = mv88e6xxx_pvt_open, ++ .read = seq_read, ++ .write = mv88e6xxx_pvt_write, ++ .llseek = no_llseek, ++ .release = single_release, ++ .owner = THIS_MODULE, ++}; ++ ++static int mv88e6xxx_vtu_show(struct seq_file *s, void *p) ++{ ++ struct mv88e6xxx_chip *chip = s->private; ++ struct mv88e6xxx_vtu_entry next = { 0 }; ++ int port, ret = 0; ++ ++ seq_puts(s, " VID FID SID"); ++ for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) ++ seq_printf(s, " %2d", port); ++ seq_puts(s, "\n"); ++ ++ if (!chip->info->ops->vtu_getnext) ++ return 0; ++ ++ next.vid = chip->info->max_vid; /* first or lowest VID */ ++ ++ do { ++ mutex_lock(&chip->reg_lock); ++ ret = chip->info->ops->vtu_getnext(chip, &next); ++ mutex_unlock(&chip->reg_lock); ++ if (ret < 0) ++ break; ++ ++ if (!next.valid) ++ break; ++ ++ seq_printf(s, "%4d %4d %2d", next.vid, next.fid, next.sid); ++ for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) { ++ switch (next.member[port]) { ++ case MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED: ++ seq_puts(s, " ="); ++ break; ++ case MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED: ++ seq_puts(s, " u"); ++ break; ++ case MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED: ++ seq_puts(s, " t"); ++ break; ++ case MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER: ++ seq_puts(s, " x"); ++ break; ++ default: ++ seq_puts(s, " ??"); ++ break; ++ } ++ } ++ seq_puts(s, "\n"); ++ } while (next.vid < chip->info->max_vid); ++ ++ return ret; ++} ++ ++static ssize_t mv88e6xxx_vtu_write(struct file *file, const char __user *buf, ++ size_t count, loff_t *ppos) ++{ ++ struct seq_file *s = file->private_data; ++ struct mv88e6xxx_chip *chip = s->private; ++ struct mv88e6xxx_vtu_entry entry = { 0 }; ++ bool valid = true; ++ char cmd[64], tags[12]; /* DSA_MAX_PORTS */ ++ int vid, fid, sid, port, ret; ++ ++ if (!chip->info->ops->vtu_loadpurge) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(cmd, buf, sizeof(cmd))) ++ return -EFAULT; ++ ++ /* scan 12 chars instead of num_ports to avoid dynamic scanning... */ ++ ret = sscanf(cmd, "%d %d %d %c %c %c %c %c %c %c %c %c %c %c %c", &vid, ++ &fid, &sid, &tags[0], &tags[1], &tags[2], &tags[3], ++ &tags[4], &tags[5], &tags[6], &tags[7], &tags[8], &tags[9], ++ &tags[10], &tags[11]); ++ if (ret == 1) ++ valid = false; ++ else if (ret != 3 + mv88e6xxx_num_ports(chip)) ++ return -EINVAL; ++ ++ entry.vid = vid; ++ entry.valid = valid; ++ ++ if (valid) { ++ entry.fid = fid; ++ entry.sid = sid; ++ /* Note: The VTU entry pointed by VID will be loaded but not ++ * considered valid until the STU entry pointed by SID is valid. ++ */ ++ ++ for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) { ++ u8 tag; ++ ++ switch (tags[port]) { ++ case 'u': ++ tag = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; ++ break; ++ case 't': ++ tag = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; ++ break; ++ case 'x': ++ tag = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; ++ break; ++ case '=': ++ tag = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ entry.member[port] = tag; ++ } ++ } ++ ++ mutex_lock(&chip->reg_lock); ++ ret = chip->info->ops->vtu_loadpurge(chip, &entry); ++ mutex_unlock(&chip->reg_lock); ++ ++ return ret < 0 ? ret : count; ++} ++ ++static int mv88e6xxx_vtu_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, mv88e6xxx_vtu_show, inode->i_private); ++} ++ ++static const struct file_operations mv88e6xxx_vtu_fops = { ++ .open = mv88e6xxx_vtu_open, ++ .read = seq_read, ++ .write = mv88e6xxx_vtu_write, ++ .llseek = no_llseek, ++ .release = single_release, ++ .owner = THIS_MODULE, ++}; ++#if 0 ++static int mv88e6xxx_stats_show(struct seq_file *s, void *p) ++{ ++ struct mv88e6xxx_chip *chip = s->private; ++ char *strs; ++ u64 *stats; ++ int stat, port, num_stats, num_ports; ++ int err = 0; ++ ++ num_stats = mv88e6xxx_get_sset_count(chip->ds); ++ if (num_stats == 0) ++ return 0; ++ ++ num_ports = mv88e6xxx_num_ports(chip); ++ ++ strs = kcalloc(num_stats, ETH_GSTRING_LEN, GFP_KERNEL); ++ stats = kcalloc(num_stats, num_ports * sizeof(*stats), GFP_KERNEL); ++ if (!strs || !strs) { ++ kfree(strs); ++ kfree(stats); ++ return -ENOMEM; ++ } ++ ++ mv88e6xxx_get_strings(chip->ds, 0, strs); ++ ++ for (port = 0; port < num_ports; port++) ++ mv88e6xxx_get_ethtool_stats(chip->ds, port, stats + (port * num_stats)); ++ ++ seq_puts(s, " Statistic "); ++ for (port = 0; port < mv88e6xxx_num_ports(chip); port++) ++ seq_printf(s, " Port %2d ", port); ++ seq_puts(s, "\n"); ++ ++ for (stat = 0; stat < num_stats; stat++) { ++ seq_printf(s, "%19s: ", strs + stat * ETH_GSTRING_LEN); ++ for (port = 0 ; port < num_ports; port++) { ++ u64 value = stats[stat + port * num_stats]; ++ ++ seq_printf(s, "%8llu ", value); ++ } ++ seq_puts(s, "\n"); ++ } ++ ++ kfree(stats); ++ kfree(strs); ++ ++ return err; ++} ++ ++static int mv88e6xxx_stats_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, mv88e6xxx_stats_show, inode->i_private); ++} ++ ++static const struct file_operations mv88e6xxx_stats_fops = { ++ .open = mv88e6xxx_stats_open, ++ .read = seq_read, ++ .llseek = no_llseek, ++ .release = single_release, ++ .owner = THIS_MODULE, ++}; ++#endif ++static int mv88e6xxx_device_map_show(struct seq_file *s, void *p) ++{ ++ struct mv88e6xxx_chip *chip = s->private; ++ int target, ret; ++ u16 data, port_mask; ++ ++ seq_puts(s, "Target Port\n"); ++ ++ /* FIXME */ ++ port_mask = MV88E6390_G2_DEVICE_MAPPING_PORT_MASK; ++ ++ mutex_lock(&chip->reg_lock); ++ for (target = 0; target < 32; target++) { ++ ret = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_DEVICE_MAPPING, ++ target << 8 /* MV88E6XXX_G2_DEVICE_MAPPING_DEV_MASK */); ++ if (ret < 0) ++ goto out; ++ ret = mv88e6xxx_g2_read(chip, MV88E6XXX_G2_DEVICE_MAPPING, &data); ++ if (ret < 0) ++ goto out; ++ seq_printf(s, " %2d %2d\n", target, data & port_mask); ++ } ++out: ++ mutex_unlock(&chip->reg_lock); ++ ++ return 0; ++} ++ ++static int mv88e6xxx_device_map_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, mv88e6xxx_device_map_show, inode->i_private); ++} ++ ++static const struct file_operations mv88e6xxx_device_map_fops = { ++ .open = mv88e6xxx_device_map_open, ++ .read = seq_read, ++ .llseek = no_llseek, ++ .release = single_release, ++ .owner = THIS_MODULE, ++}; ++ ++/* Must be called with SMI lock held */ ++static int _mv88e6xxx_scratch_wait(struct mv88e6xxx_chip *chip) ++{ ++ return mv88e6xxx_wait_mask(chip, ADDR_GLOBAL2, ++ MV88E6XXX_G2_SCRATCH_MISC_MISC, ++ MV88E6XXX_G2_SCRATCH_MISC_UPDATE, 0); ++} ++ ++static int mv88e6xxx_scratch_show(struct seq_file *s, void *p) ++{ ++ struct mv88e6xxx_chip *chip = s->private; ++ int reg, ret; ++ u16 data; ++ ++ seq_puts(s, "Register Value\n"); ++ ++ mutex_lock(&chip->reg_lock); ++ for (reg = 0; reg < 0x80; reg++) { ++ ret = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_SCRATCH_MISC_MISC, ++ reg << 8 /* MV88E6XXX_G2_SCRATCH_MISC_PTR_MASK */); ++ if (ret < 0) ++ goto out; ++ ++ ret = _mv88e6xxx_scratch_wait(chip); ++ if (ret < 0) ++ goto out; ++ ++ ret = mv88e6xxx_g2_read(chip, MV88E6XXX_G2_SCRATCH_MISC_MISC, &data); ++ seq_printf(s, " %2x %2x\n", reg, ++ data & MV88E6XXX_G2_SCRATCH_MISC_DATA_MASK); ++ } ++out: ++ mutex_unlock(&chip->reg_lock); ++ ++ return 0; ++} ++ ++static int mv88e6xxx_scratch_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, mv88e6xxx_scratch_show, inode->i_private); ++} ++ ++static const struct file_operations mv88e6xxx_scratch_fops = { ++ .open = mv88e6xxx_scratch_open, ++ .read = seq_read, ++ .llseek = no_llseek, ++ .release = single_release, ++ .owner = THIS_MODULE, ++}; ++ ++static void mv88e6xxx_init_debugfs(struct mv88e6xxx_chip *chip) ++{ ++ char *name; ++ ++ name = kasprintf(GFP_KERNEL, "mv88e6xxx.%d", chip->ds->index); ++ chip->dbgfs = debugfs_create_dir(name, NULL); ++ ++ kfree(name); ++ ++ debugfs_create_file("regs", S_IRUGO | S_IWUSR, chip->dbgfs, chip, ++ &mv88e6xxx_regs_fops); ++ ++ debugfs_create_file("name", S_IRUGO, chip->dbgfs, chip, ++ &mv88e6xxx_name_fops); ++ ++ debugfs_create_file("atu", S_IRUGO | S_IWUSR, chip->dbgfs, chip, ++ &mv88e6xxx_atu_fops); ++ ++ debugfs_create_file("default_vid", S_IRUGO | S_IWUSR, chip->dbgfs, chip, ++ &mv88e6xxx_default_vid_fops); ++ ++ debugfs_create_file("fid", S_IRUGO, chip->dbgfs, chip, &mv88e6xxx_fid_fops); ++ ++ debugfs_create_file("state", S_IRUGO, chip->dbgfs, chip, ++ &mv88e6xxx_state_fops); ++ ++ debugfs_create_file("8021q_mode", S_IRUGO, chip->dbgfs, chip, ++ &mv88e6xxx_8021q_mode_fops); ++ ++ debugfs_create_file("vlan_table", S_IRUGO, chip->dbgfs, chip, ++ &mv88e6xxx_vlan_table_fops); ++ ++ debugfs_create_file("pvt", S_IRUGO | S_IWUSR, chip->dbgfs, chip, ++ &mv88e6xxx_pvt_fops); ++ ++ debugfs_create_file("vtu", S_IRUGO | S_IWUSR, chip->dbgfs, chip, ++ &mv88e6xxx_vtu_fops); ++#if 0 ++ debugfs_create_file("stats", S_IRUGO, chip->dbgfs, chip, ++ &mv88e6xxx_stats_fops); ++#endif ++ debugfs_create_file("device_map", S_IRUGO, chip->dbgfs, chip, ++ &mv88e6xxx_device_map_fops); ++ ++ debugfs_create_file("scratch", S_IRUGO, chip->dbgfs, chip, ++ &mv88e6xxx_scratch_fops); ++} ++ ++static void mv88e6xxx_remove_debugfs(struct mv88e6xxx_chip *chip) ++{ ++ debugfs_remove_recursive(chip->dbgfs); ++} +-- +cgit +From 88f0fb731db6e340495995aea0e6be5d7d220841 Mon Sep 17 00:00:00 2001 +From: Russell King +Date: Mon, 27 Jan 2020 14:00:12 +0000 +Subject: net: dsa: mv88e6xxx: debugfs hacks to fix the compile + +This is the problem with out-of-tree maintained patches; they break, +sometimes requiring substantial rework. It's all very well promising +to publish new versions as that happens, but it causes pain when they +aren't published in a timely manner. Hence this hack. + +Signed-off-by: Russell King +--- + drivers/net/dsa/mv88e6xxx/mv88e6xxx_debugfs.c | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +diff --git a/drivers/net/dsa/mv88e6xxx/mv88e6xxx_debugfs.c b/drivers/net/dsa/mv88e6xxx/mv88e6xxx_debugfs.c +index 931e769fe9ce..4005a4760884 100644 +--- a/drivers/net/dsa/mv88e6xxx/mv88e6xxx_debugfs.c ++++ b/drivers/net/dsa/mv88e6xxx/mv88e6xxx_debugfs.c +@@ -668,6 +668,7 @@ static const struct file_operations mv88e6xxx_vlan_table_fops = { + + static int mv88e6xxx_pvt_show(struct seq_file *s, void *p) + { ++#if 0 + struct mv88e6xxx_chip *chip = s->private; + struct dsa_switch_tree *dst = chip->ds->dst; + int port, src_dev, src_port; +@@ -716,8 +717,10 @@ static int mv88e6xxx_pvt_show(struct seq_file *s, void *p) + + unlock: + mutex_unlock(&chip->reg_lock); +- + return err; ++#else ++ return 0; ++#endif + } + + static ssize_t mv88e6xxx_pvt_write(struct file *file, const char __user *buf, +-- +cgit +FFrom e693b19d96a9c0a21dc767676594e99645a565ff Mon Sep 17 00:00:00 2001 +From: Russell King +Date: Thu, 28 Sep 2017 12:09:56 +0100 +Subject: Revert "net: dsa: mv88e6xxx: remove LED control register" + +This reverts commit c56a71a92114e3198e249593841cb744abaadcb7. +--- + drivers/net/dsa/mv88e6xxx/port.h | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/drivers/net/dsa/mv88e6xxx/port.h b/drivers/net/dsa/mv88e6xxx/port.h +index e0a705d82019..72e2edb6d779 100644 +--- a/drivers/net/dsa/mv88e6xxx/port.h ++++ b/drivers/net/dsa/mv88e6xxx/port.h +@@ -291,6 +291,9 @@ + /* Offset 0x13: OutFiltered Counter */ + #define MV88E6XXX_PORT_OUT_FILTERED 0x13 + ++/* Offset 0x16: LED Control */ ++#define MV88E6XXX_PORT_LED_CONTROL 0x16 ++ + /* Offset 0x18: IEEE Priority Mapping Table */ + #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE 0x18 + #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_UPDATE 0x8000 +-- +cgit +From da28daf741e3365c3b6b021427186b64aac5e5e3 Mon Sep 17 00:00:00 2001 +From: Russell King +Date: Sat, 7 Jan 2017 20:47:36 +0000 +Subject: net: dsa: program 6176 LED registers + +Signed-off-by: Russell King +--- + drivers/net/dsa/mv88e6xxx/chip.c | 20 ++++++++++++++++++++ + 1 file changed, 20 insertions(+) + +diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c +index 6fde0e0fec5e..fdd069891f06 100644 +--- a/drivers/net/dsa/mv88e6xxx/chip.c ++++ b/drivers/net/dsa/mv88e6xxx/chip.c +@@ -3276,6 +3276,20 @@ static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) + return 0; + } + ++static int mv88e6xxx_setup_led(struct mv88e6xxx_chip *chip, int port) ++{ ++ int err; ++ ++ /* LED0 = link/activity, LED1 = 10/100 */ ++ err = mv88e6xxx_wait_bit(chip, chip->info->port_base_addr + port, ++ MV88E6XXX_PORT_LED_CONTROL, 15, 0); ++ if (err) ++ return err; ++ ++ return mv88e6xxx_write(chip, chip->info->port_base_addr + port, ++ MV88E6XXX_PORT_LED_CONTROL, 0x80b3); ++} ++ + static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) + { + struct device_node *phy_handle = NULL; +@@ -3334,6 +3348,12 @@ static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) + if (err) + return err; + ++ if (chip->info->num_gpio) { ++ err = mv88e6xxx_setup_led(chip, port); ++ if (err) ++ return err; ++ } ++ + /* Port Control 2: don't force a good FCS, set the MTU size to + * 10222 bytes, disable 802.1q tags checking, don't discard + * tagged or untagged frames on this port, skip destination +-- +cgit +From 76e0fe4eb780fe291402c677d8c8d2c62736fcca Mon Sep 17 00:00:00 2001 +From: Russell King +Date: Wed, 8 Jul 2020 12:31:01 +0100 +Subject: net: dsa/mv88e6xxx: add support for rate-matching PHYs + +Add basic support for rate-matching 10G PHYs for mv88e6xxx - if we are +in RXAUI, XAUI or 10GBASE-R mode, the link speed is 10G, even if the +media is running at a slower speed. + +Signed-off-by: Russell King +--- + drivers/net/dsa/mv88e6xxx/chip.c | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c +index fdd069891f06..593959612334 100644 +--- a/drivers/net/dsa/mv88e6xxx/chip.c ++++ b/drivers/net/dsa/mv88e6xxx/chip.c +@@ -951,6 +951,18 @@ static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port, + if (err) + goto error; + ++ /* The link parameters passed in are the media side parameters. ++ * If in RXAUI, XAUI or 10GBASE-R with a rate matching PHY, we ++ * need to operate our link at 10G. Only full duplex is ++ * supported at this speed. ++ */ ++ if (interface == PHY_INTERFACE_MODE_RXAUI || ++ interface == PHY_INTERFACE_MODE_XAUI || ++ interface == PHY_INTERFACE_MODE_10GBASER) { ++ speed = SPEED_10000; ++ duplex = DUPLEX_FULL; ++ } ++ + if (ops->port_set_speed_duplex) { + err = ops->port_set_speed_duplex(chip, port, + speed, duplex); +-- +cgit diff --git a/patch/kernel/archive/mvebu-6.1/20-pcie-bridge-emul.patch b/patch/kernel/archive/mvebu-6.1/20-pcie-bridge-emul.patch new file mode 100644 index 0000000000..24e6f27d29 --- /dev/null +++ b/patch/kernel/archive/mvebu-6.1/20-pcie-bridge-emul.patch @@ -0,0 +1,55 @@ +From f1149effc7fd438ac5925a8e58ee2da294033ec5 Mon Sep 17 00:00:00 2001 +From: Russell King +Date: Tue, 2 Feb 2021 13:45:28 +0000 +Subject: PCI: pci-bridge-emul: re-arrange register tests + +Re-arrange the tests for which sets of registers are being accessed +so that it is easier to add further regions later. No functional +change. + +Signed-off-by: Russell King +--- + drivers/pci/pci-bridge-emul.c | 15 ++++++++++----- + 1 file changed, 10 insertions(+), 5 deletions(-) + +diff --git a/drivers/pci/pci-bridge-emul.c b/drivers/pci/pci-bridge-emul.c +index 9334b2dd4764..d746116104c6 100644 +--- a/drivers/pci/pci-bridge-emul.c ++++ b/drivers/pci/pci-bridge-emul.c +@@ -477,8 +477,11 @@ int pci_bridge_emul_conf_read(struct pci_bridge_emul *bridge, int where, + read_op = pci_bridge_emul_read_ssid; + cfgspace = NULL; + behavior = NULL; +- } else if (reg >= bridge->pcie_start && reg < bridge->pcie_start + PCI_CAP_PCIE_SIZEOF && +- bridge->has_pcie) { ++ } else if (!bridge->has_pcie) { ++ /* PCIe space is not implemented, and no PCI capabilities */ ++ *value = 0; ++ return PCIBIOS_SUCCESSFUL; ++ } else if (reg >= bridge->pcie_start && reg < bridge->pcie_start + PCI_CAP_PCIE_SIZEOF) { + /* Our emulated PCIe capability */ + reg -= bridge->pcie_start; + read_op = bridge->ops->read_pcie; +@@ -551,14 +554,16 @@ int pci_bridge_emul_conf_write(struct pci_bridge_emul *bridge, int where, + write_op = bridge->ops->write_base; + cfgspace = (__le32 *) &bridge->conf; + behavior = bridge->pci_regs_behavior; +- } else if (reg >= bridge->pcie_start && reg < bridge->pcie_start + PCI_CAP_PCIE_SIZEOF && +- bridge->has_pcie) { ++ } else if (!bridge->has_pcie) { ++ /* PCIe space is not implemented, and no PCI capabilities */ ++ return PCIBIOS_SUCCESSFUL; ++ } else if (reg >= bridge->pcie_start && reg < bridge->pcie_start + PCI_CAP_PCIE_SIZEOF) { + /* Our emulated PCIe capability */ + reg -= bridge->pcie_start; + write_op = bridge->ops->write_pcie; + cfgspace = (__le32 *) &bridge->pcie_conf; + behavior = bridge->pcie_cap_regs_behavior; +- } else if (reg >= PCI_CFG_SPACE_SIZE && bridge->has_pcie) { ++ } else if (reg >= PCI_CFG_SPACE_SIZE) { + /* PCIe extended capability space */ + reg -= PCI_CFG_SPACE_SIZE; + write_op = bridge->ops->write_ext; +-- +cgit + diff --git a/patch/kernel/archive/mvebu-6.1/412-ARM-dts-armada388-clearfog-emmc-on-clearfog-base.patch b/patch/kernel/archive/mvebu-6.1/412-ARM-dts-armada388-clearfog-emmc-on-clearfog-base.patch new file mode 100644 index 0000000000..dd2bef7f63 --- /dev/null +++ b/patch/kernel/archive/mvebu-6.1/412-ARM-dts-armada388-clearfog-emmc-on-clearfog-base.patch @@ -0,0 +1,87 @@ +From 8137da20701c776ad3481115305a5e8e410871ba Mon Sep 17 00:00:00 2001 +From: Russell King +Date: Tue, 29 Nov 2016 10:15:45 +0000 +Subject: ARM: dts: armada388-clearfog: emmc on clearfog base + +Signed-off-by: Russell King +--- + arch/arm/boot/dts/armada-388-clearfog-base.dts | 1 + + .../dts/armada-38x-solidrun-microsom-emmc.dtsi | 62 ++++++++++++++++++++++ + 2 files changed, 63 insertions(+) + create mode 100644 arch/arm/boot/dts/armada-38x-solidrun-microsom-emmc.dtsi + +--- a/arch/arm/boot/dts/armada-388-clearfog-base.dts ++++ b/arch/arm/boot/dts/armada-388-clearfog-base.dts +@@ -7,6 +7,7 @@ + + /dts-v1/; + #include "armada-388-clearfog.dtsi" ++#include "armada-38x-solidrun-microsom-emmc.dtsi" + + / { + model = "SolidRun Clearfog Base A1"; +--- /dev/null ++++ b/arch/arm/boot/dts/armada-38x-solidrun-microsom-emmc.dtsi +@@ -0,0 +1,62 @@ ++/* ++ * Device Tree file for SolidRun Armada 38x Microsom add-on for eMMC ++ * ++ * Copyright (C) 2015 Russell King ++ * ++ * This board is in development; the contents of this file work with ++ * the A1 rev 2.0 of the board, which does not represent final ++ * production board. Things will change, don't expect this file to ++ * remain compatible info the future. ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This file is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * version 2 as published by the Free Software Foundation. ++ * ++ * This file is distributed in the hope that it will be useful ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++/ { ++ soc { ++ internal-regs { ++ sdhci@d8000 { ++ bus-width = <4>; ++ no-1-8-v; ++ non-removable; ++ pinctrl-0 = <µsom_sdhci_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ wp-inverted; ++ }; ++ }; ++ }; ++}; diff --git a/patch/kernel/archive/mvebu-6.1/91-01-libata-add-ledtrig-support.patch.disable b/patch/kernel/archive/mvebu-6.1/91-01-libata-add-ledtrig-support.patch.disable new file mode 100644 index 0000000000..a52e712d8c --- /dev/null +++ b/patch/kernel/archive/mvebu-6.1/91-01-libata-add-ledtrig-support.patch.disable @@ -0,0 +1,149 @@ +From: Daniel Golle +Subject: libata: add ledtrig support + +This adds a LED trigger for each ATA port indicating disk activity. + +As this is needed only on specific platforms (NAS SoCs and such), +these platforms should define ARCH_WANTS_LIBATA_LEDS if there +are boards with LED(s) intended to indicate ATA disk activity and +need the OS to take care of that. +In that way, if not selected, LED trigger support not will be +included in libata-core and both, codepaths and structures remain +untouched. + +Signed-off-by: Daniel Golle +--- + drivers/ata/Kconfig | 16 ++++++++++++++++ + drivers/ata/libata-core.c | 41 +++++++++++++++++++++++++++++++++++++++++ + include/linux/libata.h | 9 +++++++++ + 3 files changed, 66 insertions(+) + +--- a/drivers/ata/Kconfig ++++ b/drivers/ata/Kconfig +@@ -67,6 +67,22 @@ config ATA_FORCE + + If unsure, say Y. + ++config ARCH_WANT_LIBATA_LEDS ++ bool ++ ++config ATA_LEDS ++ bool "support ATA port LED triggers" ++ depends on ARCH_WANT_LIBATA_LEDS ++ select NEW_LEDS ++ select LEDS_CLASS ++ select LEDS_TRIGGERS ++ default y ++ help ++ This option adds a LED trigger for each registered ATA port. ++ It is used to drive disk activity leds connected via GPIO. ++ ++ If unsure, say N. ++ + config ATA_ACPI + bool "ATA ACPI Support" + depends on ACPI +--- a/drivers/ata/libata-core.c ++++ b/drivers/ata/libata-core.c +@@ -650,6 +650,19 @@ u64 ata_tf_read_block(const struct ata_t + return block; + } + ++#ifdef CONFIG_ATA_LEDS ++#define LIBATA_BLINK_DELAY 20 /* ms */ ++static inline void ata_led_act(struct ata_port *ap) ++{ ++ unsigned long led_delay = LIBATA_BLINK_DELAY; ++ ++ if (unlikely(!ap->ledtrig)) ++ return; ++ ++ led_trigger_blink_oneshot(ap->ledtrig, &led_delay, &led_delay, 0); ++} ++#endif ++ + /** + * ata_build_rw_tf - Build ATA taskfile for given read/write request + * @tf: Target ATA taskfile +@@ -4513,6 +4526,9 @@ struct ata_queued_cmd *ata_qc_new_init(s + if (tag < 0) + return NULL; + } ++#ifdef CONFIG_ATA_LEDS ++ ata_led_act(ap); ++#endif + + qc = __ata_qc_from_tag(ap, tag); + qc->tag = qc->hw_tag = tag; +@@ -5291,6 +5307,9 @@ struct ata_port *ata_port_alloc(struct a + ap->stats.unhandled_irq = 1; + ap->stats.idle_irq = 1; + #endif ++#ifdef CONFIG_ATA_LEDS ++ ap->ledtrig = kzalloc(sizeof(struct led_trigger), GFP_KERNEL); ++#endif + ata_sff_port_init(ap); + + return ap; +@@ -5326,6 +5345,12 @@ static void ata_host_release(struct kref + + kfree(ap->pmp_link); + kfree(ap->slave_link); ++#ifdef CONFIG_ATA_LEDS ++ if (ap->ledtrig) { ++ led_trigger_unregister(ap->ledtrig); ++ kfree(ap->ledtrig); ++ }; ++#endif + kfree(ap); + host->ports[i] = NULL; + } +@@ -5732,7 +5757,23 @@ int ata_host_register(struct ata_host *h + host->ports[i]->print_id = atomic_inc_return(&ata_print_id); + host->ports[i]->local_port_no = i + 1; + } ++#ifdef CONFIG_ATA_LEDS ++ for (i = 0; i < host->n_ports; i++) { ++ if (unlikely(!host->ports[i]->ledtrig)) ++ continue; + ++ snprintf(host->ports[i]->ledtrig_name, ++ sizeof(host->ports[i]->ledtrig_name), "ata%u", ++ host->ports[i]->print_id); ++ ++ host->ports[i]->ledtrig->name = host->ports[i]->ledtrig_name; ++ ++ if (led_trigger_register(host->ports[i]->ledtrig)) { ++ kfree(host->ports[i]->ledtrig); ++ host->ports[i]->ledtrig = NULL; ++ } ++ } ++#endif + /* Create associated sysfs transport objects */ + for (i = 0; i < host->n_ports; i++) { + rc = ata_tport_add(host->dev,host->ports[i]); +--- a/include/linux/libata.h ++++ b/include/linux/libata.h +@@ -23,6 +23,9 @@ + #include + #include + #include ++#ifdef CONFIG_ATA_LEDS ++#include ++#endif + + /* + * Define if arch has non-standard setup. This is a _PCI_ standard +@@ -882,6 +885,12 @@ struct ata_port { + #ifdef CONFIG_ATA_ACPI + struct ata_acpi_gtm __acpi_init_gtm; /* use ata_acpi_init_gtm() */ + #endif ++ ++#ifdef CONFIG_ATA_LEDS ++ struct led_trigger *ledtrig; ++ char ledtrig_name[8]; ++#endif ++ + /* owned by EH */ + u8 sector_buf[ATA_SECT_SIZE] ____cacheline_aligned; + }; diff --git a/patch/kernel/archive/mvebu-6.1/91-02-Enable-ATA-port-LED-trigger.patch.disabled b/patch/kernel/archive/mvebu-6.1/91-02-Enable-ATA-port-LED-trigger.patch.disabled new file mode 100644 index 0000000000..10680f98cb --- /dev/null +++ b/patch/kernel/archive/mvebu-6.1/91-02-Enable-ATA-port-LED-trigger.patch.disabled @@ -0,0 +1,30 @@ +From 9ee6345ef82f7af5f98e17a40e667f8ad6b2fa1b Mon Sep 17 00:00:00 2001 +From: aprayoga +Date: Sun, 3 Sep 2017 18:10:12 +0800 +Subject: Enable ATA port LED trigger + +--- + arch/arm/configs/mvebu_v7_defconfig | 1 + + arch/arm/mach-mvebu/Kconfig | 1 + + 2 files changed, 2 insertions(+) + +--- a/arch/arm/configs/mvebu_v7_defconfig ++++ b/arch/arm/configs/mvebu_v7_defconfig +@@ -58,6 +58,7 @@ CONFIG_MTD_UBI=y + CONFIG_EEPROM_AT24=y + CONFIG_BLK_DEV_SD=y + CONFIG_ATA=y ++CONFIG_ATA_LEDS=y + CONFIG_SATA_AHCI=y + CONFIG_AHCI_MVEBU=y + CONFIG_SATA_MV=y +--- a/arch/arm/mach-mvebu/Kconfig ++++ b/arch/arm/mach-mvebu/Kconfig +@@ -56,6 +56,7 @@ config MACH_ARMADA_375 + config MACH_ARMADA_38X + bool "Marvell Armada 380/385 boards" + depends on ARCH_MULTI_V7 ++ select ARCH_WANT_LIBATA_LEDS + select ARM_ERRATA_720789 + select PL310_ERRATA_753970 + select ARM_GIC diff --git a/patch/kernel/archive/mvebu-6.1/92-mvebu-gpio-add_wake_on_gpio_support.patch b/patch/kernel/archive/mvebu-6.1/92-mvebu-gpio-add_wake_on_gpio_support.patch new file mode 100644 index 0000000000..9274f2b1a1 --- /dev/null +++ b/patch/kernel/archive/mvebu-6.1/92-mvebu-gpio-add_wake_on_gpio_support.patch @@ -0,0 +1,88 @@ +--- a/drivers/gpio/gpio-mvebu.c ++++ b/drivers/gpio/gpio-mvebu.c +@@ -40,6 +40,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -111,7 +112,7 @@ struct mvebu_gpio_chip { + struct regmap *regs; + u32 offset; + struct regmap *percpu_regs; +- int irqbase; ++ int bank_irq[4]; + struct irq_domain *domain; + int soc_variant; + +@@ -601,6 +602,33 @@ static void mvebu_gpio_irq_handler(struc + } + + /* ++ * Set interrupt number "irq" in the GPIO as a wake-up source. ++ * While system is running, all registered GPIO interrupts need to have ++ * wake-up enabled. When system is suspended, only selected GPIO interrupts ++ * need to have wake-up enabled. ++ * @param irq interrupt source number ++ * @param enable enable as wake-up if equal to non-zero ++ * @return This function returns 0 on success. ++ */ ++static int mvebu_gpio_set_wake_irq(struct irq_data *d, unsigned int enable) ++{ ++ struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); ++ struct mvebu_gpio_chip *mvchip = gc->private; ++ int irq; ++ int bank; ++ ++ bank = d->hwirq % 8; ++ irq = mvchip->bank_irq[bank]; ++ ++ if (enable) ++ enable_irq_wake(irq); ++ else ++ disable_irq_wake(irq); ++ ++ return 0; ++} ++ ++/* + * Functions implementing the pwm_chip methods + */ + static struct mvebu_pwm *to_mvebu_pwm(struct pwm_chip *chip) +@@ -1219,7 +1247,7 @@ static int mvebu_gpio_probe(struct platf + + err = irq_alloc_domain_generic_chips( + mvchip->domain, ngpios, 2, np->name, handle_level_irq, +- IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_LEVEL, 0, 0); ++ IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_LEVEL, 0, IRQ_GC_INIT_NESTED_LOCK); + if (err) { + dev_err(&pdev->dev, "couldn't allocate irq chips %s (DT).\n", + mvchip->chip.label); +@@ -1237,6 +1265,8 @@ static int mvebu_gpio_probe(struct platf + ct->chip.irq_mask = mvebu_gpio_level_irq_mask; + ct->chip.irq_unmask = mvebu_gpio_level_irq_unmask; + ct->chip.irq_set_type = mvebu_gpio_irq_set_type; ++ ct->chip.irq_set_wake = mvebu_gpio_set_wake_irq; ++ ct->chip.flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_MASK_ON_SUSPEND; + ct->chip.name = mvchip->chip.label; + + ct = &gc->chip_types[1]; +@@ -1245,6 +1275,8 @@ static int mvebu_gpio_probe(struct platf + ct->chip.irq_mask = mvebu_gpio_edge_irq_mask; + ct->chip.irq_unmask = mvebu_gpio_edge_irq_unmask; + ct->chip.irq_set_type = mvebu_gpio_irq_set_type; ++ ct->chip.irq_set_wake = mvebu_gpio_set_wake_irq; ++ ct->chip.flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_MASK_ON_SUSPEND; + ct->handler = handle_edge_irq; + ct->chip.name = mvchip->chip.label; + +@@ -1260,6 +1292,7 @@ static int mvebu_gpio_probe(struct platf + continue; + irq_set_chained_handler_and_data(irq, mvebu_gpio_irq_handler, + mvchip); ++ mvchip->bank_irq[i] = irq; + } + + return 0; diff --git a/patch/kernel/archive/mvebu-6.1/92-mvebu-gpio-remove-hardcoded-timer-assignment.patch b/patch/kernel/archive/mvebu-6.1/92-mvebu-gpio-remove-hardcoded-timer-assignment.patch new file mode 100644 index 0000000000..c8f586ca24 --- /dev/null +++ b/patch/kernel/archive/mvebu-6.1/92-mvebu-gpio-remove-hardcoded-timer-assignment.patch @@ -0,0 +1,417 @@ +From e4728fcf779c37d1bcbd4b6505c9b40d4bb9ff48 Mon Sep 17 00:00:00 2001 +From: Heisath +Date: Thu, 03 Jun 2021 10:56:53 +0200 +Subject: [PATCH] Removes the hardcoded timer assignment of timers to pwm controllers +This allows to use more than one pwm per gpio bank. + +Original patch by helios4 team, updated to work on LK5.11+ + +Signed-off-by: Heisath +--- + +diff --git a/drivers/gpio/gpio-mvebu.c b/drivers/gpio/gpio-mvebu.c +index bad399e3f..d3fdaf177 100644 +--- a/drivers/gpio/gpio-mvebu.c ++++ b/drivers/gpio/gpio-mvebu.c +@@ -97,21 +97,42 @@ + + #define MVEBU_MAX_GPIO_PER_BANK 32 + +-struct mvebu_pwm { ++enum mvebu_pwm_ctrl { ++ MVEBU_PWM_CTRL_SET_A = 0, ++ MVEBU_PWM_CTRL_SET_B, ++ MVEBU_PWM_CTRL_MAX ++}; ++ ++struct mvebu_pwmchip { + struct regmap *regs; + u32 offset; + unsigned long clk_rate; +- struct gpio_desc *gpiod; +- struct pwm_chip chip; + spinlock_t lock; +- struct mvebu_gpio_chip *mvchip; ++ bool in_use; + + /* Used to preserve GPIO/PWM registers across suspend/resume */ +- u32 blink_select; + u32 blink_on_duration; + u32 blink_off_duration; + }; + ++struct mvebu_pwm_chip_drv { ++ enum mvebu_pwm_ctrl ctrl; ++ struct gpio_desc *gpiod; ++ bool master; ++}; ++ ++struct mvebu_pwm { ++ struct pwm_chip chip; ++ struct mvebu_gpio_chip *mvchip; ++ struct mvebu_pwmchip controller; ++ enum mvebu_pwm_ctrl default_counter; ++ ++ /* Used to preserve GPIO/PWM registers across suspend/resume */ ++ u32 blink_select; ++}; ++ ++static struct mvebu_pwmchip *mvebu_pwm_list[MVEBU_PWM_CTRL_MAX]; ++ + struct mvebu_gpio_chip { + struct gpio_chip chip; + struct regmap *regs; +@@ -288,12 +309,12 @@ mvebu_gpio_write_level_mask(struct mvebu_gpio_chip *mvchip, u32 val) + * Functions returning offsets of individual registers for a given + * PWM controller. + */ +-static unsigned int mvebu_pwmreg_blink_on_duration(struct mvebu_pwm *mvpwm) ++static unsigned int mvebu_pwmreg_blink_on_duration(struct mvebu_pwmchip *mvpwm) + { + return mvpwm->offset + PWM_BLINK_ON_DURATION_OFF; + } + +-static unsigned int mvebu_pwmreg_blink_off_duration(struct mvebu_pwm *mvpwm) ++static unsigned int mvebu_pwmreg_blink_off_duration(struct mvebu_pwmchip *mvpwm) + { + return mvpwm->offset + PWM_BLINK_OFF_DURATION_OFF; + } +@@ -653,39 +674,84 @@ static int mvebu_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) + struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip); + struct mvebu_gpio_chip *mvchip = mvpwm->mvchip; + struct gpio_desc *desc; ++ enum mvebu_pwm_ctrl id; + unsigned long flags; + int ret = 0; ++ struct mvebu_pwm_chip_drv *chip_data; + +- spin_lock_irqsave(&mvpwm->lock, flags); ++ spin_lock_irqsave(&mvpwm->controller.lock, flags); + +- if (mvpwm->gpiod) { ++ if (pwm->chip_data || (mvchip->blink_en_reg & BIT(pwm->hwpwm))) { + ret = -EBUSY; +- } else { +- desc = gpiochip_request_own_desc(&mvchip->chip, +- pwm->hwpwm, "mvebu-pwm", +- GPIO_ACTIVE_HIGH, +- GPIOD_OUT_LOW); +- if (IS_ERR(desc)) { +- ret = PTR_ERR(desc); +- goto out; +- } ++ goto out; ++ } ++ ++ ++ ++ desc = gpiochip_request_own_desc(&mvchip->chip, ++ pwm->hwpwm, "mvebu-pwm", ++ GPIO_ACTIVE_HIGH, ++ GPIOD_OUT_LOW); ++ ++ if (IS_ERR(desc)) { ++ ret = PTR_ERR(desc); ++ goto out; ++ } ++ ++ ret = gpiod_direction_output(desc, 0); ++ if (ret) { ++ gpiochip_free_own_desc(desc); ++ goto out; ++ } + +- mvpwm->gpiod = desc; ++ chip_data = kzalloc(sizeof(struct mvebu_pwm_chip_drv), GFP_KERNEL); ++ if (!chip_data) { ++ gpiochip_free_own_desc(desc); ++ ret = -ENOMEM; ++ goto out; ++ } ++ ++ for (id = MVEBU_PWM_CTRL_SET_A; id < MVEBU_PWM_CTRL_MAX; id++) { ++ if (!mvebu_pwm_list[id]->in_use) { ++ chip_data->ctrl = id; ++ chip_data->master = true; ++ mvebu_pwm_list[id]->in_use = true; ++ break; ++ } + } ++ ++ if (!chip_data->master) ++ chip_data->ctrl = mvpwm->default_counter; ++ ++ regmap_update_bits(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, ++ BIT(pwm->hwpwm), chip_data->ctrl ? BIT(pwm->hwpwm) : 0); ++ ++ chip_data->gpiod = desc; ++ pwm->chip_data = chip_data; ++ ++ regmap_read(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, ++ &mvpwm->blink_select); ++ + out: +- spin_unlock_irqrestore(&mvpwm->lock, flags); ++ spin_unlock_irqrestore(&mvpwm->controller.lock, flags); + return ret; + } + + static void mvebu_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) + { + struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip); ++ struct mvebu_pwm_chip_drv *chip_data = (struct mvebu_pwm_chip_drv*) pwm->chip_data; + unsigned long flags; + +- spin_lock_irqsave(&mvpwm->lock, flags); +- gpiochip_free_own_desc(mvpwm->gpiod); +- mvpwm->gpiod = NULL; +- spin_unlock_irqrestore(&mvpwm->lock, flags); ++ spin_lock_irqsave(&mvpwm->controller.lock, flags); ++ if (chip_data->master) ++ mvebu_pwm_list[chip_data->ctrl]->in_use = false; ++ ++ ++ gpiochip_free_own_desc(chip_data->gpiod); ++ kfree(chip_data); ++ pwm->chip_data = NULL; ++ spin_unlock_irqrestore(&mvpwm->controller.lock, flags); + } + + static void mvebu_pwm_get_state(struct pwm_chip *chip, +@@ -693,29 +759,36 @@ static void mvebu_pwm_get_state(struct pwm_chip *chip, + struct pwm_state *state) { + + struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip); ++ struct mvebu_pwm_chip_drv *chip_data = (struct mvebu_pwm_chip_drv*) pwm->chip_data; ++ struct mvebu_pwmchip *controller; + struct mvebu_gpio_chip *mvchip = mvpwm->mvchip; + unsigned long long val; + unsigned long flags; + u32 u; + +- spin_lock_irqsave(&mvpwm->lock, flags); ++ if (chip_data) ++ controller = mvebu_pwm_list[chip_data->ctrl]; ++ else ++ controller = &mvpwm->controller; ++ ++ spin_lock_irqsave(&controller->lock, flags); + +- regmap_read(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm), &u); ++ regmap_read(controller->regs, mvebu_pwmreg_blink_on_duration(controller), &u); + /* Hardware treats zero as 2^32. See mvebu_pwm_apply(). */ + if (u > 0) + val = u; + else + val = UINT_MAX + 1ULL; + state->duty_cycle = DIV_ROUND_UP_ULL(val * NSEC_PER_SEC, +- mvpwm->clk_rate); ++ controller->clk_rate); + +- regmap_read(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm), &u); ++ regmap_read(controller->regs, mvebu_pwmreg_blink_off_duration(controller), &u); + /* period = on + off duration */ + if (u > 0) + val += u; + else + val += UINT_MAX + 1ULL; +- state->period = DIV_ROUND_UP_ULL(val * NSEC_PER_SEC, mvpwm->clk_rate); ++ state->period = DIV_ROUND_UP_ULL(val * NSEC_PER_SEC, controller->clk_rate); + + regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &u); + if (u) +@@ -796,13 +796,15 @@ static void mvebu_pwm_get_state(struct pwm_chip *chip, + else + state->enabled = false; + +- spin_unlock_irqrestore(&mvpwm->lock, flags); ++ spin_unlock_irqrestore(&controller->lock, flags); + } + + static int mvebu_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, + const struct pwm_state *state) + { + struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip); ++ struct mvebu_pwm_chip_drv *chip_data = (struct mvebu_pwm_chip_drv*) pwm->chip_data; ++ struct mvebu_pwmchip *controller; + struct mvebu_gpio_chip *mvchip = mvpwm->mvchip; + unsigned long long val; + unsigned long flags; +@@ -811,7 +813,12 @@ static int mvebu_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, + if (state->polarity != PWM_POLARITY_NORMAL) + return -EINVAL; + +- val = (unsigned long long) mvpwm->clk_rate * state->duty_cycle; ++ if (chip_data) ++ controller = mvebu_pwm_list[chip_data->ctrl]; ++ else ++ controller = &mvpwm->controller; ++ ++ val = (unsigned long long) controller->clk_rate * state->duty_cycle; + do_div(val, NSEC_PER_SEC); + if (val > UINT_MAX + 1ULL) + return -EINVAL; +@@ -750,7 +830,7 @@ static int mvebu_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, + else + on = 1; + +- val = (unsigned long long) mvpwm->clk_rate * state->period; ++ val = (unsigned long long) controller->clk_rate * state->period; + do_div(val, NSEC_PER_SEC); + val -= on; + if (val > UINT_MAX + 1ULL) +@@ -762,16 +842,16 @@ static int mvebu_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, + else + off = 1; + +- spin_lock_irqsave(&mvpwm->lock, flags); ++ spin_lock_irqsave(&controller->lock, flags); + +- regmap_write(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm), on); +- regmap_write(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm), off); ++ regmap_write(controller->regs, mvebu_pwmreg_blink_on_duration(controller), on); ++ regmap_write(controller->regs, mvebu_pwmreg_blink_off_duration(controller), off); + if (state->enabled) + mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 1); + else + mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 0); + +- spin_unlock_irqrestore(&mvpwm->lock, flags); ++ spin_unlock_irqrestore(&controller->lock, flags); + + return 0; + } +@@ -787,25 +867,27 @@ static const struct pwm_ops mvebu_pwm_ops = { + static void __maybe_unused mvebu_pwm_suspend(struct mvebu_gpio_chip *mvchip) + { + struct mvebu_pwm *mvpwm = mvchip->mvpwm; ++ struct mvebu_pwmchip *controller = &mvpwm->controller; + + regmap_read(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, + &mvpwm->blink_select); +- regmap_read(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm), +- &mvpwm->blink_on_duration); +- regmap_read(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm), +- &mvpwm->blink_off_duration); ++ regmap_read(controller->regs, mvebu_pwmreg_blink_on_duration(controller), ++ &controller->blink_on_duration); ++ regmap_read(controller->regs, mvebu_pwmreg_blink_off_duration(controller), ++ &controller->blink_off_duration); + } + + static void __maybe_unused mvebu_pwm_resume(struct mvebu_gpio_chip *mvchip) + { + struct mvebu_pwm *mvpwm = mvchip->mvpwm; ++ struct mvebu_pwmchip *controller = &mvpwm->controller; + + regmap_write(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, + mvpwm->blink_select); +- regmap_write(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm), +- mvpwm->blink_on_duration); +- regmap_write(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm), +- mvpwm->blink_off_duration); ++ regmap_write(controller->regs, mvebu_pwmreg_blink_on_duration(controller), ++ controller->blink_on_duration); ++ regmap_write(controller->regs, mvebu_pwmreg_blink_off_duration(controller), ++ controller->blink_off_duration); + } + + static int mvebu_pwm_probe(struct platform_device *pdev, +@@ -902,6 +902,7 @@ static int mvebu_pwm_probe(struct platform_device *pdev, + void __iomem *base; + u32 offset; + u32 set; ++ enum mvebu_pwm_ctrl ctrl_set; + + if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K) { + int ret = of_property_read_u32(dev->of_node, +@@ -844,54 +920,39 @@ static int mvebu_pwm_probe(struct platform_device *pdev, + mvpwm = devm_kzalloc(dev, sizeof(struct mvebu_pwm), GFP_KERNEL); + if (!mvpwm) + return -ENOMEM; ++ + mvchip->mvpwm = mvpwm; + mvpwm->mvchip = mvchip; +- mvpwm->offset = offset; ++ ++ ++ base = devm_platform_ioremap_resource_byname(pdev, "pwm"); ++ if (IS_ERR(base)) ++ return PTR_ERR(base); + +- if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K) { +- mvpwm->regs = mvchip->regs; ++ mvpwm->controller.regs = devm_regmap_init_mmio(&pdev->dev, base, ++ &mvebu_gpio_regmap_config); ++ if (IS_ERR(mvpwm->controller.regs)) ++ return PTR_ERR(mvpwm->controller.regs); + +- switch (mvchip->offset) { +- case AP80X_GPIO0_OFF_A8K: +- case CP11X_GPIO0_OFF_A8K: +- /* Blink counter A */ +- set = 0; +- break; +- case CP11X_GPIO1_OFF_A8K: +- /* Blink counter B */ +- set = U32_MAX; +- mvpwm->offset += PWM_BLINK_COUNTER_B_OFF; +- break; +- default: +- return -EINVAL; +- } ++ /* ++ * Use set A for lines of GPIO chip with id 0, B for GPIO chip ++ * with id 1. Don't allow further GPIO chips to be used for PWM. ++ */ ++ if (id == 0) { ++ set = 0; ++ ctrl_set = MVEBU_PWM_CTRL_SET_A; ++ } else if (id == 1) { ++ set = U32_MAX; ++ ctrl_set = MVEBU_PWM_CTRL_SET_B; + } else { +- base = devm_platform_ioremap_resource_byname(pdev, "pwm"); +- if (IS_ERR(base)) +- return PTR_ERR(base); +- +- mvpwm->regs = devm_regmap_init_mmio(&pdev->dev, base, +- &mvebu_gpio_regmap_config); +- if (IS_ERR(mvpwm->regs)) +- return PTR_ERR(mvpwm->regs); +- +- /* +- * Use set A for lines of GPIO chip with id 0, B for GPIO chip +- * with id 1. Don't allow further GPIO chips to be used for PWM. +- */ +- if (id == 0) +- set = 0; +- else if (id == 1) +- set = U32_MAX; +- else +- return -EINVAL; ++ return -EINVAL; + } + + regmap_write(mvchip->regs, + GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, set); + +- mvpwm->clk_rate = clk_get_rate(mvchip->clk); +- if (!mvpwm->clk_rate) { ++ mvpwm->controller.clk_rate = clk_get_rate(mvchip->clk); ++ if (!mvpwm->controller.clk_rate) { + dev_err(dev, "failed to get clock rate\n"); + return -EINVAL; + } +@@ -907,7 +968,10 @@ static int mvebu_pwm_probe(struct platform_device *pdev, + */ + mvpwm->chip.base = -1; + +- spin_lock_init(&mvpwm->lock); ++ spin_lock_init(&mvpwm->controller.lock); ++ ++ mvpwm->default_counter = ctrl_set; ++ mvebu_pwm_list[ctrl_set] = &mvpwm->controller; + + return pwmchip_add(&mvpwm->chip); + } diff --git a/patch/kernel/archive/mvebu-6.1/94-helios4-dts-add-wake-on-lan-support.patch b/patch/kernel/archive/mvebu-6.1/94-helios4-dts-add-wake-on-lan-support.patch new file mode 100644 index 0000000000..b3daf09f9a --- /dev/null +++ b/patch/kernel/archive/mvebu-6.1/94-helios4-dts-add-wake-on-lan-support.patch @@ -0,0 +1,21 @@ +--- a/arch/arm/boot/dts/armada-388-helios4.dts ++++ b/arch/arm/boot/dts/armada-388-helios4.dts +@@ -84,6 +84,18 @@ + }; + }; + ++ gpio-keys { ++ compatible = "gpio-keys"; ++ pinctrl-0 = <µsom_phy0_int_pins>; ++ ++ wol { ++ label = "Wake-On-LAN"; ++ linux,code = ; ++ gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; ++ wakeup-source; ++ }; ++ }; ++ + io-leds { + compatible = "gpio-leds"; + sata1-led { diff --git a/patch/kernel/archive/mvebu-6.1/compile-dtb-with-symbol-support.patch b/patch/kernel/archive/mvebu-6.1/compile-dtb-with-symbol-support.patch new file mode 100644 index 0000000000..a2bd279ae4 --- /dev/null +++ b/patch/kernel/archive/mvebu-6.1/compile-dtb-with-symbol-support.patch @@ -0,0 +1,12 @@ +--- a/scripts/Makefile.lib ++++ b/scripts/Makefile.lib +@@ -277,6 +277,9 @@ quiet_cmd_gzip = GZIP $@ + DTC ?= $(objtree)/scripts/dtc/dtc + DTC_FLAGS += -Wno-interrupt_provider + ++# Enable overlay support ++DTC_FLAGS += -@ ++ + # Disable noisy checks by default + ifeq ($(findstring 1,$(KBUILD_EXTRA_WARN)),) + DTC_FLAGS += -Wno-unit_address_vs_reg \ diff --git a/patch/kernel/archive/mvebu-6.1/dts-disable-spi-flash-on-a388-microsom.patch b/patch/kernel/archive/mvebu-6.1/dts-disable-spi-flash-on-a388-microsom.patch new file mode 100644 index 0000000000..b6597a72ff --- /dev/null +++ b/patch/kernel/archive/mvebu-6.1/dts-disable-spi-flash-on-a388-microsom.patch @@ -0,0 +1,10 @@ +--- a/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi ++++ b/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi +@@ -107,6 +107,7 @@ + compatible = "w25q32", "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <3000000>; ++ status = "disabled"; + }; + }; + diff --git a/patch/kernel/archive/mvebu-6.1/general-increasing_DMA_block_memory_allocation_to_2048.patch b/patch/kernel/archive/mvebu-6.1/general-increasing_DMA_block_memory_allocation_to_2048.patch new file mode 100644 index 0000000000..eef7296e75 --- /dev/null +++ b/patch/kernel/archive/mvebu-6.1/general-increasing_DMA_block_memory_allocation_to_2048.patch @@ -0,0 +1,11 @@ +--- a/arch/arm/mm/dma-mapping.c ++++ b/arch/arm/mm/dma-mapping.c +@@ -315,7 +315,7 @@ static void *__alloc_remap_buffer(struct + pgprot_t prot, struct page **ret_page, + const void *caller, bool want_vaddr); + +-#define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_256K ++#define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_2M + static struct gen_pool *atomic_pool __ro_after_init; + + static size_t atomic_pool_size __initdata = DEFAULT_DMA_COHERENT_POOL_SIZE; diff --git a/patch/kernel/archive/mvebu-6.1/unlock_atheros_regulatory_restrictions.patch b/patch/kernel/archive/mvebu-6.1/unlock_atheros_regulatory_restrictions.patch new file mode 100644 index 0000000000..7e57c379ad --- /dev/null +++ b/patch/kernel/archive/mvebu-6.1/unlock_atheros_regulatory_restrictions.patch @@ -0,0 +1,70 @@ +--- a/drivers/net/wireless/ath/regd.c ++++ b/drivers/net/wireless/ath/regd.c +@@ -50,12 +50,9 @@ static int __ath_regd_init(struct ath_re + #define ATH_5GHZ_5725_5850 REG_RULE(5725-10, 5850+10, 80, 0, 30,\ + NL80211_RRF_NO_IR) + +-#define ATH_2GHZ_ALL ATH_2GHZ_CH01_11, \ +- ATH_2GHZ_CH12_13, \ +- ATH_2GHZ_CH14 ++#define ATH_2GHZ_ALL REG_RULE(2400, 2483, 40, 0, 30, 0) + +-#define ATH_5GHZ_ALL ATH_5GHZ_5150_5350, \ +- ATH_5GHZ_5470_5850 ++#define ATH_5GHZ_ALL REG_RULE(5140, 5860, 40, 0, 30, 0) + + /* This one skips what we call "mid band" */ + #define ATH_5GHZ_NO_MIDBAND ATH_5GHZ_5150_5350, \ +@@ -77,9 +74,8 @@ static const struct ieee80211_regdomain + .n_reg_rules = 4, + .alpha2 = "99", + .reg_rules = { +- ATH_2GHZ_CH01_11, +- ATH_2GHZ_CH12_13, +- ATH_5GHZ_NO_MIDBAND, ++ ATH_2GHZ_ALL, ++ ATH_5GHZ_ALL, + } + }; + +@@ -88,8 +84,8 @@ static const struct ieee80211_regdomain + .n_reg_rules = 3, + .alpha2 = "99", + .reg_rules = { +- ATH_2GHZ_CH01_11, +- ATH_5GHZ_NO_MIDBAND, ++ ATH_2GHZ_ALL, ++ ATH_5GHZ_ALL, + } + }; + +@@ -98,7 +94,7 @@ static const struct ieee80211_regdomain + .n_reg_rules = 3, + .alpha2 = "99", + .reg_rules = { +- ATH_2GHZ_CH01_11, ++ ATH_2GHZ_ALL, + ATH_5GHZ_ALL, + } + }; +@@ -108,8 +104,7 @@ static const struct ieee80211_regdomain + .n_reg_rules = 4, + .alpha2 = "99", + .reg_rules = { +- ATH_2GHZ_CH01_11, +- ATH_2GHZ_CH12_13, ++ ATH_2GHZ_ALL, + ATH_5GHZ_ALL, + } + }; +@@ -258,9 +253,7 @@ static bool ath_is_radar_freq(u16 center + struct ath_regulatory *reg) + + { +- if (reg->country_code == CTRY_INDIA) +- return (center_freq >= 5500 && center_freq <= 5700); +- return (center_freq >= 5260 && center_freq <= 5700); ++ return false; + } + + static void ath_force_clear_no_ir_chan(struct wiphy *wiphy, diff --git a/patch/kernel/archive/mvebu-6.1/use-1000BaseX-clearfog-switch.patch b/patch/kernel/archive/mvebu-6.1/use-1000BaseX-clearfog-switch.patch new file mode 100644 index 0000000000..900d0f1142 --- /dev/null +++ b/patch/kernel/archive/mvebu-6.1/use-1000BaseX-clearfog-switch.patch @@ -0,0 +1,39 @@ +From 219f80b5cc03dab87fd05210b95c0b1a5afa8d33 Mon Sep 17 00:00:00 2001 +From: Russell King +Date: Thu, 14 Jul 2016 15:31:42 +0100 +Subject: ARM: dts: armada388-clearfog: use 1000BaseX mode for 88e6176 switch + +Use 1000BaseX mode for the 88e6176 switch, which allows mvneta to +negotiate correctly without needing to be forced. + +Signed-off-by: Russell King +--- + arch/arm/boot/dts/armada-388-clearfog.dts | 10 ++-------- + 1 file changed, 2 insertions(+), 8 deletions(-) + +--- a/arch/arm/boot/dts/armada-388-clearfog.dts ++++ b/arch/arm/boot/dts/armada-388-clearfog.dts +@@ -47,10 +47,8 @@ + + ð1 { + /* ethernet@30000 */ +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; ++ phy-mode = "1000base-x"; ++ managed = "in-band-status"; + }; + + &expander0 { +@@ -131,10 +129,6 @@ + reg = <5>; + label = "cpu"; + ethernet = <ð1>; +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; + }; + + port@6 { diff --git a/patch/kernel/mvebu-edge b/patch/kernel/mvebu-edge index adf2c3c23d..63b8e4b4b5 120000 --- a/patch/kernel/mvebu-edge +++ b/patch/kernel/mvebu-edge @@ -1 +1 @@ -archive/mvebu-5.16 \ No newline at end of file +archive/mvebu-6.1/ \ No newline at end of file