From a73e79a73f1b19bae3e66dd96fba1818b4b911b2 Mon Sep 17 00:00:00 2001 From: The-going <48602507+The-going@users.noreply.github.com> Date: Sat, 12 Apr 2025 14:10:11 +0300 Subject: [PATCH] u-boot: v2025-sunxi: switching to v2025.04 - Fix dram, mmc for h616. - The prefix is missing if we use OF_UPSTREAM - upstream: arm64: sun50i-h616: sync with sunxi-6.12 kernel - upstream: arm64: Add sun50i-h618-bananapi-m4-berry.dts --- config/boards/bananapim4berry.csc | 4 +- ...unxi-h616-dram-Rework-size-detection.patch | 76 ++ ...m-Improve-address-wrapping-detection.patch | 121 ++++ ...03-sunxi-mmc-Improve-reset-procedure.patch | 116 +++ ...Add-MACH_SUN8I_A83T-to-can-calibrate.patch | 26 + ...fix-is-missing-if-we-use-OF_UPSTREAM.patch | 28 + ...50i-h616-sync-with-sunxi-6.12-kernel.patch | 671 ++++++++++++++++++ ...d-sun50i-h618-bananapi-m4-berry.dts.patch} | 419 +++++------ ...50i-h618-bananapi-m4berry-defconfig.patch} | 32 +- ...50i-h616-add-emac1-node-pinctrl-pins.patch | 129 ---- ...boot-v2025-DEBUG-sunxi-mmc-fix-logik.patch | 72 -- .../0005-h616-THS-workaround.patch | 32 - ...0006-h616-GPU-enable.-Magic-register.patch | 25 - 13 files changed, 1247 insertions(+), 504 deletions(-) create mode 100644 patch/u-boot/v2025-sunxi/0001-sunxi-h616-dram-Rework-size-detection.patch create mode 100644 patch/u-boot/v2025-sunxi/0002-sunxi-H616-dram-Improve-address-wrapping-detection.patch create mode 100644 patch/u-boot/v2025-sunxi/0003-sunxi-mmc-Improve-reset-procedure.patch create mode 100644 patch/u-boot/v2025-sunxi/0004-Add-MACH_SUN8I_A83T-to-can-calibrate.patch create mode 100644 patch/u-boot/v2025-sunxi/0005-board-sunxi-The-prefix-is-missing-if-we-use-OF_UPSTREAM.patch create mode 100644 patch/u-boot/v2025-sunxi/0006-dts-upstream-arm64-sun50i-h616-sync-with-sunxi-6.12-kernel.patch rename patch/u-boot/{v2025.01/board_bananapim4berry/0003-dts-upstream-arm64-Add-sun50i-h618-bananapi-m4-berry.patch => v2025-sunxi/0007-dts-upstream-arm64-Add-sun50i-h618-bananapi-m4-berry.dts.patch} (67%) rename patch/u-boot/{v2025.01/board_bananapim4berry/0001-u-boot-configs-Add-sun50i-h618-bananapi-m4berry-defc.patch => v2025-sunxi/0008-u-boot-configs-Add-sun50i-h618-bananapi-m4berry-defconfig.patch} (59%) delete mode 100644 patch/u-boot/v2025.01/board_bananapim4berry/0002-dts-upstream-sun50i-h616-add-emac1-node-pinctrl-pins.patch delete mode 100644 patch/u-boot/v2025.01/board_bananapim4berry/0004-u-boot-v2025-DEBUG-sunxi-mmc-fix-logik.patch delete mode 100644 patch/u-boot/v2025.01/board_bananapim4berry/0005-h616-THS-workaround.patch delete mode 100644 patch/u-boot/v2025.01/board_bananapim4berry/0006-h616-GPU-enable.-Magic-register.patch diff --git a/config/boards/bananapim4berry.csc b/config/boards/bananapim4berry.csc index e483fe93fa..29cbf66733 100644 --- a/config/boards/bananapim4berry.csc +++ b/config/boards/bananapim4berry.csc @@ -4,8 +4,8 @@ BOARDFAMILY="sun50iw9-bpi" BOARD_MAINTAINER="The-going" BOOTCONFIG="bananapi_m4_berry_defconfig" -BOOTPATCHDIR="v2025.01/board_bananapim4berry" -BOOTBRANCH_BOARD="tag:v2025.01" +BOOTPATCHDIR="v2025-sunxi" +BOOTBRANCH_BOARD="tag:v2025.04" OVERLAY_PREFIX="sun50i-h616" BOOT_FDT_FILE="sun50i-h618-bananapi-m4-berry.dtb" diff --git a/patch/u-boot/v2025-sunxi/0001-sunxi-h616-dram-Rework-size-detection.patch b/patch/u-boot/v2025-sunxi/0001-sunxi-h616-dram-Rework-size-detection.patch new file mode 100644 index 0000000000..283ab4459c --- /dev/null +++ b/patch/u-boot/v2025-sunxi/0001-sunxi-h616-dram-Rework-size-detection.patch @@ -0,0 +1,76 @@ +From 3e51ab767091957ccfeb4ba778dd546234044a4b Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sun, 9 Mar 2025 07:31:42 +0100 +Subject: sunxi: h616: dram: Rework size detection + +Since there is quite a few possible DRAM configurations in terms of bus +width, rank and rows and columns count, size detection algorithm must be +very careful not to test combination which would be bigger than H616 is +actually capable of handling. + +Ideally, we should always detect memory aliasing, even for 4 GB memory +size, which is the maximum amount of memory that H616 is capable of +handling. For this reason, we have to configure minimum amount of +supported rows when testing for columns and vice versa. This way test +code will never step out of 4 GB boundary. + +While at it, check for 17 rows maximum. This aligns code with BSP DRAM +driver. There is probably no such configuration which would make sense +with 4 GB memory. + +Signed-off-by: Jernej Skrabec +--- + arch/arm/mach-sunxi/dram_sun50i_h616.c | 20 ++++++++++++-------- + 1 file changed, 12 insertions(+), 8 deletions(-) + +diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c +index b3554cc64bf5..6f84e59e39cd 100644 +--- a/arch/arm/mach-sunxi/dram_sun50i_h616.c ++++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c +@@ -1363,7 +1363,7 @@ static void mctl_auto_detect_rank_width(const struct dram_para *para, + static void mctl_auto_detect_dram_size(const struct dram_para *para, + struct dram_config *config) + { +- unsigned int shift; ++ unsigned int shift, cols, rows; + + /* max. config for columns, but not rows */ + config->cols = 11; +@@ -1373,23 +1373,27 @@ static void mctl_auto_detect_dram_size(const struct dram_para *para, + shift = config->bus_full_width + 1; + + /* detect column address bits */ +- for (config->cols = 8; config->cols < 11; config->cols++) { +- if (mctl_mem_matches(1ULL << (config->cols + shift))) ++ for (cols = 8; cols < 11; cols++) { ++ if (mctl_mem_matches(1ULL << (cols + shift))) + break; + } +- debug("detected %u columns\n", config->cols); ++ debug("detected %u columns\n", cols); + + /* reconfigure to make sure that all active rows are accessible */ +- config->rows = 18; ++ config->cols = 8; ++ config->rows = 17; + mctl_core_init(para, config); + + /* detect row address bits */ + shift = config->bus_full_width + 4 + config->cols; +- for (config->rows = 13; config->rows < 18; config->rows++) { +- if (mctl_mem_matches(1ULL << (config->rows + shift))) ++ for (rows = 13; rows < 17; rows++) { ++ if (mctl_mem_matches(1ULL << (rows + shift))) + break; + } +- debug("detected %u rows\n", config->rows); ++ debug("detected %u rows\n", rows); ++ ++ config->cols = cols; ++ config->rows = rows; + } + + static unsigned long mctl_calc_size(const struct dram_config *config) +-- +2.35.3 + diff --git a/patch/u-boot/v2025-sunxi/0002-sunxi-H616-dram-Improve-address-wrapping-detection.patch b/patch/u-boot/v2025-sunxi/0002-sunxi-H616-dram-Improve-address-wrapping-detection.patch new file mode 100644 index 0000000000..4746954292 --- /dev/null +++ b/patch/u-boot/v2025-sunxi/0002-sunxi-H616-dram-Improve-address-wrapping-detection.patch @@ -0,0 +1,121 @@ +From c13c238328e1e4909330b96fba51705eba917748 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sun, 9 Mar 2025 07:31:43 +0100 +Subject: sunxi: H616: dram: Improve address wrapping detection + +It turns out that checking just one write is not enough. Due to +unexplained reasons scan procedure detected double the size. +By making 16 dword writes and comparisons that never happens. + +New procedure is also inverted. Instead of writing two different values +to base address and some offset and then reading both and comparing +values, simplify this by writing pattern at the base address and then +search for this pattern at some offset. + +Signed-off-by: Jernej Skrabec +--- + arch/arm/mach-sunxi/dram_sun50i_h616.c | 58 +++++++++++++++++++++++++- + 1 file changed, 56 insertions(+), 2 deletions(-) + +diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c +index 6f84e59e39cd..cd9d321a0185 100644 +--- a/arch/arm/mach-sunxi/dram_sun50i_h616.c ++++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c +@@ -1360,38 +1360,92 @@ static void mctl_auto_detect_rank_width(const struct dram_para *para, + panic("This DRAM setup is currently not supported.\n"); + } + ++static void mctl_write_pattern(void) ++{ ++ unsigned int i; ++ u32 *ptr, val; ++ ++ ptr = (u32 *)CFG_SYS_SDRAM_BASE; ++ for (i = 0; i < 16; ptr++, i++) { ++ if (i & 1) ++ val = ~(ulong)ptr; ++ else ++ val = (ulong)ptr; ++ writel(val, ptr); ++ } ++} ++ ++static bool mctl_check_pattern(ulong offset) ++{ ++ unsigned int i; ++ u32 *ptr, val; ++ ++ ptr = (u32 *)CFG_SYS_SDRAM_BASE; ++ for (i = 0; i < 16; ptr++, i++) { ++ if (i & 1) ++ val = ~(ulong)ptr; ++ else ++ val = (ulong)ptr; ++ if (val != *(ptr + offset / 4)) ++ return false; ++ } ++ ++ return true; ++} ++ + static void mctl_auto_detect_dram_size(const struct dram_para *para, + struct dram_config *config) + { + unsigned int shift, cols, rows; ++ u32 buffer[16]; + + /* max. config for columns, but not rows */ + config->cols = 11; + config->rows = 13; + mctl_core_init(para, config); + ++ /* ++ * Store content so it can be restored later. This is important ++ * if controller was already initialized and holds any data ++ * which is important for restoring system. ++ */ ++ memcpy(buffer, (u32 *)CFG_SYS_SDRAM_BASE, sizeof(buffer)); ++ ++ mctl_write_pattern(); ++ + shift = config->bus_full_width + 1; + + /* detect column address bits */ + for (cols = 8; cols < 11; cols++) { +- if (mctl_mem_matches(1ULL << (cols + shift))) ++ if (mctl_check_pattern(1ULL << (cols + shift))) + break; + } + debug("detected %u columns\n", cols); + ++ /* restore data */ ++ memcpy((u32 *)CFG_SYS_SDRAM_BASE, buffer, sizeof(buffer)); ++ + /* reconfigure to make sure that all active rows are accessible */ + config->cols = 8; + config->rows = 17; + mctl_core_init(para, config); + ++ /* store data again as it might be moved */ ++ memcpy(buffer, (u32 *)CFG_SYS_SDRAM_BASE, sizeof(buffer)); ++ ++ mctl_write_pattern(); ++ + /* detect row address bits */ + shift = config->bus_full_width + 4 + config->cols; + for (rows = 13; rows < 17; rows++) { +- if (mctl_mem_matches(1ULL << (rows + shift))) ++ if (mctl_check_pattern(1ULL << (rows + shift))) + break; + } + debug("detected %u rows\n", rows); + ++ /* restore data again */ ++ memcpy((u32 *)CFG_SYS_SDRAM_BASE, buffer, sizeof(buffer)); ++ + config->cols = cols; + config->rows = rows; + } +-- +2.35.3 + diff --git a/patch/u-boot/v2025-sunxi/0003-sunxi-mmc-Improve-reset-procedure.patch b/patch/u-boot/v2025-sunxi/0003-sunxi-mmc-Improve-reset-procedure.patch new file mode 100644 index 0000000000..0d9e628dfc --- /dev/null +++ b/patch/u-boot/v2025-sunxi/0003-sunxi-mmc-Improve-reset-procedure.patch @@ -0,0 +1,116 @@ +From e4768f280b975f8f5523d188350eb77cc55aad63 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sun, 9 Mar 2025 07:12:41 +0100 +Subject: sunxi: mmc: Improve reset procedure + +Cards should always be reset and threshold set. This fixes eMMC on H616. + +Signed-off-by: Jernej Skrabec +--- + drivers/mmc/sunxi_mmc.c | 28 ++++++++++++++++++++++------ + drivers/mmc/sunxi_mmc.h | 15 +++++++++++++-- + 2 files changed, 35 insertions(+), 8 deletions(-) + +diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c +index 0b56d1405bee..335def4b9738 100644 +--- a/drivers/mmc/sunxi_mmc.c ++++ b/drivers/mmc/sunxi_mmc.c +@@ -442,6 +442,26 @@ out: + return error; + } + ++static void sunxi_mmc_reset(struct sunxi_mmc *regs) ++{ ++ /* Reset controller */ ++ writel(SUNXI_MMC_GCTRL_RESET, ®s->gctrl); ++ udelay(1000); ++ ++ if (IS_ENABLED(CONFIG_SUN50I_GEN_H6) || IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) { ++ /* Reset card */ ++ writel(SUNXI_MMC_HWRST_ASSERT, ®s->hwrst); ++ udelay(10); ++ writel(SUNXI_MMC_HWRST_DEASSERT, ®s->hwrst); ++ udelay(300); ++ ++ /* Setup FIFO R/W threshold. Needed on H616. */ ++ writel(SUNXI_MMC_THLDC_READ_THLD(512) | ++ SUNXI_MMC_THLDC_WRITE_EN | ++ SUNXI_MMC_THLDC_READ_EN, ®s->thldc); ++ } ++} ++ + /* non-DM code here is used by the (ARM) SPL only */ + + #if !CONFIG_IS_ENABLED(DM_MMC) +@@ -489,9 +509,7 @@ static int sunxi_mmc_core_init(struct mmc *mmc) + { + struct sunxi_mmc_priv *priv = mmc->priv; + +- /* Reset controller */ +- writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl); +- udelay(1000); ++ sunxi_mmc_reset(priv->reg); + + return 0; + } +@@ -684,9 +702,7 @@ static int sunxi_mmc_probe(struct udevice *dev) + + upriv->mmc = &plat->mmc; + +- /* Reset controller */ +- writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl); +- udelay(1000); ++ sunxi_mmc_reset(priv->reg); + + return 0; + } +diff --git a/drivers/mmc/sunxi_mmc.h b/drivers/mmc/sunxi_mmc.h +index f4ae5a790c87..9d55904c213c 100644 +--- a/drivers/mmc/sunxi_mmc.h ++++ b/drivers/mmc/sunxi_mmc.h +@@ -37,7 +37,9 @@ struct sunxi_mmc { + u32 res0; /* 0x54 reserved */ + u32 a12a; /* 0x58 Auto command 12 argument */ + u32 ntsr; /* 0x5c New timing set register */ +- u32 res1[8]; ++ u32 res1[6]; ++ u32 hwrst; /* 0x78 Hardware Reset */ ++ u32 res5; + u32 dmac; /* 0x80 internal DMA control */ + u32 dlba; /* 0x84 internal DMA descr list base address */ + u32 idst; /* 0x88 internal DMA status */ +@@ -46,7 +48,8 @@ struct sunxi_mmc { + u32 cbda; /* 0x94 */ + u32 res2[26]; + #if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6) || defined(CONFIG_SUNXI_GEN_NCAT2) +- u32 res3[17]; ++ u32 thldc; /* 0x100 Threshold control */ ++ u32 res3[16]; + u32 samp_dl; + u32 res4[46]; + #endif +@@ -123,6 +126,9 @@ struct sunxi_mmc { + + #define SUNXI_MMC_NTSR_MODE_SEL_NEW (0x1 << 31) + ++#define SUNXI_MMC_HWRST_ASSERT (0x0 << 0) ++#define SUNXI_MMC_HWRST_DEASSERT (0x1 << 0) ++ + #define SUNXI_MMC_IDMAC_RESET (0x1 << 0) + #define SUNXI_MMC_IDMAC_FIXBURST (0x1 << 1) + #define SUNXI_MMC_IDMAC_ENABLE (0x1 << 7) +@@ -133,6 +139,11 @@ struct sunxi_mmc { + #define SUNXI_MMC_COMMON_CLK_GATE (1 << 16) + #define SUNXI_MMC_COMMON_RESET (1 << 18) + ++#define SUNXI_MMC_THLDC_READ_EN (0x1 << 0) ++#define SUNXI_MMC_THLDC_BSY_CLR_INT_EN (0x1 << 1) ++#define SUNXI_MMC_THLDC_WRITE_EN (0x1 << 2) ++#define SUNXI_MMC_THLDC_READ_THLD(x) (((x) & 0xfff) << 16) ++ + #define SUNXI_MMC_CAL_DL_SW_EN (0x1 << 7) + + #endif /* _SUNXI_MMC_H */ +-- +2.35.3 + diff --git a/patch/u-boot/v2025-sunxi/0004-Add-MACH_SUN8I_A83T-to-can-calibrate.patch b/patch/u-boot/v2025-sunxi/0004-Add-MACH_SUN8I_A83T-to-can-calibrate.patch new file mode 100644 index 0000000000..c78685247d --- /dev/null +++ b/patch/u-boot/v2025-sunxi/0004-Add-MACH_SUN8I_A83T-to-can-calibrate.patch @@ -0,0 +1,26 @@ +From 202b992764421a6d96323c3abcdaa24e9082f53b Mon Sep 17 00:00:00 2001 +From: leo +Date: Sun, 15 Sep 2024 10:50:38 +0300 +Subject: Add MACH_SUN8I_A83T to can calibrate + +Add the A83T processor to the sunxi_mmc_can_calibrate +logic function for proper configuration. +--- + drivers/mmc/sunxi_mmc.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c +index 335def4b9738..7fea7982a5d4 100644 +--- a/drivers/mmc/sunxi_mmc.c ++++ b/drivers/mmc/sunxi_mmc.c +@@ -61,6 +61,7 @@ static bool sunxi_mmc_can_calibrate(void) + IS_ENABLED(CONFIG_MACH_SUN50I_H5) || + IS_ENABLED(CONFIG_SUN50I_GEN_H6) || + IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2) || ++ IS_ENABLED(CONFIG_MACH_SUN8I_A83T) || + IS_ENABLED(CONFIG_MACH_SUN8I_R40); + } + +-- +2.35.3 + diff --git a/patch/u-boot/v2025-sunxi/0005-board-sunxi-The-prefix-is-missing-if-we-use-OF_UPSTREAM.patch b/patch/u-boot/v2025-sunxi/0005-board-sunxi-The-prefix-is-missing-if-we-use-OF_UPSTREAM.patch new file mode 100644 index 0000000000..0a841f1eb3 --- /dev/null +++ b/patch/u-boot/v2025-sunxi/0005-board-sunxi-The-prefix-is-missing-if-we-use-OF_UPSTREAM.patch @@ -0,0 +1,28 @@ +From a34b6a50de81cc5cb1a82ea2196a198fb6719cb3 Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Tue, 1 Apr 2025 15:55:05 +0300 +Subject: board: sunxi: The prefix is missing if we use OF_UPSTREAM + +--- + board/sunxi/board.c | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/board/sunxi/board.c b/board/sunxi/board.c +index c7a2205ed610..2797cf5e00da 100644 +--- a/board/sunxi/board.c ++++ b/board/sunxi/board.c +@@ -826,7 +826,11 @@ int misc_init_r(void) + /* Set fdtfile to match the FIT configuration chosen in SPL. */ + spl_dt_name = get_spl_dt_name(); + if (spl_dt_name) { ++#ifdef CONFIG_OF_UPSTREAM ++ char *prefix = ""; ++#else + char *prefix = IS_ENABLED(CONFIG_ARM64) ? "allwinner/" : ""; ++#endif + char str[64]; + + snprintf(str, sizeof(str), "%s%s.dtb", prefix, spl_dt_name); +-- +2.35.3 + diff --git a/patch/u-boot/v2025-sunxi/0006-dts-upstream-arm64-sun50i-h616-sync-with-sunxi-6.12-kernel.patch b/patch/u-boot/v2025-sunxi/0006-dts-upstream-arm64-sun50i-h616-sync-with-sunxi-6.12-kernel.patch new file mode 100644 index 0000000000..59a26354e5 --- /dev/null +++ b/patch/u-boot/v2025-sunxi/0006-dts-upstream-arm64-sun50i-h616-sync-with-sunxi-6.12-kernel.patch @@ -0,0 +1,671 @@ +From 41657e210df86844b522e88cb1fba0239ea4bcd4 Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Wed, 2 Apr 2025 20:26:51 +0300 +Subject: dts: upstream: arm64: sun50i-h616: sync with sunxi-6.12 kernel + +--- + .../src/arm64/allwinner/sun50i-h616.dtsi | 516 +++++++++++++++++- + 1 file changed, 511 insertions(+), 5 deletions(-) + +diff --git a/dts/upstream/src/arm64/allwinner/sun50i-h616.dtsi b/dts/upstream/src/arm64/allwinner/sun50i-h616.dtsi +index cdce3dcb8ec0..3fb5c6e25af4 100644 +--- a/dts/upstream/src/arm64/allwinner/sun50i-h616.dtsi ++++ b/dts/upstream/src/arm64/allwinner/sun50i-h616.dtsi +@@ -7,8 +7,11 @@ + #include + #include + #include ++#include ++#include + #include + #include ++#include + #include + + / { +@@ -94,18 +97,24 @@ + }; + }; + ++ de: display-engine { ++ compatible = "allwinner,sun50i-h6-display-engine"; ++ allwinner,pipelines = <&mixer0>; ++ status = "disabled"; ++ }; ++ + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* +- * 256 KiB reserved for Trusted Firmware-A (BL31). ++ * 512 KiB reserved for Trusted Firmware-A (BL31). + * This is added by BL31 itself, but some bootloaders fail + * to propagate this into the DTB handed to kernels. + */ + secmon@40000000 { +- reg = <0x0 0x40000000 0x0 0x40000>; ++ reg = <0x0 0x40000000 0x0 0x80000>; + no-map; + }; + }; +@@ -150,6 +159,65 @@ + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x40000000>; + ++ bus@1000000 { ++ compatible = "allwinner,sun50i-h616-de33", ++ "allwinner,sun50i-a64-de2"; ++ reg = <0x1000000 0x400000>; ++ allwinner,sram = <&de3_sram 1>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0 0x1000000 0x400000>; ++ ++ display_clocks: clock@8000 { ++ compatible = "allwinner,sun50i-h616-de33-clk"; ++ reg = <0x8000 0x100>; ++ clocks = <&ccu CLK_DE>, <&ccu CLK_BUS_DE>; ++ clock-names = "mod", "bus"; ++ resets = <&ccu RST_BUS_DE>; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ }; ++ ++ mixer0: mixer@100000 { ++ compatible = "allwinner,sun50i-h616-de33-mixer-0"; ++ reg = <0x100000 0x100000>, ++ <0x8100 0x40>, ++ <0x280000 0x20000>; ++ clocks = <&display_clocks CLK_BUS_MIXER0>, ++ <&display_clocks CLK_MIXER0>; ++ clock-names = "bus", "mod"; ++ resets = <&display_clocks RST_MIXER0>; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ mixer0_out: port@1 { ++ reg = <1>; ++ ++ mixer0_out_tcon_top_mixer0: endpoint { ++ remote-endpoint = <&tcon_top_mixer0_in_mixer0>; ++ }; ++ }; ++ }; ++ }; ++ }; ++ ++ gpu: gpu@1800000 { ++ compatible = "allwinner,sun50i-h616-mali", ++ "arm,mali-bifrost"; ++ reg = <0x1800000 0x40000>; ++ interrupts = , ++ , ++ ; ++ interrupt-names = "job", "mmu", "gpu"; ++ clocks = <&ccu CLK_GPU0>, <&ccu CLK_BUS_GPU>; ++ clock-names = "core", "bus"; ++ power-domains = <&prcm_ppu 2>; ++ resets = <&ccu RST_BUS_GPU>; ++ status = "disabled"; ++ }; ++ + crypto: crypto@1904000 { + compatible = "allwinner,sun50i-h616-crypto"; + reg = <0x01904000 0x800>; +@@ -160,6 +228,17 @@ + resets = <&ccu RST_BUS_CE>; + }; + ++ video-codec@1c0e000 { ++ compatible = "allwinner,sun50i-h616-video-engine"; ++ reg = <0x01c0e000 0x2000>; ++ clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, ++ <&ccu CLK_MBUS_VE>; ++ clock-names = "ahb", "mod", "ram"; ++ resets = <&ccu RST_BUS_VE>; ++ interrupts = ; ++ allwinner,sram = <&ve_sram 1>; ++ }; ++ + syscon: syscon@3000000 { + compatible = "allwinner,sun50i-h616-system-control"; + reg = <0x03000000 0x1000>; +@@ -167,12 +246,44 @@ + #size-cells = <1>; + ranges; + ++ sram_a2: sram@100000 { ++ compatible = "mmio-sram"; ++ reg = <0x00100000 0x18000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0 0x00100000 0x18000>; ++ ++ scpi_sram: scpi-sram@17c00 { ++ compatible = "arm,scp-shmem"; ++ reg = <0x17c00 0x200>; ++ }; ++ }; ++ + sram_c: sram@28000 { + compatible = "mmio-sram"; + reg = <0x00028000 0x30000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00028000 0x30000>; ++ ++ de3_sram: sram-section@0 { ++ compatible = "allwinner,sun50i-h616-sram-c", ++ "allwinner,sun50i-a64-sram-c"; ++ reg = <0x0000 0x1e000>; ++ }; ++ }; ++ ++ sram_c1: sram@1a00000 { ++ compatible = "mmio-sram"; ++ reg = <0x01a00000 0x200000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0 0x01a00000 0x200000>; ++ ++ ve_sram: sram-section@0 { ++ compatible = "allwinner,sun50i-h616-sram-c1"; ++ reg = <0x000000 0x200000>; ++ }; + }; + }; + +@@ -248,16 +359,66 @@ + drive-strength = <40>; + }; + ++ rmii_pins: rmii-pins { ++ pins = "PA0", "PA1", "PA2", "PA3", "PA4", ++ "PA5", "PA6", "PA7", "PA8", "PA9"; ++ function = "emac1"; ++ drive-strength = <40>; ++ }; ++ + i2c0_pins: i2c0-pins { + pins = "PI5", "PI6"; + function = "i2c0"; + }; + ++ /omit-if-no-ref/ ++ i2c1_pi_pins: i2c1-pi-pins { ++ pins = "PI7", "PI8"; ++ function = "i2c1"; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c2_ph_pins: i2c2-ph-pins { ++ pins = "PH2", "PH3"; ++ function = "i2c2"; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c2_pi_pins: i2c2-pi-pins { ++ pins = "PI9", "PI10"; ++ function = "i2c2"; ++ }; ++ ++ i2c3_pa_pins: i2c3-pa-pins { ++ pins = "PA10", "PA11"; ++ function = "i2c3"; ++ bias-pull-up; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c3_pg_pins: i2c3-pg-pins { ++ pins = "PG17", "PG18"; ++ function = "i2c3"; ++ }; ++ ++ /omit-if-no-ref/ + i2c3_ph_pins: i2c3-ph-pins { + pins = "PH4", "PH5"; + function = "i2c3"; + }; + ++ /omit-if-no-ref/ ++ i2c4_pg_pins: i2c4-pg-pins { ++ pins = "PG15", "PG16"; ++ function = "i2c4"; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c4_ph_pins: i2c4-ph-pins { ++ pins = "PH6", "PH7"; ++ function = "i2c4"; ++ }; ++ + ir_rx_pin: ir-rx-pin { + pins = "PH10"; + function = "ir_rx"; +@@ -289,6 +450,48 @@ + bias-pull-up; + }; + ++ /omit-if-no-ref/ ++ pwm1_pg_pin: pwm1-pg-pin { ++ pins = "PG19"; ++ function = "pwm1"; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm1_ph_pin: pwm1-ph-pin { ++ pins = "PH3"; ++ function = "pwm1"; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm1_pi_pin: pwm1-pi-pin { ++ pins = "PI11"; ++ function = "pwm1"; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm2_ph_pin: pwm2-ph-pin { ++ pins = "PH2"; ++ function = "pwm2"; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm3_ph_pin: pwm3-ph-pin { ++ pins = "PH0"; ++ function = "pwm3"; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm4_ph_pin: pwm4-ph-pin { ++ pins = "PH1"; ++ function = "pwm4"; ++ }; ++ ++ pwm5_pin: pwm5-pin { ++ pins = "PA12"; ++ function = "pwm5"; ++ bias-pull-up; ++ }; ++ + /omit-if-no-ref/ + spi0_pins: spi0-pins { + pins = "PC0", "PC2", "PC4"; +@@ -313,6 +516,12 @@ + function = "spi1"; + }; + ++ /omit-if-no-ref/ ++ spi1_cs1_pin: spi1-cs1-pin { ++ pins = "PH9"; ++ function = "spi1"; ++ }; ++ + spdif_tx_pin: spdif-tx-pin { + pins = "PH4"; + function = "spdif"; +@@ -335,6 +544,60 @@ + function = "uart1"; + }; + ++ /omit-if-no-ref/ ++ uart2_pi_pins: uart2-pi-pins { ++ pins = "PI5", "PI6"; ++ function = "uart2"; ++ }; ++ ++ /omit-if-no-ref/ ++ uart2_pg_pins: uart2-pg-pins { ++ pins = "PG15", "PG16"; ++ function = "uart2"; ++ }; ++ ++ /omit-if-no-ref/ ++ uart2_pg_rts_cts_pins: uart2-pg-rts-cts-pins { ++ pins = "PG17", "PG18"; ++ function = "uart2"; ++ }; ++ ++ /omit-if-no-ref/ ++ uart2_ph_pins: uart2-ph-pins { ++ pins = "PH5", "PH6"; ++ function = "uart2"; ++ }; ++ ++ /omit-if-no-ref/ ++ uart2_ph_rts_cts_pins: uart2-ph-rts-cts-pins { ++ pins = "PH7", "PH8"; ++ function = "uart2"; ++ }; ++ ++ /omit-if-no-ref/ ++ uart3_pi_pins: uart3-pi-pins { ++ pins = "PI9", "PI10"; ++ function = "uart3"; ++ }; ++ ++ /omit-if-no-ref/ ++ uart4_pi_pins: uart4-pi-pins { ++ pins = "PI13", "PI14"; ++ function = "uart4"; ++ }; ++ ++ /omit-if-no-ref/ ++ uart4_pi_rts_cts_pins: uart4-pi-rts-cts-pins { ++ pins = "PI15", "PI16"; ++ function = "uart4"; ++ }; ++ ++ /omit-if-no-ref/ ++ uart5_pins: uart5-pins { ++ pins = "PH2", "PH3"; ++ function = "uart5"; ++ }; ++ + /omit-if-no-ref/ + x32clk_fanout_pin: x32clk-fanout-pin { + pins = "PG10"; +@@ -354,7 +617,8 @@ + }; + + iommu: iommu@30f0000 { +- compatible = "allwinner,sun50i-h616-iommu"; ++ compatible = "allwinner,sun50i-h616-iommu", ++ "allwinner,sun50i-h6-iommu"; + reg = <0x030f0000 0x10000>; + interrupts = ; + clocks = <&ccu CLK_BUS_IOMMU>; +@@ -630,6 +894,25 @@ + }; + }; + ++ emac1: ethernet@5030000 { ++ compatible = "allwinner,sun50i-h616-emac"; ++ syscon = <&syscon 1>; ++ reg = <0x05030000 0x10000>; ++ interrupts = ; ++ interrupt-names = "macirq"; ++ resets = <&ccu RST_BUS_EMAC1>; ++ reset-names = "stmmaceth"; ++ clocks = <&ccu CLK_BUS_EMAC1>; ++ clock-names = "stmmaceth"; ++ status = "disabled"; ++ ++ mdio1: mdio { ++ compatible = "snps,dwmac-mdio"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ }; ++ + gpadc: adc@5070000 { + compatible = "allwinner,sun50i-h616-gpadc", + "allwinner,sun20i-d1-gpadc"; +@@ -685,14 +968,71 @@ + reg = <0x05096000 0x31c>; + interrupts = ; + clocks = <&ccu CLK_BUS_AUDIO_CODEC>, +- <&ccu CLK_AUDIO_CODEC_1X>; +- clock-names = "apb", "codec"; ++ <&ccu CLK_AUDIO_CODEC_1X>, ++ <&ccu CLK_AUDIO_CODEC_4X>; ++ clock-names = "apb", "audio-codec-1x", "audio-codec-4x"; + resets = <&ccu RST_BUS_AUDIO_CODEC>; + dmas = <&dma 6>; + dma-names = "tx"; + status = "disabled"; + }; + ++ ahub_dam_plat:ahub_dam_plat@5097000 { ++ #sound-dai-cells = <0>; ++ /* sound card without pcm for hardware mix setting */ ++ compatible = "allwinner,sunxi-snd-plat-ahub_dam"; ++ reg = <0x05097000 0x1000>; ++ resets = <&ccu RST_BUS_AUDIO_HUB>; ++ clocks = <&ccu CLK_AUDIO_CODEC_1X>, ++ <&ccu CLK_AUDIO_CODEC_4X>, ++ <&ccu CLK_AUDIO_HUB>, ++ <&ccu CLK_BUS_AUDIO_HUB>; ++ clock-names = "clk_pll_audio", ++ "clk_pll_audio_4x", ++ "clk_audio_hub", ++ "clk_bus_audio_hub"; ++ status = "disabled"; ++ }; ++ ++ ahub1_plat:ahub1_plat { ++ #sound-dai-cells = <0>; ++ compatible = "allwinner,sunxi-snd-plat-ahub"; ++ apb_num = <1>; /* for dma port 4 */ ++ dmas = <&dma 4>, <&dma 4>; ++ dma-names = "tx", "rx"; ++ playback_cma = <128>; ++ capture_cma = <128>; ++ tx_fifo_size = <128>; ++ rx_fifo_size = <128>; ++ tdm_num = <1>; ++ tx_pin = <0>; ++ rx_pin = <0>; ++ status = "disabled"; ++ }; ++ ++ ahub1_mach:ahub1_mach { ++ compatible = "allwinner,sunxi-snd-mach"; ++ soundcard-mach,name = "HDMI"; ++ ++ soundcard-mach,format = "i2s"; ++ soundcard-mach,frame-master = <&ahub1_cpu>; ++ soundcard-mach,bitclock-master = <&ahub1_cpu>; ++ /* soundcard-mach,frame-inversion; */ ++ /* soundcard-mach,bitclock-inversion; */ ++ soundcard-mach,slot-num = <2>; ++ soundcard-mach,slot-width = <32>; ++ status = "disabled"; ++ ahub1_cpu: soundcard-mach,cpu { ++ sound-dai = <&ahub1_plat>; ++ soundcard-mach,pll-fs = <4>; ++ soundcard-mach,mclk-fs = <0>; ++ }; ++ ++ ahub1_codec: soundcard-mach,codec { ++ sound-dai = <&hdmi>; ++ }; ++ }; ++ + usbotg: usb@5100000 { + compatible = "allwinner,sun50i-h616-musb", + "allwinner,sun8i-h3-musb"; +@@ -853,6 +1193,147 @@ + status = "disabled"; + }; + ++ hdmi: hdmi@6000000 { ++ #sound-dai-cells = <0>; ++ compatible = "allwinner,sun50i-h616-dw-hdmi", ++ "allwinner,sun50i-h6-dw-hdmi"; ++ reg = <0x06000000 0x10000>; ++ reg-io-width = <1>; ++ interrupts = ; ++ clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>, ++ <&ccu CLK_HDMI>, <&ccu CLK_HDMI_CEC>, ++ <&ccu CLK_HDCP>, <&ccu CLK_BUS_HDCP>; ++ clock-names = "iahb", "isfr", "tmds", "cec", "hdcp", ++ "hdcp-bus"; ++ resets = <&ccu RST_BUS_HDMI>, <&ccu RST_BUS_HDCP>; ++ reset-names = "ctrl", "hdcp"; ++ phys = <&hdmi_phy>; ++ phy-names = "phy"; ++ status = "disabled"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ hdmi_in: port@0 { ++ reg = <0>; ++ ++ hdmi_in_tcon_top: endpoint { ++ remote-endpoint = <&tcon_top_hdmi_out_hdmi>; ++ }; ++ }; ++ ++ hdmi_out: port@1 { ++ reg = <1>; ++ }; ++ }; ++ }; ++ ++ hdmi_phy: hdmi-phy@6010000 { ++ compatible = "allwinner,sun50i-h616-hdmi-phy"; ++ reg = <0x06010000 0x10000>; ++ clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>; ++ clock-names = "bus", "mod"; ++ resets = <&ccu RST_BUS_HDMI_SUB>; ++ reset-names = "phy"; ++ #phy-cells = <0>; ++ }; ++ ++ tcon_top: tcon-top@6510000 { ++ compatible = "allwinner,sun50i-h6-tcon-top"; ++ reg = <0x06510000 0x1000>; ++ clocks = <&ccu CLK_BUS_TCON_TOP>, ++ <&ccu CLK_TCON_TV0>; ++ clock-names = "bus", ++ "tcon-tv0"; ++ clock-output-names = "tcon-top-tv0"; ++ resets = <&ccu RST_BUS_TCON_TOP>; ++ #clock-cells = <1>; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ tcon_top_mixer0_in: port@0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0>; ++ ++ tcon_top_mixer0_in_mixer0: endpoint@0 { ++ reg = <0>; ++ remote-endpoint = <&mixer0_out_tcon_top_mixer0>; ++ }; ++ }; ++ ++ tcon_top_mixer0_out: port@1 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <1>; ++ ++ tcon_top_mixer0_out_tcon_tv: endpoint@2 { ++ reg = <2>; ++ remote-endpoint = <&tcon_tv_in_tcon_top_mixer0>; ++ }; ++ }; ++ ++ tcon_top_hdmi_in: port@4 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <4>; ++ ++ tcon_top_hdmi_in_tcon_tv: endpoint@0 { ++ reg = <0>; ++ remote-endpoint = <&tcon_tv_out_tcon_top>; ++ }; ++ }; ++ ++ tcon_top_hdmi_out: port@5 { ++ reg = <5>; ++ ++ tcon_top_hdmi_out_hdmi: endpoint { ++ remote-endpoint = <&hdmi_in_tcon_top>; ++ }; ++ }; ++ }; ++ }; ++ ++ tcon_tv: lcd-controller@6515000 { ++ compatible = "allwinner,sun50i-h6-tcon-tv", ++ "allwinner,sun8i-r40-tcon-tv"; ++ reg = <0x06515000 0x1000>; ++ interrupts = ; ++ clocks = <&ccu CLK_BUS_TCON_TV0>, ++ <&tcon_top CLK_TCON_TOP_TV0>; ++ clock-names = "ahb", ++ "tcon-ch1"; ++ resets = <&ccu RST_BUS_TCON_TV0>; ++ reset-names = "lcd"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ tcon_tv_in: port@0 { ++ reg = <0>; ++ ++ tcon_tv_in_tcon_top_mixer0: endpoint { ++ remote-endpoint = <&tcon_top_mixer0_out_tcon_tv>; ++ }; ++ }; ++ ++ tcon_tv_out: port@1 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <1>; ++ ++ tcon_tv_out_tcon_top: endpoint@1 { ++ reg = <1>; ++ remote-endpoint = <&tcon_top_hdmi_in_tcon_tv>; ++ }; ++ }; ++ }; ++ }; ++ + rtc: rtc@7000000 { + compatible = "allwinner,sun50i-h616-rtc"; + reg = <0x07000000 0x400>; +@@ -874,6 +1355,12 @@ + #reset-cells = <1>; + }; + ++ prcm_ppu: power-controller@7010250 { ++ compatible = "allwinner,sun50i-h616-prcm-ppu"; ++ reg = <0x07010250 0x10>; ++ #power-domain-cells = <1>; ++ }; ++ + nmi_intc: interrupt-controller@7010320 { + compatible = "allwinner,sun50i-h616-nmi", + "allwinner,sun9i-a80-nmi"; +@@ -949,6 +1436,25 @@ + #address-cells = <1>; + #size-cells = <0>; + }; ++ ++ dump_reg: dump_reg@20000 { ++ compatible = "allwinner,sunxi-dump-reg"; ++ reg = <0x0 0x03001000 0x0 0x0f20>; ++ status = "okay"; ++ }; ++ ++ sunxi-info { ++ compatible = "allwinner,sun50i-h616-sys-info"; ++ status = "okay"; ++ }; ++ ++ addr_mgt: addr-mgt { ++ compatible = "allwinner,sunxi-addr_mgt"; ++ type_addr_wifi = <0x2>; ++ type_addr_bt = <0x2>; ++ type_addr_eth = <0x2>; ++ status = "okay"; ++ }; + }; + + thermal-zones { +-- +2.35.3 + diff --git a/patch/u-boot/v2025.01/board_bananapim4berry/0003-dts-upstream-arm64-Add-sun50i-h618-bananapi-m4-berry.patch b/patch/u-boot/v2025-sunxi/0007-dts-upstream-arm64-Add-sun50i-h618-bananapi-m4-berry.dts.patch similarity index 67% rename from patch/u-boot/v2025.01/board_bananapim4berry/0003-dts-upstream-arm64-Add-sun50i-h618-bananapi-m4-berry.patch rename to patch/u-boot/v2025-sunxi/0007-dts-upstream-arm64-Add-sun50i-h618-bananapi-m4-berry.dts.patch index ab439f5f3c..6d4a69ad0b 100644 --- a/patch/u-boot/v2025.01/board_bananapim4berry/0003-dts-upstream-arm64-Add-sun50i-h618-bananapi-m4-berry.patch +++ b/patch/u-boot/v2025-sunxi/0007-dts-upstream-arm64-Add-sun50i-h618-bananapi-m4-berry.dts.patch @@ -1,31 +1,121 @@ -From 505d989ac115c9efe43742fe3fba557c271e944b Mon Sep 17 00:00:00 2001 +From 07306aba1fd53935ae6df436d4f71313f49614ac Mon Sep 17 00:00:00 2001 From: The-going <48602507+The-going@users.noreply.github.com> -Date: Sat, 25 Jan 2025 19:30:16 +0300 -Subject: [PATCH 3/6] dts: upstream: arm64: Add - sun50i-h618-bananapi-m4-berry.dts +Date: Sun, 30 Mar 2025 18:12:38 +0300 +Subject: dts: upstream: arm64: Add sun50i-h618-bananapi-m4-berry.dts --- - .../sun50i-h618-bananapi-m4-berry.dts | 438 ++++++++++++++++++ - 1 file changed, 438 insertions(+) + dts/upstream/src/arm64/allwinner/axp313a.dtsi | 64 ++++ + .../src/arm64/allwinner/sun50i-h616.dtsi | 4 +- + .../sun50i-h618-bananapi-m4-berry.dts | 312 ++++++++++++++++++ + 3 files changed, 378 insertions(+), 2 deletions(-) + create mode 100644 dts/upstream/src/arm64/allwinner/axp313a.dtsi create mode 100644 dts/upstream/src/arm64/allwinner/sun50i-h618-bananapi-m4-berry.dts +diff --git a/dts/upstream/src/arm64/allwinner/axp313a.dtsi b/dts/upstream/src/arm64/allwinner/axp313a.dtsi +new file mode 100644 +index 000000000000..99057e975574 +--- /dev/null ++++ b/dts/upstream/src/arm64/allwinner/axp313a.dtsi +@@ -0,0 +1,64 @@ ++ ++&r_i2c { ++ status = "okay"; ++ ++ axp313a: pmic@36 { ++ compatible = "x-powers,axp313a"; ++ reg = <0x36>; ++ #interrupt-cells = <1>; ++ interrupt-controller; ++ interrupt-parent = <&pio>; ++ ++ vin1-supply = <®_vcc5v>; ++ vin2-supply = <®_vcc5v>; ++ vin3-supply = <®_vcc5v>; ++ ++ regulators { ++ reg_dcdc1: dcdc1 { ++ regulator-name = "vdd-gpu"; ++ regulator-min-microvolt = <810000>; ++ regulator-max-microvolt = <990000>; ++ regulator-step-delay-us = <25>; ++ regulator-final-delay-us = <50>; ++ regulator-always-on; ++ }; ++ ++ reg_dcdc2: dcdc2 { ++ regulator-name = "vdd-cpu"; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1200000>; ++ regulator-step-delay-us = <25>; ++ regulator-final-delay-us = <50>; ++ regulator-ramp-delay = <200>; ++ regulator-always-on; ++ }; ++ ++ reg_dcdc3: dcdc3 { ++ regulator-name = "vcc-dram"; ++ regulator-min-microvolt = <1100000>; ++ regulator-max-microvolt = <1100000>; ++ regulator-step-delay-us = <25>; ++ regulator-final-delay-us = <50>; ++ regulator-always-on; ++ }; ++ ++ reg_aldo1: aldo1 { ++ regulator-name = "vcc-1v8"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-step-delay-us = <25>; ++ regulator-final-delay-us = <50>; ++ regulator-always-on; ++ }; ++ ++ reg_dldo1: dldo1 { ++ regulator-name = "vcc-3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-step-delay-us = <25>; ++ regulator-final-delay-us = <50>; ++ regulator-always-on; ++ }; ++ }; ++ }; ++}; +diff --git a/dts/upstream/src/arm64/allwinner/sun50i-h616.dtsi b/dts/upstream/src/arm64/allwinner/sun50i-h616.dtsi +index 3fb5c6e25af4..0573e208c855 100644 +--- a/dts/upstream/src/arm64/allwinner/sun50i-h616.dtsi ++++ b/dts/upstream/src/arm64/allwinner/sun50i-h616.dtsi +@@ -353,8 +353,8 @@ + ext_rgmii_pins: rgmii-pins { + pins = "PI0", "PI1", "PI2", "PI3", "PI4", + "PI5", "PI7", "PI8", "PI9", "PI10", +- "PI11", "PI12", "PI13", "PI14", "PI15", +- "PI16"; ++ "PI11", "PI12", "PI13", "PI14", "PI15"; ++ /* "PI16" Managed by mdio */ + function = "emac0"; + drive-strength = <40>; + }; diff --git a/dts/upstream/src/arm64/allwinner/sun50i-h618-bananapi-m4-berry.dts b/dts/upstream/src/arm64/allwinner/sun50i-h618-bananapi-m4-berry.dts new file mode 100644 -index 00000000000..95280c81056 +index 000000000000..2d3d8589eff4 --- /dev/null +++ b/dts/upstream/src/arm64/allwinner/sun50i-h618-bananapi-m4-berry.dts -@@ -0,0 +1,438 @@ +@@ -0,0 +1,312 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* + * Copyright (C) 2020 Arm Ltd. ++ * Copyright 2025 Armbian community. + */ + +/dts-v1/; + +#include "sun50i-h616.dtsi" +#include "sun50i-h616-cpu-opp.dtsi" ++#include "axp313a.dtsi" + +#include ++#include +#include +#include + @@ -35,9 +125,7 @@ index 00000000000..95280c81056 + + aliases { + ethernet0 = &emac0; -+ ethernet1 = &emac1; + serial0 = &uart0; -+ serial5 = &uart5; + }; + + chosen { @@ -47,20 +135,24 @@ index 00000000000..95280c81056 + leds: leds { + compatible = "gpio-leds"; + -+ led-greed { ++ led-0 { + label = "red_led"; + gpios = <&pio 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */ + linux,default-trigger = "heartbeat"; + }; + }; + -+ wifi_usb { -+ compatible = "usb-wifi"; -+ status = "okay"; -+ power_on_pin = <&pio 2 2 GPIO_ACTIVE_HIGH>; /* PC2 */ ++ gpio-keys { ++ compatible = "gpio-keys"; ++ ++ key-sw3 { ++ label = "sw3"; ++ linux,code = ; ++ gpios = <&pio 2 7 GPIO_ACTIVE_LOW>; /* PC7 */ ++ }; + }; + -+ reg_vcc5v: reg-vcc5v { ++ reg_vcc5v: vcc5v { + /* board wide 5V supply directly from the USB-C socket */ + compatible = "regulator-fixed"; + regulator-name = "vcc-5v"; @@ -69,15 +161,36 @@ index 00000000000..95280c81056 + regulator-always-on; + }; + -+ reg_usb1_vbus: reg-usb1-vbus { ++ reg_usb_vbus: regulator-usb-vbus { + /* separate discrete regulator for the USB ports */ + compatible = "regulator-fixed"; ++ regulator-name = "usb-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_vcc5v>; + }; + -+ reg_gmac_3v3: reg-gmac-3v3 { ++ reg_vcc3v3: vcc3v3 { ++ /* SY8089 DC/DC converter */ ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc-3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <®_dldo1>; ++ regulator-always-on; ++ }; ++ ++ reg_vcc1v8: vcc1v8 { ++ /* Always on 1.8V/300mA regulator for WiFi and BT IO */ ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc-1v8"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ vin-supply = <®_aldo1>; ++ }; ++ ++ reg_gmac_3v3: gmac-3v3 { + compatible = "regulator-fixed"; + regulator-name = "gmac-3v3"; + regulator-min-microvolt = <3300000>; @@ -86,13 +199,11 @@ index 00000000000..95280c81056 + vin-supply = <®_vcc5v>; + }; + -+ ac200_pwm_clk: ac200_clk { -+ compatible = "pwm-clock"; -+ #clock-cells = <0>; -+ // pwm5 period_ns = 500 > 334 for select 24M clock. -+ pwms = <&pwm 5 500 0>; -+ clock-frequency = <2000000>; ++ wifi_usb { ++ compatible = "usb-wifi"; + status = "okay"; ++ reset-gpios = <&pio 2 2 GPIO_ACTIVE_HIGH>; /* PC2 */ ++ vin-supply = <®_vcc1v8>; + }; + + soc { @@ -104,7 +215,8 @@ index 00000000000..95280c81056 + resets = <&ccu RST_BUS_PWM>; + pwm-number = <6>; + pwm-base = <0x0>; -+ sunxi-pwms = <&pwm0>, <&pwm1>, <&pwm2>, <&pwm3>, <&pwm4>, <&pwm5>; ++ sunxi-pwms = <&pwm0>, <&pwm1>, <&pwm2>, ++ <&pwm3>, <&pwm4>, <&pwm5>; + #pwm-cells = <3>; + status = "okay"; + }; @@ -112,7 +224,6 @@ index 00000000000..95280c81056 + pwm0: pwm0@0300a000 { + compatible = "allwinner,sunxi-pwm0"; + pinctrl-names = "default"; -+ pinctrl-0 = <&pwm0_pd_pin>; + }; + + pwm1: pwm1@0300a000 { @@ -141,8 +252,6 @@ index 00000000000..95280c81056 + + pwm5: pwm5@0300a000 { + compatible = "allwinner,sunxi-pwm5"; -+ reg = <0x0 0x0300a015 0x0 0x4>; -+ reg_base = <0x0300a000>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm5_pin>; + clk_bypass_output = <0x1>; @@ -151,149 +260,14 @@ index 00000000000..95280c81056 + }; +}; + -+&pio { -+ vcc-pc-supply = <®_aldo1>; -+ vcc-pf-supply = <®_dldo1>; -+ vcc-pg-supply = <®_dldo1>; -+ vcc-ph-supply = <®_dldo1>; -+ vcc-pi-supply = <®_dldo1>; -+ -+ /omit-if-no-ref/ -+ pwm0_pd_pin: pwm0-pd-pin { -+ pins = "PD28"; -+ function = "pwm0"; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm1_pg_pin: pwm1-pg-pin { -+ pins = "PG19"; -+ function = "pwm1"; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm1_ph_pin: pwm1-ph-pin { -+ pins = "PH3"; -+ function = "pwm1"; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm2_ph_pin: pwm2-ph-pin { -+ pins = "PH2"; -+ function = "pwm2"; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm3_ph_pin: pwm3-ph-pin { -+ pins = "PH0"; -+ function = "pwm3"; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm4_ph_pin: pwm4-ph-pin { -+ pins = "PH1"; -+ function = "pwm4"; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm5_pin: pwm5-pin { -+ pins = "PA12"; -+ function = "pwm5"; -+ }; -+}; -+ -+&r_i2c { -+ pinctrl-0 = <&r_i2c_pins>; -+ pinctrl-names = "default"; ++&cpu0 { ++ cpu-supply = <®_dcdc2>; + status = "okay"; -+ -+ axp313a: pmic@36 { -+ compatible = "x-powers,axp313a"; -+ reg = <0x36>; -+ -+ vin1-supply = <®_vcc5v>; -+ vin2-supply = <®_vcc5v>; -+ vin3-supply = <®_vcc5v>; -+ -+ regulators{ -+ reg_dcdc1: dcdc1 { -+ regulator-name = "dcdc1-gpu"; -+ regulator-min-microvolt = <810000>; -+ regulator-max-microvolt = <990000>; -+ regulator-step-delay-us = <25>; -+ regulator-final-delay-us = <50>; -+ regulator-always-on; -+ }; -+ -+ reg_dcdc2: dcdc2 { -+ regulator-name = "dcdc2-cpu"; -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <1200000>; -+ regulator-step-delay-us = <25>; -+ regulator-final-delay-us = <50>; -+ regulator-ramp-delay = <200>; -+ regulator-always-on; -+ }; -+ -+ reg_dcdc3: dcdc3 { -+ regulator-name = "dcdc3-dram"; -+ regulator-min-microvolt = <1100000>; -+ regulator-max-microvolt = <1100000>; -+ regulator-step-delay-us = <25>; -+ regulator-final-delay-us = <50>; -+ regulator-always-on; -+ }; -+ -+ reg_aldo1: aldo1 { -+ regulator-name = "aldo1-1v8"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-step-delay-us = <25>; -+ regulator-final-delay-us = <50>; -+ regulator-always-on; -+ }; -+ -+ reg_dldo1: dldo1 { -+ regulator-name = "dldo1-3v3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-step-delay-us = <25>; -+ regulator-final-delay-us = <50>; -+ regulator-always-on; -+ }; -+ }; -+ }; +}; + -+&emac0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&ext_rgmii_pins>; -+ phy-mode = "rgmii"; -+ phy-handle = <&ext_rgmii_phy>; -+ allwinner,rx-delay-ps = <3100>; -+ allwinner,tx-delay-ps = <700>; -+ status = "disabled"; -+}; -+ -+&mdio0 { -+ ext_rgmii_phy: ethernet-phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <1>; -+ }; -+}; -+ -+&emac1 { -+ phy-mode = "rmii"; -+ phy-handle = <&rmii_phy>; -+ phy-supply = <®_dldo1>; -+ allwinner,rx-delay-ps = <3100>; -+ allwinner,tx-delay-ps = <700>; -+ status = "disabled"; -+}; -+ -+&mdio1 { -+ rmii_phy: ethernet-phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <1>; ++&sid { ++ ephy_calibration: ephy-calibration@2c { ++ reg = <0x2c 0x2>; + }; +}; + @@ -307,14 +281,59 @@ index 00000000000..95280c81056 + +&mmc2 { + pinctrl-names = "default"; -+ ++ pinctrl-0 = <&mmc2_pins>; + vmmc-supply = <®_dldo1>; + bus-width = <8>; ++ max-frequency = <150000000>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; + ++&pio { ++ vcc-pc-supply = <®_aldo1>; ++ vcc-pf-supply = <®_dldo1>; ++ vcc-pg-supply = <®_dldo1>; ++ vcc-ph-supply = <®_dldo1>; ++ vcc-pi-supply = <®_dldo1>; ++}; ++ ++&emac0 { ++ compatible = "allwinner,sun50i-h616-emac"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&ext_rgmii_pins>; ++ phy-mode = "rgmii"; ++ phy-handle = <&ext_rgmii_phy>; ++ phy-supply = <®_gmac_3v3>; ++ phy-io-supply = <®_dldo1>; ++ allwinner,rx-delay-ps = <3100>; ++ allwinner,tx-delay-ps = <700>; ++ use_ephy25m = <0x00>; ++ status = "okay"; ++}; ++ ++&mdio0 { ++ ext_rgmii_phy: ethernet-phy@1 { ++ /* rtl8211F compatible string for mdio and phy */ ++ compatible = "ethernet-phy-id001c.c916"; ++ reg = <1>; ++ reset-assert-us = <20000>; ++ reset-deassert-us = <100000>; ++ reset-gpios = <&pio 8 16 GPIO_ACTIVE_LOW>; /* PI16 */ ++ }; ++}; ++ ++&emac1 { ++ status = "disabled"; ++}; ++ ++&mdio1 { ++ rmii_phy: ethernet-phy@1 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <1>; ++ }; ++}; ++ +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ph_pins>; @@ -338,7 +357,7 @@ index 00000000000..95280c81056 +}; + +&usbphy { -+ usb1_vbus-supply = <®_vcc5v>; ++ usb1_vbus-supply = <®_usb_vbus>; + status = "okay"; +}; + @@ -374,10 +393,6 @@ index 00000000000..95280c81056 + status = "okay"; +}; + -+&ir { -+ status = "disabled"; -+}; -+ +&i2c1 { + status = "disabled"; +}; @@ -387,23 +402,7 @@ index 00000000000..95280c81056 +}; + +&i2c3 { -+ status = "okay"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c3_pa_pins>; -+ -+ ac200_x: mfd@10 { -+ compatible = "x-powers,ac200-sunxi"; -+ reg = <0x10>; -+ clocks = <&ac200_pwm_clk>; -+ // ephy id -+ nvmem-cells = <&ephy_calibration>; -+ nvmem-cell-names = "calibration"; -+ -+ ac200_ephy: phy { -+ compatible = "x-powers,ac200-ephy-sunxi"; -+ status = "okay"; -+ }; -+ }; ++ status = "disabled"; +}; + +&i2c4 { @@ -415,44 +414,6 @@ index 00000000000..95280c81056 + pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; + status = "disabled"; +}; -+ -+&uart2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart2_pins>; -+ status = "disabled"; -+}; -+ -+&uart5 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart5_pins>; -+ status = "okay"; -+}; -+ -+&spi1 { -+ status = "okay"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi1_pins>, <&spi1_cs1_pin>; -+ -+ spidev@1 { -+ compatible = "rohm,dh2228fv"; -+ status = "okay"; -+ reg = <1>; -+ spi-max-frequency = <1000000>; -+ }; -+}; -+ -+&cpu0 { -+ cpu-supply = <®_dcdc2>; -+ status = "okay"; -+}; -+ -+&sid { -+ ephy_calibration: ephy-calibration@2c { -+ reg = <0x2c 0x2>; -+ }; -+}; -- 2.35.3 diff --git a/patch/u-boot/v2025.01/board_bananapim4berry/0001-u-boot-configs-Add-sun50i-h618-bananapi-m4berry-defc.patch b/patch/u-boot/v2025-sunxi/0008-u-boot-configs-Add-sun50i-h618-bananapi-m4berry-defconfig.patch similarity index 59% rename from patch/u-boot/v2025.01/board_bananapim4berry/0001-u-boot-configs-Add-sun50i-h618-bananapi-m4berry-defc.patch rename to patch/u-boot/v2025-sunxi/0008-u-boot-configs-Add-sun50i-h618-bananapi-m4berry-defconfig.patch index fd95e52b15..37ba09ab22 100644 --- a/patch/u-boot/v2025.01/board_bananapim4berry/0001-u-boot-configs-Add-sun50i-h618-bananapi-m4berry-defc.patch +++ b/patch/u-boot/v2025-sunxi/0008-u-boot-configs-Add-sun50i-h618-bananapi-m4berry-defconfig.patch @@ -1,37 +1,38 @@ -From 1fbb4fc8a902b1ceb73e5848000b340715886d4d Mon Sep 17 00:00:00 2001 +From 33131f3e125f28b65fa9d0972030eda517983b54 Mon Sep 17 00:00:00 2001 From: The-going <48602507+The-going@users.noreply.github.com> Date: Tue, 21 Jan 2025 23:04:54 +0300 -Subject: [PATCH 1/6] u-boot: configs: Add sun50i-h618-bananapi-m4berry - defconfig +Subject: u-boot: configs: Add sun50i-h618-bananapi-m4berry defconfig --- - configs/bananapi_m4_berry_defconfig | 30 +++++++++++++++++++++++++++++ - 1 file changed, 30 insertions(+) + configs/bananapi_m4_berry_defconfig | 33 +++++++++++++++++++++++++++++ + 1 file changed, 33 insertions(+) create mode 100644 configs/bananapi_m4_berry_defconfig diff --git a/configs/bananapi_m4_berry_defconfig b/configs/bananapi_m4_berry_defconfig new file mode 100644 -index 00000000000..c5a97c739a0 +index 000000000000..94eb4bac7afb --- /dev/null +++ b/configs/bananapi_m4_berry_defconfig -@@ -0,0 +1,30 @@ +@@ -0,0 +1,33 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun50i-h618-bananapi-m4-berry" +CONFIG_OF_UPSTREAM=y +CONFIG_SPL=y -+CONFIG_DRAM_SUN50I_H616_DX_ODT=0x07070707 -+CONFIG_DRAM_SUN50I_H616_DX_DRI=0x0e0e0e0e -+CONFIG_DRAM_SUN50I_H616_CA_DRI=0x0e0e -+CONFIG_DRAM_SUN50I_H616_ODT_EN=0xaaaaeeee -+CONFIG_DRAM_SUN50I_H616_TPR6=0x48808080 -+CONFIG_DRAM_SUN50I_H616_TPR10=0x402f6663 -+CONFIG_DRAM_SUN50I_H616_TPR11=0x26262524 -+CONFIG_DRAM_SUN50I_H616_TPR12=0x100f100f ++CONFIG_DRAM_SUNXI_DX_ODT=0x07070707 ++CONFIG_DRAM_SUNXI_DX_DRI=0x0e0e0e0e ++CONFIG_DRAM_SUNXI_CA_DRI=0x0e0e ++CONFIG_DRAM_SUNXI_ODT_EN=0xaaaaeeee ++CONFIG_DRAM_SUNXI_TPR6=0x48808080 ++CONFIG_DRAM_SUNXI_TPR10=0x402f6663 ++CONFIG_DRAM_SUNXI_TPR11=0x26262524 ++CONFIG_DRAM_SUNXI_TPR12=0x100f100f +CONFIG_MACH_SUN50I_H616=y +CONFIG_SUNXI_DRAM_H616_LPDDR4=y +CONFIG_DRAM_CLK=792 +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 ++CONFIG_MMC_HS400_SUPPORT=y ++CONFIG_SPL_MMC_HS400_SUPPORT=y +CONFIG_R_I2C_ENABLE=y +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_I2C=y @@ -40,6 +41,7 @@ index 00000000000..c5a97c739a0 +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 +CONFIG_SUN8I_EMAC=y ++CONFIG_PHY_REALTEK=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_AXP313_POWER=y +CONFIG_USB_EHCI_HCD=y diff --git a/patch/u-boot/v2025.01/board_bananapim4berry/0002-dts-upstream-sun50i-h616-add-emac1-node-pinctrl-pins.patch b/patch/u-boot/v2025.01/board_bananapim4berry/0002-dts-upstream-sun50i-h616-add-emac1-node-pinctrl-pins.patch deleted file mode 100644 index ce36b0b431..0000000000 --- a/patch/u-boot/v2025.01/board_bananapim4berry/0002-dts-upstream-sun50i-h616-add-emac1-node-pinctrl-pins.patch +++ /dev/null @@ -1,129 +0,0 @@ -From 573dcff4016af4570a577d7e72c54538d911ab30 Mon Sep 17 00:00:00 2001 -From: The-going <48602507+The-going@users.noreply.github.com> -Date: Sun, 16 Feb 2025 16:01:17 +0300 -Subject: [PATCH 2/6] dts: upstream: sun50i-h616: add emac1 node, pinctrl pins - ---- - .../src/arm64/allwinner/sun50i-h616.dtsi | 69 ++++++++++++++++++- - 1 file changed, 67 insertions(+), 2 deletions(-) - -diff --git a/dts/upstream/src/arm64/allwinner/sun50i-h616.dtsi b/dts/upstream/src/arm64/allwinner/sun50i-h616.dtsi -index e88c1fbac6a..278ffdf2264 100644 ---- a/dts/upstream/src/arm64/allwinner/sun50i-h616.dtsi -+++ b/dts/upstream/src/arm64/allwinner/sun50i-h616.dtsi -@@ -100,12 +100,12 @@ - ranges; - - /* -- * 256 KiB reserved for Trusted Firmware-A (BL31). -+ * 512 KiB reserved for Trusted Firmware-A (BL31). - * This is added by BL31 itself, but some bootloaders fail - * to propagate this into the DTB handed to kernels. - */ - secmon@40000000 { -- reg = <0x0 0x40000000 0x0 0x40000>; -+ reg = <0x0 0x40000000 0x0 0x80000>; - no-map; - }; - }; -@@ -248,11 +248,23 @@ - drive-strength = <40>; - }; - -+ rmii_pins: rmii-pins { -+ pins = "PA0", "PA1", "PA2", "PA3", "PA4", -+ "PA5", "PA6", "PA7", "PA8", "PA9"; -+ function = "emac1"; -+ drive-strength = <40>; -+ }; -+ - i2c0_pins: i2c0-pins { - pins = "PI5", "PI6"; - function = "i2c0"; - }; - -+ i2c3_pa_pins: i2c3-pa-pins { -+ pins = "PA10", "PA11"; -+ function = "i2c3"; -+ }; -+ - i2c3_ph_pins: i2c3-ph-pins { - pins = "PH4", "PH5"; - function = "i2c3"; -@@ -313,6 +325,12 @@ - function = "spi1"; - }; - -+ /omit-if-no-ref/ -+ spi1_cs1_pin: spi1-cs1-pin { -+ pins = "PH9"; -+ function = "spi1"; -+ }; -+ - spdif_tx_pin: spdif-tx-pin { - pins = "PH4"; - function = "spdif"; -@@ -335,6 +353,24 @@ - function = "uart1"; - }; - -+ /omit-if-no-ref/ -+ uart2_pins: uart2-pins { -+ pins = "PH5", "PH6"; -+ function = "uart2"; -+ }; -+ -+ /omit-if-no-ref/ -+ uart2_rts_cts_pins: uart2-rts-cts-pins { -+ pins = "PH7", "PH8"; -+ function = "uart2"; -+ }; -+ -+ /omit-if-no-ref/ -+ uart5_pins: uart5-pins { -+ pins = "PH2", "PH3"; -+ function = "uart5"; -+ }; -+ - /omit-if-no-ref/ - x32clk_fanout_pin: x32clk-fanout-pin { - pins = "PG10"; -@@ -630,6 +666,35 @@ - }; - }; - -+ emac1: ethernet@5030000 { -+ compatible = "allwinner,sunxi-gmac"; -+ reg = <0x05030000 0x10000>, -+ <0x03000034 0x4>; -+ reg-names = "gmac1_reg","ephy_reg"; -+ interrupts = ; -+ interrupt-names = "gmacirq"; -+ resets = <&ccu RST_BUS_EMAC1>; -+ reset-names = "stmmaceth"; -+ clocks = <&ccu CLK_BUS_EMAC1>,<&ccu CLK_EMAC_25M>; -+ clock-names = "bus-emac1","emac-25m"; -+ pinctrl-0 = <&rmii_pins>; -+ pinctrl-names = "default"; -+ phy-mode = "rmii"; -+ tx-delay = <7>; -+ rx-delay = <31>; -+ phy-rst; -+ gmac-power0; -+ gmac-power1; -+ gmac-power2; -+ status = "disabled"; -+ -+ mdio1: mdio { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ }; -+ - spdif: spdif@5093000 { - compatible = "allwinner,sun50i-h616-spdif"; - reg = <0x05093000 0x400>; --- -2.35.3 - diff --git a/patch/u-boot/v2025.01/board_bananapim4berry/0004-u-boot-v2025-DEBUG-sunxi-mmc-fix-logik.patch b/patch/u-boot/v2025.01/board_bananapim4berry/0004-u-boot-v2025-DEBUG-sunxi-mmc-fix-logik.patch deleted file mode 100644 index 5fcdad4a4b..0000000000 --- a/patch/u-boot/v2025.01/board_bananapim4berry/0004-u-boot-v2025-DEBUG-sunxi-mmc-fix-logik.patch +++ /dev/null @@ -1,72 +0,0 @@ -From 783a11dad0e9c049e12efebbbd876703002ff992 Mon Sep 17 00:00:00 2001 -From: The-going <48602507+The-going@users.noreply.github.com> -Date: Fri, 21 Feb 2025 14:21:13 +0300 -Subject: [PATCH 4/6] u-boot: v2025: DEBUG sunxi mmc fix logik - ---- - drivers/mmc/sunxi_mmc.c | 18 +++++++++++++----- - 1 file changed, 13 insertions(+), 5 deletions(-) - -diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c -index 0b56d1405be..78814ecd50b 100644 ---- a/drivers/mmc/sunxi_mmc.c -+++ b/drivers/mmc/sunxi_mmc.c -@@ -36,6 +36,8 @@ - #define CCM_MMC_CTRL_MODE_SEL_NEW 0 - #endif - -+#define DEBUG 1 -+ - struct sunxi_mmc_plat { - struct mmc_config cfg; - struct mmc mmc; -@@ -61,6 +63,7 @@ static bool sunxi_mmc_can_calibrate(void) - IS_ENABLED(CONFIG_MACH_SUN50I_H5) || - IS_ENABLED(CONFIG_SUN50I_GEN_H6) || - IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2) || -+ IS_ENABLED(CONFIG_MACH_SUN8I_A83T) || - IS_ENABLED(CONFIG_MACH_SUN8I_R40); - } - -@@ -639,20 +642,25 @@ static int sunxi_mmc_probe(struct udevice *dev) - struct mmc_config *cfg = &plat->cfg; - struct ofnode_phandle_args args; - u32 *ccu_reg; -- int ret; -+ int ret, bus_width; - - cfg->name = dev->name; -+ bus_width = dev_read_u32_default(dev, "bus-width", 1); - - cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; -+ cfg->host_caps = 0; -+ if (bus_width == 8) -+ cfg->host_caps |= MMC_MODE_8BIT; -+ if (bus_width >= 4) -+ cfg->host_caps |= MMC_MODE_4BIT; - cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS; - cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; - - cfg->f_min = 400000; - cfg->f_max = 52000000; - -- ret = mmc_of_parse(dev, cfg); -- if (ret) -- return ret; -+ if (bus_width == 8) -+ cfg->f_max = 52000000; - - priv->reg = dev_read_addr_ptr(dev); - -@@ -686,7 +694,7 @@ static int sunxi_mmc_probe(struct udevice *dev) - - /* Reset controller */ - writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl); -- udelay(1000); -+ udelay(2000); - - return 0; - } --- -2.35.3 - diff --git a/patch/u-boot/v2025.01/board_bananapim4berry/0005-h616-THS-workaround.patch b/patch/u-boot/v2025.01/board_bananapim4berry/0005-h616-THS-workaround.patch deleted file mode 100644 index 26326e908f..0000000000 --- a/patch/u-boot/v2025.01/board_bananapim4berry/0005-h616-THS-workaround.patch +++ /dev/null @@ -1,32 +0,0 @@ -From f6e223575f0f74e008e4688a58600eda615460e2 Mon Sep 17 00:00:00 2001 -From: The-going <48602507+The-going@users.noreply.github.com> -Date: Thu, 6 Feb 2025 14:00:06 +0300 -Subject: [PATCH 5/6] h616: THS workaround - ---- - board/sunxi/board.c | 9 +++++++++ - 1 file changed, 9 insertions(+) - -diff --git a/board/sunxi/board.c b/board/sunxi/board.c -index 824c322a0dc..981f406aeea 100644 ---- a/board/sunxi/board.c -+++ b/board/sunxi/board.c -@@ -227,6 +227,15 @@ int board_init(void) - - eth_init_board(); - -+#if CONFIG_MACH_SUN50I_H616 -+ /* -+ * The bit[16] of register reg[0x03000000] must be zero for the THS -+ * driver to work properly in the kernel. The BSP u-boot is putting -+ * the whole register to zero so we are doing the same. -+ */ -+ writel(0x0, SUNXI_SRAMC_BASE); -+#endif -+ - return 0; - } - --- -2.35.3 - diff --git a/patch/u-boot/v2025.01/board_bananapim4berry/0006-h616-GPU-enable.-Magic-register.patch b/patch/u-boot/v2025.01/board_bananapim4berry/0006-h616-GPU-enable.-Magic-register.patch deleted file mode 100644 index a4bb594e83..0000000000 --- a/patch/u-boot/v2025.01/board_bananapim4berry/0006-h616-GPU-enable.-Magic-register.patch +++ /dev/null @@ -1,25 +0,0 @@ -From d2a852603b364b90903dc0a9040d4b11f79b8fea Mon Sep 17 00:00:00 2001 -From: The-going <48602507+The-going@users.noreply.github.com> -Date: Thu, 6 Feb 2025 15:11:40 +0300 -Subject: [PATCH 6/6] h616: GPU enable. Magic register. - ---- - arch/arm/mach-sunxi/clock_sun50i_h6.c | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c -index b424a7893ea..9ed5852d547 100644 ---- a/arch/arm/mach-sunxi/clock_sun50i_h6.c -+++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c -@@ -15,6 +15,8 @@ void clock_init_safe(void) - /* this seems to enable PLLs on H616 */ - setbits_le32(&prcm->sys_pwroff_gating, 0x10); - setbits_le32(&prcm->res_cal_ctrl, 2); -+ /* enable GPU */ -+ writel(0, 0x7010254); - } - - if (IS_ENABLED(CONFIG_MACH_SUN50I_H616) || --- -2.35.3 -