From a3374fd9844d6902ddc6a97402984b374915d1f9 Mon Sep 17 00:00:00 2001 From: Rosen Penev Date: Fri, 8 Jan 2021 19:02:03 -0800 Subject: [PATCH] mvebu: split pci clearfot patch as done in original git This is how Russell King has it in his tree instead of one patch. Signed-off-by: Rosen Penev --- ...h => 10-mvebu-clearfog-pcie-updates.patch} | 92 +++++++------------ .../11-implement-slot-capabilities-SSPL.patch | 55 +++++++++++ 2 files changed, 89 insertions(+), 58 deletions(-) rename patch/kernel/mvebu-dev/{40-pci-add-irq-change-handler-sspl.patch => 10-mvebu-clearfog-pcie-updates.patch} (83%) create mode 100644 patch/kernel/mvebu-dev/11-implement-slot-capabilities-SSPL.patch diff --git a/patch/kernel/mvebu-dev/40-pci-add-irq-change-handler-sspl.patch b/patch/kernel/mvebu-dev/10-mvebu-clearfog-pcie-updates.patch similarity index 83% rename from patch/kernel/mvebu-dev/40-pci-add-irq-change-handler-sspl.patch rename to patch/kernel/mvebu-dev/10-mvebu-clearfog-pcie-updates.patch index dd87eade81..6ee38c55de 100644 --- a/patch/kernel/mvebu-dev/40-pci-add-irq-change-handler-sspl.patch +++ b/patch/kernel/mvebu-dev/10-mvebu-clearfog-pcie-updates.patch @@ -1,20 +1,20 @@ -From 9a0c072c8eadc20f8eedc78cf33daa70f8bd5b11 Mon Sep 17 00:00:00 2001 +From 527312a74d9d85ba9520c8cb2979004f6d23c4da Mon Sep 17 00:00:00 2001 From: Russell King Date: Tue, 29 Nov 2016 10:13:46 +0000 -Subject: mvebu/clearfog pcie updates +Subject: [PATCH] mvebu/clearfog pcie updates Signed-off-by: Russell King --- - drivers/pci/controller/pci-mvebu.c | 112 ++++++++++++++++++++++++++++++++++++- - drivers/pci/pci-bridge-emul.c | 83 ++++++++++++++++----------- - drivers/pci/pci-bridge-emul.h | 15 +++++ - drivers/pci/pcie/aspm.c | 2 + + drivers/pci/controller/pci-mvebu.c | 112 ++++++++++++++++++++++++++++- + drivers/pci/pci-bridge-emul.c | 83 ++++++++++++--------- + drivers/pci/pci-bridge-emul.h | 15 ++++ + drivers/pci/pcie/aspm.c | 6 ++ drivers/pci/pcie/portdrv_core.c | 2 + - 5 files changed, 180 insertions(+), 34 deletions(-) + 5 files changed, 184 insertions(+), 34 deletions(-) --- a/drivers/pci/controller/pci-mvebu.c +++ b/drivers/pci/controller/pci-mvebu.c -@@ -53,13 +53,26 @@ +@@ -52,7 +52,14 @@ PCIE_CONF_ADDR_EN) #define PCIE_CONF_DATA_OFF 0x18fc #define PCIE_MASK_OFF 0x1910 @@ -29,19 +29,7 @@ Signed-off-by: Russell King #define PCIE_CTRL_OFF 0x1a00 #define PCIE_CTRL_X1_MODE 0x0001 #define PCIE_STAT_OFF 0x1a04 - #define PCIE_STAT_BUS 0xff00 - #define PCIE_STAT_DEV 0x1f0000 - #define PCIE_STAT_LINK_DOWN BIT(0) -+#define PCIE_SSPL 0x1a0c -+#define PCIE_SSPL_MSGEN BIT(14) -+#define PCIE_SSPL_SPLS(x) (((x) & 3) << 8) -+#define PCIE_SSPL_SPLS_VAL(x) (((x) >> 8) & 3) -+#define PCIE_SSPL_SPLV(x) ((x) & 0xff) -+#define PCIE_SSPL_SPLV_VAL(x) ((x) & 0xff) - #define PCIE_RC_RTSTA 0x1a14 - #define PCIE_DEBUG_CTRL 0x1a60 - #define PCIE_DEBUG_SOFT_RESET BIT(20) -@@ -432,6 +445,54 @@ static void mvebu_pcie_handle_membase_ch +@@ -430,6 +437,54 @@ static void mvebu_pcie_handle_membase_ch &port->memwin); } @@ -96,22 +84,7 @@ Signed-off-by: Russell King static pci_bridge_emul_read_status_t mvebu_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge, int reg, u32 *value) -@@ -462,6 +523,14 @@ mvebu_pci_bridge_emul_pcie_conf_read(str - *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL); - break; - -+ case PCI_EXP_SLTCAP: -+ { -+ u32 tmp = mvebu_readl(port, PCIE_SSPL); -+ *value = PCIE_SSPL_SPLS_VAL(tmp) << 15 | -+ PCIE_SSPL_SPLV_VAL(tmp) << 7; -+ break; -+ } -+ - case PCI_EXP_SLTCTL: - *value = PCI_EXP_SLTSTA_PDS << 16; - break; -@@ -477,6 +546,30 @@ mvebu_pci_bridge_emul_pcie_conf_read(str +@@ -475,6 +530,30 @@ mvebu_pci_bridge_emul_pcie_conf_read(str return PCI_BRIDGE_EMUL_HANDLED; } @@ -142,7 +115,7 @@ Signed-off-by: Russell King static void mvebu_pci_bridge_emul_base_conf_write(struct pci_bridge_emul *bridge, int reg, u32 old, u32 new, u32 mask) -@@ -494,7 +587,8 @@ mvebu_pci_bridge_emul_base_conf_write(st +@@ -492,7 +571,8 @@ mvebu_pci_bridge_emul_base_conf_write(st mvebu_pcie_handle_iobase_change(port); if ((old ^ new) & PCI_COMMAND_MEMORY) mvebu_pcie_handle_membase_change(port); @@ -152,7 +125,7 @@ Signed-off-by: Russell King break; } -@@ -517,6 +611,11 @@ mvebu_pci_bridge_emul_base_conf_write(st +@@ -515,6 +595,11 @@ mvebu_pci_bridge_emul_base_conf_write(st mvebu_pcie_handle_iobase_change(port); break; @@ -164,7 +137,7 @@ Signed-off-by: Russell King case PCI_PRIMARY_BUS: mvebu_pcie_set_local_bus_nr(port, conf->secondary_bus); break; -@@ -534,6 +633,10 @@ mvebu_pci_bridge_emul_pcie_conf_write(st +@@ -532,6 +617,10 @@ mvebu_pci_bridge_emul_pcie_conf_write(st switch (reg) { case PCI_EXP_DEVCTL: @@ -175,19 +148,7 @@ Signed-off-by: Russell King /* * Armada370 data says these bits must always * be zero when in root complex mode. -@@ -556,9 +659,37 @@ mvebu_pci_bridge_emul_pcie_conf_write(st - mvebu_writel(port, new, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL); - break; - -+ case PCI_EXP_SLTCAP: -+ { -+ u32 sspl = PCIE_SSPL_SPLV((new & PCI_EXP_SLTCAP_SPLV) >> 7) | -+ PCIE_SSPL_SPLS((new & PCI_EXP_SLTCAP_SPLS) >> 15) | -+ PCIE_SSPL_MSGEN; -+ mvebu_writel(port, sspl, PCIE_SSPL); -+ break; -+ } -+ +@@ -557,6 +646,25 @@ mvebu_pci_bridge_emul_pcie_conf_write(st case PCI_EXP_RTSTA: mvebu_writel(port, new, PCIE_RC_RTSTA); break; @@ -213,7 +174,7 @@ Signed-off-by: Russell King } } -@@ -566,6 +697,8 @@ static struct pci_bridge_emul_ops mvebu_ +@@ -564,6 +672,8 @@ static struct pci_bridge_emul_ops mvebu_ .write_base = mvebu_pci_bridge_emul_base_conf_write, .read_pcie = mvebu_pci_bridge_emul_pcie_conf_read, .write_pcie = mvebu_pci_bridge_emul_pcie_conf_write, @@ -240,7 +201,7 @@ Signed-off-by: Russell King bridge->pci_regs_behavior = kmemdup(pci_regs_behavior, sizeof(pci_regs_behavior), GFP_KERNEL); -@@ -321,25 +323,26 @@ int pci_bridge_emul_conf_read(struct pci +@@ -323,25 +325,26 @@ int pci_bridge_emul_conf_read(struct pci __le32 *cfgspace; const struct pci_bridge_reg_behavior *behavior; @@ -279,7 +240,7 @@ Signed-off-by: Russell King } if (read_op) -@@ -347,15 +350,20 @@ int pci_bridge_emul_conf_read(struct pci +@@ -349,15 +352,20 @@ int pci_bridge_emul_conf_read(struct pci else ret = PCI_BRIDGE_EMUL_NOT_HANDLED; @@ -304,7 +265,7 @@ Signed-off-by: Russell King if (size == 1) *value = (*value >> (8 * (where & 3))) & 0xff; -@@ -382,12 +390,6 @@ int pci_bridge_emul_conf_write(struct pc +@@ -385,12 +393,6 @@ int pci_bridge_emul_conf_write(struct pc __le32 *cfgspace; const struct pci_bridge_reg_behavior *behavior; @@ -317,7 +278,7 @@ Signed-off-by: Russell King shift = (where & 0x3) * 8; if (size == 4) -@@ -403,27 +405,42 @@ int pci_bridge_emul_conf_write(struct pc +@@ -406,27 +408,42 @@ int pci_bridge_emul_conf_write(struct pc if (ret != PCIBIOS_SUCCESSFUL) return ret; @@ -402,6 +363,21 @@ Signed-off-by: Russell King }; struct pci_bridge_reg_behavior; +--- a/drivers/pci/pcie/aspm.c ++++ b/drivers/pci/pcie/aspm.c +@@ -578,6 +578,12 @@ static void pcie_aspm_cap_init(struct pc + pcie_capability_read_dword(child, PCI_EXP_LNKCAP, &child_lnkcap); + pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &parent_lnkctl); + pcie_capability_read_word(child, PCI_EXP_LNKCTL, &child_lnkctl); ++dev_info(&parent->dev, "up support %x enabled %x\n", ++ (parent_lnkcap & PCI_EXP_LNKCAP_ASPMS) >> 10, ++ !!(parent_lnkctl & PCI_EXP_LNKCTL_ASPMC)); ++dev_info(&parent->dev, "dn support %x enabled %x\n", ++ (child_lnkcap & PCI_EXP_LNKCAP_ASPMS) >> 10, ++ !!(child_lnkctl & PCI_EXP_LNKCTL_ASPMC)); + + /* + * Setup L0s state --- a/drivers/pci/pcie/portdrv_core.c +++ b/drivers/pci/pcie/portdrv_core.c @@ -325,6 +325,7 @@ int pcie_port_device_register(struct pci diff --git a/patch/kernel/mvebu-dev/11-implement-slot-capabilities-SSPL.patch b/patch/kernel/mvebu-dev/11-implement-slot-capabilities-SSPL.patch new file mode 100644 index 0000000000..95282f307a --- /dev/null +++ b/patch/kernel/mvebu-dev/11-implement-slot-capabilities-SSPL.patch @@ -0,0 +1,55 @@ +From 2298f59cecc69b0fc6471c5fd3f7629af2d274b2 Mon Sep 17 00:00:00 2001 +From: Russell King +Date: Tue, 29 Nov 2016 10:13:48 +0000 +Subject: [PATCH] implement slot capabilities (SSPL) + +--- + drivers/pci/controller/pci-mvebu.c | 23 +++++++++++++++++++++++ + 1 file changed, 23 insertions(+) + +--- a/drivers/pci/controller/pci-mvebu.c ++++ b/drivers/pci/controller/pci-mvebu.c +@@ -66,6 +66,12 @@ + #define PCIE_STAT_BUS 0xff00 + #define PCIE_STAT_DEV 0x1f0000 + #define PCIE_STAT_LINK_DOWN BIT(0) ++#define PCIE_SSPL 0x1a0c ++#define PCIE_SSPL_MSGEN BIT(14) ++#define PCIE_SSPL_SPLS(x) (((x) & 3) << 8) ++#define PCIE_SSPL_SPLS_VAL(x) (((x) >> 8) & 3) ++#define PCIE_SSPL_SPLV(x) ((x) & 0xff) ++#define PCIE_SSPL_SPLV_VAL(x) ((x) & 0xff) + #define PCIE_RC_RTSTA 0x1a14 + #define PCIE_DEBUG_CTRL 0x1a60 + #define PCIE_DEBUG_SOFT_RESET BIT(20) +@@ -515,6 +521,14 @@ mvebu_pci_bridge_emul_pcie_conf_read(str + *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL); + break; + ++ case PCI_EXP_SLTCAP: ++ { ++ u32 tmp = mvebu_readl(port, PCIE_SSPL); ++ *value = PCIE_SSPL_SPLS_VAL(tmp) << 15 | ++ PCIE_SSPL_SPLV_VAL(tmp) << 7; ++ break; ++ } ++ + case PCI_EXP_SLTCTL: + *value = PCI_EXP_SLTSTA_PDS << 16; + break; +@@ -643,6 +657,15 @@ mvebu_pci_bridge_emul_pcie_conf_write(st + mvebu_writel(port, new, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL); + break; + ++ case PCI_EXP_SLTCAP: ++ { ++ u32 sspl = PCIE_SSPL_SPLV((new & PCI_EXP_SLTCAP_SPLV) >> 7) | ++ PCIE_SSPL_SPLS((new & PCI_EXP_SLTCAP_SPLS) >> 15) | ++ PCIE_SSPL_MSGEN; ++ mvebu_writel(port, sspl, PCIE_SSPL); ++ break; ++ } ++ + case PCI_EXP_RTSTA: + mvebu_writel(port, new, PCIE_RC_RTSTA); + break;