From a0bb089a801a3b7097a282a763c4e0583d205532 Mon Sep 17 00:00:00 2001 From: zador-blood-stained Date: Sat, 28 Jan 2017 15:37:08 +0300 Subject: [PATCH] Update H3 HDMI driver in u-boot --- .../h3-add-disp2-video-driver-jernej.patch | 1037 ++++++++++------- 1 file changed, 594 insertions(+), 443 deletions(-) diff --git a/patch/u-boot/u-boot-sunxi/h3-add-disp2-video-driver-jernej.patch b/patch/u-boot/u-boot-sunxi/h3-add-disp2-video-driver-jernej.patch index ad6a660219..09add1b94e 100644 --- a/patch/u-boot/u-boot-sunxi/h3-add-disp2-video-driver-jernej.patch +++ b/patch/u-boot/u-boot-sunxi/h3-add-disp2-video-driver-jernej.patch @@ -1,20 +1,25 @@ -commit 6b19f528f7650c659806f0b100e155337d3b37b3 -Author: Jernej Skrabec -Date: Tue Nov 8 01:04:32 2016 +0100 +From fc86af03e9ac503d78f837686901c4da10c95e9e Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Fri, 9 Dec 2016 19:07:34 +0100 +Subject: [PATCH] sunxi: Add clocks for DE2/HDMI/TCON - sunxi: video: Add video driver for H3 SoC - - Signed-off-by: Jernej Skrabec +This is needed for HDMI support, which will be added later. + +Signed-off-by: Jernej Skrabec +--- + arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 43 +++++++++++++++++++++++++++ + arch/arm/mach-sunxi/clock_sun6i.c | 28 +++++++++++++++++ + 2 files changed, 71 insertions(+) diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h -index be9fcfd..02d4a8c 100644 +index be9fcfd..c19c200 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -67,12 +67,20 @@ struct sunxi_ccm_reg { u32 dram_pll_cfg; /* 0xf8 PLL_DDR cfg register, A33 only */ u32 mbus_reset; /* 0xfc MBUS reset control, A33 only */ u32 dram_clk_gate; /* 0x100 DRAM module gating */ -+#ifdef CONFIG_SUNXI_DE2 ++#ifdef CONFIG_MACH_SUN8I_H3 + u32 de_clk_cfg; /* 0x104 DE module clock */ +#else u32 be0_clk_cfg; /* 0x104 BE0 module clock */ @@ -23,7 +28,7 @@ index be9fcfd..02d4a8c 100644 u32 fe0_clk_cfg; /* 0x10c FE0 module clock */ u32 fe1_clk_cfg; /* 0x110 FE1 module clock */ u32 mp_clk_cfg; /* 0x114 MP module clock */ -+#ifdef CONFIG_SUNXI_DE2 ++#ifdef CONFIG_MACH_SUN8I_H3 + u32 tcon0_clk_cfg; /* 0x118 TCON0 module clock */ +#else u32 lcd0_ch0_clk_cfg; /* 0x118 LCD0 CH0 module clock */ @@ -35,7 +40,7 @@ index be9fcfd..02d4a8c 100644 u32 dmic_clk_cfg; /* 0x148 Digital Mic module clock*/ u32 reserved15; u32 hdmi_clk_cfg; /* 0x150 HDMI module clock */ -+#ifdef CONFIG_SUNXI_DE2 ++#ifdef CONFIG_MACH_SUN8I_H3 + u32 hdmi_slow_clk_cfg; /* 0x154 HDMI slow module clock */ +#else u32 ps_clk_cfg; /* 0x154 PS module clock */ @@ -113,27 +118,21 @@ index be9fcfd..02d4a8c 100644 /* ahb_reset2 offsets */ #define AHB_RESET_OFFSET_EPHY 2 -@@ -406,6 +440,7 @@ struct sunxi_ccm_reg { - - /* CCM bits common to all Display Engine (and IEP) clock ctrl regs */ - #define CCM_DE_CTRL_M(n) ((((n) - 1) & 0xf) << 0) -+#ifndef CONFIG_SUNXI_DE2 - #define CCM_DE_CTRL_PLL_MASK (0xf << 24) - #define CCM_DE_CTRL_PLL3 (0 << 24) - #define CCM_DE_CTRL_PLL7 (1 << 24) -@@ -413,6 +448,11 @@ struct sunxi_ccm_reg { - #define CCM_DE_CTRL_PLL8 (3 << 24) - #define CCM_DE_CTRL_PLL9 (4 << 24) +@@ -415,6 +449,13 @@ struct sunxi_ccm_reg { #define CCM_DE_CTRL_PLL10 (5 << 24) -+#else -+#define CCM_DE_CTRL_PLL_MASK (3 << 24) -+#define CCM_DE_CTRL_PLL6_2X (0 << 24) -+#define CCM_DE_CTRL_PLL10 (1 << 24) -+#endif #define CCM_DE_CTRL_GATE (1 << 31) ++/* CCM bits common to all Display Engine 2.0 clock ctrl regs */ ++#define CCM_DE2_CTRL_M(n) ((((n) - 1) & 0xf) << 0) ++#define CCM_DE2_CTRL_PLL_MASK (3 << 24) ++#define CCM_DE2_CTRL_PLL6_2X (0 << 24) ++#define CCM_DE2_CTRL_PLL10 (1 << 24) ++#define CCM_DE2_CTRL_GATE (1 << 31) ++ /* CCU security switch, H3 only */ -@@ -423,7 +463,9 @@ struct sunxi_ccm_reg { + #define CCM_SEC_SWITCH_MBUS_NONSEC (1 << 2) + #define CCM_SEC_SWITCH_BUS_NONSEC (1 << 1) +@@ -423,7 +464,9 @@ struct sunxi_ccm_reg { #ifndef __ASSEMBLY__ void clock_set_pll1(unsigned int hz); void clock_set_pll3(unsigned int hz); @@ -143,7 +142,84 @@ index be9fcfd..02d4a8c 100644 void clock_set_pll11(unsigned int clk, bool sigma_delta_enable); void clock_set_mipi_pll(unsigned int hz); unsigned int clock_get_pll3(void); +diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c +index ed8cd9b..b4ccb8d 100644 +--- a/arch/arm/mach-sunxi/clock_sun6i.c ++++ b/arch/arm/mach-sunxi/clock_sun6i.c +@@ -141,6 +141,17 @@ void clock_set_pll3(unsigned int clk) + &ccm->pll3_cfg); + } + ++void clock_set_pll3_factors(int m, int n) ++{ ++ struct sunxi_ccm_reg * const ccm = ++ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; ++ ++ /* PLL3 rate = 24000000 * n / m */ ++ writel(CCM_PLL3_CTRL_EN | CCM_PLL3_CTRL_INTEGER_MODE | ++ CCM_PLL3_CTRL_N(n) | CCM_PLL3_CTRL_M(m), ++ &ccm->pll3_cfg); ++} ++ + void clock_set_pll5(unsigned int clk, bool sigma_delta_enable) + { + struct sunxi_ccm_reg * const ccm = +@@ -213,6 +224,23 @@ void clock_set_mipi_pll(unsigned int clk) + } + #endif + ++void clock_set_pll10(unsigned int clk) ++{ ++ struct sunxi_ccm_reg * const ccm = ++ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; ++ const int m = 2; /* 12 MHz steps */ ++ ++ if (clk == 0) { ++ clrbits_le32(&ccm->pll10_cfg, CCM_PLL10_CTRL_EN); ++ return; ++ } ++ ++ /* PLL10 rate = 24000000 * n / m */ ++ writel(CCM_PLL10_CTRL_EN | CCM_PLL10_CTRL_INTEGER_MODE | ++ CCM_PLL10_CTRL_N(clk / (24000000 / m)) | CCM_PLL10_CTRL_M(m), ++ &ccm->pll10_cfg); ++} ++ + #ifdef CONFIG_MACH_SUN8I_A33 + void clock_set_pll11(unsigned int clk, bool sigma_delta_enable) + { +From b484223c2c40539bc6bd322c38dd8ced89e8b2cf Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Tue, 13 Dec 2016 00:19:01 +0100 +Subject: [PATCH] sunxi: video: Add video driver for H3 SoC + +This patch adds support for hdmi output. It is designed in the same +way as video driver for older Allwinner SoCs. + +First it checks if monitor is attached. If it is, recommended +timings are read from EDID. After that, DE2, TCON and HDMI are +configured according to this timings. + +32MB of RAM is used for framebuffer. This is just enough to support +4K resolution. + +SimpleFB is also supported by this driver. + +Signed-off-by: Jernej Skrabec +--- + arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 8 + + arch/arm/include/asm/arch-sunxi/display2.h | 377 ++++++++++ + board/sunxi/Kconfig | 4 +- + drivers/video/Makefile | 1 + + drivers/video/sunxi_display2.c | 1037 +++++++++++++++++++++++++++ + include/configs/sunxi-common.h | 17 +- + scripts/config_whitelist.txt | 1 + + 7 files changed, 1438 insertions(+), 7 deletions(-) + create mode 100644 arch/arm/include/asm/arch-sunxi/display2.h + create mode 100644 drivers/video/sunxi_display2.c + diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h +index 7232f6d..9df6212 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h @@ -18,6 +18,8 @@ @@ -159,7 +235,7 @@ diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/ #define SUNXI_USB1_BASE 0x01c14000 #endif #define SUNXI_SS_BASE 0x01c15000 -+#ifndef CONFIG_SUNXI_DE2 ++#ifndef CONFIG_MACH_SUN8I_H3 #define SUNXI_HDMI_BASE 0x01c16000 +#endif #define SUNXI_SPI2_BASE 0x01c17000 @@ -169,7 +245,7 @@ diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/ #define SUNXI_MP_BASE 0x01e80000 #define SUNXI_AVG_BASE 0x01ea0000 -+#ifdef CONFIG_SUNXI_DE2 ++#ifdef CONFIG_MACH_SUN8I_H3 +#define SUNXI_HDMI_BASE 0x01ee0000 +#endif + @@ -178,9 +254,10 @@ diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/ diff --git a/arch/arm/include/asm/arch-sunxi/display2.h b/arch/arm/include/asm/arch-sunxi/display2.h new file mode 100644 +index 0000000..b1d99d7 --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/display2.h -@@ -0,0 +1,282 @@ +@@ -0,0 +1,377 @@ +/* + * Sunxi platform display controller register and constant defines + * @@ -189,10 +266,10 @@ new file mode 100644 + * Based on Linux DRM driver defines: + * Copyright (C) 2016 Jean-Francois Moine + * Copyright (c) 2016 Allwinnertech Co., Ltd. -+ * ++ * + * Based on display.h: + * (C) Copyright 2014 Hans de Goede -+ * ++ * + * SPDX-License-Identifier: GPL-2.0+ + */ + @@ -254,7 +331,6 @@ new file mode 100644 +/* global control */ +struct de_glb { + u32 ctl; -+#define DE_MUX_GLB_CTL_rt_en BIT(0) + u32 status; + u32 dbuff; + u32 size; @@ -307,14 +383,6 @@ new file mode 100644 +struct de_ui { + struct { + u32 attr; -+#define UI_CFG_ATTR_en BIT(0) -+#define UI_CFG_ATTR_alpmod_SHIFT 1 -+#define UI_CFG_ATTR_alpmod_MASK GENMASK(2, 1) -+#define UI_CFG_ATTR_fcolor_en BIT(4) -+#define UI_CFG_ATTR_fmt_SHIFT 8 -+#define UI_CFG_ATTR_fmt_MASK GENMASK(12, 8) -+#define UI_CFG_ATTR_alpha_SHIFT 24 -+#define UI_CFG_ATTR_alpha_MASK GENMASK(31, 24) + u32 size; + u32 coord; + u32 pitch; @@ -328,89 +396,163 @@ new file mode 100644 + u32 ovl_size; /* 88 */ +}; + -+struct sunxi_phy_hdmi_reg { -+ u32 pol; -+ u32 dum0[3]; -+ u32 read_en; -+ u32 dum1[3]; -+ u32 ctrl; -+ u32 unk1; -+ u32 unk2; -+ u32 pll; -+ u32 clk; -+ u32 unk3; -+ u32 status; ++struct sunxi_dwc_hdmi { ++ u8 reserved0[0x100]; ++ u8 ih_fc_stat0; ++ u8 ih_fc_stat1; ++ u8 ih_fc_stat2; ++ u8 ih_as_stat0; ++ u8 ih_phy_stat0; ++ u8 ih_i2cm_stat0; ++ u8 ih_cec_stat0; ++ u8 ih_vp_stat0; ++ u8 ih_i2cmphy_stat0; ++ u8 ih_ahbdmaaud_stat0; ++ u8 reserved1[0x17f-0x109]; ++ u8 ih_mute_fc_stat0; ++ u8 ih_mute_fc_stat1; ++ u8 ih_mute_fc_stat2; ++ u8 ih_mute_as_stat0; ++ u8 ih_mute_phy_stat0; ++ u8 ih_mute_i2cm_stat0; ++ u8 ih_mute_cec_stat0; ++ u8 ih_mute_vp_stat0; ++ u8 ih_mute_i2cmphy_stat0; ++ u8 ih_mute_ahbdmaaud_stat0; ++ u8 reserved2[0x1fe - 0x189]; ++ u8 ih_mute; ++ u8 tx_invid0; ++ u8 tx_instuffing; ++ u8 tx_gydata0; ++ u8 tx_gydata1; ++ u8 tx_rcrdata0; ++ u8 tx_rcrdata1; ++ u8 tx_bcbdata0; ++ u8 tx_bcbdata1; ++ u8 reserved3[0x7ff-0x207]; ++ u8 vp_status; ++ u8 vp_pr_cd; ++ u8 vp_stuff; ++ u8 vp_remap; ++ u8 vp_conf; ++ u8 vp_stat; ++ u8 vp_int; ++ u8 vp_mask; ++ u8 vp_pol; ++ u8 reserved4[0xfff-0x808]; ++ u8 fc_invidconf; ++ u8 fc_inhactv0; ++ u8 fc_inhactv1; ++ u8 fc_inhblank0; ++ u8 fc_inhblank1; ++ u8 fc_invactv0; ++ u8 fc_invactv1; ++ u8 fc_invblank; ++ u8 fc_hsyncindelay0; ++ u8 fc_hsyncindelay1; ++ u8 fc_hsyncinwidth0; ++ u8 fc_hsyncinwidth1; ++ u8 fc_vsyncindelay; ++ u8 fc_vsyncinwidth; ++ u8 fc_infreq0; ++ u8 fc_infreq1; ++ u8 fc_infreq2; ++ u8 fc_ctrldur; ++ u8 fc_exctrldur; ++ u8 fc_exctrlspac; ++ u8 fc_ch0pream; ++ u8 fc_ch1pream; ++ u8 fc_ch2pream; ++ u8 fc_aviconf3; ++ u8 fc_gcp; ++ u8 fc_aviconf0; ++ u8 fc_aviconf1; ++ u8 fc_aviconf2; ++ u8 fc_avivid; ++ u8 fc_avietb0; ++ u8 fc_avietb1; ++ u8 fc_avisbb0; ++ u8 fc_avisbb1; ++ u8 fc_avielb0; ++ u8 fc_avielb1; ++ u8 fc_avisrb0; ++ u8 fc_avisrb1; ++ u8 fc_audiconf0; ++ u8 fc_audiconf1; ++ u8 fc_audiconf2; ++ u8 fc_audiconf3; ++ u8 fc_vsdieeeid0; ++ u8 fc_vsdsize; ++ u8 reserved5[0x30ff-0x102a]; ++ u8 aud_conf0; ++ u8 aud_conf1; ++ u8 aud_int; ++ u8 aud_conf2; ++ u8 aud_int1; ++ u8 reserved6[0x31ff-0x3104]; ++ u8 aud_n1; ++ u8 aud_n2; ++ u8 aud_n3; ++ u8 aud_cts1; ++ u8 aud_cts2; ++ u8 aud_cts3; ++ u8 aud_inputclkfs; ++ u8 reserved7[0x3fff-0x3206]; ++ u8 mc_sfrdiv; ++ u8 mc_clkdis; ++ u8 mc_swrstz; ++ u8 mc_opctrl; ++ u8 mc_flowctrl; ++ u8 mc_phyrstz; ++ u8 mc_lockonclock; ++ u8 mc_heacphy_rst; ++ u8 reserved8[0x40ff-0x4007]; ++ u8 csc_cfg; ++ u8 csc_scale; ++ struct { ++ u8 msb; ++ u8 lsb; ++ } csc_coef[3][4]; ++ u8 reserved9[0x7dff-0x4119]; ++ u8 i2cm_slave; ++ u8 i2c_address; ++ u8 i2cm_datao; ++ u8 i2cm_datai; ++ u8 i2cm_operation; ++ u8 i2cm_int; ++ u8 i2cm_ctlint; ++ u8 i2cm_div; ++ u8 i2cm_segaddr; ++ u8 i2cm_softrstz; ++ u8 i2cm_segptr; ++ u8 i2cm_ss_scl_hcnt_1_addr; ++ u8 i2cm_ss_scl_hcnt_0_addr; ++ u8 i2cm_ss_scl_lcnt_1_addr; ++ u8 i2cm_ss_scl_lcnt_0_addr; ++ u8 i2cm_fs_scl_hcnt_1_addr; ++ u8 i2cm_fs_scl_hcnt_0_addr; ++ u8 i2cm_fs_scl_lcnt_1_addr; ++ u8 i2cm_fs_scl_lcnt_0_addr; ++ u8 reserved10[0xffff-0x7e12]; ++ u32 phy_pol; ++ u32 phy_reserved11[3]; ++ u32 phy_read_en; ++ u32 phy_unscramble; ++ u32 reserved12[2]; ++ u32 phy_ctrl; ++ u32 phy_unk1; ++ u32 phy_unk2; ++ u32 phy_pll; ++ u32 phy_clk; ++ u32 phy_unk3; ++ u32 phy_status; +}; + +/* -+ * HDMI register addresses -+ */ -+#define SUNXI_HDMI_PHY_BASE (u32*)(SUNXI_HDMI_BASE + 0x10000) -+ -+/* Naming is taken from Linux, drivers/gpu/drm/bridge/dw-hdmi.h */ -+#define SUNXI_HDMI_IH_I2CM_STAT0 (u8*)(SUNXI_HDMI_BASE + 0x0013) -+#define SUNXI_HDMI_IH_MUTE (u8*)(SUNXI_HDMI_BASE + 0xF01F) -+ -+#define SUNXI_HDMI_TX_INVID0 (u8*)(SUNXI_HDMI_BASE + 0x0800) -+#define SUNXI_HDMI_TX_INSTUFFING (u8*)(SUNXI_HDMI_BASE + 0x0801) -+#define SUNXI_HDMI_TX_GYDATA0 (u8*)(SUNXI_HDMI_BASE + 0x8800) -+#define SUNXI_HDMI_TX_GYDATA1 (u8*)(SUNXI_HDMI_BASE + 0x8801) -+#define SUNXI_HDMI_TX_RCRDATA0 (u8*)(SUNXI_HDMI_BASE + 0x0802) -+#define SUNXI_HDMI_TX_RCRDATA1 (u8*)(SUNXI_HDMI_BASE + 0x0803) -+#define SUNXI_HDMI_TX_BCBDATA0 (u8*)(SUNXI_HDMI_BASE + 0x8802) -+#define SUNXI_HDMI_TX_BCBDATA1 (u8*)(SUNXI_HDMI_BASE + 0x8803) -+ -+#define SUNXI_HDMI_VP_PR_CD (u8*)(SUNXI_HDMI_BASE + 0x0401) -+#define SUNXI_HDMI_VP_STUFF (u8*)(SUNXI_HDMI_BASE + 0x8400) -+#define SUNXI_HDMI_VP_REMAP (u8*)(SUNXI_HDMI_BASE + 0x8401) -+#define SUNXI_HDMI_VP_CONF (u8*)(SUNXI_HDMI_BASE + 0x0402) -+ -+#define SUNXI_HDMI_FC_INVIDCONF (u8*)(SUNXI_HDMI_BASE + 0x0040) -+#define SUNXI_HDMI_FC_INHACTV0 (u8*)(SUNXI_HDMI_BASE + 0x0041) -+#define SUNXI_HDMI_FC_INHACTV1 (u8*)(SUNXI_HDMI_BASE + 0x8040) -+#define SUNXI_HDMI_FC_INHBLANK0 (u8*)(SUNXI_HDMI_BASE + 0x8041) -+#define SUNXI_HDMI_FC_INHBLANK1 (u8*)(SUNXI_HDMI_BASE + 0x0042) -+#define SUNXI_HDMI_FC_INVACTV0 (u8*)(SUNXI_HDMI_BASE + 0x0043) -+#define SUNXI_HDMI_FC_INVACTV1 (u8*)(SUNXI_HDMI_BASE + 0x8042) -+#define SUNXI_HDMI_FC_INVBLANK (u8*)(SUNXI_HDMI_BASE + 0x8043) -+#define SUNXI_HDMI_FC_HSYNCINDELAY0 (u8*)(SUNXI_HDMI_BASE + 0x4040) -+#define SUNXI_HDMI_FC_HSYNCINDELAY1 (u8*)(SUNXI_HDMI_BASE + 0x4041) -+#define SUNXI_HDMI_FC_HSYNCINWIDTH0 (u8*)(SUNXI_HDMI_BASE + 0xC040) -+#define SUNXI_HDMI_FC_HSYNCINWIDTH1 (u8*)(SUNXI_HDMI_BASE + 0xC041) -+#define SUNXI_HDMI_FC_VSYNCINDELAY (u8*)(SUNXI_HDMI_BASE + 0x4042) -+#define SUNXI_HDMI_FC_VSYNCINWIDTH (u8*)(SUNXI_HDMI_BASE + 0x4043) -+#define SUNXI_HDMI_FC_CTRLDUR (u8*)(SUNXI_HDMI_BASE + 0x0045) -+#define SUNXI_HDMI_FC_EXCTRLDUR (u8*)(SUNXI_HDMI_BASE + 0x8044) -+#define SUNXI_HDMI_FC_EXCTRLSPAC (u8*)(SUNXI_HDMI_BASE + 0x8045) -+#define SUNXI_HDMI_FC_CH0PREAM (u8*)(SUNXI_HDMI_BASE + 0x0046) -+#define SUNXI_HDMI_FC_CH1PREAM (u8*)(SUNXI_HDMI_BASE + 0x0047) -+#define SUNXI_HDMI_FC_CH2PREAM (u8*)(SUNXI_HDMI_BASE + 0x8046) -+#define SUNXI_HDMI_FC_AVICONF0 (u8*)(SUNXI_HDMI_BASE + 0x4045) -+#define SUNXI_HDMI_FC_AVICONF1 (u8*)(SUNXI_HDMI_BASE + 0xC044) -+#define SUNXI_HDMI_FC_AVICONF2 (u8*)(SUNXI_HDMI_BASE + 0xC045) -+ -+#define SUNXI_HDMI_MC_CLKDIS (u8*)(SUNXI_HDMI_BASE + 0x0081) -+#define SUNXI_HDMI_MC_SWRSTZ (u8*)(SUNXI_HDMI_BASE + 0x8080) -+#define SUNXI_HDMI_MC_FLOWCTRL (u8*)(SUNXI_HDMI_BASE + 0x0082) -+ -+#define SUNXI_HDMI_I2CM_SLAVE (u8*)(SUNXI_HDMI_BASE + 0x0EE0) -+#define SUNXI_HDMI_I2CM_ADDRESS (u8*)(SUNXI_HDMI_BASE + 0x0EE1) -+#define SUNXI_HDMI_I2CM_DATAI (u8*)(SUNXI_HDMI_BASE + 0x8EE1) -+#define SUNXI_HDMI_I2CM_OPERATION (u8*)(SUNXI_HDMI_BASE + 0x0EE2) -+#define SUNXI_HDMI_I2CM_INT (u8*)(SUNXI_HDMI_BASE + 0x0EE3) -+#define SUNXI_HDMI_I2CM_CTLINT (u8*)(SUNXI_HDMI_BASE + 0x8EE2) -+#define SUNXI_HDMI_I2CM_DIV (u8*)(SUNXI_HDMI_BASE + 0x8EE3) -+#define SUNXI_HDMI_I2CM_SEGADDR (u8*)(SUNXI_HDMI_BASE + 0x4EE0) -+#define SUNXI_HDMI_I2CM_SOFTRSTZ (u8*)(SUNXI_HDMI_BASE + 0x4EE1) -+#define SUNXI_HDMI_I2CM_SEGPTR (u8*)(SUNXI_HDMI_BASE + 0xCEE0) -+#define SUNXI_HDMI_I2CM_SS_SCL_HCNT_0_ADDR (u8*)(SUNXI_HDMI_BASE + 0x4EE2) -+#define SUNXI_HDMI_I2CM_SS_SCL_LCNT_0_ADDR (u8*)(SUNXI_HDMI_BASE + 0xCEE2) -+ -+/* + * DE register constants. + */ -+#define SUNXI_DE2_MUX0_BASE (u8*)(SUNXI_DE2_BASE + 0x00100000) -+/* MUX registers (addr / MUX base) */ ++#define SUNXI_DE2_MUX0_BASE (u8 *)(SUNXI_DE2_BASE + 0x100000) ++ +#define SUNXI_DE2_MUX_GLB_REGS 0x00000 +#define SUNXI_DE2_MUX_BLD_REGS 0x01000 +#define SUNXI_DE2_MUX_CHAN_REGS 0x02000 @@ -427,15 +569,20 @@ new file mode 100644 +#define SUNXI_DE2_MUX_FCC_REGS 0xaa000 +#define SUNXI_DE2_MUX_DCSC_REGS 0xb0000 + -+#define SUNXI_DE2_FORMAT_ARGB_8888 0 -+#define SUNXI_DE2_FORMAT_BGRA_8888 3 -+#define SUNXI_DE2_FORMAT_XRGB_8888 4 -+#define SUNXI_DE2_FORMAT_RGB_888 8 -+#define SUNXI_DE2_FORMAT_BGR_888 9 ++#define SUNXI_DE2_FORMAT_ARGB_8888 0 ++#define SUNXI_DE2_FORMAT_BGRA_8888 3 ++#define SUNXI_DE2_FORMAT_XRGB_8888 4 ++#define SUNXI_DE2_FORMAT_RGB_888 8 ++#define SUNXI_DE2_FORMAT_BGR_888 9 + -+/* coordinates and sizes */ -+#define XY(x, y) (((y) << 16) | (x)) -+#define WH(w, h) (((h - 1) << 16) | (w - 1)) ++#define SUNXI_DE2_MUX_GLB_CTL_RT_EN (1 << 0) ++ ++#define SUNXI_DE2_UI_CFG_ATTR_EN (1 << 0) ++#define SUNXI_DE2_UI_CFG_ATTR_ALPMOD(m) ((m & 3) << 1) ++#define SUNXI_DE2_UI_CFG_ATTR_FMT(f) ((f & 0xf) << 8) ++#define SUNXI_DE2_UI_CFG_ATTR_ALPHA(a) ((a & 0xff) << 24) ++ ++#define SUNXI_DE2_WH(w, h) (((h - 1) << 16) | (w - 1)) + +/* + * LCDC register constants. @@ -455,76 +602,44 @@ new file mode 100644 +/* + * HDMI register constants. + */ -+#define SUNXI_HDMI_HPD_DETECT (1 << 19) ++#define HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT 0x02 ++#define HDMI_IH_MUTE_MUTE_ALL_INTERRUPT 0x01 + -+#define SUN8I_HMDI_DDC_CTRL_RESET (1 << 0) -+#define SUN8I_HMDI_DDC_ADDR_SLAVE_ADDR (0x50 << 0) -+#define SUN8I_HMDI_DDC_ADDR_SEG_ADDR (0x30 << 0) ++#define HDMI_TX_INSTUFFING_BDBDATA_STUFFING_EN 0x04 ++#define HDMI_TX_INSTUFFING_RCRDATA_STUFFING_EN 0x02 ++#define HDMI_TX_INSTUFFING_GYDATA_STUFFING_EN 0x01 ++ ++#define HDMI_FC_INVIDCONF_DVI_MODE_HDMI 0x08 ++#define HDMI_FC_INVIDCONF_DE_IN_POL_ACTIVE_HIGH 0x10 ++ ++#define HDMI_FC_AVICONF0_ACTIVE_FORMAT 0x40 ++#define HDMI_FC_AVICONF0_SCAN_INFO_UNDERSCAN 0x20 ++ ++#define HDMI_FC_AVICONF2_RGB_QUANT_FULL_RANGE 0x08 ++#define HDMI_FC_AVICONF2_IT_CONTENT_VALID 0x80 ++ ++#define HDMI_MC_CLKDIS_TMDSCLK_DISABLE 0x02 ++ ++#define HDMI_MC_FLOWCTRL_CSC_BYPASS 0x00 ++ ++#define HDMI_I2CM_CTLINT_ADDR_NACK_POL 0x80 ++#define HDMI_I2CM_CTLINT_ADDR_NACK_MSK 0x40 ++#define HDMI_I2CM_CTLINT_ADDR_ARB_POL 0x08 ++#define HDMI_I2CM_CTLINT_ADDR_ARB_MSK 0x04 ++ ++#define HMDI_DDC_CTRL_RESET (1 << 0) ++#define HMDI_DDC_ADDR_SLAVE_ADDR (0x50 << 0) ++#define HMDI_DDC_ADDR_SEG_ADDR (0x30 << 0) ++ ++#define SUNXI_HDMI_HPD_DETECT (1 << 19) + + +#endif /* _SUNXI_DISPLAY_H */ -diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c ---- a/arch/arm/mach-sunxi/clock_sun6i.c -+++ b/arch/arm/mach-sunxi/clock_sun6i.c -@@ -141,6 +141,17 @@ void clock_set_pll3(unsigned int clk) - &ccm->pll3_cfg); - } - -+void clock_set_pll3_factors(int m, int n) -+{ -+ struct sunxi_ccm_reg * const ccm = -+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; -+ -+ /* PLL3 rate = 24000000 * n / m */ -+ writel(CCM_PLL3_CTRL_EN | CCM_PLL3_CTRL_INTEGER_MODE | -+ CCM_PLL3_CTRL_N(n) | CCM_PLL3_CTRL_M(m), -+ &ccm->pll3_cfg); -+} -+ - void clock_set_pll5(unsigned int clk, bool sigma_delta_enable) - { - struct sunxi_ccm_reg * const ccm = -@@ -213,6 +224,23 @@ done: - } - #endif - -+void clock_set_pll10(unsigned int clk) -+{ -+ struct sunxi_ccm_reg * const ccm = -+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; -+ const int m = 2; /* 12 MHz steps */ -+ -+ if (clk == 0) { -+ clrbits_le32(&ccm->pll10_cfg, CCM_PLL10_CTRL_EN); -+ return; -+ } -+ -+ /* PLL10 rate = 24000000 * n / m */ -+ writel(CCM_PLL10_CTRL_EN | CCM_PLL10_CTRL_INTEGER_MODE | -+ CCM_PLL10_CTRL_N(clk / (24000000 / m)) | CCM_PLL10_CTRL_M(m), -+ &ccm->pll10_cfg); -+} -+ - #ifdef CONFIG_MACH_SUN8I_A33 - void clock_set_pll11(unsigned int clk, bool sigma_delta_enable) - { -@@ -267,6 +295,7 @@ unsigned int clock_get_mipi_pll(void) - return ((src / 1000) * n * k / m) * 1000; - } - -+#ifndef CONFIG_SUNXI_DE2 - void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz) - { - int pll = clock_get_pll6() * 2; -@@ -278,3 +307,4 @@ void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz) - writel(CCM_DE_CTRL_GATE | CCM_DE_CTRL_PLL6_2X | CCM_DE_CTRL_M(div), - clk_cfg); - } -+#endif diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig +index e1d4ab1..1c393eb 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig -@@ -458,7 +458,7 @@ config AXP_GPIO +@@ -462,7 +462,7 @@ config AXP_GPIO config VIDEO bool "Enable graphical uboot console on HDMI, LCD or VGA" @@ -533,7 +648,7 @@ diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig default y ---help--- Say Y here to add support for using a cfb console on the HDMI, LCD -@@ -467,7 +467,7 @@ config VIDEO +@@ -471,7 +471,7 @@ config VIDEO config VIDEO_HDMI bool "HDMI output support" @@ -542,63 +657,8 @@ diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig default y ---help--- Say Y here to add support for outputting video over HDMI. -diff --git a/configs/orangepi_2_defconfig b/configs/orangepi_2_defconfig ---- a/configs/orangepi_2_defconfig -+++ b/configs/orangepi_2_defconfig -@@ -16,3 +16,4 @@ CONFIG_SPL=y - CONFIG_SUN8I_EMAC=y - CONFIG_SY8106A_POWER=y - CONFIG_USB_EHCI_HCD=y -+CONFIG_VIDEO=y -diff --git a/configs/orangepi_lite_defconfig b/configs/orangepi_lite_defconfig ---- a/configs/orangepi_lite_defconfig -+++ b/configs/orangepi_lite_defconfig -@@ -12,3 +12,4 @@ CONFIG_SPL=y - # CONFIG_CMD_FLASH is not set - # CONFIG_CMD_FPGA is not set - CONFIG_USB_EHCI_HCD=y -+CONFIG_VIDEO=y -diff --git a/configs/orangepi_one_defconfig b/configs/orangepi_one_defconfig ---- a/configs/orangepi_one_defconfig -+++ b/configs/orangepi_one_defconfig -@@ -13,3 +13,4 @@ CONFIG_SPL=y - # CONFIG_CMD_FPGA is not set - CONFIG_SUN8I_EMAC=y - CONFIG_USB_EHCI_HCD=y -+CONFIG_VIDEO=y -diff --git a/configs/orangepi_pc_defconfig b/configs/orangepi_pc_defconfig ---- a/configs/orangepi_pc_defconfig -+++ b/configs/orangepi_pc_defconfig -@@ -15,3 +15,4 @@ CONFIG_SPL=y - CONFIG_SUN8I_EMAC=y - CONFIG_SY8106A_POWER=y - CONFIG_USB_EHCI_HCD=y -+CONFIG_VIDEO=y -diff --git a/configs/orangepi_pc_plus_defconfig b/configs/orangepi_pc_plus_defconfig ---- a/configs/orangepi_pc_plus_defconfig -+++ b/configs/orangepi_pc_plus_defconfig -@@ -16,3 +16,4 @@ CONFIG_SPL=y - CONFIG_SUN8I_EMAC=y - CONFIG_SY8106A_POWER=y - CONFIG_USB_EHCI_HCD=y -+CONFIG_VIDEO=y -diff --git a/configs/orangepi_plus2e_defconfig b/configs/orangepi_plus2e_defconfig ---- a/configs/orangepi_plus2e_defconfig -+++ b/configs/orangepi_plus2e_defconfig -@@ -17,3 +17,4 @@ CONFIG_SPL=y - CONFIG_SUN8I_EMAC=y - CONFIG_SY8106A_POWER=y - CONFIG_USB_EHCI_HCD=y -+CONFIG_VIDEO=y -diff --git a/configs/orangepi_plus_defconfig b/configs/orangepi_plus_defconfig ---- a/configs/orangepi_plus_defconfig -+++ b/configs/orangepi_plus_defconfig -@@ -18,3 +18,4 @@ CONFIG_SPL=y - CONFIG_SUN8I_EMAC=y - CONFIG_SY8106A_POWER=y - CONFIG_USB_EHCI_HCD=y -+CONFIG_VIDEO=y diff --git a/drivers/video/Makefile b/drivers/video/Makefile +index db34904..3097b82 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -52,6 +52,7 @@ obj-$(CONFIG_VIDEO_OMAP3) += omap3_dss.o @@ -611,18 +671,19 @@ diff --git a/drivers/video/Makefile b/drivers/video/Makefile obj-$(CONFIG_VIDEO_VESA) += vesa.o diff --git a/drivers/video/sunxi_display2.c b/drivers/video/sunxi_display2.c new file mode 100644 +index 0000000..db376d9 --- /dev/null +++ b/drivers/video/sunxi_display2.c -@@ -0,0 +1,982 @@ +@@ -0,0 +1,1037 @@ +/* + * Display driver for sunxi Allwinner SoCs with DE2. -+ * ++ * + * Copyright (C) 2016 Jernej Skrabec + * + * Based on sunxi_display.c: + * (C) Copyright 2013-2014 Luc Verhaegen + * (C) Copyright 2014-2015 Hans de Goede -+ * ++ * + * Based on Linux DRM driver: + * Copyright (C) 2016 Jean-Francois Moine + * Copyright (c) 2016 Allwinnertech Co., Ltd. @@ -630,7 +691,7 @@ new file mode 100644 + * Based on rk_hdmi.c: + * Copyright (c) 2015 Google, Inc + * Copyright 2014 Rockchip Inc. -+ * ++ * + * SPDX-License-Identifier: GPL-2.0+ + */ + @@ -667,8 +728,8 @@ new file mode 100644 + +static void sunxi_hdmi_phy_init(void) +{ -+ struct sunxi_phy_hdmi_reg * const phy = -+ (struct sunxi_phy_hdmi_reg *)SUNXI_HDMI_PHY_BASE; ++ struct sunxi_dwc_hdmi * const hdmi = ++ (struct sunxi_dwc_hdmi *)SUNXI_HDMI_BASE; + unsigned long tmo; + u32 tmp; + @@ -676,66 +737,80 @@ new file mode 100644 + * HDMI PHY settings are taken as-is from Allwinner BSP code. + * There is no documentation. + */ -+ writel(0, &phy->ctrl); -+ setbits_le32(&phy->ctrl, BIT(0)); ++ writel(0, &hdmi->phy_ctrl); ++ setbits_le32(&hdmi->phy_ctrl, BIT(0)); + udelay(5); -+ setbits_le32(&phy->ctrl, BIT(16)); -+ setbits_le32(&phy->ctrl, BIT(1)); ++ setbits_le32(&hdmi->phy_ctrl, BIT(16)); ++ setbits_le32(&hdmi->phy_ctrl, BIT(1)); + udelay(10); -+ setbits_le32(&phy->ctrl, BIT(2)); ++ setbits_le32(&hdmi->phy_ctrl, BIT(2)); + udelay(5); -+ setbits_le32(&phy->ctrl, BIT(3)); ++ setbits_le32(&hdmi->phy_ctrl, BIT(3)); + udelay(40); -+ setbits_le32(&phy->ctrl, BIT(19)); ++ setbits_le32(&hdmi->phy_ctrl, BIT(19)); + udelay(100); -+ setbits_le32(&phy->ctrl, BIT(18)); -+ setbits_le32(&phy->ctrl, 7 << 4); ++ setbits_le32(&hdmi->phy_ctrl, BIT(18)); ++ setbits_le32(&hdmi->phy_ctrl, 7 << 4); + + /* Note that Allwinner code doesn't fail in case of timeout */ + tmo = timer_get_us() + 2000; -+ while ((readl(&phy->status) & 0x80) == 0) { ++ while ((readl(&hdmi->phy_status) & 0x80) == 0) { + if (timer_get_us() > tmo) { + printf("Warning: HDMI PHY init timeout!\n"); + break; + } + } + -+ setbits_le32(&phy->ctrl, 0xf << 8); -+ setbits_le32(&phy->ctrl, BIT(7)); ++ setbits_le32(&hdmi->phy_ctrl, 0xf << 8); ++ setbits_le32(&hdmi->phy_ctrl, BIT(7)); + -+ writel(0x39dc5040, &phy->pll); -+ writel(0x80084343, &phy->clk); ++ writel(0x39dc5040, &hdmi->phy_pll); ++ writel(0x80084343, &hdmi->phy_clk); + udelay(10000); -+ writel(1, &phy->unk3); -+ setbits_le32(&phy->pll, BIT(25)); ++ writel(1, &hdmi->phy_unk3); ++ setbits_le32(&hdmi->phy_pll, BIT(25)); + udelay(100000); -+ tmp = (readl(&phy->status) & 0x1f800) >> 11; -+ setbits_le32(&phy->pll, BIT(31) | BIT(30)); -+ setbits_le32(&phy->pll, tmp); -+ writel(0x01FF0F7F, &phy->ctrl); -+ writel(0x80639000, &phy->unk1); -+ writel(0x0F81C405, &phy->unk2); ++ tmp = (readl(&hdmi->phy_status) & 0x1f800) >> 11; ++ setbits_le32(&hdmi->phy_pll, BIT(31) | BIT(30)); ++ setbits_le32(&hdmi->phy_pll, tmp); ++ writel(0x01FF0F7F, &hdmi->phy_ctrl); ++ writel(0x80639000, &hdmi->phy_unk1); ++ writel(0x0F81C405, &hdmi->phy_unk2); + + /* enable read access to HDMI controller */ -+ writel(0x54524545, &phy->read_en); ++ writel(0x54524545, &hdmi->phy_read_en); ++ /* descramble register offsets */ ++ writel(0x42494E47, &hdmi->phy_unscramble); +} + +static void sunxi_hdmi_ctrl_init(void) +{ ++ struct sunxi_dwc_hdmi * const hdmi = ++ (struct sunxi_dwc_hdmi *)SUNXI_HDMI_BASE; ++ + /* soft reset HDMI controller */ -+ writeb(0x00, SUNXI_HDMI_MC_SWRSTZ); ++ writeb(0x00, &hdmi->mc_swrstz); ++ + udelay(1); -+ writeb(0x03, SUNXI_HDMI_IH_MUTE); -+ writeb(0xff, SUNXI_HDMI_I2CM_CTLINT); -+ writeb(0xfd, SUNXI_HDMI_MC_CLKDIS); ++ ++ writeb(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT | ++ HDMI_IH_MUTE_MUTE_ALL_INTERRUPT, ++ &hdmi->ih_mute); ++ writeb(HDMI_I2CM_CTLINT_ADDR_NACK_POL | ++ HDMI_I2CM_CTLINT_ADDR_NACK_MSK | ++ HDMI_I2CM_CTLINT_ADDR_ARB_POL | ++ HDMI_I2CM_CTLINT_ADDR_ARB_MSK, ++ &hdmi->i2cm_ctlint); ++ writeb(0xff & ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE, ++ &hdmi->mc_clkdis); +} + +static int sunxi_hdmi_hpd_detect(int hpd_delay) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; -+ struct sunxi_phy_hdmi_reg * const phy = -+ (struct sunxi_phy_hdmi_reg *)SUNXI_HDMI_PHY_BASE; ++ struct sunxi_dwc_hdmi * const hdmi = ++ (struct sunxi_dwc_hdmi *)SUNXI_HDMI_BASE; + unsigned long tmo = timer_get_us() + hpd_delay * 1000; + int status = 0; + @@ -759,7 +834,7 @@ new file mode 100644 + sunxi_hdmi_ctrl_init(); + + while (timer_get_us() < tmo) { -+ if (readl(&phy->status) & SUNXI_HDMI_HPD_DETECT) { ++ if (readl(&hdmi->phy_status) & SUNXI_HDMI_HPD_DETECT) { + status = 1; + break; + } @@ -772,10 +847,10 @@ new file mode 100644 +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; -+ struct sunxi_phy_hdmi_reg * const phy = -+ (struct sunxi_phy_hdmi_reg *)SUNXI_HDMI_PHY_BASE; ++ struct sunxi_dwc_hdmi * const hdmi = ++ (struct sunxi_dwc_hdmi *)SUNXI_HDMI_BASE; + -+ writel(0, &phy->ctrl); ++ writel(0, &hdmi->phy_ctrl); + clrbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE); + clrbits_le32(&ccm->hdmi_slow_clk_cfg, CCM_HDMI_SLOW_CTRL_DDC_GATE); + clrbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI); @@ -786,13 +861,15 @@ new file mode 100644 + +static int sunxi_hdmi_ddc_wait_i2c_done(int msec) +{ ++ struct sunxi_dwc_hdmi * const hdmi = ++ (struct sunxi_dwc_hdmi *)SUNXI_HDMI_BASE; + u32 val; + ulong start; + + start = get_timer(0); + do { -+ val = readb(SUNXI_HDMI_IH_I2CM_STAT0); -+ writeb(val, SUNXI_HDMI_IH_I2CM_STAT0); ++ val = readb(&hdmi->ih_i2cm_stat0); ++ writeb(val, &hdmi->ih_i2cm_stat0); + + if (val & 0x2) + return 0; @@ -807,27 +884,29 @@ new file mode 100644 + +static int sunxi_hdmi_ddc_read(int block, u8 *buf) +{ ++ struct sunxi_dwc_hdmi * const hdmi = ++ (struct sunxi_dwc_hdmi *)SUNXI_HDMI_BASE; + int shift = (block % 2) * 0x80; + int trytime = 5; + int edid_read_err = 0; + u32 op = (block == 0) ? 1 : 2; + int n; + -+ writeb(block >> 1, SUNXI_HDMI_I2CM_SEGPTR); ++ writeb(block >> 1, &hdmi->i2cm_segptr); + + while (trytime--) { + edid_read_err = 0; + + for (n = 0; n < 128; n++) { -+ writeb(shift + n, SUNXI_HDMI_I2CM_ADDRESS); -+ writeb(op, SUNXI_HDMI_I2CM_OPERATION); ++ writeb(shift + n, &hdmi->i2c_address); ++ writeb(op, &hdmi->i2cm_operation); + + if (sunxi_hdmi_ddc_wait_i2c_done(10)) { + edid_read_err = 1; + break; + } + -+ *buf++ = readb(SUNXI_HDMI_I2CM_DATAI); ++ *buf++ = readb(&hdmi->i2cm_datai); + } + + if (!edid_read_err) @@ -857,6 +936,8 @@ new file mode 100644 + +static int sunxi_hdmi_edid_get_mode(struct ctfb_res_modes *mode) +{ ++ struct sunxi_dwc_hdmi * const hdmi = ++ (struct sunxi_dwc_hdmi *)SUNXI_HDMI_BASE; + struct edid1_info edid1; + struct edid_cea861_info cea681[4]; + struct edid_detailed_timing *t = @@ -864,14 +945,17 @@ new file mode 100644 + int i, r, ext_blocks = 0; + + /* Reset i2c controller */ -+ writeb(0, SUNXI_HDMI_I2CM_SOFTRSTZ); ++ writeb(0, &hdmi->i2cm_softrstz); + -+ writeb(0x05, SUNXI_HDMI_I2CM_DIV); -+ writeb(0x08, SUNXI_HDMI_I2CM_INT); -+ writeb(0xd8, SUNXI_HDMI_I2CM_SS_SCL_HCNT_0_ADDR); -+ writeb(0xfe, SUNXI_HDMI_I2CM_SS_SCL_LCNT_0_ADDR); -+ writeb(SUN8I_HMDI_DDC_ADDR_SLAVE_ADDR, SUNXI_HDMI_I2CM_SLAVE); -+ writeb(SUN8I_HMDI_DDC_ADDR_SEG_ADDR, SUNXI_HDMI_I2CM_SEGADDR); ++ writeb(0x05, &hdmi->i2cm_div); ++ writeb(0x08, &hdmi->i2cm_int); ++ ++ /* set DDC timing*/ ++ writeb(0xd8, &hdmi->i2cm_ss_scl_hcnt_0_addr); ++ writeb(0xfe, &hdmi->i2cm_ss_scl_lcnt_0_addr); ++ ++ writeb(HMDI_DDC_ADDR_SLAVE_ADDR, &hdmi->i2cm_slave); ++ writeb(HMDI_DDC_ADDR_SEG_ADDR, &hdmi->i2cm_segaddr); + + r = sunxi_hdmi_edid_get_block(0, (u8 *)&edid1); + if (r == 0) { @@ -944,15 +1028,15 @@ new file mode 100644 + clock_set_pll10(432000000); + + /* Set DE parent to pll10 */ -+ clrsetbits_le32(&ccm->de_clk_cfg, CCM_DE_CTRL_PLL_MASK, -+ CCM_DE_CTRL_PLL10); ++ clrsetbits_le32(&ccm->de_clk_cfg, CCM_DE2_CTRL_PLL_MASK, ++ CCM_DE2_CTRL_PLL10); + + /* Set ahb gating to pass */ + setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DE); + setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_DE); + + /* Clock on */ -+ setbits_le32(&ccm->de_clk_cfg, CCM_DE_CTRL_GATE); ++ setbits_le32(&ccm->de_clk_cfg, CCM_DE2_CTRL_GATE); +} + +static void sunxi_composer_mode_set(const struct ctfb_res_modes *mode, @@ -961,13 +1045,16 @@ new file mode 100644 + struct de_clk * const de_clk_regs = + (struct de_clk *)(SUNXI_DE2_BASE); + struct de_glb * const de_glb_regs = -+ (struct de_glb *)(SUNXI_DE2_MUX0_BASE + SUNXI_DE2_MUX_GLB_REGS); ++ (struct de_glb *)(SUNXI_DE2_MUX0_BASE + ++ SUNXI_DE2_MUX_GLB_REGS); + struct de_bld * const de_bld_regs = -+ (struct de_bld *)(SUNXI_DE2_MUX0_BASE + SUNXI_DE2_MUX_BLD_REGS); ++ (struct de_bld *)(SUNXI_DE2_MUX0_BASE + ++ SUNXI_DE2_MUX_BLD_REGS); + struct de_ui * const de_ui_regs = -+ (struct de_ui *)(SUNXI_DE2_MUX0_BASE + SUNXI_DE2_MUX_CHAN_REGS + -+ SUNXI_DE2_MUX_CHAN_SZ * 1); -+ u32 size = WH(mode->xres, mode->yres); ++ (struct de_ui *)(SUNXI_DE2_MUX0_BASE + ++ SUNXI_DE2_MUX_CHAN_REGS + ++ SUNXI_DE2_MUX_CHAN_SZ * 1); ++ u32 size = SUNXI_DE2_WH(mode->xres, mode->yres); + int channel, i; + u32 data; + @@ -978,7 +1065,7 @@ new file mode 100644 + + clrbits_le32(&de_clk_regs->sel_cfg, 1); + -+ writel(DE_MUX_GLB_CTL_rt_en, &de_glb_regs->ctl); ++ writel(SUNXI_DE2_MUX_GLB_CTL_RT_EN, &de_glb_regs->ctl); + writel(0, &de_glb_regs->status); + writel(1, &de_glb_regs->dbuff); + writel(size, &de_glb_regs->size); @@ -989,8 +1076,8 @@ new file mode 100644 + memset(chan, 0, channel == 0 ? + sizeof(struct de_vi) : sizeof(struct de_ui)); + } -+ memset(de_bld_regs, 0, 0x44); -+ ++ memset(de_bld_regs, 0, sizeof(struct de_bld)); ++ + writel(0x00000101, &de_bld_regs->fcolor_ctl); + + writel(1, &de_bld_regs->route); @@ -1000,10 +1087,10 @@ new file mode 100644 + + writel(0x03010301, &de_bld_regs->bld_mode[0]); + writel(0x03010301, &de_bld_regs->bld_mode[1]); -+ ++ + writel(size, &de_bld_regs->output_size); + writel(mode->vmode & FB_VMODE_INTERLACED ? 2 : 0, -+ &de_bld_regs->out_ctl); ++ &de_bld_regs->out_ctl); + writel(0, &de_bld_regs->ck_ctl); + + for (i = 0; i < 4; i++) { @@ -1024,8 +1111,10 @@ new file mode 100644 + writel(0, SUNXI_DE2_MUX0_BASE + SUNXI_DE2_MUX_FCC_REGS); + writel(0, SUNXI_DE2_MUX0_BASE + SUNXI_DE2_MUX_DCSC_REGS); + -+ data = UI_CFG_ATTR_en | (SUNXI_DE2_FORMAT_XRGB_8888 << UI_CFG_ATTR_fmt_SHIFT) | -+ (1 << UI_CFG_ATTR_alpmod_SHIFT) | (0xff << UI_CFG_ATTR_alpha_SHIFT); ++ data = SUNXI_DE2_UI_CFG_ATTR_EN | ++ SUNXI_DE2_UI_CFG_ATTR_FMT(SUNXI_DE2_FORMAT_XRGB_8888) | ++ SUNXI_DE2_UI_CFG_ATTR_ALPMOD(1) | ++ SUNXI_DE2_UI_CFG_ATTR_ALPHA(0xff); + writel(data, &de_ui_regs->cfg[0].attr); + writel(size, &de_ui_regs->cfg[0].size); + writel(0, &de_ui_regs->cfg[0].coord); @@ -1037,7 +1126,8 @@ new file mode 100644 +static void sunxi_composer_enable(void) +{ + struct de_glb * const de_glb_regs = -+ (struct de_glb *)(SUNXI_DE2_MUX0_BASE + SUNXI_DE2_MUX_GLB_REGS); ++ (struct de_glb *)(SUNXI_DE2_MUX0_BASE + ++ SUNXI_DE2_MUX_GLB_REGS); + + writel(1, &de_glb_regs->dbuff); +} @@ -1087,8 +1177,8 @@ new file mode 100644 + + clock_set_pll3_factors(best_m, best_n); + debug("dotclock: %dkHz = %dkHz: (24MHz * %d) / %d / %d\n", -+ dotclock, (clock_get_pll3() / 1000) / x, -+ best_n, best_m, x); ++ dotclock, (clock_get_pll3() / 1000) / x, ++ best_n, best_m, x); + + writel(CCM_TCON0_CTRL_GATE | CCM_TCON0_CTRL_M(x), + &ccm->tcon0_clk_cfg); @@ -1185,6 +1275,8 @@ new file mode 100644 + +static void sunxi_hdmi_setup_info_frames(const struct ctfb_res_modes *mode) +{ ++ struct sunxi_dwc_hdmi * const hdmi = ++ (struct sunxi_dwc_hdmi *)SUNXI_HDMI_BASE; + u8 tmp; + + if (mode->pixclock_khz <= 27000) @@ -1197,82 +1289,87 @@ new file mode 100644 + else + tmp |= 0x28; /* 16 : 9 */ + -+ setbits_8(SUNXI_HDMI_FC_INVIDCONF, 0x08); -+ writeb(0x60, SUNXI_HDMI_FC_AVICONF0); -+ writeb(tmp, SUNXI_HDMI_FC_AVICONF1); -+ writeb(0x88, SUNXI_HDMI_FC_AVICONF2); ++ setbits_8(&hdmi->fc_invidconf, ++ HDMI_FC_INVIDCONF_DVI_MODE_HDMI); ++ writeb(HDMI_FC_AVICONF0_ACTIVE_FORMAT | ++ HDMI_FC_AVICONF0_SCAN_INFO_UNDERSCAN, ++ &hdmi->fc_aviconf0); ++ writeb(tmp, &hdmi->fc_aviconf1); ++ writeb(HDMI_FC_AVICONF2_RGB_QUANT_FULL_RANGE | ++ HDMI_FC_AVICONF2_IT_CONTENT_VALID, ++ &hdmi->fc_aviconf2); +} + +static void sunxi_hdmi_phy_set(u32 divider) +{ -+ struct sunxi_phy_hdmi_reg * const phy = -+ (struct sunxi_phy_hdmi_reg *)SUNXI_HDMI_PHY_BASE; ++ struct sunxi_dwc_hdmi * const hdmi = ++ (struct sunxi_dwc_hdmi *)SUNXI_HDMI_BASE; + u32 tmp; + -+ /* ++ /* + * Unfortunatelly, we don't know much about those magic + * numbers. They are taken from Allwinner BSP driver. + */ -+ switch(divider) { ++ switch (divider) { + case 1: -+ writel(0x30dc5fc0, &phy->pll); -+ writel(0x800863C0, &phy->clk); ++ writel(0x30dc5fc0, &hdmi->phy_pll); ++ writel(0x800863C0, &hdmi->phy_clk); + mdelay(10); -+ writel(0x00000001, &phy->unk3); -+ setbits_le32(&phy->pll, BIT(25)); ++ writel(0x00000001, &hdmi->phy_unk3); ++ setbits_le32(&hdmi->phy_pll, BIT(25)); + mdelay(200); -+ tmp = (readl(&phy->status) & 0x1f800) >> 11; -+ setbits_le32(&phy->pll, BIT(31) | BIT(30)); ++ tmp = (readl(&hdmi->phy_status) & 0x1f800) >> 11; ++ setbits_le32(&hdmi->phy_pll, BIT(31) | BIT(30)); + if (tmp < 0x3d) -+ setbits_le32(&phy->pll, tmp + 2); ++ setbits_le32(&hdmi->phy_pll, tmp + 2); + else -+ setbits_le32(&phy->pll, 0x3f); ++ setbits_le32(&hdmi->phy_pll, 0x3f); + mdelay(100); -+ writel(0x01FFFF7F, &phy->ctrl); -+ writel(0x8063b000, &phy->unk1); -+ writel(0x0F8246B5, &phy->unk2); ++ writel(0x01FFFF7F, &hdmi->phy_ctrl); ++ writel(0x8063b000, &hdmi->phy_unk1); ++ writel(0x0F8246B5, &hdmi->phy_unk2); + break; + case 2: -+ writel(0x39dc5040, &phy->pll); -+ writel(0x80084381, &phy->clk); ++ writel(0x39dc5040, &hdmi->phy_pll); ++ writel(0x80084381, &hdmi->phy_clk); + mdelay(10); -+ writel(0x00000001, &phy->unk3); -+ setbits_le32(&phy->pll, BIT(25)); ++ writel(0x00000001, &hdmi->phy_unk3); ++ setbits_le32(&hdmi->phy_pll, BIT(25)); + mdelay(100); -+ tmp = (readl(&phy->status) & 0x1f800) >> 11; -+ setbits_le32(&phy->pll, BIT(31) | BIT(30)); -+ setbits_le32(&phy->pll, tmp); -+ writel(0x01FFFF7F, &phy->ctrl); -+ writel(0x8063a800, &phy->unk1); -+ writel(0x0F81C485, &phy->unk2); ++ tmp = (readl(&hdmi->phy_status) & 0x1f800) >> 11; ++ setbits_le32(&hdmi->phy_pll, BIT(31) | BIT(30)); ++ setbits_le32(&hdmi->phy_pll, tmp); ++ writel(0x01FFFF7F, &hdmi->phy_ctrl); ++ writel(0x8063a800, &hdmi->phy_unk1); ++ writel(0x0F81C485, &hdmi->phy_unk2); + break; + case 4: -+ writel(0x39dc5040, &phy->pll); -+ writel(0x80084343, &phy->clk); ++ writel(0x39dc5040, &hdmi->phy_pll); ++ writel(0x80084343, &hdmi->phy_clk); + mdelay(10); -+ writel(0x00000001, &phy->unk3); -+ setbits_le32(&phy->pll, BIT(25)); ++ writel(0x00000001, &hdmi->phy_unk3); ++ setbits_le32(&hdmi->phy_pll, BIT(25)); + mdelay(100); -+ tmp = (readl(&phy->status) & 0x1f800) >> 11; -+ setbits_le32(&phy->pll, BIT(31) | BIT(30)); -+ setbits_le32(&phy->pll, tmp); -+ writel(0x01FFFF7F, &phy->ctrl); -+ writel(0x8063b000, &phy->unk1); -+ writel(0x0F81C405, &phy->unk2); ++ tmp = (readl(&hdmi->phy_status) & 0x1f800) >> 11; ++ setbits_le32(&hdmi->phy_pll, BIT(31) | BIT(30)); ++ setbits_le32(&hdmi->phy_pll, tmp); ++ writel(0x01FFFF7F, &hdmi->phy_ctrl); ++ writel(0x8063b000, &hdmi->phy_unk1); ++ writel(0x0F81C405, &hdmi->phy_unk2); + break; + case 11: -+ writel(0x39dc5040, &phy->pll); -+ writel(0x8008430a, &phy->clk); ++ writel(0x39dc5040, &hdmi->phy_pll); ++ writel(0x8008430a, &hdmi->phy_clk); + mdelay(10); -+ writel(0x00000001, &phy->unk3); -+ setbits_le32(&phy->pll, BIT(25)); ++ writel(0x00000001, &hdmi->phy_unk3); ++ setbits_le32(&hdmi->phy_pll, BIT(25)); + mdelay(100); -+ tmp = (readl(&phy->status) & 0x1f800) >> 11; -+ setbits_le32(&phy->pll, BIT(31) | BIT(30)); -+ setbits_le32(&phy->pll, tmp); -+ writel(0x01FFFF7F, &phy->ctrl); -+ writel(0x8063b000, &phy->unk1); -+ writel(0x0F81C405, &phy->unk2); ++ tmp = (readl(&hdmi->phy_status) & 0x1f800) >> 11; ++ setbits_le32(&hdmi->phy_pll, BIT(31) | BIT(30)); ++ setbits_le32(&hdmi->phy_pll, tmp); ++ writel(0x01FFFF7F, &hdmi->phy_ctrl); ++ writel(0x8063b000, &hdmi->phy_unk1); ++ writel(0x0F81C405, &hdmi->phy_unk2); + break; + } +} @@ -1280,89 +1377,108 @@ new file mode 100644 +static void sunxi_hdmi_mode_set(const struct ctfb_res_modes *mode, + int clk_div) +{ -+ struct sunxi_phy_hdmi_reg * const phy = -+ (struct sunxi_phy_hdmi_reg *)SUNXI_HDMI_PHY_BASE; ++ struct sunxi_dwc_hdmi * const hdmi = ++ (struct sunxi_dwc_hdmi *)SUNXI_HDMI_BASE; + u8 invidconf, v_blanking; + u32 h_blanking; + + sunxi_hdmi_phy_set(clk_div); + + invidconf = 0; -+ if(mode->vmode & FB_VMODE_INTERLACED) ++ if (mode->vmode & FB_VMODE_INTERLACED) + invidconf |= 0x01; -+ if(mode->sync & FB_SYNC_HOR_HIGH_ACT) ++ if (mode->sync & FB_SYNC_HOR_HIGH_ACT) + invidconf |= 0x20; -+ if(mode->sync & FB_SYNC_VERT_HIGH_ACT) ++ if (mode->sync & FB_SYNC_VERT_HIGH_ACT) + invidconf |= 0x40; + + h_blanking = mode->left_margin + mode->right_margin + mode->hsync_len; + v_blanking = mode->upper_margin + mode->lower_margin + mode->vsync_len; + -+ writeb(invidconf | 0x10, SUNXI_HDMI_FC_INVIDCONF); ++ writeb(invidconf | ++ HDMI_FC_INVIDCONF_DE_IN_POL_ACTIVE_HIGH, ++ &hdmi->fc_invidconf); + if (invidconf < 96) -+ setbits_le32(&phy->pol, 0x300); ++ setbits_le32(&hdmi->phy_pol, 0x300); + -+ writeb(mode->xres, SUNXI_HDMI_FC_INHACTV0); -+ writeb(mode->xres >> 8, SUNXI_HDMI_FC_INHACTV1); -+ writeb(mode->yres, SUNXI_HDMI_FC_INVACTV0); -+ writeb(mode->yres >> 8, SUNXI_HDMI_FC_INVACTV1); -+ writeb(mode->vsync_len, SUNXI_HDMI_FC_VSYNCINWIDTH); -+ writeb(h_blanking, SUNXI_HDMI_FC_INHBLANK0); -+ writeb(h_blanking >> 8, SUNXI_HDMI_FC_INHBLANK1); -+ writeb(mode->lower_margin, SUNXI_HDMI_FC_VSYNCINDELAY); -+ writeb(mode->right_margin, SUNXI_HDMI_FC_HSYNCINDELAY0); -+ writeb(mode->right_margin >> 8, SUNXI_HDMI_FC_HSYNCINDELAY1); -+ writeb(mode->hsync_len, SUNXI_HDMI_FC_HSYNCINWIDTH0); -+ writeb(mode->hsync_len >> 8, SUNXI_HDMI_FC_HSYNCINWIDTH1); -+ writeb(v_blanking, SUNXI_HDMI_FC_INVBLANK); ++ writeb(mode->xres, &hdmi->fc_inhactv0); ++ writeb(mode->xres >> 8, &hdmi->fc_inhactv1); ++ writeb(h_blanking, &hdmi->fc_inhblank0); ++ writeb(h_blanking >> 8, &hdmi->fc_inhblank1); ++ writeb(mode->yres, &hdmi->fc_invactv0); ++ writeb(mode->yres >> 8, &hdmi->fc_invactv1); ++ writeb(v_blanking, &hdmi->fc_invblank); ++ writeb(mode->right_margin, &hdmi->fc_hsyncindelay0); ++ writeb(mode->right_margin >> 8, &hdmi->fc_hsyncindelay1); ++ writeb(mode->hsync_len, &hdmi->fc_hsyncinwidth0); ++ writeb(mode->hsync_len >> 8, &hdmi->fc_hsyncinwidth1); ++ writeb(mode->lower_margin, &hdmi->fc_vsyncindelay); ++ writeb(mode->vsync_len, &hdmi->fc_vsyncinwidth); + -+ writeb(0x0c, SUNXI_HDMI_FC_CTRLDUR); -+ writeb(0x20, SUNXI_HDMI_FC_EXCTRLDUR); -+ writeb(0x01, SUNXI_HDMI_FC_EXCTRLSPAC); -+ writeb(0x0b, SUNXI_HDMI_FC_CH0PREAM); -+ writeb(0x16, SUNXI_HDMI_FC_CH1PREAM); -+ writeb(0x21, SUNXI_HDMI_FC_CH2PREAM); ++ /* control period minimum duration */ ++ writeb(0x0c, &hdmi->fc_ctrldur); ++ writeb(0x20, &hdmi->fc_exctrldur); ++ writeb(0x01, &hdmi->fc_exctrlspac); + -+ writeb(0x40, SUNXI_HDMI_VP_PR_CD); -+ writeb(0x07, SUNXI_HDMI_VP_STUFF); ++ /* set to fill tmds data channels */ ++ writeb(0x0b, &hdmi->fc_ch0pream); ++ writeb(0x16, &hdmi->fc_ch1pream); ++ writeb(0x21, &hdmi->fc_ch2pream); + -+ // default value, written 0 by rk_hdmi -+ writeb(0x00, SUNXI_HDMI_VP_REMAP); ++ writeb(0x40, &hdmi->vp_pr_cd); ++ writeb(0x07, &hdmi->vp_stuff); ++ writeb(0x00, &hdmi->vp_remap); ++ writeb(0x47, &hdmi->vp_conf); + -+ writeb(0x47, SUNXI_HDMI_VP_CONF); -+ writeb(0x01, SUNXI_HDMI_TX_INVID0); -+ writeb(0x07, SUNXI_HDMI_TX_INSTUFFING); -+ writeb(0x00, SUNXI_HDMI_TX_GYDATA0); -+ writeb(0x00, SUNXI_HDMI_TX_GYDATA1); -+ writeb(0x00, SUNXI_HDMI_TX_RCRDATA0); -+ writeb(0x00, SUNXI_HDMI_TX_RCRDATA1); -+ writeb(0x00, SUNXI_HDMI_TX_BCBDATA0); -+ writeb(0x00, SUNXI_HDMI_TX_BCBDATA1); ++ writeb(0x01, &hdmi->tx_invid0); ++ ++ /* enable tx stuffing: when de is inactive, fix the output data to 0 */ ++ writeb(HDMI_TX_INSTUFFING_BDBDATA_STUFFING_EN | ++ HDMI_TX_INSTUFFING_RCRDATA_STUFFING_EN | ++ HDMI_TX_INSTUFFING_GYDATA_STUFFING_EN, ++ &hdmi->tx_instuffing); ++ writeb(0x00, &hdmi->tx_gydata0); ++ writeb(0x00, &hdmi->tx_gydata1); ++ writeb(0x00, &hdmi->tx_rcrdata0); ++ writeb(0x00, &hdmi->tx_rcrdata1); ++ writeb(0x00, &hdmi->tx_bcbdata0); ++ writeb(0x00, &hdmi->tx_bcbdata1); + + if (sunxi_display.monitor == sunxi_monitor_hdmi) + sunxi_hdmi_setup_info_frames(mode); + -+ writeb(0x00, SUNXI_HDMI_MC_FLOWCTRL); -+ writeb(0x74, SUNXI_HDMI_MC_CLKDIS); ++ writeb(HDMI_MC_FLOWCTRL_CSC_BYPASS, &hdmi->mc_flowctrl); ++ /* enable audio, TMDS and pixel clock */ ++ writeb(0x74, &hdmi->mc_clkdis); ++ ++ /* ++ * This is last hdmi access before boot, ++ * so scramble addresses again. Othwerwise ++ * BSP or current DRM driver won't work. ++ * Dummy read is needed or otherwise last ++ * write doesn't get written correctly. ++ */ ++ (void)readb(&hdmi->reserved0[0]); ++ writel(0, &hdmi->phy_unscramble); +} + +static void sunxi_hdmi_enable(void) +{ -+ struct sunxi_phy_hdmi_reg * const phy = -+ (struct sunxi_phy_hdmi_reg *)SUNXI_HDMI_PHY_BASE; ++ struct sunxi_dwc_hdmi * const hdmi = ++ (struct sunxi_dwc_hdmi *)SUNXI_HDMI_BASE; + -+ setbits_le32(&phy->ctrl, 0xf << 12); ++ setbits_le32(&hdmi->phy_ctrl, 0xf << 12); + printf("hdmi enabled\n"); +} + +#endif /* CONFIG_VIDEO_HDMI */ -+ ++ +static void sunxi_engines_init(void) +{ + sunxi_composer_init(); + sunxi_lcdc_init(); +} -+ ++ +static void sunxi_mode_set(const struct ctfb_res_modes *mode, + unsigned int address) +{ @@ -1596,65 +1712,44 @@ new file mode 100644 + return ret; +} +#endif /* CONFIG_OF_BOARD_SETUP && CONFIG_VIDEO_DT_SIMPLEFB */ -diff --git a/include/configs/sun8i.h b/include/configs/sun8i.h -index 011d70f..c4eb3ba 100644 ---- a/include/configs/sun8i.h -+++ b/include/configs/sun8i.h -@@ -26,6 +26,10 @@ - #define CONFIG_SUNXI_USB_PHYS 2 - #endif - -+#if defined(CONFIG_MACH_SUN8I_H3) -+ #define CONFIG_SUNXI_DE2 1 -+#endif -+ - /* - * Include common sunxi configuration where most the settings are - */ diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h +index b0bfc0d..818408f 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h -@@ -277,16 +277,23 @@ extern int soft_i2c_gpio_scl; +@@ -276,16 +276,23 @@ extern int soft_i2c_gpio_scl; #define CONFIG_SUNXI_GPIO #ifdef CONFIG_VIDEO +/* Do we want to initialize a simple FB? */ +#define CONFIG_VIDEO_DT_SIMPLEFB -+#ifndef CONFIG_MACH_SUN8I_H3 -+#define CONFIG_VIDEO_SUNXI -+#else ++#ifdef CONFIG_MACH_SUN8I_H3 +#define CONFIG_VIDEO_SUNXI2 ++#else ++#define CONFIG_VIDEO_SUNXI +#endif + /* * The amount of RAM to keep free at the top of RAM when relocating u-boot, * to use as framebuffer. This must be a multiple of 4096. */ -+#ifndef CONFIG_VIDEO_SUNXI2 ++#ifdef CONFIG_VIDEO_SUNXI2 ++#define CONFIG_SUNXI_MAX_FB_SIZE (32 << 20) ++#else #define CONFIG_SUNXI_MAX_FB_SIZE (16 << 20) - -/* Do we want to initialize a simple FB? */ -#define CONFIG_VIDEO_DT_SIMPLEFB - -#define CONFIG_VIDEO_SUNXI -+#else -+#define CONFIG_SUNXI_MAX_FB_SIZE (32 << 20) +#endif #define CONFIG_VIDEO_LOGO #define CONFIG_VIDEO_STD_TIMINGS diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt +index 8814841..fdee9d9 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt -@@ -4357,6 +4357,7 @@ CONFIG_ST_SMI - CONFIG_SUN4 - CONFIG_SUNXI - CONFIG_SUNXI_AHCI -+CONFIG_SUNXI_DE2 - CONFIG_SUNXI_EMAC - CONFIG_SUNXI_GMAC - CONFIG_SUNXI_GPIO -@@ -8270,6 +8271,7 @@ CONFIG_VIDEO_SM501_8BPP +@@ -8165,6 +8165,7 @@ CONFIG_VIDEO_SM501_8BPP CONFIG_VIDEO_SM501_PCI CONFIG_VIDEO_STD_TIMINGS CONFIG_VIDEO_SUNXI @@ -1662,3 +1757,59 @@ diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt CONFIG_VIDEO_VCXK CONFIG_VID_FLS_ENV CONFIG_VM86 +diff --git a/configs/orangepi_2_defconfig b/configs/orangepi_2_defconfig +--- a/configs/orangepi_2_defconfig ++++ b/configs/orangepi_2_defconfig +@@ -16,3 +16,4 @@ CONFIG_SPL=y + CONFIG_SUN8I_EMAC=y + CONFIG_SY8106A_POWER=y + CONFIG_USB_EHCI_HCD=y ++CONFIG_VIDEO=y +diff --git a/configs/orangepi_lite_defconfig b/configs/orangepi_lite_defconfig +--- a/configs/orangepi_lite_defconfig ++++ b/configs/orangepi_lite_defconfig +@@ -12,3 +12,4 @@ CONFIG_SPL=y + # CONFIG_CMD_FLASH is not set + # CONFIG_CMD_FPGA is not set + CONFIG_USB_EHCI_HCD=y ++CONFIG_VIDEO=y +diff --git a/configs/orangepi_one_defconfig b/configs/orangepi_one_defconfig +--- a/configs/orangepi_one_defconfig ++++ b/configs/orangepi_one_defconfig +@@ -13,3 +13,4 @@ CONFIG_SPL=y + # CONFIG_CMD_FPGA is not set + CONFIG_SUN8I_EMAC=y + CONFIG_USB_EHCI_HCD=y ++CONFIG_VIDEO=y +diff --git a/configs/orangepi_pc_defconfig b/configs/orangepi_pc_defconfig +--- a/configs/orangepi_pc_defconfig ++++ b/configs/orangepi_pc_defconfig +@@ -15,3 +15,4 @@ CONFIG_SPL=y + CONFIG_SUN8I_EMAC=y + CONFIG_SY8106A_POWER=y + CONFIG_USB_EHCI_HCD=y ++CONFIG_VIDEO=y +diff --git a/configs/orangepi_pc_plus_defconfig b/configs/orangepi_pc_plus_defconfig +--- a/configs/orangepi_pc_plus_defconfig ++++ b/configs/orangepi_pc_plus_defconfig +@@ -16,3 +16,4 @@ CONFIG_SPL=y + CONFIG_SUN8I_EMAC=y + CONFIG_SY8106A_POWER=y + CONFIG_USB_EHCI_HCD=y ++CONFIG_VIDEO=y +diff --git a/configs/orangepi_plus2e_defconfig b/configs/orangepi_plus2e_defconfig +--- a/configs/orangepi_plus2e_defconfig ++++ b/configs/orangepi_plus2e_defconfig +@@ -17,3 +17,4 @@ CONFIG_SPL=y + CONFIG_SUN8I_EMAC=y + CONFIG_SY8106A_POWER=y + CONFIG_USB_EHCI_HCD=y ++CONFIG_VIDEO=y +diff --git a/configs/orangepi_plus_defconfig b/configs/orangepi_plus_defconfig +--- a/configs/orangepi_plus_defconfig ++++ b/configs/orangepi_plus_defconfig +@@ -18,3 +18,4 @@ CONFIG_SPL=y + CONFIG_SUN8I_EMAC=y + CONFIG_SY8106A_POWER=y + CONFIG_USB_EHCI_HCD=y ++CONFIG_VIDEO=y