From 9ba4563ad9207e00bd2b184f65404dbf8fe844d2 Mon Sep 17 00:00:00 2001 From: EvilOlaf Date: Wed, 4 Mar 2026 17:11:32 +0000 Subject: [PATCH] rockchip64: remove patches upstreamed in 6.19.6 --- ...icon-AV1-Fix-enable-cdef-computation.patch | 49 ------------ ...n-AV1-Set-IDR-flag-for-intra_only-fr.patch | 31 -------- ...isilicon-AV1-Fix-tx-mode-bit-setting.patch | 78 ------------------- 3 files changed, 158 deletions(-) delete mode 100644 patch/kernel/archive/rockchip64-6.19/media-0004-media-verisilicon-AV1-Fix-enable-cdef-computation.patch delete mode 100644 patch/kernel/archive/rockchip64-6.19/media-0005-media-verisilicon-AV1-Set-IDR-flag-for-intra_only-fr.patch delete mode 100644 patch/kernel/archive/rockchip64-6.19/media-0006-media-verisilicon-AV1-Fix-tx-mode-bit-setting.patch diff --git a/patch/kernel/archive/rockchip64-6.19/media-0004-media-verisilicon-AV1-Fix-enable-cdef-computation.patch b/patch/kernel/archive/rockchip64-6.19/media-0004-media-verisilicon-AV1-Fix-enable-cdef-computation.patch deleted file mode 100644 index 2298fd78c9..0000000000 --- a/patch/kernel/archive/rockchip64-6.19/media-0004-media-verisilicon-AV1-Fix-enable-cdef-computation.patch +++ /dev/null @@ -1,49 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Benjamin Gaignard -Date: Mon, 22 Sep 2025 13:15:02 +0200 -Subject: media: verisilicon: AV1: Fix enable cdef computation - -Testing V4L2_AV1_SEQUENCE_FLAG_ENABLE_CDEF flag isn't enough -to know if cdef bit has to be set. -If any of the used cdef fields isn't zero then we must enable -cdef feature on the hardware. - -Signed-off-by: Benjamin Gaignard -Fixes: 727a400686a2c ("media: verisilicon: Add Rockchip AV1 decoder") ---- - drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c | 10 ++++++++-- - 1 file changed, 8 insertions(+), 2 deletions(-) - -diff --git a/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c b/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c -+++ b/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c -@@ -1396,8 +1396,16 @@ static void rockchip_vpu981_av1_dec_set_cdef(struct hantro_ctx *ctx) - u16 luma_sec_strength = 0; - u32 chroma_pri_strength = 0; - u16 chroma_sec_strength = 0; -+ bool enable_cdef; - int i; - -+ enable_cdef = !(cdef->bits == 0 && -+ cdef->damping_minus_3 == 0 && -+ cdef->y_pri_strength[0] == 0 && -+ cdef->y_sec_strength[0] == 0 && -+ cdef->uv_pri_strength[0] == 0 && -+ cdef->uv_sec_strength[0] == 0); -+ hantro_reg_write(vpu, &av1_enable_cdef, enable_cdef); - hantro_reg_write(vpu, &av1_cdef_bits, cdef->bits); - hantro_reg_write(vpu, &av1_cdef_damping, cdef->damping_minus_3); - -@@ -1953,8 +1961,6 @@ static void rockchip_vpu981_av1_dec_set_parameters(struct hantro_ctx *ctx) - !!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_SHOW_FRAME)); - hantro_reg_write(vpu, &av1_switchable_motion_mode, - !!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_IS_MOTION_MODE_SWITCHABLE)); -- hantro_reg_write(vpu, &av1_enable_cdef, -- !!(ctrls->sequence->flags & V4L2_AV1_SEQUENCE_FLAG_ENABLE_CDEF)); - hantro_reg_write(vpu, &av1_allow_masked_compound, - !!(ctrls->sequence->flags - & V4L2_AV1_SEQUENCE_FLAG_ENABLE_MASKED_COMPOUND)); --- -Armbian - diff --git a/patch/kernel/archive/rockchip64-6.19/media-0005-media-verisilicon-AV1-Set-IDR-flag-for-intra_only-fr.patch b/patch/kernel/archive/rockchip64-6.19/media-0005-media-verisilicon-AV1-Set-IDR-flag-for-intra_only-fr.patch deleted file mode 100644 index b5121b2215..0000000000 --- a/patch/kernel/archive/rockchip64-6.19/media-0005-media-verisilicon-AV1-Set-IDR-flag-for-intra_only-fr.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Benjamin Gaignard -Date: Thu, 8 Jan 2026 10:56:28 +0100 -Subject: media: verisilicon: AV1: Set IDR flag for intra_only frame type - -Intra_only frame could be considered as a key frame so -Instantaneous Decoding Refresh (IDR) flag must be set of the both -case and not only for key frames. - -Signed-off-by: Benjamin Gaignard -Fixes: 727a400686a2c ("media: verisilicon: Add Rockchip AV1 decoder") ---- - drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c b/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c -+++ b/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c -@@ -1995,7 +1995,7 @@ static void rockchip_vpu981_av1_dec_set_parameters(struct hantro_ctx *ctx) - !!(ctrls->frame->quantization.flags - & V4L2_AV1_QUANTIZATION_FLAG_DELTA_Q_PRESENT)); - -- hantro_reg_write(vpu, &av1_idr_pic_e, !ctrls->frame->frame_type); -+ hantro_reg_write(vpu, &av1_idr_pic_e, IS_INTRA(ctrls->frame->frame_type)); - hantro_reg_write(vpu, &av1_quant_base_qindex, ctrls->frame->quantization.base_q_idx); - hantro_reg_write(vpu, &av1_bit_depth_y_minus8, ctx->bit_depth - 8); - hantro_reg_write(vpu, &av1_bit_depth_c_minus8, ctx->bit_depth - 8); --- -Armbian - diff --git a/patch/kernel/archive/rockchip64-6.19/media-0006-media-verisilicon-AV1-Fix-tx-mode-bit-setting.patch b/patch/kernel/archive/rockchip64-6.19/media-0006-media-verisilicon-AV1-Fix-tx-mode-bit-setting.patch deleted file mode 100644 index 63ab52c15d..0000000000 --- a/patch/kernel/archive/rockchip64-6.19/media-0006-media-verisilicon-AV1-Fix-tx-mode-bit-setting.patch +++ /dev/null @@ -1,78 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Benjamin Gaignard -Date: Tue, 9 Dec 2025 11:34:17 +0100 -Subject: media: verisilicon: AV1: Fix tx mode bit setting - -AV1 specification describes 3 possibles tx modes: 4x4 only, -largest and select. -Hardware allows 5 possibles tx modes: 4x4 only, 8x8, 16x16, -32x32 and select. -Since the both aren't exactly matching we need to add a mapping -function to set the correct mode on hardware. - -Signed-off-by: Benjamin Gaignard -Fixes: 727a400686a2c ("media: verisilicon: Add Rockchip AV1 decoder") ---- - drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c | 27 +++++++++- - 1 file changed, 26 insertions(+), 1 deletion(-) - -diff --git a/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c b/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c -+++ b/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c -@@ -72,6 +72,14 @@ - : AV1_DIV_ROUND_UP_POW2((_value_), (_n_))); \ - }) - -+enum rockchip_av1_tx_mode { -+ ROCKCHIP_AV1_TX_MODE_ONLY_4X4 = 0, -+ ROCKCHIP_AV1_TX_MODE_8X8 = 1, -+ ROCKCHIP_AV1_TX_MODE_16x16 = 2, -+ ROCKCHIP_AV1_TX_MODE_32x32 = 3, -+ ROCKCHIP_AV1_TX_MODE_SELECT = 4, -+}; -+ - struct rockchip_av1_film_grain { - u8 scaling_lut_y[256]; - u8 scaling_lut_cb[256]; -@@ -1935,11 +1943,26 @@ static void rockchip_vpu981_av1_dec_set_reference_frames(struct hantro_ctx *ctx) - rockchip_vpu981_av1_dec_set_other_frames(ctx); - } - -+static int rockchip_vpu981_av1_get_hardware_tx_mode(enum v4l2_av1_tx_mode tx_mode) -+{ -+ switch (tx_mode) { -+ case V4L2_AV1_TX_MODE_ONLY_4X4: -+ return ROCKCHIP_AV1_TX_MODE_ONLY_4X4; -+ case V4L2_AV1_TX_MODE_LARGEST: -+ return ROCKCHIP_AV1_TX_MODE_32x32; -+ case V4L2_AV1_TX_MODE_SELECT: -+ return ROCKCHIP_AV1_TX_MODE_SELECT; -+ } -+ -+ return ROCKCHIP_AV1_TX_MODE_32x32; -+} -+ - static void rockchip_vpu981_av1_dec_set_parameters(struct hantro_ctx *ctx) - { - struct hantro_dev *vpu = ctx->dev; - struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; - struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; -+ int tx_mode; - - hantro_reg_write(vpu, &av1_skip_mode, - !!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_SKIP_MODE_PRESENT)); -@@ -2005,7 +2028,9 @@ static void rockchip_vpu981_av1_dec_set_parameters(struct hantro_ctx *ctx) - !!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_ALLOW_HIGH_PRECISION_MV)); - hantro_reg_write(vpu, &av1_comp_pred_mode, - (ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_REFERENCE_SELECT) ? 2 : 0); -- hantro_reg_write(vpu, &av1_transform_mode, (ctrls->frame->tx_mode == 1) ? 3 : 4); -+ -+ tx_mode = rockchip_vpu981_av1_get_hardware_tx_mode(ctrls->frame->tx_mode); -+ hantro_reg_write(vpu, &av1_transform_mode, tx_mode); - hantro_reg_write(vpu, &av1_max_cb_size, - (ctrls->sequence->flags - & V4L2_AV1_SEQUENCE_FLAG_USE_128X128_SUPERBLOCK) ? 7 : 6); --- -Armbian -