diff --git a/config/linux-sunxi-dev.config b/config/linux-sunxi-dev.config index d26b0e0ed4..a8017f029c 100644 --- a/config/linux-sunxi-dev.config +++ b/config/linux-sunxi-dev.config @@ -1859,6 +1859,7 @@ CONFIG_ATM_DRIVERS=y CONFIG_ETHERNET=y CONFIG_NET_VENDOR_ALLWINNER=y CONFIG_SUN4I_EMAC=y +CONFIG_SUN8I_EMAC=y # CONFIG_ALTERA_TSE is not set # CONFIG_NET_VENDOR_ARC is not set # CONFIG_NET_VENDOR_AURORA is not set diff --git a/patch/kernel/sunxi-next/0000-sun8i-h3.patch b/patch/kernel/sunxi-dev/0000-sun8i-h3.patch similarity index 100% rename from patch/kernel/sunxi-next/0000-sun8i-h3.patch rename to patch/kernel/sunxi-dev/0000-sun8i-h3.patch diff --git a/patch/kernel/sunxi-next/0001-ARM-dts-sun8i-add-sun8i-emac-ethernet-driver.patch b/patch/kernel/sunxi-dev/0001-ARM-dts-sun8i-add-sun8i-emac-ethernet-driver.patch similarity index 100% rename from patch/kernel/sunxi-next/0001-ARM-dts-sun8i-add-sun8i-emac-ethernet-driver.patch rename to patch/kernel/sunxi-dev/0001-ARM-dts-sun8i-add-sun8i-emac-ethernet-driver.patch diff --git a/patch/kernel/sunxi-next/0002-ARM-dts-sun8i-Add-Orange-Pi-PC-support.patch b/patch/kernel/sunxi-dev/0002-ARM-dts-sun8i-Add-Orange-Pi-PC-support.patch similarity index 100% rename from patch/kernel/sunxi-next/0002-ARM-dts-sun8i-Add-Orange-Pi-PC-support.patch rename to patch/kernel/sunxi-dev/0002-ARM-dts-sun8i-Add-Orange-Pi-PC-support.patch diff --git a/patch/kernel/sunxi-next/0003-ARM-dts-sun8i-Enable-sun8i-emac-on-the-Orange-PI-PC.patch b/patch/kernel/sunxi-dev/0003-ARM-dts-sun8i-Enable-sun8i-emac-on-the-Orange-PI-PC.patch similarity index 100% rename from patch/kernel/sunxi-next/0003-ARM-dts-sun8i-Enable-sun8i-emac-on-the-Orange-PI-PC.patch rename to patch/kernel/sunxi-dev/0003-ARM-dts-sun8i-Enable-sun8i-emac-on-the-Orange-PI-PC.patch diff --git a/patch/kernel/sunxi-next/0005-ethernet-add-sun8i-emac-driver.patch b/patch/kernel/sunxi-dev/0005-ethernet-add-sun8i-emac-driver.patch similarity index 100% rename from patch/kernel/sunxi-next/0005-ethernet-add-sun8i-emac-driver.patch rename to patch/kernel/sunxi-dev/0005-ethernet-add-sun8i-emac-driver.patch diff --git a/patch/kernel/sunxi-next/OrangePI-01-h3-2733b9fa0ad18f1deb240d8d1ea92957d7f2270d.patch.disabled b/patch/kernel/sunxi-next/OrangePI-01-h3-2733b9fa0ad18f1deb240d8d1ea92957d7f2270d.patch.disabled deleted file mode 100644 index 3cabed7b6f..0000000000 --- a/patch/kernel/sunxi-next/OrangePI-01-h3-2733b9fa0ad18f1deb240d8d1ea92957d7f2270d.patch.disabled +++ /dev/null @@ -1,103 +0,0 @@ -From 2733b9fa0ad18f1deb240d8d1ea92957d7f2270d Mon Sep 17 00:00:00 2001 -From: Jens Kuske -Date: Tue, 27 Oct 2015 17:50:21 +0100 -Subject: [PATCH] clk: sunxi: Let divs clocks read the base factor clock name - from devicetree - -Currently, the sunxi clock driver gets the name for the base factor clock -of divs clocks from the name field in factors_data. This prevents reusing -of the factor clock for clocks with same properties, but different name. - -This commit makes the divs setup function try to get a name from -clock-output-names in the devicetree. It also removes the name field where -possible and merges the sun4i PLL5 and PLL6 clocks. - -Signed-off-by: Jens Kuske ---- - drivers/clk/sunxi/clk-sunxi.c | 38 +++++++++++++++++++++++++++----------- - 1 file changed, 27 insertions(+), 11 deletions(-) - -diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c -index 9c79af0c..270de427 100644 ---- a/drivers/clk/sunxi/clk-sunxi.c -+++ b/drivers/clk/sunxi/clk-sunxi.c -@@ -704,21 +704,12 @@ static const struct factors_data sun4i_pll5_data __initconst = { - .enable = 31, - .table = &sun4i_pll5_config, - .getter = sun4i_get_pll5_factors, -- .name = "pll5", --}; -- --static const struct factors_data sun4i_pll6_data __initconst = { -- .enable = 31, -- .table = &sun4i_pll5_config, -- .getter = sun4i_get_pll5_factors, -- .name = "pll6", - }; - - static const struct factors_data sun6i_a31_pll6_data __initconst = { - .enable = 31, - .table = &sun6i_a31_pll6_config, - .getter = sun6i_a31_get_pll6_factors, -- .name = "pll6x2", - }; - - static const struct factors_data sun5i_a13_ahb_data __initconst = { -@@ -902,6 +893,7 @@ struct gates_data { - - #define SUNXI_DIVS_MAX_QTY 4 - #define SUNXI_DIVISOR_WIDTH 2 -+#define SUNXI_DIVS_BASE_NAME_MAX_LEN 8 - - struct divs_data { - const struct factors_data *factors; /* data for the factor clock */ -@@ -941,7 +933,7 @@ static const struct divs_data pll5_divs_data __initconst = { - }; - - static const struct divs_data pll6_divs_data __initconst = { -- .factors = &sun4i_pll6_data, -+ .factors = &sun4i_pll5_data, - .ndivs = 4, - .div = { - { .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */ -@@ -983,6 +975,8 @@ static void __init sunxi_divs_clk_setup(struct device_node *node, - struct clk_gate *gate = NULL; - struct clk_fixed_factor *fix_factor; - struct clk_divider *divider; -+ struct factors_data factors = *data->factors; -+ char base_name[SUNXI_DIVS_BASE_NAME_MAX_LEN]; - void __iomem *reg; - int ndivs = SUNXI_DIVS_MAX_QTY, i = 0; - int flags, clkflags; -@@ -991,8 +985,30 @@ static void __init sunxi_divs_clk_setup(struct device_node *node, - if (data->ndivs) - ndivs = data->ndivs; - -+ /* Try to find a name for base factor clock */ -+ for (i = 0; i < ndivs; i++) { -+ if (data->div[i].self) { -+ of_property_read_string_index(node, "clock-output-names", -+ i, &factors.name); -+ break; -+ } -+ } -+ /* If we don't have a .self clk use the first output-name up to '_' */ -+ if (factors.name == NULL) { -+ of_property_read_string_index(node, "clock-output-names", -+ 0, &clk_name); -+ -+ for (i = 0; i < SUNXI_DIVS_BASE_NAME_MAX_LEN - 1 && -+ clk_name[i] != '_' && -+ clk_name[i] != '\0'; i++) -+ base_name[i] = clk_name[i]; -+ -+ base_name[i] = '\0'; -+ factors.name = base_name; -+ } -+ - /* Set up factor clock that we will be dividing */ -- pclk = sunxi_factors_clk_setup(node, data->factors); -+ pclk = sunxi_factors_clk_setup(node, &factors); - parent = __clk_get_name(pclk); - - reg = of_iomap(node, 0); diff --git a/patch/kernel/sunxi-next/OrangePI-02-h3-3bff045590a3dd40341398b4ba15859fb9f7001e.patch.disabled b/patch/kernel/sunxi-next/OrangePI-02-h3-3bff045590a3dd40341398b4ba15859fb9f7001e.patch.disabled deleted file mode 100644 index 4ba6c3cbf8..0000000000 --- a/patch/kernel/sunxi-next/OrangePI-02-h3-3bff045590a3dd40341398b4ba15859fb9f7001e.patch.disabled +++ /dev/null @@ -1,217 +0,0 @@ -From 3bff045590a3dd40341398b4ba15859fb9f7001e Mon Sep 17 00:00:00 2001 -From: Jens Kuske -Date: Tue, 27 Oct 2015 17:50:22 +0100 -Subject: [PATCH] clk: sunxi: Add H3 clocks support - -The H3 clock control unit is similar to the those of other sun8i family -members like the A23. - -It adds a new bus gates clock similar to the simple gates, but with a -different parent clock for each single gate. -Some of the gates use the new AHB2 clock as parent, whose clock source -is muxable between AHB1 and PLL6/2. The documentation isn't totally clear -about which devices belong to AHB2 now, especially USB EHIC/OHIC, so it -is mostly based on Allwinner kernel source code. - -Signed-off-by: Jens Kuske ---- - Documentation/devicetree/bindings/clock/sunxi.txt | 2 + - drivers/clk/sunxi/Makefile | 1 + - drivers/clk/sunxi/clk-sun8i-bus-gates.c | 111 ++++++++++++++++++++++ - drivers/clk/sunxi/clk-sunxi.c | 9 +- - 4 files changed, 122 insertions(+), 1 deletion(-) - create mode 100644 drivers/clk/sunxi/clk-sun8i-bus-gates.c - -diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt -index 8a47b77..d303decb3 100644 ---- a/Documentation/devicetree/bindings/clock/sunxi.txt -+++ b/Documentation/devicetree/bindings/clock/sunxi.txt -@@ -28,6 +28,7 @@ Required properties: - "allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20 - "allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31 - "allwinner,sun6i-a31-ahb1-clk" - for the AHB1 clock on A31 -+ "allwinner,sun8i-h3-ahb2-clk" - for the AHB2 clock on H3 - "allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31 - "allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23 - "allwinner,sun9i-a80-ahb0-gates-clk" - for the AHB0 gates on A80 -@@ -55,6 +56,7 @@ Required properties: - "allwinner,sun9i-a80-apb1-gates-clk" - for the APB1 gates on A80 - "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31 - "allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23 -+ "allwinner,sun8i-h3-bus-gates-clk" - for the bus gates on H3 - "allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13 - "allwinner,sun4i-a10-mmc-clk" - for the MMC clock - "allwinner,sun9i-a80-mmc-clk" - for mmc module clocks on A80 -diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile -index cb4c2992..f520af6 100644 ---- a/drivers/clk/sunxi/Makefile -+++ b/drivers/clk/sunxi/Makefile -@@ -10,6 +10,7 @@ obj-y += clk-a10-pll2.o - obj-y += clk-a20-gmac.o - obj-y += clk-mod0.o - obj-y += clk-simple-gates.o -+obj-y += clk-sun8i-bus-gates.o - obj-y += clk-sun8i-mbus.o - obj-y += clk-sun9i-core.o - obj-y += clk-sun9i-mmc.o -diff --git a/drivers/clk/sunxi/clk-sun8i-bus-gates.c b/drivers/clk/sunxi/clk-sun8i-bus-gates.c -new file mode 100644 -index 0000000..ad605fa4 ---- /dev/null -+++ b/drivers/clk/sunxi/clk-sun8i-bus-gates.c -@@ -0,0 +1,111 @@ -+/* -+ * Copyright (C) 2015 Jens Kuske -+ * -+ * Based on clk-simple-gates.c, which is: -+ * Copyright 2015 Maxime Ripard -+ * -+ * Maxime Ripard -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+static DEFINE_SPINLOCK(gates_lock); -+ -+static void __init sun8i_h3_bus_gates_init(struct device_node *node) -+{ -+ const char *clocks[] = { "ahb1", "ahb2", "apb1", "apb2" }; -+ enum { AHB1, AHB2, APB1, APB2 } clk_parent; -+ struct clk_onecell_data *clk_data; -+ const char *clk_name; -+ struct property *prop; -+ struct resource res; -+ void __iomem *clk_reg; -+ void __iomem *reg; -+ const __be32 *p; -+ int number, i; -+ u8 clk_bit; -+ u32 index; -+ -+ reg = of_io_request_and_map(node, 0, of_node_full_name(node)); -+ if (IS_ERR(reg)) -+ return; -+ -+ for (i = 0; i < ARRAY_SIZE(clocks); i++) { -+ index = of_property_match_string(node, "clock-names", clocks[i]); -+ if (index < 0) -+ return; -+ -+ clocks[i] = of_clk_get_parent_name(node, index); -+ } -+ -+ clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL); -+ if (!clk_data) -+ goto err_unmap; -+ -+ number = of_property_count_u32_elems(node, "clock-indices"); -+ of_property_read_u32_index(node, "clock-indices", number - 1, &number); -+ -+ clk_data->clks = kcalloc(number + 1, sizeof(struct clk *), GFP_KERNEL); -+ if (!clk_data->clks) -+ goto err_free_data; -+ -+ i = 0; -+ of_property_for_each_u32(node, "clock-indices", prop, p, index) { -+ of_property_read_string_index(node, "clock-output-names", -+ i, &clk_name); -+ -+ if (index == 17 || (index >= 29 && index <= 31)) -+ clk_parent = AHB2; -+ else if (index <= 63 || index >= 128) -+ clk_parent = AHB1; -+ else if (index >= 64 && index <= 95) -+ clk_parent = APB1; -+ else if (index >= 96 && index <= 127) -+ clk_parent = APB2; -+ -+ clk_reg = reg + 4 * (index / 32); -+ clk_bit = index % 32; -+ -+ clk_data->clks[index] = clk_register_gate(NULL, clk_name, -+ clocks[clk_parent], 0, -+ clk_reg, -+ clk_bit, -+ 0, &gates_lock); -+ i++; -+ -+ if (IS_ERR(clk_data->clks[index])) { -+ WARN_ON(true); -+ continue; -+ } -+ } -+ -+ clk_data->clk_num = number + 1; -+ of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); -+ -+ return; -+ -+err_free_data: -+ kfree(clk_data); -+err_unmap: -+ iounmap(reg); -+ of_address_to_resource(node, 0, &res); -+ release_mem_region(res.start, resource_size(&res)); -+} -+ -+CLK_OF_DECLARE(sun8i_h3_bus_gates, "allwinner,sun8i-h3-bus-gates-clk", -+ sun8i_h3_bus_gates_init); -diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c -index 270de427..6293c65 100644 ---- a/drivers/clk/sunxi/clk-sunxi.c -+++ b/drivers/clk/sunxi/clk-sunxi.c -@@ -769,6 +769,10 @@ static const struct mux_data sun6i_a31_ahb1_mux_data __initconst = { - .shift = 12, - }; - -+static const struct mux_data sun8i_h3_ahb2_mux_data __initconst = { -+ .shift = 0, -+}; -+ - static void __init sunxi_mux_clk_setup(struct device_node *node, - struct mux_data *data) - { -@@ -945,10 +949,11 @@ static const struct divs_data pll6_divs_data __initconst = { - - static const struct divs_data sun6i_a31_pll6_divs_data __initconst = { - .factors = &sun6i_a31_pll6_data, -- .ndivs = 2, -+ .ndivs = 3, - .div = { - { .fixed = 2 }, /* normal output */ - { .self = 1 }, /* base factor clock, 2x */ -+ { .fixed = 4 }, /* divided output, /2 */ - } - }; - -@@ -1146,6 +1151,7 @@ static const struct of_device_id clk_divs_match[] __initconst = { - static const struct of_device_id clk_mux_match[] __initconst = { - {.compatible = "allwinner,sun4i-a10-cpu-clk", .data = &sun4i_cpu_mux_data,}, - {.compatible = "allwinner,sun6i-a31-ahb1-mux-clk", .data = &sun6i_a31_ahb1_mux_data,}, -+ {.compatible = "allwinner,sun8i-h3-ahb2-clk", .data = &sun8i_h3_ahb2_mux_data,}, - {} - }; - -@@ -1228,6 +1234,7 @@ CLK_OF_DECLARE(sun6i_a31_clk_init, "allwinner,sun6i-a31", sun6i_init_clocks); - CLK_OF_DECLARE(sun6i_a31s_clk_init, "allwinner,sun6i-a31s", sun6i_init_clocks); - CLK_OF_DECLARE(sun8i_a23_clk_init, "allwinner,sun8i-a23", sun6i_init_clocks); - CLK_OF_DECLARE(sun8i_a33_clk_init, "allwinner,sun8i-a33", sun6i_init_clocks); -+CLK_OF_DECLARE(sun8i_h3_clk_init, "allwinner,sun8i-h3", sun6i_init_clocks); - - static void __init sun9i_init_clocks(struct device_node *node) - { diff --git a/patch/kernel/sunxi-next/OrangePI-03-h3-08c956b56c98e500ac79ac4957025c2c05460fad.patch.disabled b/patch/kernel/sunxi-next/OrangePI-03-h3-08c956b56c98e500ac79ac4957025c2c05460fad.patch.disabled deleted file mode 100644 index 14f7b981b2..0000000000 --- a/patch/kernel/sunxi-next/OrangePI-03-h3-08c956b56c98e500ac79ac4957025c2c05460fad.patch.disabled +++ /dev/null @@ -1,577 +0,0 @@ -From 08c956b56c98e500ac79ac4957025c2c05460fad Mon Sep 17 00:00:00 2001 -From: Jens Kuske -Date: Tue, 27 Oct 2015 17:50:23 +0100 -Subject: [PATCH] pinctrl: sunxi: Add H3 PIO controller support - -The H3 uses the same pin controller as previous SoC's from Allwinner. -Add support for the pins controlled by the main PIO controller. - -Signed-off-by: Jens Kuske -Acked-by: Maxime Ripard ---- - .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 + - drivers/pinctrl/sunxi/Kconfig | 4 + - drivers/pinctrl/sunxi/Makefile | 1 + - drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c | 516 +++++++++++++++++++++ - 4 files changed, 522 insertions(+) - create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c - -diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt -index b321b26..e6ba6028 100644 ---- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt -+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt -@@ -18,6 +18,7 @@ Required properties: - "allwinner,sun8i-a23-r-pinctrl" - "allwinner,sun8i-a33-pinctrl" - "allwinner,sun8i-a83t-pinctrl" -+ "allwinner,sun8i-h3-pinctrl" - - - reg: Should contain the register physical address and length for the - pin controller. -diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig -index e68fd95..89ab7f56a5 100644 ---- a/drivers/pinctrl/sunxi/Kconfig -+++ b/drivers/pinctrl/sunxi/Kconfig -@@ -51,6 +51,10 @@ config PINCTRL_SUN8I_A23_R - depends on RESET_CONTROLLER - select PINCTRL_SUNXI_COMMON - -+config PINCTRL_SUN8I_H3 -+ def_bool MACH_SUN8I -+ select PINCTRL_SUNXI_COMMON -+ - config PINCTRL_SUN9I_A80 - def_bool MACH_SUN9I - select PINCTRL_SUNXI_COMMON -diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile -index e080290..6bd818e 100644 ---- a/drivers/pinctrl/sunxi/Makefile -+++ b/drivers/pinctrl/sunxi/Makefile -@@ -13,4 +13,5 @@ obj-$(CONFIG_PINCTRL_SUN8I_A23) += pinctrl-sun8i-a23.o - obj-$(CONFIG_PINCTRL_SUN8I_A23_R) += pinctrl-sun8i-a23-r.o - obj-$(CONFIG_PINCTRL_SUN8I_A33) += pinctrl-sun8i-a33.o - obj-$(CONFIG_PINCTRL_SUN8I_A83T) += pinctrl-sun8i-a83t.o -+obj-$(CONFIG_PINCTRL_SUN8I_H3) += pinctrl-sun8i-h3.o - obj-$(CONFIG_PINCTRL_SUN9I_A80) += pinctrl-sun9i-a80.o -diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c -new file mode 100644 -index 0000000..98d465d ---- /dev/null -+++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c -@@ -0,0 +1,516 @@ -+/* -+ * Allwinner H3 SoCs pinctrl driver. -+ * -+ * Copyright (C) 2015 Jens Kuske -+ * -+ * Based on pinctrl-sun8i-a23.c, which is: -+ * Copyright (C) 2014 Chen-Yu Tsai -+ * Copyright (C) 2014 Maxime Ripard -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include "pinctrl-sunxi.h" -+ -+static const struct sunxi_desc_pin sun8i_h3_pins[] = { -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "uart2"), /* TX */ -+ SUNXI_FUNCTION(0x3, "jtag"), /* MS */ -+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PA_EINT0 */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "uart2"), /* RX */ -+ SUNXI_FUNCTION(0x3, "jtag"), /* CK */ -+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PA_EINT1 */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "uart2"), /* RTS */ -+ SUNXI_FUNCTION(0x3, "jtag"), /* DO */ -+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PA_EINT2 */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "uart2"), /* CTS */ -+ SUNXI_FUNCTION(0x3, "jtag"), /* DI */ -+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PA_EINT3 */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "uart0"), /* TX */ -+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PA_EINT4 */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "uart0"), /* RX */ -+ SUNXI_FUNCTION(0x3, "pwm0"), -+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PA_EINT5 */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "sim"), /* PWREN */ -+ SUNXI_FUNCTION(0x3, "pwm1"), -+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PA_EINT6 */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "sim"), /* CLK */ -+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PA_EINT7 */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "sim"), /* DATA */ -+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PA_EINT8 */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "sim"), /* RST */ -+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PA_EINT9 */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "sim"), /* DET */ -+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PA_EINT10 */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */ -+ SUNXI_FUNCTION(0x3, "di"), /* TX */ -+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PA_EINT11 */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "i2c0"), /* SDA */ -+ SUNXI_FUNCTION(0x3, "di"), /* RX */ -+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PA_EINT12 */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "spi1"), /* CS */ -+ SUNXI_FUNCTION(0x3, "uart3"), /* TX */ -+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)), /* PA_EINT13 */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "spi1"), /* CLK */ -+ SUNXI_FUNCTION(0x3, "uart3"), /* RX */ -+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)), /* PA_EINT14 */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */ -+ SUNXI_FUNCTION(0x3, "uart3"), /* RTS */ -+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), /* PA_EINT15 */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "spi1"), /* MISO */ -+ SUNXI_FUNCTION(0x3, "uart3"), /* CTS */ -+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), /* PA_EINT16 */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "spdif"), /* OUT */ -+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)), /* PA_EINT17 */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 18), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "i2s0"), /* SYNC */ -+ SUNXI_FUNCTION(0x3, "i2c1"), /* SCK */ -+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)), /* PA_EINT18 */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 19), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "i2s0"), /* CLK */ -+ SUNXI_FUNCTION(0x3, "i2c1"), /* SDA */ -+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 19)), /* PA_EINT19 */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 20), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "i2s0"), /* DOUT */ -+ SUNXI_FUNCTION(0x3, "sim"), /* VPPEN */ -+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 20)), /* PA_EINT20 */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 21), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "i2s0"), /* DIN */ -+ SUNXI_FUNCTION(0x3, "sim"), /* VPPPP */ -+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 21)), /* PA_EINT21 */ -+ /* Hole */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "nand0"), /* WE */ -+ SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "nand0"), /* ALE */ -+ SUNXI_FUNCTION(0x3, "spi0")), /* MISO */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "nand0"), /* CLE */ -+ SUNXI_FUNCTION(0x3, "spi0")), /* CLK */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "nand0"), /* CE1 */ -+ SUNXI_FUNCTION(0x3, "spi0")), /* CS */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "nand0")), /* CE0 */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "nand0"), /* RE */ -+ SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */ -+ SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "nand0")), /* RB1 */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */ -+ SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */ -+ SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */ -+ SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */ -+ SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */ -+ SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */ -+ SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "nand"), /* DQ6 */ -+ SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "nand"), /* DQ7 */ -+ SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "nand"), /* DQS */ -+ SUNXI_FUNCTION(0x3, "mmc2")), /* RST */ -+ /* Hole */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "emac")), /* RXD3 */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "emac")), /* RXD2 */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "emac")), /* RXD1 */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "emac")), /* RXD0 */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "emac")), /* RXCK */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "emac")), /* RXCTL/RCDV */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "emac")), /* RXERR */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "emac")), /* TXD3 */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "emac")), /* TXD2L */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "emac")), /* TXD1 */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "emac")), /* TXD0 */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "emac")), /* CRS */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "emac")), /* TXCK */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "emac")), /* TXCTL/TXEN */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "emac")), /* TXERR */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "emac")), /* CLKIN/COL */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "emac")), /* MDC */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "emac")), /* MDIO */ -+ /* Hole */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "csi"), /* PCLK */ -+ SUNXI_FUNCTION(0x3, "ts")), /* CLK */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "csi"), /* MCLK */ -+ SUNXI_FUNCTION(0x3, "ts")), /* ERR */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */ -+ SUNXI_FUNCTION(0x3, "ts")), /* SYNC */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */ -+ SUNXI_FUNCTION(0x3, "ts")), /* DVLD */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "csi"), /* D0 */ -+ SUNXI_FUNCTION(0x3, "ts")), /* D0 */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "csi"), /* D1 */ -+ SUNXI_FUNCTION(0x3, "ts")), /* D1 */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "csi"), /* D2 */ -+ SUNXI_FUNCTION(0x3, "ts")), /* D2 */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "csi"), /* D3 */ -+ SUNXI_FUNCTION(0x3, "ts")), /* D3 */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "csi"), /* D4 */ -+ SUNXI_FUNCTION(0x3, "ts")), /* D4 */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "csi"), /* D5 */ -+ SUNXI_FUNCTION(0x3, "ts")), /* D5 */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "csi"), /* D6 */ -+ SUNXI_FUNCTION(0x3, "ts")), /* D6 */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "csi"), /* D7 */ -+ SUNXI_FUNCTION(0x3, "ts")), /* D7 */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "csi"), /* SCK */ -+ SUNXI_FUNCTION(0x3, "i2c2")), /* SCK */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "csi"), /* SDA */ -+ SUNXI_FUNCTION(0x3, "i2c2")), /* SDA */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out")), -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out")), -+ /* Hole */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */ -+ SUNXI_FUNCTION(0x3, "jtag")), /* MS */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */ -+ SUNXI_FUNCTION(0x3, "jtag")), /* DI */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */ -+ SUNXI_FUNCTION(0x3, "uart0")), /* TX */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */ -+ SUNXI_FUNCTION(0x3, "jtag")), /* DO */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */ -+ SUNXI_FUNCTION(0x3, "uart0")), /* RX */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */ -+ SUNXI_FUNCTION(0x3, "jtag")), /* CK */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "mmc0")), /* DET */ -+ /* Hole */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */ -+ SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 0)), /* PG_EINT0 */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */ -+ SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 1)), /* PG_EINT1 */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */ -+ SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 2)), /* PG_EINT2 */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */ -+ SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 3)), /* PG_EINT3 */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */ -+ SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 4)), /* PG_EINT4 */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */ -+ SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 5)), /* PG_EINT5 */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "uart1"), /* TX */ -+ SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 6)), /* PG_EINT6 */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "uart1"), /* RX */ -+ SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 7)), /* PG_EINT7 */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "uart1"), /* RTS */ -+ SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 8)), /* PG_EINT8 */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "uart1"), /* CTS */ -+ SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 9)), /* PG_EINT9 */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "i2s1"), /* SYNC */ -+ SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 10)), /* PG_EINT10 */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "i2s1"), /* CLK */ -+ SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 11)), /* PG_EINT11 */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "i2s1"), /* DOUT */ -+ SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 12)), /* PG_EINT12 */ -+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13), -+ SUNXI_FUNCTION(0x0, "gpio_in"), -+ SUNXI_FUNCTION(0x1, "gpio_out"), -+ SUNXI_FUNCTION(0x2, "i2s1"), /* DIN */ -+ SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 13)), /* PG_EINT13 */ -+}; -+ -+static const struct sunxi_pinctrl_desc sun8i_h3_pinctrl_data = { -+ .pins = sun8i_h3_pins, -+ .npins = ARRAY_SIZE(sun8i_h3_pins), -+ .irq_banks = 2, -+}; -+ -+static int sun8i_h3_pinctrl_probe(struct platform_device *pdev) -+{ -+ return sunxi_pinctrl_init(pdev, -+ &sun8i_h3_pinctrl_data); -+} -+ -+static const struct of_device_id sun8i_h3_pinctrl_match[] = { -+ { .compatible = "allwinner,sun8i-h3-pinctrl", }, -+ {} -+}; -+ -+static struct platform_driver sun8i_h3_pinctrl_driver = { -+ .probe = sun8i_h3_pinctrl_probe, -+ .driver = { -+ .name = "sun8i-h3-pinctrl", -+ .of_match_table = sun8i_h3_pinctrl_match, -+ }, -+}; -+builtin_platform_driver(sun8i_h3_pinctrl_driver); diff --git a/patch/kernel/sunxi-next/OrangePI-04-h3-e49065f413b616b6c2fa794e20510f821361f08d.patch.disabled b/patch/kernel/sunxi-next/OrangePI-04-h3-e49065f413b616b6c2fa794e20510f821361f08d.patch.disabled deleted file mode 100644 index 389b2009eb..0000000000 --- a/patch/kernel/sunxi-next/OrangePI-04-h3-e49065f413b616b6c2fa794e20510f821361f08d.patch.disabled +++ /dev/null @@ -1,95 +0,0 @@ -From e49065f413b616b6c2fa794e20510f821361f08d Mon Sep 17 00:00:00 2001 -From: Jens Kuske -Date: Tue, 27 Oct 2015 17:50:24 +0100 -Subject: [PATCH] reset: sunxi: Add Allwinner H3 bus resets - -The H3 bus resets have some holes between the registers, so we add -an of_xlate() function to skip them according to the datasheet. - -Signed-off-by: Jens Kuske ---- - .../bindings/reset/allwinner,sunxi-clock-reset.txt | 1 + - drivers/reset/reset-sunxi.c | 30 +++++++++++++++++++--- - 2 files changed, 28 insertions(+), 3 deletions(-) - -diff --git a/Documentation/devicetree/bindings/reset/allwinner,sunxi-clock-reset.txt b/Documentation/devicetree/bindings/reset/allwinner,sunxi-clock-reset.txt -index c8f77571..e11f023 100644 ---- a/Documentation/devicetree/bindings/reset/allwinner,sunxi-clock-reset.txt -+++ b/Documentation/devicetree/bindings/reset/allwinner,sunxi-clock-reset.txt -@@ -8,6 +8,7 @@ Required properties: - - compatible: Should be one of the following: - "allwinner,sun6i-a31-ahb1-reset" - "allwinner,sun6i-a31-clock-reset" -+ "allwinner,sun8i-h3-bus-reset" - - reg: should be register base and length as documented in the - datasheet - - #reset-cells: 1, see below -diff --git a/drivers/reset/reset-sunxi.c b/drivers/reset/reset-sunxi.c -index 3d95c87..c91e1469 100644 ---- a/drivers/reset/reset-sunxi.c -+++ b/drivers/reset/reset-sunxi.c -@@ -75,7 +75,9 @@ static struct reset_control_ops sunxi_reset_ops = { - .deassert = sunxi_reset_deassert, - }; - --static int sunxi_reset_init(struct device_node *np) -+static int sunxi_reset_init(struct device_node *np, -+ int (*of_xlate)(struct reset_controller_dev *rcdev, -+ const struct of_phandle_args *reset_spec)) - { - struct sunxi_reset_data *data; - struct resource res; -@@ -108,6 +110,7 @@ static int sunxi_reset_init(struct device_node *np) - data->rcdev.nr_resets = size * 32; - data->rcdev.ops = &sunxi_reset_ops; - data->rcdev.of_node = np; -+ data->rcdev.of_xlate = of_xlate; - reset_controller_register(&data->rcdev); - - return 0; -@@ -117,6 +120,21 @@ static int sunxi_reset_init(struct device_node *np) - return ret; - }; - -+static int sun8i_h3_bus_reset_xlate(struct reset_controller_dev *rcdev, -+ const struct of_phandle_args *reset_spec) -+{ -+ unsigned int index = reset_spec->args[0]; -+ -+ if (index < 96) -+ return index; -+ else if (index < 128) -+ return index + 32; -+ else if (index < 160) -+ return index + 64; -+ else -+ return -EINVAL; -+} -+ - /* - * These are the reset controller we need to initialize early on in - * our system, before we can even think of using a regular device -@@ -124,15 +142,21 @@ static int sunxi_reset_init(struct device_node *np) - */ - static const struct of_device_id sunxi_early_reset_dt_ids[] __initdata = { - { .compatible = "allwinner,sun6i-a31-ahb1-reset", }, -+ { .compatible = "allwinner,sun8i-h3-bus-reset", .data = sun8i_h3_bus_reset_xlate, }, - { /* sentinel */ }, - }; - - void __init sun6i_reset_init(void) - { - struct device_node *np; -+ const struct of_device_id *match; -+ int (*of_xlate)(struct reset_controller_dev *rcdev, -+ const struct of_phandle_args *reset_spec); - -- for_each_matching_node(np, sunxi_early_reset_dt_ids) -- sunxi_reset_init(np); -+ for_each_matching_node_and_match(np, sunxi_early_reset_dt_ids, &match) { -+ of_xlate = match->data; -+ sunxi_reset_init(np, of_xlate); -+ } - } - - /* diff --git a/patch/kernel/sunxi-next/OrangePI-05-h3-1832b6cde1381ac783d5921c2c916bf1423aa60f.patch.disabled b/patch/kernel/sunxi-next/OrangePI-05-h3-1832b6cde1381ac783d5921c2c916bf1423aa60f.patch.disabled deleted file mode 100644 index 2eeceb4d7b..0000000000 --- a/patch/kernel/sunxi-next/OrangePI-05-h3-1832b6cde1381ac783d5921c2c916bf1423aa60f.patch.disabled +++ /dev/null @@ -1,502 +0,0 @@ -From 1832b6cde1381ac783d5921c2c916bf1423aa60f Mon Sep 17 00:00:00 2001 -From: Jens Kuske -Date: Tue, 27 Oct 2015 17:50:25 +0100 -Subject: [PATCH] ARM: dts: sunxi: Add Allwinner H3 DTSI - -The Allwinner H3 is a home entertainment system oriented SoC with -four Cortex-A7 cores and a Mali-400MP2 GPU. - -Signed-off-by: Jens Kuske ---- - arch/arm/boot/dts/sun8i-h3.dtsi | 482 ++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 482 insertions(+) - create mode 100644 arch/arm/boot/dts/sun8i-h3.dtsi - -diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi -new file mode 100644 -index 0000000..c18b5f7c ---- /dev/null -+++ b/arch/arm/boot/dts/sun8i-h3.dtsi -@@ -0,0 +1,482 @@ -+/* -+ * Copyright (C) 2015 Jens Kuske -+ * -+ * This file is dual-licensed: you can use it either under the terms -+ * of the GPL or the X11 license, at your option. Note that this dual -+ * licensing only applies to this file, and not this project as a -+ * whole. -+ * -+ * a) This file is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * This file is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * Or, alternatively, -+ * -+ * b) Permission is hereby granted, free of charge, to any person -+ * obtaining a copy of this software and associated documentation -+ * files (the "Software"), to deal in the Software without -+ * restriction, including without limitation the rights to use, -+ * copy, modify, merge, publish, distribute, sublicense, and/or -+ * sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following -+ * conditions: -+ * -+ * The above copyright notice and this permission notice shall be -+ * included in all copies or substantial portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -+ * OTHER DEALINGS IN THE SOFTWARE. -+ */ -+ -+#include "skeleton.dtsi" -+ -+#include -+#include -+ -+/ { -+ interrupt-parent = <&gic>; -+ -+ cpus { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ cpu@0 { -+ compatible = "arm,cortex-a7"; -+ device_type = "cpu"; -+ reg = <0>; -+ }; -+ -+ cpu@1 { -+ compatible = "arm,cortex-a7"; -+ device_type = "cpu"; -+ reg = <1>; -+ }; -+ -+ cpu@2 { -+ compatible = "arm,cortex-a7"; -+ device_type = "cpu"; -+ reg = <2>; -+ }; -+ -+ cpu@3 { -+ compatible = "arm,cortex-a7"; -+ device_type = "cpu"; -+ reg = <3>; -+ }; -+ }; -+ -+ timer { -+ compatible = "arm,armv7-timer"; -+ interrupts = , -+ , -+ , -+ ; -+ clock-frequency = <24000000>; -+ arm,cpu-registers-not-fw-configured; -+ }; -+ -+ memory { -+ reg = <0x40000000 0x80000000>; -+ }; -+ -+ clocks { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ -+ osc24M: osc24M_clk { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <24000000>; -+ clock-output-names = "osc24M"; -+ }; -+ -+ osc32k: osc32k_clk { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <32768>; -+ clock-output-names = "osc32k"; -+ }; -+ -+ pll1: clk@01c20000 { -+ #clock-cells = <0>; -+ compatible = "allwinner,sun8i-a23-pll1-clk"; -+ reg = <0x01c20000 0x4>; -+ clocks = <&osc24M>; -+ clock-output-names = "pll1"; -+ }; -+ -+ /* dummy clock until actually implemented */ -+ pll5: pll5_clk { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <0>; -+ clock-output-names = "pll5"; -+ }; -+ -+ pll6: clk@01c20028 { -+ #clock-cells = <1>; -+ compatible = "allwinner,sun6i-a31-pll6-clk"; -+ reg = <0x01c20028 0x4>; -+ clocks = <&osc24M>; -+ clock-output-names = "pll6", "pll6x2", "pll6d2"; -+ }; -+ -+ pll8: clk@01c20044 { -+ #clock-cells = <1>; -+ compatible = "allwinner,sun6i-a31-pll6-clk"; -+ reg = <0x01c20044 0x4>; -+ clocks = <&osc24M>; -+ clock-output-names = "pll8", "pll8x2"; -+ }; -+ -+ cpu: cpu_clk@01c20050 { -+ #clock-cells = <0>; -+ compatible = "allwinner,sun4i-a10-cpu-clk"; -+ reg = <0x01c20050 0x4>; -+ clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>; -+ clock-output-names = "cpu"; -+ }; -+ -+ axi: axi_clk@01c20050 { -+ #clock-cells = <0>; -+ compatible = "allwinner,sun4i-a10-axi-clk"; -+ reg = <0x01c20050 0x4>; -+ clocks = <&cpu>; -+ clock-output-names = "axi"; -+ }; -+ -+ ahb1: ahb1_clk@01c20054 { -+ #clock-cells = <0>; -+ compatible = "allwinner,sun6i-a31-ahb1-clk"; -+ reg = <0x01c20054 0x4>; -+ clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>; -+ clock-output-names = "ahb1"; -+ }; -+ -+ ahb2: ahb2_clk@01c2005c { -+ #clock-cells = <0>; -+ compatible = "allwinner,sun8i-h3-ahb2-clk"; -+ reg = <0x01c2005c 0x4>; -+ clocks = <&ahb1>, <&pll6 2>; -+ clock-output-names = "ahb2"; -+ }; -+ -+ apb1: apb1_clk@01c20054 { -+ #clock-cells = <0>; -+ compatible = "allwinner,sun4i-a10-apb0-clk"; -+ reg = <0x01c20054 0x4>; -+ clocks = <&ahb1>; -+ clock-output-names = "apb1"; -+ }; -+ -+ apb2: apb2_clk@01c20058 { -+ #clock-cells = <0>; -+ compatible = "allwinner,sun4i-a10-apb1-clk"; -+ reg = <0x01c20058 0x4>; -+ clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>; -+ clock-output-names = "apb2"; -+ }; -+ -+ bus_gates: clk@01c20060 { -+ #clock-cells = <1>; -+ compatible = "allwinner,sun8i-h3-bus-gates-clk"; -+ reg = <0x01c20060 0x14>; -+ clocks = <&ahb1>, <&ahb2>, <&apb1>, <&apb2>; -+ clock-names = "ahb1", "ahb2", "apb1", "apb2"; -+ clock-indices = <5>, <6>, <8>, -+ <9>, <10>, <13>, -+ <14>, <17>, <18>, -+ <19>, <20>, -+ <21>, <23>, -+ <24>, <25>, -+ <26>, <27>, -+ <28>, <29>, -+ <30>, <31>, <32>, -+ <35>, <36>, <37>, -+ <40>, <41>, <43>, -+ <44>, <52>, <53>, -+ <54>, <64>, -+ <65>, <69>, <72>, -+ <76>, <77>, <78>, -+ <96>, <97>, <98>, -+ <112>, <113>, -+ <114>, <115>, <116>, -+ <128>, <135>; -+ clock-output-names = "ahb1_ce", "ahb1_dma", "ahb1_mmc0", -+ "ahb1_mmc1", "ahb1_mmc2", "ahb1_nand", -+ "ahb1_sdram", "ahb2_gmac", "ahb1_ts", -+ "ahb1_hstimer", "ahb1_spi0", -+ "ahb1_spi1", "ahb1_otg", -+ "ahb1_otg_ehci0", "ahb1_ehic1", -+ "ahb1_ehic2", "ahb1_ehic3", -+ "ahb1_otg_ohci0", "ahb2_ohic1", -+ "ahb2_ohic2", "ahb2_ohic3", "ahb1_ve", -+ "ahb1_lcd0", "ahb1_lcd1", "ahb1_deint", -+ "ahb1_csi", "ahb1_tve", "ahb1_hdmi", -+ "ahb1_de", "ahb1_gpu", "ahb1_msgbox", -+ "ahb1_spinlock", "apb1_codec", -+ "apb1_spdif", "apb1_pio", "apb1_ths", -+ "apb1_i2s0", "apb1_i2s1", "apb1_i2s2", -+ "apb2_i2c0", "apb2_i2c1", "apb2_i2c2", -+ "apb2_uart0", "apb2_uart1", -+ "apb2_uart2", "apb2_uart3", "apb2_scr", -+ "ahb1_ephy", "ahb1_dbg"; -+ }; -+ -+ mmc0_clk: clk@01c20088 { -+ #clock-cells = <1>; -+ compatible = "allwinner,sun4i-a10-mmc-clk"; -+ reg = <0x01c20088 0x4>; -+ clocks = <&osc24M>, <&pll6 0>, <&pll8 0>; -+ clock-output-names = "mmc0", -+ "mmc0_output", -+ "mmc0_sample"; -+ }; -+ -+ mmc1_clk: clk@01c2008c { -+ #clock-cells = <1>; -+ compatible = "allwinner,sun4i-a10-mmc-clk"; -+ reg = <0x01c2008c 0x4>; -+ clocks = <&osc24M>, <&pll6 0>, <&pll8 0>; -+ clock-output-names = "mmc1", -+ "mmc1_output", -+ "mmc1_sample"; -+ }; -+ -+ mmc2_clk: clk@01c20090 { -+ #clock-cells = <1>; -+ compatible = "allwinner,sun4i-a10-mmc-clk"; -+ reg = <0x01c20090 0x4>; -+ clocks = <&osc24M>, <&pll6 0>, <&pll8 0>; -+ clock-output-names = "mmc2", -+ "mmc2_output", -+ "mmc2_sample"; -+ }; -+ -+ mbus_clk: clk@01c2015c { -+ #clock-cells = <0>; -+ compatible = "allwinner,sun8i-a23-mbus-clk"; -+ reg = <0x01c2015c 0x4>; -+ clocks = <&osc24M>, <&pll6 1>, <&pll5>; -+ clock-output-names = "mbus"; -+ }; -+ }; -+ -+ soc { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ -+ dma: dma-controller@01c02000 { -+ compatible = "allwinner,sun8i-h3-dma"; -+ reg = <0x01c02000 0x1000>; -+ interrupts = ; -+ clocks = <&bus_gates 6>; -+ resets = <&bus_rst 6>; -+ #dma-cells = <1>; -+ }; -+ -+ mmc0: mmc@01c0f000 { -+ compatible = "allwinner,sun5i-a13-mmc"; -+ reg = <0x01c0f000 0x1000>; -+ clocks = <&bus_gates 8>, -+ <&mmc0_clk 0>, -+ <&mmc0_clk 1>, -+ <&mmc0_clk 2>; -+ clock-names = "ahb", -+ "mmc", -+ "output", -+ "sample"; -+ resets = <&bus_rst 8>; -+ reset-names = "ahb"; -+ interrupts = ; -+ status = "disabled"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ mmc1: mmc@01c10000 { -+ compatible = "allwinner,sun5i-a13-mmc"; -+ reg = <0x01c10000 0x1000>; -+ clocks = <&bus_gates 9>, -+ <&mmc1_clk 0>, -+ <&mmc1_clk 1>, -+ <&mmc1_clk 2>; -+ clock-names = "ahb", -+ "mmc", -+ "output", -+ "sample"; -+ resets = <&bus_rst 9>; -+ reset-names = "ahb"; -+ interrupts = ; -+ status = "disabled"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ mmc2: mmc@01c11000 { -+ compatible = "allwinner,sun5i-a13-mmc"; -+ reg = <0x01c11000 0x1000>; -+ clocks = <&bus_gates 10>, -+ <&mmc2_clk 0>, -+ <&mmc2_clk 1>, -+ <&mmc2_clk 2>; -+ clock-names = "ahb", -+ "mmc", -+ "output", -+ "sample"; -+ resets = <&bus_rst 10>; -+ reset-names = "ahb"; -+ interrupts = ; -+ status = "disabled"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ pio: pinctrl@01c20800 { -+ compatible = "allwinner,sun8i-h3-pinctrl"; -+ reg = <0x01c20800 0x400>; -+ interrupts = , -+ ; -+ clocks = <&bus_gates 69>; -+ gpio-controller; -+ #gpio-cells = <3>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ -+ uart0_pins_a: uart0@0 { -+ allwinner,pins = "PA4", "PA5"; -+ allwinner,function = "uart0"; -+ allwinner,drive = ; -+ allwinner,pull = ; -+ }; -+ -+ mmc0_pins_a: mmc0@0 { -+ allwinner,pins = "PF0", "PF1", "PF2", "PF3", -+ "PF4", "PF5"; -+ allwinner,function = "mmc0"; -+ allwinner,drive = ; -+ allwinner,pull = ; -+ }; -+ -+ mmc0_cd_pin: mmc0_cd_pin@0 { -+ allwinner,pins = "PF6"; -+ allwinner,function = "gpio_in"; -+ allwinner,drive = ; -+ allwinner,pull = ; -+ }; -+ -+ mmc1_pins_a: mmc1@0 { -+ allwinner,pins = "PG0", "PG1", "PG2", "PG3", -+ "PG4", "PG5"; -+ allwinner,function = "mmc1"; -+ allwinner,drive = ; -+ allwinner,pull = ; -+ }; -+ }; -+ -+ bus_rst: reset@01c202c0 { -+ #reset-cells = <1>; -+ compatible = "allwinner,sun8i-h3-bus-reset"; -+ reg = <0x01c202c0 0x1c>; -+ }; -+ -+ timer@01c20c00 { -+ compatible = "allwinner,sun4i-a10-timer"; -+ reg = <0x01c20c00 0xa0>; -+ interrupts = , -+ ; -+ clocks = <&osc24M>; -+ }; -+ -+ wdt0: watchdog@01c20ca0 { -+ compatible = "allwinner,sun6i-a31-wdt"; -+ reg = <0x01c20ca0 0x20>; -+ interrupts = ; -+ }; -+ -+ uart0: serial@01c28000 { -+ compatible = "snps,dw-apb-uart"; -+ reg = <0x01c28000 0x400>; -+ interrupts = ; -+ reg-shift = <2>; -+ reg-io-width = <4>; -+ clocks = <&bus_gates 112>; -+ resets = <&bus_rst 144>; -+ dmas = <&dma 6>, <&dma 6>; -+ dma-names = "rx", "tx"; -+ status = "disabled"; -+ }; -+ -+ uart1: serial@01c28400 { -+ compatible = "snps,dw-apb-uart"; -+ reg = <0x01c28400 0x400>; -+ interrupts = ; -+ reg-shift = <2>; -+ reg-io-width = <4>; -+ clocks = <&bus_gates 113>; -+ resets = <&bus_rst 145>; -+ dmas = <&dma 7>, <&dma 7>; -+ dma-names = "rx", "tx"; -+ status = "disabled"; -+ }; -+ -+ uart2: serial@01c28800 { -+ compatible = "snps,dw-apb-uart"; -+ reg = <0x01c28800 0x400>; -+ interrupts = ; -+ reg-shift = <2>; -+ reg-io-width = <4>; -+ clocks = <&bus_gates 114>; -+ resets = <&bus_rst 146>; -+ dmas = <&dma 8>, <&dma 8>; -+ dma-names = "rx", "tx"; -+ status = "disabled"; -+ }; -+ -+ uart3: serial@01c28c00 { -+ compatible = "snps,dw-apb-uart"; -+ reg = <0x01c28c00 0x400>; -+ interrupts = ; -+ reg-shift = <2>; -+ reg-io-width = <4>; -+ clocks = <&bus_gates 115>; -+ resets = <&bus_rst 147>; -+ dmas = <&dma 9>, <&dma 9>; -+ dma-names = "rx", "tx"; -+ status = "disabled"; -+ }; -+ -+ gic: interrupt-controller@01c81000 { -+ compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; -+ reg = <0x01c81000 0x1000>, -+ <0x01c82000 0x1000>, -+ <0x01c84000 0x2000>, -+ <0x01c86000 0x2000>; -+ interrupt-controller; -+ #interrupt-cells = <3>; -+ interrupts = ; -+ }; -+ -+ rtc: rtc@01f00000 { -+ compatible = "allwinner,sun6i-a31-rtc"; -+ reg = <0x01f00000 0x54>; -+ interrupts = , -+ ; -+ }; -+ }; -+}; diff --git a/patch/kernel/sunxi-next/OrangePI-06-h3-4e776aacfc9f723783806246cea618f413db55e3.patch.disabled b/patch/kernel/sunxi-next/OrangePI-06-h3-4e776aacfc9f723783806246cea618f413db55e3.patch.disabled deleted file mode 100644 index 732f226ef0..0000000000 --- a/patch/kernel/sunxi-next/OrangePI-06-h3-4e776aacfc9f723783806246cea618f413db55e3.patch.disabled +++ /dev/null @@ -1,115 +0,0 @@ -From 4e776aacfc9f723783806246cea618f413db55e3 Mon Sep 17 00:00:00 2001 -From: Jens Kuske -Date: Tue, 27 Oct 2015 17:50:26 +0100 -Subject: [PATCH] ARM: dts: sun8i: Add Orange Pi Plus support - -The Orange Pi Plus is a SBC based on the Allwinner H3 SoC -with 8GB eMMC, multiple USB ports through a USB hub chip, SATA through -a USB-SATA bridge, one uSD slot, a 10/100/1000M ethernet port, -WiFi, HDMI, headphone jack, IR receiver, a microphone, a CSI connector -and a 40-pin GPIO header. - -Signed-off-by: Jens Kuske ---- - arch/arm/boot/dts/Makefile | 3 +- - arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 77 ++++++++++++++++++++++++++++ - 2 files changed, 79 insertions(+), 1 deletion(-) - create mode 100644 arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts - -diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile -index 30bbc374..4e8026e 100644 ---- a/arch/arm/boot/dts/Makefile -+++ b/arch/arm/boot/dts/Makefile -@@ -660,7 +660,8 @@ dtb-$(CONFIG_MACH_SUN8I) += \ - sun8i-a33-ga10h-v1.1.dtb \ - sun8i-a33-ippo-q8h-v1.2.dtb \ - sun8i-a33-q8-tablet.dtb \ -- sun8i-a33-sinlinx-sina33.dtb -+ sun8i-a33-sinlinx-sina33.dtb \ -+ sun8i-h3-orangepi-plus.dtb - dtb-$(CONFIG_MACH_SUN9I) += \ - sun9i-a80-optimus.dtb \ - sun9i-a80-cubieboard4.dtb -diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts -new file mode 100644 -index 0000000..e67df59 ---- /dev/null -+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts -@@ -0,0 +1,77 @@ -+/* -+ * Copyright (C) 2015 Jens Kuske -+ * -+ * This file is dual-licensed: you can use it either under the terms -+ * of the GPL or the X11 license, at your option. Note that this dual -+ * licensing only applies to this file, and not this project as a -+ * whole. -+ * -+ * a) This file is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * This file is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * Or, alternatively, -+ * -+ * b) Permission is hereby granted, free of charge, to any person -+ * obtaining a copy of this software and associated documentation -+ * files (the "Software"), to deal in the Software without -+ * restriction, including without limitation the rights to use, -+ * copy, modify, merge, publish, distribute, sublicense, and/or -+ * sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following -+ * conditions: -+ * -+ * The above copyright notice and this permission notice shall be -+ * included in all copies or substantial portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -+ * OTHER DEALINGS IN THE SOFTWARE. -+ */ -+ -+/dts-v1/; -+#include "sun8i-h3.dtsi" -+#include "sunxi-common-regulators.dtsi" -+ -+#include -+#include -+ -+/ { -+ model = "Xunlong Orange Pi Plus"; -+ compatible = "xunlong,orangepi-plus", "allwinner,sun8i-h3"; -+ -+ aliases { -+ serial0 = &uart0; -+ }; -+ -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+}; -+ -+&mmc0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; -+ vmmc-supply = <®_vcc3v3>; -+ bus-width = <4>; -+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ -+ cd-inverted; -+ status = "okay"; -+}; -+ -+&uart0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart0_pins_a>; -+ status = "okay"; -+}; diff --git a/patch/kernel/sunxi-next/OrangePI-07-h3-c54e26726f75e388d39aa80e604774b0ea6d5a2f.patch.disabled b/patch/kernel/sunxi-next/OrangePI-07-h3-c54e26726f75e388d39aa80e604774b0ea6d5a2f.patch.disabled deleted file mode 100644 index ea58736c62..0000000000 --- a/patch/kernel/sunxi-next/OrangePI-07-h3-c54e26726f75e388d39aa80e604774b0ea6d5a2f.patch.disabled +++ /dev/null @@ -1,84 +0,0 @@ -From c54e26726f75e388d39aa80e604774b0ea6d5a2f Mon Sep 17 00:00:00 2001 -From: Reinder de Haan -Date: Sun, 15 Nov 2015 14:06:26 +0100 -Subject: [PATCH] reset: Add of_reset_control_get_by_index - -In some cases it is useful to be able to get a reset-controller by -index rather then by name. E.g. for a generic ip-block driver such -as the ehci-platform drivers which needs to support more then one reset, -without knowing the names of the reset lines (as that would make it -non generic). - -Signed-off-by: Reinder de Haan -Signed-off-by: Hans de Goede ---- - drivers/reset/core.c | 23 +++++++++++++++++++---- - include/linux/reset.h | 8 ++++++++ - 2 files changed, 27 insertions(+), 4 deletions(-) - -diff --git a/drivers/reset/core.c b/drivers/reset/core.c -index 7955e00..b2405d8 100644 ---- a/drivers/reset/core.c -+++ b/drivers/reset/core.c -@@ -152,16 +152,31 @@ EXPORT_SYMBOL_GPL(reset_control_status); - struct reset_control *of_reset_control_get(struct device_node *node, - const char *id) - { -+ int index = 0; -+ -+ if (id) -+ index = of_property_match_string(node, "reset-names", id); -+ -+ return of_reset_control_get_by_index(node, index); -+} -+ -+/** -+ * of_reset_control_get_by_index - Lookup and obtain a reference to a -+ * reset controller. -+ * @node: device to be reset by the controller -+ * @index: reset line index -+ * -+ * Returns a struct reset_control or IS_ERR() condition containing errno. -+ */ -+struct reset_control *of_reset_control_get_by_index(struct device_node *node, -+ int index) -+{ - struct reset_control *rstc = ERR_PTR(-EPROBE_DEFER); - struct reset_controller_dev *r, *rcdev; - struct of_phandle_args args; -- int index = 0; - int rstc_id; - int ret; - -- if (id) -- index = of_property_match_string(node, -- "reset-names", id); - ret = of_parse_phandle_with_args(node, "resets", "#reset-cells", - index, &args); - if (ret) -diff --git a/include/linux/reset.h b/include/linux/reset.h -index 7f65f9cf..8f56b6668c 100644 ---- a/include/linux/reset.h -+++ b/include/linux/reset.h -@@ -38,6 +38,9 @@ static inline struct reset_control *devm_reset_control_get_optional( - struct reset_control *of_reset_control_get(struct device_node *node, - const char *id); - -+struct reset_control *of_reset_control_get_by_index(struct device_node *node, -+ int index); -+ - #else - - static inline int reset_control_reset(struct reset_control *rstc) -@@ -106,6 +109,11 @@ static inline struct reset_control *of_reset_control_get( - return ERR_PTR(-ENOSYS); - } - -+static inline struct reset_control *of_reset_control_get_by_index( -+ struct device_node *node, int index) -+{ -+ return ERR_PTR(-EINVAL); -+} - #endif /* CONFIG_RESET_CONTROLLER */ - - #endif diff --git a/patch/kernel/sunxi-next/OrangePI-08-h3-fe78c12c1a4f4f271d0cc8b2f5eb341c95f40c66.patch.disabled b/patch/kernel/sunxi-next/OrangePI-08-h3-fe78c12c1a4f4f271d0cc8b2f5eb341c95f40c66.patch.disabled deleted file mode 100644 index cd960470df..0000000000 --- a/patch/kernel/sunxi-next/OrangePI-08-h3-fe78c12c1a4f4f271d0cc8b2f5eb341c95f40c66.patch.disabled +++ /dev/null @@ -1,114 +0,0 @@ -From fe78c12c1a4f4f271d0cc8b2f5eb341c95f40c66 Mon Sep 17 00:00:00 2001 -From: Reinder de Haan -Date: Sun, 15 Nov 2015 14:24:46 +0100 -Subject: [PATCH] ehci-platform: Add support for controllers with multiple - reset lines - -At least the EHCI found on the Allwinnner H3 SoC needs multiple reset -lines, the controller will not initialize while the reset for its -companion OHCI is still asserted, which means we need to de-assert -2 reset-controllers for this EHCI controller to work. - -Signed-off-by: Reinder de Haan -Signed-off-by: Hans de Goede ---- - drivers/usb/host/ehci-platform.c | 47 +++++++++++++++++++++++++--------------- - 1 file changed, 29 insertions(+), 18 deletions(-) - -diff --git a/drivers/usb/host/ehci-platform.c b/drivers/usb/host/ehci-platform.c -index bd7082f2..3d3a034 100644 ---- a/drivers/usb/host/ehci-platform.c -+++ b/drivers/usb/host/ehci-platform.c -@@ -39,11 +39,12 @@ - - #define DRIVER_DESC "EHCI generic platform driver" - #define EHCI_MAX_CLKS 3 -+#define EHCI_MAX_RESETS 2 - #define hcd_to_ehci_priv(h) ((struct ehci_platform_priv *)hcd_to_ehci(h)->priv) - - struct ehci_platform_priv { - struct clk *clks[EHCI_MAX_CLKS]; -- struct reset_control *rst; -+ struct reset_control *resets[EHCI_MAX_RESETS]; - struct phy **phys; - int num_phys; - bool reset_on_resume; -@@ -149,7 +150,7 @@ static int ehci_platform_probe(struct platform_device *dev) - struct usb_ehci_pdata *pdata = dev_get_platdata(&dev->dev); - struct ehci_platform_priv *priv; - struct ehci_hcd *ehci; -- int err, irq, phy_num, clk = 0; -+ int err, irq, phy_num, clk = 0, rst = 0; - - if (usb_disabled()) - return -ENODEV; -@@ -232,18 +233,24 @@ static int ehci_platform_probe(struct platform_device *dev) - break; - } - } -- } - -- priv->rst = devm_reset_control_get_optional(&dev->dev, NULL); -- if (IS_ERR(priv->rst)) { -- err = PTR_ERR(priv->rst); -- if (err == -EPROBE_DEFER) -- goto err_put_clks; -- priv->rst = NULL; -- } else { -- err = reset_control_deassert(priv->rst); -- if (err) -- goto err_put_clks; -+ for (rst = 0; rst < EHCI_MAX_RESETS; rst++) { -+ priv->resets[rst] = -+ of_reset_control_get_by_index(dev->dev.of_node, -+ rst); -+ if (IS_ERR(priv->resets[rst])) { -+ err = PTR_ERR(priv->resets[rst]); -+ if (err == -EPROBE_DEFER) -+ goto err_reset; -+ priv->resets[rst] = NULL; -+ break; -+ } -+ err = reset_control_deassert(priv->resets[rst]); -+ if (err) { -+ reset_control_put(priv->resets[rst]); -+ goto err_reset; -+ } -+ } - } - - if (pdata->big_endian_desc) -@@ -300,8 +307,10 @@ static int ehci_platform_probe(struct platform_device *dev) - if (pdata->power_off) - pdata->power_off(dev); - err_reset: -- if (priv->rst) -- reset_control_assert(priv->rst); -+ while (--rst >= 0) { -+ reset_control_assert(priv->resets[rst]); -+ reset_control_put(priv->resets[rst]); -+ } - err_put_clks: - while (--clk >= 0) - clk_put(priv->clks[clk]); -@@ -319,15 +328,17 @@ static int ehci_platform_remove(struct platform_device *dev) - struct usb_hcd *hcd = platform_get_drvdata(dev); - struct usb_ehci_pdata *pdata = dev_get_platdata(&dev->dev); - struct ehci_platform_priv *priv = hcd_to_ehci_priv(hcd); -- int clk; -+ int clk, rst; - - usb_remove_hcd(hcd); - - if (pdata->power_off) - pdata->power_off(dev); - -- if (priv->rst) -- reset_control_assert(priv->rst); -+ for (rst = 0; rst < EHCI_MAX_RESETS && priv->resets[rst]; rst++) { -+ reset_control_assert(priv->resets[rst]); -+ reset_control_put(priv->resets[rst]); -+ } - - for (clk = 0; clk < EHCI_MAX_CLKS && priv->clks[clk]; clk++) - clk_put(priv->clks[clk]); diff --git a/patch/kernel/sunxi-next/OrangePI-09-h3-cca1f932be385e576d975836895188fa55c52945.patch.disabled b/patch/kernel/sunxi-next/OrangePI-09-h3-cca1f932be385e576d975836895188fa55c52945.patch.disabled deleted file mode 100644 index 5a5bdd1cf9..0000000000 --- a/patch/kernel/sunxi-next/OrangePI-09-h3-cca1f932be385e576d975836895188fa55c52945.patch.disabled +++ /dev/null @@ -1,51 +0,0 @@ -From cca1f932be385e576d975836895188fa55c52945 Mon Sep 17 00:00:00 2001 -From: Reinder de Haan -Date: Sun, 15 Nov 2015 20:46:13 +0100 -Subject: [PATCH] clk: sunxi: Add support for the H3 usb phy clocks - -The H3 has a usb-phy clk register which is similar to that of earlier -SoCs, but with support for a larger number of phys. So we can simply add -a new set of clk-data and a new compatible and be done with it. - -Acked-by: Chen-Yu Tsai -Acked-by: Rob Herring -Signed-off-by: Reinder de Haan -Signed-off-by: Hans de Goede -Signed-off-by: Maxime Ripard ---- - Documentation/devicetree/bindings/clock/sunxi.txt | 1 + - drivers/clk/sunxi/clk-usb.c | 12 ++++++++++++ - 2 files changed, 13 insertions(+) - -diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt -index d303decb3..23e7bceb 100644 ---- a/Documentation/devicetree/bindings/clock/sunxi.txt -+++ b/Documentation/devicetree/bindings/clock/sunxi.txt -@@ -70,6 +70,7 @@ Required properties: - "allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13 - "allwinner,sun6i-a31-usb-clk" - for usb gates + resets on A31 - "allwinner,sun8i-a23-usb-clk" - for usb gates + resets on A23 -+ "allwinner,sun8i-h3-usb-clk" - for usb gates + resets on H3 - "allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80 - "allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80 - -diff --git a/drivers/clk/sunxi/clk-usb.c b/drivers/clk/sunxi/clk-usb.c -index 1a72cd6..67b8e38 100644 ---- a/drivers/clk/sunxi/clk-usb.c -+++ b/drivers/clk/sunxi/clk-usb.c -@@ -243,3 +243,15 @@ static void __init sun9i_a80_usb_phy_setup(struct device_node *node) - sunxi_usb_clk_setup(node, &sun9i_a80_usb_phy_data, &a80_usb_phy_lock); - } - CLK_OF_DECLARE(sun9i_a80_usb_phy, "allwinner,sun9i-a80-usb-phy-clk", sun9i_a80_usb_phy_setup); -+ -+static const struct usb_clk_data sun8i_h3_usb_clk_data __initconst = { -+ .clk_mask = BIT(19) | BIT(18) | BIT(17) | BIT(16) | -+ BIT(11) | BIT(10) | BIT(9) | BIT(8), -+ .reset_mask = BIT(3) | BIT(2) | BIT(1) | BIT(0), -+}; -+ -+static void __init sun8i_h3_usb_setup(struct device_node *node) -+{ -+ sunxi_usb_clk_setup(node, &sun8i_h3_usb_clk_data, &sun4i_a10_usb_lock); -+} -+CLK_OF_DECLARE(sun8i_h3_usb, "allwinner,sun8i-h3-usb-clk", sun8i_h3_usb_setup); diff --git a/patch/kernel/sunxi-next/OrangePI-10-h3-3bde21d14f6521dc237a952ae2f6d3dea982f786.patch.disabled b/patch/kernel/sunxi-next/OrangePI-10-h3-3bde21d14f6521dc237a952ae2f6d3dea982f786.patch.disabled deleted file mode 100644 index 030ef4270c..0000000000 --- a/patch/kernel/sunxi-next/OrangePI-10-h3-3bde21d14f6521dc237a952ae2f6d3dea982f786.patch.disabled +++ /dev/null @@ -1,189 +0,0 @@ -From 3bde21d14f6521dc237a952ae2f6d3dea982f786 Mon Sep 17 00:00:00 2001 -From: Reinder de Haan -Date: Tue, 3 Nov 2015 15:08:39 +0100 -Subject: [PATCH] phy-sun4i-usb: Add support for the host usb-phys found on the - H3 SoC - -Note this commit only adds support for phys 1-3, phy 0, the otg phy, is -not yet (fully) supported after this commit. - -Signed-off-by: Reinder de Haan -Signed-off-by: Hans de Goede ---- - .../devicetree/bindings/phy/sun4i-usb-phy.txt | 1 + - drivers/phy/phy-sun4i-usb.c | 67 +++++++++++++++++----- - 2 files changed, 53 insertions(+), 15 deletions(-) - -diff --git a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt -index 0cebf74..95736d7 100644 ---- a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt -+++ b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt -@@ -9,6 +9,7 @@ Required properties: - * allwinner,sun7i-a20-usb-phy - * allwinner,sun8i-a23-usb-phy - * allwinner,sun8i-a33-usb-phy -+ * allwinner,sun8i-h3-usb-phy - - reg : a list of offset + length pairs - - reg-names : - * "phy_ctrl" -diff --git a/drivers/phy/phy-sun4i-usb.c b/drivers/phy/phy-sun4i-usb.c -index b12964b..11bc9cd 100644 ---- a/drivers/phy/phy-sun4i-usb.c -+++ b/drivers/phy/phy-sun4i-usb.c -@@ -46,6 +46,9 @@ - #define REG_PHYBIST 0x08 - #define REG_PHYTUNE 0x0c - #define REG_PHYCTL_A33 0x10 -+#define REG_PHY_UNK_H3 0x20 -+ -+#define REG_PMU_UNK_H3 0x10 - - #define PHYCTL_DATA BIT(7) - -@@ -79,7 +82,7 @@ - #define PHY_DISCON_TH_SEL 0x2a - #define PHY_SQUELCH_DETECT 0x3c - --#define MAX_PHYS 3 -+#define MAX_PHYS 4 - - /* - * Note do not raise the debounce time, we must report Vusb high within 100ms -@@ -88,12 +91,19 @@ - #define DEBOUNCE_TIME msecs_to_jiffies(50) - #define POLL_TIME msecs_to_jiffies(250) - -+enum sun4i_usb_phy_type { -+ sun4i_a10_phy, -+ sun8i_a33_phy, -+ sun8i_h3_phy -+}; -+ - struct sun4i_usb_phy_data { -+ struct device *dev; - void __iomem *base; - struct mutex mutex; - int num_phys; - u32 disc_thresh; -- bool has_a33_phyctl; -+ enum sun4i_usb_phy_type type; - struct sun4i_usb_phy { - struct phy *phy; - void __iomem *pmu; -@@ -164,12 +174,18 @@ static void sun4i_usb_phy_write(struct sun4i_usb_phy *phy, u32 addr, u32 data, - - mutex_lock(&phy_data->mutex); - -- if (phy_data->has_a33_phyctl) { -+ switch (phy_data->type) { -+ case sun4i_a10_phy: -+ phyctl = phy_data->base + REG_PHYCTL_A10; -+ break; -+ case sun8i_a33_phy: - phyctl = phy_data->base + REG_PHYCTL_A33; - /* A33 needs us to set phyctl to 0 explicitly */ - writel(0, phyctl); -- } else { -- phyctl = phy_data->base + REG_PHYCTL_A10; -+ break; -+ case sun8i_h3_phy: -+ dev_err(phy_data->dev, "H3 usb_phy_write is not supported\n"); -+ return; - } - - for (i = 0; i < len; i++) { -@@ -230,6 +246,7 @@ static int sun4i_usb_phy_init(struct phy *_phy) - struct sun4i_usb_phy *phy = phy_get_drvdata(_phy); - struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy); - int ret; -+ u32 val; - - ret = clk_prepare_enable(phy->clk); - if (ret) -@@ -241,15 +258,26 @@ static int sun4i_usb_phy_init(struct phy *_phy) - return ret; - } - -- /* Enable USB 45 Ohm resistor calibration */ -- if (phy->index == 0) -- sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN, 0x01, 1); -+ if (data->type == sun8i_h3_phy) { -+ if (phy->index == 0) { -+ val = readl(data->base + REG_PHY_UNK_H3); -+ writel(val & ~1, data->base + REG_PHY_UNK_H3); -+ } -+ -+ val = readl(phy->pmu + REG_PMU_UNK_H3); -+ writel(val & ~2, phy->pmu + REG_PMU_UNK_H3); -+ } else { -+ /* Enable USB 45 Ohm resistor calibration */ -+ if (phy->index == 0) -+ sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN, 0x01, 1); - -- /* Adjust PHY's magnitude and rate */ -- sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE, 0x14, 5); -+ /* Adjust PHY's magnitude and rate */ -+ sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE, 0x14, 5); - -- /* Disconnect threshold adjustment */ -- sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL, data->disc_thresh, 2); -+ /* Disconnect threshold adjustment */ -+ sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL, -+ data->disc_thresh, 2); -+ } - - sun4i_usb_phy_passby(phy, 1); - -@@ -522,11 +550,14 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev) - mutex_init(&data->mutex); - INIT_DELAYED_WORK(&data->detect, sun4i_usb_phy0_id_vbus_det_scan); - dev_set_drvdata(dev, data); -+ data->dev = dev; - - if (of_device_is_compatible(np, "allwinner,sun5i-a13-usb-phy") || - of_device_is_compatible(np, "allwinner,sun8i-a23-usb-phy") || - of_device_is_compatible(np, "allwinner,sun8i-a33-usb-phy")) - data->num_phys = 2; -+ else if (of_device_is_compatible(np, "allwinner,sun8i-h3-usb-phy")) -+ data->num_phys = 4; - else - data->num_phys = 3; - -@@ -538,13 +569,18 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev) - - if (of_device_is_compatible(np, "allwinner,sun6i-a31-usb-phy") || - of_device_is_compatible(np, "allwinner,sun8i-a23-usb-phy") || -- of_device_is_compatible(np, "allwinner,sun8i-a33-usb-phy")) -+ of_device_is_compatible(np, "allwinner,sun8i-a33-usb-phy") || -+ of_device_is_compatible(np, "allwinner,sun8i-h3-usb-phy")) - dedicated_clocks = true; - else - dedicated_clocks = false; - - if (of_device_is_compatible(np, "allwinner,sun8i-a33-usb-phy")) -- data->has_a33_phyctl = true; -+ data->type = sun8i_a33_phy; -+ else if (of_device_is_compatible(np, "allwinner,sun8i-h3-usb-phy")) -+ data->type = sun8i_h3_phy; -+ else -+ data->type = sun4i_a10_phy; - - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy_ctrl"); - data->base = devm_ioremap_resource(dev, res); -@@ -620,7 +656,7 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev) - return PTR_ERR(phy->reset); - } - -- if (i) { /* No pmu for usbc0 */ -+ if (data->type == sun8i_h3_phy || i != 0) { - snprintf(name, sizeof(name), "pmu%d", i); - res = platform_get_resource_byname(pdev, - IORESOURCE_MEM, name); -@@ -696,6 +732,7 @@ static const struct of_device_id sun4i_usb_phy_of_match[] = { - { .compatible = "allwinner,sun7i-a20-usb-phy" }, - { .compatible = "allwinner,sun8i-a23-usb-phy" }, - { .compatible = "allwinner,sun8i-a33-usb-phy" }, -+ { .compatible = "allwinner,sun8i-h3-usb-phy" }, - { }, - }; - MODULE_DEVICE_TABLE(of, sun4i_usb_phy_of_match); diff --git a/patch/kernel/sunxi-next/OrangePI-11-h3-303ed9315574a4764eba097b5c2fe00cd5a90e8f.patch.disabled b/patch/kernel/sunxi-next/OrangePI-11-h3-303ed9315574a4764eba097b5c2fe00cd5a90e8f.patch.disabled deleted file mode 100644 index 8ccca5363f..0000000000 --- a/patch/kernel/sunxi-next/OrangePI-11-h3-303ed9315574a4764eba097b5c2fe00cd5a90e8f.patch.disabled +++ /dev/null @@ -1,36 +0,0 @@ -From 303ed9315574a4764eba097b5c2fe00cd5a90e8f Mon Sep 17 00:00:00 2001 -From: Reinder de Haan -Date: Tue, 3 Nov 2015 15:13:00 +0100 -Subject: [PATCH] ARM: dts: sun8i: Add support for H3 usb clocks - -Add a node describing the usb-clks found on the H3. - -Signed-off-by: Reinder de Haan -Signed-off-by: Hans de Goede ---- - arch/arm/boot/dts/sun8i-h3.dtsi | 12 ++++++++++++ - 1 file changed, 12 insertions(+) - -diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi -index c18b5f7c..22ff593 100644 ---- a/arch/arm/boot/dts/sun8i-h3.dtsi -+++ b/arch/arm/boot/dts/sun8i-h3.dtsi -@@ -266,6 +266,18 @@ - "mmc2_sample"; - }; - -+ usb_clk: clk@01c200cc { -+ #clock-cells = <1>; -+ #reset-cells = <1>; -+ compatible = "allwinner,sun8i-h3-usb-clk"; -+ reg = <0x01c200cc 0x4>; -+ clocks = <&osc24M>; -+ clock-output-names = "usb_phy0", "usb_phy1", -+ "usb_phy2", "usb_phy3", -+ "usb_ohci0", "usb_ohci1", -+ "usb_ohci2", "usb_ohci3"; -+ }; -+ - mbus_clk: clk@01c2015c { - #clock-cells = <0>; - compatible = "allwinner,sun8i-a23-mbus-clk"; diff --git a/patch/kernel/sunxi-next/OrangePI-12-h3-5b030647d83ab4680901d42cb115d9dc95b22440.patch.disabled b/patch/kernel/sunxi-next/OrangePI-12-h3-5b030647d83ab4680901d42cb115d9dc95b22440.patch.disabled deleted file mode 100644 index c210df08cc..0000000000 --- a/patch/kernel/sunxi-next/OrangePI-12-h3-5b030647d83ab4680901d42cb115d9dc95b22440.patch.disabled +++ /dev/null @@ -1,125 +0,0 @@ -From 5b030647d83ab4680901d42cb115d9dc95b22440 Mon Sep 17 00:00:00 2001 -From: Reinder de Haan -Date: Tue, 3 Nov 2015 15:14:20 +0100 -Subject: [PATCH] ARM: dts: sun8i: Add usbphy and usb host controller nodes - -Add nodes describing the H3's usbphy and usb host controller nodes. - -Signed-off-by: Reinder de Haan -Signed-off-by: Hans de Goede ---- - arch/arm/boot/dts/sun8i-h3.dtsi | 101 ++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 101 insertions(+) - -diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi -index 22ff593..0faa38a 100644 ---- a/arch/arm/boot/dts/sun8i-h3.dtsi -+++ b/arch/arm/boot/dts/sun8i-h3.dtsi -@@ -359,6 +359,107 @@ - #size-cells = <0>; - }; - -+ usbphy: phy@01c19400 { -+ compatible = "allwinner,sun8i-h3-usb-phy"; -+ reg = <0x01c19400 0x2c>, -+ <0x01c1a800 0x4>, -+ <0x01c1b800 0x4>, -+ <0x01c1c800 0x4>, -+ <0x01c1d800 0x4>; -+ reg-names = "phy_ctrl", -+ "pmu0", -+ "pmu1", -+ "pmu2", -+ "pmu3"; -+ clocks = <&usb_clk 8>, -+ <&usb_clk 9>, -+ <&usb_clk 10>, -+ <&usb_clk 11>; -+ clock-names = "usb0_phy", -+ "usb1_phy", -+ "usb2_phy", -+ "usb3_phy"; -+ resets = <&usb_clk 0>, -+ <&usb_clk 1>, -+ <&usb_clk 2>, -+ <&usb_clk 3>; -+ reset-names = "usb0_reset", -+ "usb1_reset", -+ "usb2_reset", -+ "usb3_reset"; -+ status = "disabled"; -+ #phy-cells = <1>; -+ }; -+ -+ ehci1: usb@01c1b000 { -+ compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; -+ reg = <0x01c1b000 0x100>; -+ interrupts = ; -+ clocks = <&bus_gates 25>, <&bus_gates 29>; -+ resets = <&bus_rst 25>, <&bus_rst 29>; -+ phys = <&usbphy 1>; -+ phy-names = "usb"; -+ status = "disabled"; -+ }; -+ -+ ohci1: usb@01c1b400 { -+ compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; -+ reg = <0x01c1b400 0x100>; -+ interrupts = ; -+ clocks = <&bus_gates 29>, <&bus_gates 25>, -+ <&usb_clk 17>; -+ resets = <&bus_rst 29>, <&bus_rst 25>; -+ phys = <&usbphy 1>; -+ phy-names = "usb"; -+ status = "disabled"; -+ }; -+ -+ ehci2: usb@01c1c000 { -+ compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; -+ reg = <0x01c1c000 0x100>; -+ interrupts = ; -+ clocks = <&bus_gates 26>, <&bus_gates 30>; -+ resets = <&bus_rst 26>, <&bus_rst 30>; -+ phys = <&usbphy 2>; -+ phy-names = "usb"; -+ status = "disabled"; -+ }; -+ -+ ohci2: usb@01c1c400 { -+ compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; -+ reg = <0x01c1c400 0x100>; -+ interrupts = ; -+ clocks = <&bus_gates 30>, <&bus_gates 26>, -+ <&usb_clk 18>; -+ resets = <&bus_rst 30>, <&bus_rst 26>; -+ phys = <&usbphy 2>; -+ phy-names = "usb"; -+ status = "disabled"; -+ }; -+ -+ ehci3: usb@01c1d000 { -+ compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; -+ reg = <0x01c1d000 0x100>; -+ interrupts = ; -+ clocks = <&bus_gates 27>, <&bus_gates 31>; -+ resets = <&bus_rst 27>, <&bus_rst 31>; -+ phys = <&usbphy 3>; -+ phy-names = "usb"; -+ status = "disabled"; -+ }; -+ -+ ohci3: usb@01c1d400 { -+ compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; -+ reg = <0x01c1d400 0x100>; -+ interrupts = ; -+ clocks = <&bus_gates 31>, <&bus_gates 27>, -+ <&usb_clk 19>; -+ resets = <&bus_rst 31>, <&bus_rst 27>; -+ phys = <&usbphy 3>; -+ phy-names = "usb"; -+ status = "disabled"; -+ }; -+ - pio: pinctrl@01c20800 { - compatible = "allwinner,sun8i-h3-pinctrl"; - reg = <0x01c20800 0x400>; diff --git a/patch/kernel/sunxi-next/OrangePI-13-h3-f31f74a2c3070ba35e9eea03f7afda86d3e715ee.patch.disabled b/patch/kernel/sunxi-next/OrangePI-13-h3-f31f74a2c3070ba35e9eea03f7afda86d3e715ee.patch.disabled deleted file mode 100644 index d43a3e74dc..0000000000 --- a/patch/kernel/sunxi-next/OrangePI-13-h3-f31f74a2c3070ba35e9eea03f7afda86d3e715ee.patch.disabled +++ /dev/null @@ -1,79 +0,0 @@ -From f31f74a2c3070ba35e9eea03f7afda86d3e715ee Mon Sep 17 00:00:00 2001 -From: Jens Kuske -Date: Tue, 17 Nov 2015 17:12:07 +0100 -Subject: [PATCH] ARM: dts: sun8i-h3-orangepi-plus: Enable USB host controllers - -Enable the 2 USB host controllers used on the Orange Pi Plus -and add the necessary regulators. - -Signed-off-by: Reinder de Haan -Signed-off-by: Hans de Goede -Signed-off-by: Jens Kuske ---- - arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 44 ++++++++++++++++++++++++++++ - 1 file changed, 44 insertions(+) - -diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts -index e67df59..1cb6c66 100644 ---- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts -+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts -@@ -58,6 +58,35 @@ - chosen { - stdout-path = "serial0:115200n8"; - }; -+ -+ reg_usb3_vbus: usb3-vbus { -+ compatible = "regulator-fixed"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&usb3_vbus_pin_a>; -+ regulator-name = "usb3-vbus"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ regulator-boot-on; -+ enable-active-high; -+ gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>; -+ }; -+}; -+ -+&ehci1 { -+ status = "okay"; -+}; -+ -+&ehci3 { -+ status = "okay"; -+}; -+ -+&pio { -+ usb3_vbus_pin_a: usb3_vbus_pin@0 { -+ allwinner,pins = "PG11"; -+ allwinner,function = "gpio_out"; -+ allwinner,drive = ; -+ allwinner,pull = ; -+ }; - }; - - &mmc0 { -@@ -70,8 +99,23 @@ - status = "okay"; - }; - -+®_usb1_vbus { -+ gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>; -+ status = "okay"; -+}; -+ - &uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; - }; -+ -+&usb1_vbus_pin_a { -+ allwinner,pins = "PG13"; -+}; -+ -+&usbphy { -+ usb1_vbus-supply = <®_usb1_vbus>; -+ usb3_vbus-supply = <®_usb3_vbus>; -+ status = "okay"; -+}; diff --git a/patch/kernel/sunxi-next/OrangePI-14-h3-42bbc4bb30ac2e1abaf34357d6e122d8881d6d17.patch.disabled b/patch/kernel/sunxi-next/OrangePI-14-h3-42bbc4bb30ac2e1abaf34357d6e122d8881d6d17.patch.disabled deleted file mode 100644 index 85d18ee671..0000000000 --- a/patch/kernel/sunxi-next/OrangePI-14-h3-42bbc4bb30ac2e1abaf34357d6e122d8881d6d17.patch.disabled +++ /dev/null @@ -1,142 +0,0 @@ -From 42bbc4bb30ac2e1abaf34357d6e122d8881d6d17 Mon Sep 17 00:00:00 2001 -From: Chen-Yu Tsai -Date: Wed, 18 Nov 2015 13:40:33 +0800 -Subject: [PATCH] ARM: dts: sun8i: Add Orange Pi PC support - -The Orange Pi PC is an SBC based on the Allwinner H3 SoC with a uSD slot, -3 USB ports directly from the SoC, a 10/100M ethernet port using the -SoC's integrated PHY, USB OTG, HDMI, a TRRS headphone jack for stereo out -and composite out, a microphone, an IR receiver, a CSI connector, 2 LEDs, -a 3 pin UART header, and a 40-pin GPIO header. - -Signed-off-by: Chen-Yu Tsai ---- - arch/arm/boot/dts/Makefile | 1 + - arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 106 +++++++++++++++++++++++++++++ - 2 files changed, 107 insertions(+) - create mode 100644 arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts - -diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile -index 4e8026e..0ef528a 100644 ---- a/arch/arm/boot/dts/Makefile -+++ b/arch/arm/boot/dts/Makefile -@@ -661,6 +661,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ - sun8i-a33-ippo-q8h-v1.2.dtb \ - sun8i-a33-q8-tablet.dtb \ - sun8i-a33-sinlinx-sina33.dtb \ -+ sun8i-h3-orangepi-pc.dtb \ - sun8i-h3-orangepi-plus.dtb - dtb-$(CONFIG_MACH_SUN9I) += \ - sun9i-a80-optimus.dtb \ -diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts -new file mode 100644 -index 0000000..4b25dcc ---- /dev/null -+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts -@@ -0,0 +1,106 @@ -+/* -+ * Copyright (C) 2015 Chen-Yu Tsai -+ * -+ * This file is dual-licensed: you can use it either under the terms -+ * of the GPL or the X11 license, at your option. Note that this dual -+ * licensing only applies to this file, and not this project as a -+ * whole. -+ * -+ * a) This file is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * This file is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * Or, alternatively, -+ * -+ * b) Permission is hereby granted, free of charge, to any person -+ * obtaining a copy of this software and associated documentation -+ * files (the "Software"), to deal in the Software without -+ * restriction, including without limitation the rights to use, -+ * copy, modify, merge, publish, distribute, sublicense, and/or -+ * sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following -+ * conditions: -+ * -+ * The above copyright notice and this permission notice shall be -+ * included in all copies or substantial portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -+ * OTHER DEALINGS IN THE SOFTWARE. -+ */ -+ -+/dts-v1/; -+#include "sun8i-h3.dtsi" -+#include "sunxi-common-regulators.dtsi" -+ -+#include -+#include -+ -+/ { -+ model = "Xunlong Orange Pi PC"; -+ compatible = "xunlong,orangepi-pc", "allwinner,sun8i-h3"; -+ -+ aliases { -+ serial0 = &uart0; -+ }; -+ -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+}; -+ -+&ehci1 { -+ status = "okay"; -+}; -+ -+&ehci2 { -+ status = "okay"; -+}; -+ -+&ehci3 { -+ status = "okay"; -+}; -+ -+&mmc0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; -+ vmmc-supply = <®_vcc3v3>; -+ bus-width = <4>; -+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ -+ cd-inverted; -+ status = "okay"; -+}; -+ -+&ohci1 { -+ status = "okay"; -+}; -+ -+&ohci2 { -+ status = "okay"; -+}; -+ -+&ohci3 { -+ status = "okay"; -+}; -+ -+&uart0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart0_pins_a>; -+ status = "okay"; -+}; -+ -+&usbphy { -+ /* USB VBUS is always on */ -+ status = "okay"; -+}; diff --git a/patch/u-boot/u-boot-next/bananapi-enable-ldo4.patch b/patch/u-boot/u-boot-next/bananapi-enable-ldo4.patch index 47a454b79c..301ec875a8 100644 --- a/patch/u-boot/u-boot-next/bananapi-enable-ldo4.patch +++ b/patch/u-boot/u-boot-next/bananapi-enable-ldo4.patch @@ -7,13 +7,3 @@ index 6cbb76c..5ed845c 100644 CONFIG_ETH_DESIGNWARE=y CONFIG_USB_EHCI_HCD=y +CONFIG_AXP_ALDO4_VOLT=2500 -diff --git a/configs/Bananapro_defconfig b/configs/Bananapro_defconfig -index 40588b9..f1554bc 100644 ---- a/configs/Bananapro_defconfig -+++ b/configs/Bananapro_defconfig -@@ -17,3 +17,4 @@ CONFIG_CMD_GPIO=y - CONFIG_NETCONSOLE=y - CONFIG_ETH_DESIGNWARE=y - CONFIG_USB_EHCI_HCD=y -+CONFIG_AXP_ALDO4_VOLT=2500 -\ No newline at end of file