From 907c9f05316e46a80f5c5cef7fa56ae1fbdeca5c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E9=9D=92=E8=8F=9C=E8=90=9D=20=E5=8D=9C=E5=86=AC=E7=93=9C?= Date: Mon, 9 Dec 2024 21:12:16 +0800 Subject: [PATCH] add community support for LonganPi 3H (#7547) --- config/boards/longanpi-3h.csc | 15 + .../Add-board-LonganPi-3H.patch | 272 ++++++++++++++++++ patch/kernel/archive/sunxi-6.6/series.conf | 1 + .../0006-add-lpi3h-defconfig-and-dts.patch | 248 ++++++++++++++++ ...h-drivers-emmc-add-emmc-boot-support.patch | 63 ++++ 5 files changed, 599 insertions(+) create mode 100644 config/boards/longanpi-3h.csc create mode 100644 patch/kernel/archive/sunxi-6.6/patches.armbian/Add-board-LonganPi-3H.patch create mode 100644 patch/u-boot/v2024.10/board_longanpi-3h/0006-add-lpi3h-defconfig-and-dts.patch create mode 100644 patch/u-boot/v2024.10/board_longanpi-3h/0007-lpi3h-drivers-emmc-add-emmc-boot-support.patch diff --git a/config/boards/longanpi-3h.csc b/config/boards/longanpi-3h.csc new file mode 100644 index 0000000000..d0ab4ee7db --- /dev/null +++ b/config/boards/longanpi-3h.csc @@ -0,0 +1,15 @@ +# Allwinner H618 quad core 1GB/2GB/4GB RAM +BOARD_NAME="Longan Pi 3H" +BOARDFAMILY="sun50iw9" +BOARD_MAINTAINER="" +BOOTCONFIG="longanpi_3h_defconfig" +BOOTBRANCH="tag:v2024.10" +BOOTPATCHDIR="v2024.10" +BOOTDIR="u-boot-${BOARD}" # do not share u-boot directory +BOOT_LOGO="desktop" +OVERLAY_PREFIX="sun50i-h616" +KERNEL_TARGET="current,edge" +KERNEL_TEST_TARGET="current" +FORCE_BOOTSCRIPT_UPDATE="yes" +enable_extension "radxa-aic8800" # compatible with radxa-aic8800 +AIC8800_TYPE="usb" diff --git a/patch/kernel/archive/sunxi-6.6/patches.armbian/Add-board-LonganPi-3H.patch b/patch/kernel/archive/sunxi-6.6/patches.armbian/Add-board-LonganPi-3H.patch new file mode 100644 index 0000000000..b9f503d0fe --- /dev/null +++ b/patch/kernel/archive/sunxi-6.6/patches.armbian/Add-board-LonganPi-3H.patch @@ -0,0 +1,272 @@ +--- a/arch/arm64/boot/dts/allwinner/sun50i-h618-longan-module-3h.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h618-longan-module-3h.dtsi +@@ -0,0 +1,87 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (C) Jisheng Zhang ++ */ ++ ++/dts-v1/; ++ ++#include "sun50i-h616.dtsi" ++#include "sun50i-h616-cpu-opp.dtsi" ++ ++/ { ++ model = "Sipeed Longan Module 3H"; ++ compatible = "sipeed,longan-module-3h", "allwinner,sun50i-h618"; ++}; ++ ++&cpu0 { ++ cpu-supply = <®_dcdc2>; ++}; ++ ++&mmc2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc2_pins>; ++ vmmc-supply = <®_dldo1>; ++ vqmmc-supply = <®_aldo1>; ++ bus-width = <8>; ++ non-removable; ++ cap-mmc-hw-reset; ++ mmc-ddr-1_8v; ++ mmc-hs200-1_8v; ++ status = "okay"; ++}; ++ ++&r_i2c { ++ status = "okay"; ++ ++ axp313: pmic@36 { ++ compatible = "x-powers,axp313a"; ++ reg = <0x36>; ++ ++ regulators { ++ /* Supplies VCC-PLL, so needs to be always on. */ ++ reg_aldo1: aldo1 { ++ regulator-always-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc1v8"; ++ }; ++ ++ /* Supplies VCC-IO, so needs to be always on. */ ++ reg_dldo1: dldo1 { ++ regulator-always-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc3v3"; ++ }; ++ ++ reg_dcdc1: dcdc1 { ++ regulator-always-on; ++ regulator-min-microvolt = <810000>; ++ regulator-max-microvolt = <990000>; ++ regulator-name = "vdd-gpu-sys"; ++ }; ++ ++ reg_dcdc2: dcdc2 { ++ regulator-always-on; ++ regulator-min-microvolt = <810000>; ++ regulator-max-microvolt = <1100000>; ++ regulator-name = "vdd-cpu"; ++ }; ++ ++ reg_dcdc3: dcdc3 { ++ regulator-always-on; ++ regulator-min-microvolt = <1100000>; ++ regulator-max-microvolt = <1100000>; ++ regulator-name = "vdd-dram"; ++ }; ++ }; ++ }; ++}; ++ ++&pio { ++ vcc-pc-supply = <®_dldo1>; ++ vcc-pf-supply = <®_dldo1>; ++ vcc-pg-supply = <®_aldo1>; ++ vcc-ph-supply = <®_dldo1>; ++ vcc-pi-supply = <®_dldo1>; ++}; + +--- a/arch/arm64/boot/dts/allwinner/sun50i-h618-longanpi-3h.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h618-longanpi-3h.dts +@@ -0,0 +1,168 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (C) Jisheng Zhang ++ */ ++ ++/dts-v1/; ++ ++#include "sun50i-h618-longan-module-3h.dtsi" ++ ++#include ++#include ++#include ++ ++/ { ++ model = "Sipeed Longan Pi 3H"; ++ compatible = "sipeed,longan-pi-3h", "sipeed,longan-module-3h", "allwinner,sun50i-h618"; ++ ++ aliases { ++ ethernet0 = &emac0; ++ serial0 = &uart0; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ reserved-memory { ++ linux,cma { ++ compatible = "shared-dma-pool"; ++ reusable; ++ alloc-ranges = <0x0 0x40000000 0x0 0xffffffff>; ++ size = <0x0 0x8000000>; ++ linux,cma-default; ++ }; ++ }; ++ ++ hdmi_connector: connector { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi_con_in: endpoint { ++ remote-endpoint = <&hdmi_out_con>; ++ }; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ led-0 { ++ color = ; ++ function = LED_FUNCTION_INDICATOR; ++ function-enumerator = <0>; ++ gpios = <&pio 6 2 GPIO_ACTIVE_LOW>; /* PG2 */ ++ }; ++ ++ led-1 { ++ color = ; ++ function = LED_FUNCTION_INDICATOR; ++ function-enumerator = <1>; ++ gpios = <&pio 6 4 GPIO_ACTIVE_LOW>; /* PG4 */ ++ }; ++ }; ++ ++ reg_vcc5v: vcc5v { ++ /* board wide 5V supply directly from the USB-C socket */ ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc-5v"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ }; ++}; ++ ++&axp313 { ++ vin1-supply = <®_vcc5v>; ++ vin2-supply = <®_vcc5v>; ++ vin3-supply = <®_vcc5v>; ++}; ++ ++&de { ++ status = "okay"; ++}; ++ ++&ehci1 { ++ status = "okay"; ++}; ++ ++&ohci1 { ++ status = "okay"; ++}; ++ ++&ehci2 { ++ status = "okay"; ++}; ++ ++&ohci2 { ++ status = "okay"; ++}; ++ ++&ehci3 { ++ status = "okay"; ++}; ++ ++&ohci3 { ++ status = "okay"; ++}; ++ ++&emac0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&ext_rgmii_pins>; ++ phy-mode = "rgmii"; ++ phy-handle = <&ext_rgmii_phy>; ++ allwinner,rx-delay-ps = <3100>; ++ allwinner,tx-delay-ps = <700>; ++ phy-supply = <®_dldo1>; ++ status = "okay"; ++}; ++ ++&hdmi { ++ status = "okay"; ++}; ++ ++&hdmi_out { ++ hdmi_out_con: endpoint { ++ remote-endpoint = <&hdmi_con_in>; ++ }; ++}; ++ ++&mdio0 { ++ ext_rgmii_phy: ethernet-phy@1 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <1>; ++ }; ++}; ++ ++&mmc0 { ++ bus-width = <4>; ++ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ ++ vmmc-supply = <®_dldo1>; ++ status = "okay"; ++}; ++ ++&uart0 { ++ status = "okay"; ++}; ++ ++&usbotg { ++ /* ++ * PHY0 pins are connected to a USB-C socket, but a role switch ++ * is not implemented: both CC pins are pulled to GND. ++ * The VBUS pins power the device, so a fixed peripheral mode ++ * is the best choice. ++ * The board can be powered via GPIOs, in this case port0 *can* ++ * act as a host (with a cable/adapter ignoring CC), as VBUS is ++ * then provided by the GPIOs. Any user of this setup would ++ * need to adjust the DT accordingly: dr_mode set to "host", ++ * enabling OHCI0 and EHCI0. ++ */ ++ dr_mode = "peripheral"; ++ status = "okay"; ++}; ++ ++&usbphy { ++ usb1_vbus-supply = <®_vcc5v>; ++ status = "okay"; ++}; + +--- a/arch/arm64/boot/dts/allwinner/Makefile ++++ b/arch/arm64/boot/dts/allwinner/Makefile +@@ -57,6 +57,7 @@ + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-bigtreetech-cb1-sd.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-bigtreetech-cb1-emmc.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-bananapi-m4-zero.dtb ++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-longanpi-3h.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-orangepi-zero3.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-orangepi-zero2w.dtb diff --git a/patch/kernel/archive/sunxi-6.6/series.conf b/patch/kernel/archive/sunxi-6.6/series.conf index f5ff199c42..616ddd99fb 100644 --- a/patch/kernel/archive/sunxi-6.6/series.conf +++ b/patch/kernel/archive/sunxi-6.6/series.conf @@ -438,6 +438,7 @@ patches.armbian/drivers-pwm-Add-pwm-sunxi-enhance-driver-for-h616.patch patches.armbian/driver-allwinner-h618-emac.patch patches.armbian/orangepi-zero2w-add-dtb.patch + patches.armbian/Add-board-LonganPi-3H.patch patches.armbian/arm64-dts-sun50i-h616-bananapi-m4-i2c-spi1-uart-pins.patch patches.armbian/add-dtb-overlay-for-zero2w.patch patches.armbian/Add-BPI-M4-ZERO-sdio-wifi-bt-overlay.patch diff --git a/patch/u-boot/v2024.10/board_longanpi-3h/0006-add-lpi3h-defconfig-and-dts.patch b/patch/u-boot/v2024.10/board_longanpi-3h/0006-add-lpi3h-defconfig-and-dts.patch new file mode 100644 index 0000000000..66ac8a31fd --- /dev/null +++ b/patch/u-boot/v2024.10/board_longanpi-3h/0006-add-lpi3h-defconfig-and-dts.patch @@ -0,0 +1,248 @@ +From 690ebb1dae52d8c30ed4a5dadb9a5c3ef7004e9c Mon Sep 17 00:00:00 2001 +From: Jisheng Zhang +Date: Tue, 17 Oct 2023 17:40:52 +0800 +Subject: [PATCH 6/8] add lpi3h defconfig and dts + +--- + arch/arm/dts/sun50i-h618-longanpi-3h.dts | 190 ++ + configs/longanpi_3h_defconfig | 2062 ++++++++++++++++++++++ + 2 files changed, 2252 insertions(+) + create mode 100644 arch/arm/dts/sun50i-h618-longanpi-3h.dts + create mode 100644 configs/longanpi_3h_defconfig + +diff --git a/arch/arm/dts/sun50i-h618-longanpi-3h.dts b/arch/arm/dts/sun50i-h618-longanpi-3h.dts +new file mode 100644 +index 0000000000..b0ff07ce72 +--- /dev/null ++++ b/arch/arm/dts/sun50i-h618-longanpi-3h.dts +@@ -0,0 +1,190 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (C) Jisheng Zhang ++ */ ++ ++/dts-v1/; ++ ++#include "sun50i-h616.dtsi" ++ ++#include ++#include ++#include ++ ++/ { ++ model = "LonganPi 3H"; ++ compatible = "sipeed,longanpi-3h", "allwinner,sun50i-h618"; ++ ++ aliases { ++ ethernet0 = &emac0; ++ serial0 = &uart0; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ // linux,initrd-start = <0x4a000000>; ++ // linux,initrd-end = <0x4a0759bc>; ++ }; ++ ++ /*memory@41000000 { ++ device_type = "memory"; ++ reg = <0x0 0x41000000 0x0 0xff000000>; ++ };*/ ++ ++ reg_vcc5v: vcc5v { ++ /* board wide 5V supply directly from the USB-C socket */ ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc-5v"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ }; ++}; ++ ++&ehci1 { ++ status = "okay"; ++}; ++ ++&ohci1 { ++ status = "okay"; ++}; ++ ++&ehci2 { ++ status = "okay"; ++}; ++ ++&ohci2 { ++ status = "okay"; ++}; ++ ++&ehci3 { ++ status = "okay"; ++}; ++ ++&ohci3 { ++ status = "okay"; ++}; ++ ++&emac0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&ext_rgmii_pins>; ++ phy-mode = "rgmii"; ++ phy-handle = <&ext_rgmii_phy>; ++ allwinner,rx-delay-ps = <3100>; ++ allwinner,tx-delay-ps = <700>; ++ phy-supply = <®_dldo1>; ++ status = "okay"; ++}; ++ ++&mdio0 { ++ ext_rgmii_phy: ethernet-phy@1 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <1>; ++ }; ++}; ++ ++&mmc0 { ++ bus-width = <4>; ++ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ ++ vmmc-supply = <®_dldo1>; ++ status = "okay"; ++}; ++ ++&mmc2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc2_pins>; ++ vmmc-supply = <®_dldo1>; ++ vqmmc-supply = <®_aldo1>; ++ bus-width = <8>; ++ non-removable; ++ cap-mmc-hw-reset; ++ mmc-ddr-1_8v; ++ mmc-hs200-1_8v; ++ mmc-hs400-1_8v; ++ status = "okay"; ++}; ++ ++&uart0 { ++ status = "okay"; ++}; ++ ++&usbotg { ++ /* ++ * PHY0 pins are connected to a USB-C socket, but a role switch ++ * is not implemented: both CC pins are pulled to GND. ++ * The VBUS pins power the device, so a fixed peripheral mode ++ * is the best choice. ++ * The board can be powered via GPIOs, in this case port0 *can* ++ * act as a host (with a cable/adapter ignoring CC), as VBUS is ++ * then provided by the GPIOs. Any user of this setup would ++ * need to adjust the DT accordingly: dr_mode set to "host", ++ * enabling OHCI0 and EHCI0. ++ */ ++ dr_mode = "peripheral"; ++ status = "okay"; ++}; ++ ++&usbphy { ++ usb1_vbus-supply = <®_vcc5v>; ++ status = "okay"; ++}; ++ ++&r_i2c { ++ status = "okay"; ++ ++ axp313: pmic@36 { ++ compatible = "x-powers,axp313a"; ++ reg = <0x36>; ++ ++ vin1-supply = <®_vcc5v>; ++ vin2-supply = <®_vcc5v>; ++ vin3-supply = <®_vcc5v>; ++ ++ regulators { ++ /* Supplies VCC-PLL, so needs to be always on. */ ++ reg_aldo1: aldo1 { ++ regulator-always-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc1v8"; ++ }; ++ ++ /* Supplies VCC-IO, so needs to be always on. */ ++ reg_dldo1: dldo1 { ++ regulator-always-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc3v3"; ++ }; ++ ++ reg_dcdc1: dcdc1 { ++ regulator-always-on; ++ regulator-min-microvolt = <810000>; ++ regulator-max-microvolt = <990000>; ++ regulator-name = "vdd-gpu-sys"; ++ }; ++ ++ reg_dcdc2: dcdc2 { ++ regulator-always-on; ++ regulator-min-microvolt = <810000>; ++ regulator-max-microvolt = <1100000>; ++ regulator-name = "vdd-cpu"; ++ }; ++ ++ reg_dcdc3: dcdc3 { ++ regulator-always-on; ++ regulator-min-microvolt = <1100000>; ++ regulator-max-microvolt = <1100000>; ++ regulator-name = "vdd-dram"; ++ }; ++ }; ++ }; ++}; ++ ++&pio { ++ vcc-pc-supply = <®_dldo1>; ++ vcc-pf-supply = <®_dldo1>; ++ vcc-pg-supply = <®_aldo1>; ++ vcc-ph-supply = <®_dldo1>; ++ vcc-pi-supply = <®_dldo1>; ++}; +diff --git a/configs/longanpi_3h_defconfig b/configs/longanpi_3h_defconfig +new file mode 100644 +index 0000000000..7111b173be +--- /dev/null ++++ b/configs/longanpi_3h_defconfig +@@ -0,0 +1,30 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_SUNXI=y ++CONFIG_DEFAULT_DEVICE_TREE="sun50i-h618-longanpi-3h" ++CONFIG_SPL=y ++CONFIG_DRAM_SUN50I_H616_DX_ODT=0x07070707 ++CONFIG_DRAM_SUN50I_H616_DX_DRI=0x0e0e0e0e ++CONFIG_DRAM_SUN50I_H616_CA_DRI=0x0e0e ++CONFIG_DRAM_SUN50I_H616_ODT_EN=0xaaaaeeee ++CONFIG_DRAM_SUN50I_H616_TPR6=0x48808080 ++CONFIG_DRAM_SUN50I_H616_TPR10=0x402f6663 ++CONFIG_DRAM_SUN50I_H616_TPR11=0x26262524 ++CONFIG_DRAM_SUN50I_H616_TPR12=0x100f100f ++CONFIG_MACH_SUN50I_H616=y ++CONFIG_SUNXI_DRAM_H616_LPDDR4=y ++CONFIG_DRAM_CLK=792 ++CONFIG_R_I2C_ENABLE=y ++CONFIG_SPL_SPI_SUNXI=y ++# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_SPL_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 ++CONFIG_MTD=y ++CONFIG_SPI_FLASH_ZBIT=y ++CONFIG_AXP313_POWER=y ++CONFIG_SPI=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_OHCI_HCD=y ++CONFIG_USB_MUSB_GADGET=y + +-- +2.34.1 + diff --git a/patch/u-boot/v2024.10/board_longanpi-3h/0007-lpi3h-drivers-emmc-add-emmc-boot-support.patch b/patch/u-boot/v2024.10/board_longanpi-3h/0007-lpi3h-drivers-emmc-add-emmc-boot-support.patch new file mode 100644 index 0000000000..5ecf831525 --- /dev/null +++ b/patch/u-boot/v2024.10/board_longanpi-3h/0007-lpi3h-drivers-emmc-add-emmc-boot-support.patch @@ -0,0 +1,63 @@ +From 6b011e0bf404a7ebed07c535213ae54035544171 Mon Sep 17 00:00:00 2001 +From: Tiandi Zhou +Date: Fri, 19 Jan 2024 11:57:49 +0800 +Subject: [PATCH 7/8] lpi3h: drivers: emmc: add emmc boot support + +--- + arch/arm/dts/sun50i-h618-longanpi-3h.dts | 1 - + drivers/mmc/sunxi_mmc.c | 11 ++++++++++- + 2 files changed, 10 insertions(+), 2 deletions(-) + +diff --git a/arch/arm/dts/sun50i-h618-longanpi-3h.dts b/arch/arm/dts/sun50i-h618-longanpi-3h.dts +index b0ff07ce72..4965cbd345 100644 +--- a/arch/arm/dts/sun50i-h618-longanpi-3h.dts ++++ b/arch/arm/dts/sun50i-h618-longanpi-3h.dts +@@ -100,7 +100,6 @@ + cap-mmc-hw-reset; + mmc-ddr-1_8v; + mmc-hs200-1_8v; +- mmc-hs400-1_8v; + status = "okay"; + }; + +diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c +index 4d6351bf27..074b08ac5d 100644 +--- a/drivers/mmc/sunxi_mmc.c ++++ b/drivers/mmc/sunxi_mmc.c +@@ -540,6 +540,10 @@ struct mmc *sunxi_mmc_init(int sdc_no) + cfg->f_min = 400000; + cfg->f_max = 52000000; + ++ if(sdc_no==2) { ++ cfg->f_max = 20000000; ++ } ++ + if (mmc_resource_init(sdc_no) != 0) + return NULL; + +@@ -636,9 +640,10 @@ static int sunxi_mmc_probe(struct udevice *dev) + struct mmc_config *cfg = &plat->cfg; + struct ofnode_phandle_args args; + u32 *ccu_reg; +- int ret; ++ int bus_width, ret; + + cfg->name = dev->name; ++ bus_width = dev_read_u32_default(dev, "bus-width", 1); + + cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; + cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS; +@@ -651,6 +656,10 @@ static int sunxi_mmc_probe(struct udevice *dev) + if (ret) + return ret; + ++ if (bus_width == 8) { ++ cfg->f_max = 20000000; ++ } ++ + priv->reg = dev_read_addr_ptr(dev); + + /* We don't have a sunxi clock driver so find the clock address here */ +-- +2.34.1 +