diff --git a/bin/ap6210.zip b/bin/ap6210.zip new file mode 100644 index 0000000000..f34e14bbe9 Binary files /dev/null and b/bin/ap6210.zip differ diff --git a/bin/hostapd23.tgz b/bin/hostapd23.tgz new file mode 100644 index 0000000000..d63ef90c5c Binary files /dev/null and b/bin/hostapd23.tgz differ diff --git a/bin/imagewriter.exe b/bin/imagewriter.exe new file mode 100644 index 0000000000..b64f3b1b75 Binary files /dev/null and b/bin/imagewriter.exe differ diff --git a/bin/linux-firmware.zip b/bin/linux-firmware.zip new file mode 100644 index 0000000000..16f5d39eec Binary files /dev/null and b/bin/linux-firmware.zip differ diff --git a/bin/ramlog_2.0.0_all.deb b/bin/ramlog_2.0.0_all.deb new file mode 100644 index 0000000000..08f7493170 Binary files /dev/null and b/bin/ramlog_2.0.0_all.deb differ diff --git a/bin/temper.tgz b/bin/temper.tgz new file mode 100644 index 0000000000..575f4722a1 Binary files /dev/null and b/bin/temper.tgz differ diff --git a/config/bananapi.fex b/config/bananapi.fex new file mode 100644 index 0000000000..72fed34fb0 --- /dev/null +++ b/config/bananapi.fex @@ -0,0 +1,1072 @@ +[product] +version = "100" +machine = "bananapi" + +[platform] +eraseflag = 0 + +[target] +boot_clock = 912 +dcdc2_vol = 1450 +dcdc3_vol = 1300 +ldo2_vol = 3000 +ldo3_vol = 2800 +ldo4_vol = 2800 +storage_type = 0 + +[clock] +pll3 = 297 +pll4 = 300 +pll6 = 600 +pll7 = 297 +pll8 = 336 + +[card_boot] +logical_start = 40960 +sprite_gpio0 = + +[card0_boot_para] +card_ctrl = 0 +card_high_speed = 1 +card_line = 4 +sdc_d1 = port:PF00<2><1> +sdc_d0 = port:PF01<2><1> +sdc_clk = port:PF02<2><1> +sdc_cmd = port:PF03<2><1> +sdc_d3 = port:PF04<2><1> +sdc_d2 = port:PF05<2><1> + +[card2_boot_para] +card_ctrl = 2 +card_high_speed = 1 +card_line = 4 +sdc_cmd = port:PC06<3><1> +sdc_clk = port:PC07<3><1> +sdc_d0 = port:PC08<3><1> +sdc_d1 = port:PC09<3><1> +sdc_d2 = port:PC10<3><1> +sdc_d3 = port:PC11<3><1> + +[twi_para] +twi_port = 0 +twi_scl = port:PB00<2> +twi_sda = port:PB01<2> + +[uart_para] +uart_debug_port = 0 +uart_debug_tx = port:PB22<2><1> +uart_debug_rx = port:PB23<2><1> + +[uart_force_debug] +uart_debug_port = 0 +uart_debug_tx = port:PF02<4><1> +uart_debug_rx = port:PF04<4><1> + +[jtag_para] +jtag_enable = 0 +jtag_ms = port:PB14<3> +jtag_ck = port:PB15<3> +jtag_do = port:PB16<3> +jtag_di = port:PB17<3> + +[pm_para] +standby_mode = 0 + +[dram_para] +dram_baseaddr = 0x40000000 +dram_clk = 432 +dram_type = 3 +dram_rank_num = 1 +dram_chip_density = 4096 +dram_io_width = 16 +dram_bus_width = 32 +dram_cas = 9 +dram_zq = 0x7f +dram_odt_en = 0 +dram_size = 1024 +dram_tpr0 = 0x42d899b7 +dram_tpr1 = 0xa090 +dram_tpr2 = 0x22a00 +dram_tpr3 = 0x0 +dram_tpr4 = 0x1 +dram_tpr5 = 0x0 +dram_emr1 = 0x4 +dram_emr2 = 0x10 +dram_emr3 = 0x0 + +[mali_para] +mali_used = 1 +mali_clkdiv = 1 + +[gmac_para] +gmac_used = 1 +gmac_rxd3 = port:PA00<5><3> +gmac_rxd2 = port:PA01<5><3> +gmac_rxd1 = port:PA02<5><3> +gmac_rxd0 = port:PA03<5><3> +gmac_txd3 = port:PA04<5><3> +gmac_txd2 = port:PA05<5><3> +gmac_txd1 = port:PA06<5><3> +gmac_txd0 = port:PA07<5><3> +gmac_rxclk = port:PA08<5><3> +gmac_rxerr = port:PA09<0><3> +gmac_rxctl = port:PA10<5><3> +gmac_mdc = port:PA11<5><3> +gmac_mdio = port:PA12<5><3> +gmac_txctl = port:PA13<5><3> +gmac_txclk = port:PA14<0><3> +gmac_txck = port:PA15<5><3> +gmac_clkin = port:PA16<5><3> +gmac_txerr = port:PA17<0><3> + +[gmac_phy_power] +gmac_phy_power_en = port:PH23<1><0> + +[twi0_para] +twi0_used = 1 +twi0_scl = port:PB00<2> +twi0_sda = port:PB01<2> + +[twi1_para] +twi1_used = 1 +twi1_scl = port:PB18<2> +twi1_sda = port:PB19<2> + +[twi2_para] +twi2_used = 1 +twi2_scl = port:PB20<2> +twi2_sda = port:PB21<2> + +[twi3_para] +twi3_used = 1 +twi3_scl = port:PI00<3> +twi3_sda = port:PI01<3> + +[uart_para0] +uart_used = 1 +uart_port = 0 +uart_type = 2 +uart_tx = port:PB22<2><1> +uart_rx = port:PB23<2><1> + +[uart_para1] +uart_used = 0 +uart_port = 1 +uart_type = 8 +uart_tx = port:PA10<4><1> +uart_rx = port:PA11<4><1> +uart_rts = port:PA12<4><1> +uart_cts = port:PA13<4><1> +uart_dtr = port:PA14<4><1> +uart_dsr = port:PA15<4><1> +uart_dcd = port:PA16<4><1> +uart_ring = port:PA17<4><1> + +[uart_para2] +uart_used = 0 +uart_port = 2 +uart_type = 4 +uart_tx = port:PI18<3><1> +uart_rx = port:PI19<3><1> +uart_rts = port:PI16<3><1> +uart_cts = port:PI17<3><1> + +[uart_para3] +uart_used = 0 +uart_port = 3 +uart_type = 2 +uart_tx = port:PH00<4><1> +uart_rx = port:PH01<4><1> + +[uart_para4] +uart_used = 0 +uart_port = 4 +uart_type = 2 +uart_tx = port:PH04<4><1> +uart_rx = port:PH05<4><1> + +[uart_para5] +uart_used = 0 +uart_port = 5 +uart_type = 2 +uart_tx = port:PH06<4><1> +uart_rx = port:PH07<4><1> + +[uart_para6] +uart_used = 0 +uart_port = 6 +uart_type = 2 +uart_tx = port:PA12<4><1> +uart_rx = port:PA13<4><1> + +[uart_para7] +uart_used = 1 +uart_port = 7 +uart_type = 2 +uart_tx = port:PI20<3><1> +uart_rx = port:PI21<3><1> + +[spi0_para] +spi_used = 1 +spi_cs_bitmap = 3 +spi_cs0 = port:PI10<2> +spi_cs1 = port:PI14<2> +spi_sclk = port:PI11<2> +spi_mosi = port:PI12<2> +spi_miso = port:PI13<2> + +[spi1_para] +spi_used = 0 +spi_cs_bitmap = 1 +spi_cs0 = port:PA00<3> +spi_cs1 = port:PA04<3> +spi_sclk = port:PA01<3> +spi_mosi = port:PA02<3> +spi_miso = port:PA03<3> + +[spi2_para] +spi_used = 0 +spi_cs_bitmap = 1 +spi_cs0 = port:PC19<3> +spi_cs1 = port:PB13<2> +spi_sclk = port:PC20<3> +spi_mosi = port:PC21<3> +spi_miso = port:PC22<3> + +[spi3_para] +spi_used = 0 +spi_cs_bitmap = 1 +spi_cs0 = port:PA05<3> +spi_cs1 = port:PA09<3> +spi_sclk = port:PA06<3> +spi_mosi = port:PA07<3> +spi_miso = port:PA08<3> + +[spi_devices] +spi_dev_num = 1 + +[spi_board0] +modalias = "spidev" +max_speed_hz = 12000000 +bus_num = 0 +chip_select = 0 +mode = 3 +full_duplex = 0 +manual_cs = 0 + +[spi_board1] +modalias = "spidev" +max_speed_hz = 12000000 +bus_num = 0 +chip_select = 1 +mode = 3 +full_duplex = 0 +manual_cs = 0 + +[ctp_para] +ctp_used = 0 +ctp_name = "gt811" +ctp_twi_id = 2 +ctp_twi_addr = 0x40 +ctp_screen_max_x = 1024 +ctp_screen_max_y = 600 +ctp_revert_x_flag = 0 +ctp_revert_y_flag = 0 +ctp_exchange_x_y_flag = 1 +ctp_firm = 1 +ctp_int_port = port:PH21<6> +ctp_wakeup = port:PB13<1><1> + +[ctp_list_para] +ctp_det_used = 0 +ft5x_ts = 0 +gt82x = 0 +gslX680 = 0 +gt9xx_ts = 0 +gt811 = 0 + +[tkey_para] +tkey_used = 0 +tkey_twi_id = 2 +tkey_twi_addr = 0x62 +tkey_int = port:PI13<6> + +[motor_para] +motor_used = 0 +motor_shake = port:PB03<1><1> + +[gpio_para] +gpio_used = 1 +gpio_num = 88 +gpio_pin_1 = port:PB20<1> +gpio_pin_2 = port:PB21<1> +gpio_pin_3 = port:PB20<1> +gpio_pin_4 = port:PI03<1> +gpio_pin_5 = port:PB22<1> +gpio_pin_6 = port:PB23<1> +gpio_pin_7 = port:PI14<1> +gpio_pin_8 = port:PI10<1> +gpio_pin_9 = port:PI13<1> +gpio_pin_10 = port:PI12<1> +gpio_pin_11 = port:PI11<1> +gpio_pin_12 = port:PH05<1> +gpio_pin_13 = port:PH03<1> +gpio_pin_14 = port:PH00<1> +gpio_pin_15 = port:PH01<1> +gpio_pin_16 = port:PH01<1> +gpio_pin_17 = port:PI19<1> +gpio_pin_18 = port:PH02<1> +gpio_pin_19 = port:PH02<1> +gpio_pin_20 = port:PI20<1> +gpio_pin_21 = port:PI21<1> +gpio_pin_22 = port:PI17<1> +gpio_pin_23 = port:PH20<1> +gpio_pin_24 = port:PH21<1> +gpio_pin_25 = port:PI16<1> +gpio_pin_26 = port:PI16<1> +gpio_pin_27 = port:PI18<1> +gpio_pin_28 = port:PH05<1> +gpio_pin_29 = port:PI21<1> +gpio_pin_30 = port:PH03<1> +gpio_pin_31 = port:PI20<1> +gpio_pin_32 = port:PH17<1> +gpio_pin_33 = port:PB19<1> +gpio_pin_34 = port:PB18<1> +gpio_pin_35 = port:PH19<1> +gpio_pin_36 = port:PE00<1> +gpio_pin_37 = port:PH16<1> +gpio_pin_38 = port:PE01<1> +gpio_pin_39 = port:PH14<1> +gpio_pin_40 = port:PE03<1> +gpio_pin_41 = port:PE02<1> +gpio_pin_42 = port:PH18<1> +gpio_pin_43 = port:PH11<1> +gpio_pin_44 = port:PE04<1> +gpio_pin_45 = port:PE05<1> +gpio_pin_46 = port:PE06<1> +gpio_pin_47 = port:PE07<1> +gpio_pin_48 = port:PE08<1> +gpio_pin_49 = port:PE09<1> +gpio_pin_50 = port:PE10<1> +gpio_pin_51 = port:PE11<1> +gpio_pin_52 = port:PH13<1> +gpio_pin_53 = port:PI01<1> +gpio_pin_54 = port:PI00<1> +gpio_pin_55 = port:PH07<1> +gpio_pin_56 = port:PH08<1> +gpio_pin_57 = port:PB02<1> +gpio_pin_58 = port:PH09<1> +gpio_pin_59 = port:PD25<1> +gpio_pin_60 = port:PD27<1> +gpio_pin_61 = port:PD26<1> +gpio_pin_62 = port:PH06<1> +gpio_pin_63 = port:PD24<1> +gpio_pin_64 = port:PD23<1> +gpio_pin_65 = port:PD22<1> +gpio_pin_66 = port:PD21<1> +gpio_pin_67 = port:PD20<1> +gpio_pin_68 = port:PD19<1> +gpio_pin_69 = port:PD18<1> +gpio_pin_70 = port:PD17<1> +gpio_pin_71 = port:PD16<1> +gpio_pin_72 = port:PH12<1> +gpio_pin_73 = port:PD00<1> +gpio_pin_74 = port:PD01<1> +gpio_pin_75 = port:PD02<1> +gpio_pin_76 = port:PD03<1> +gpio_pin_77 = port:PD04<1> +gpio_pin_78 = port:PD05<1> +gpio_pin_79 = port:PD06<1> +gpio_pin_80 = port:PD07<1> +gpio_pin_81 = port:PD08<1> +gpio_pin_82 = port:PD09<1> +gpio_pin_83 = port:PD10<1> +gpio_pin_84 = port:PD11<1> +gpio_pin_85 = port:PD12<1> +gpio_pin_86 = port:PD13<1> +gpio_pin_87 = port:PD14<1> +gpio_pin_88 = port:PD15<1> + +[nand_para] +nand_used = 0 +nand_we = port:PC00<2> +nand_ale = port:PC01<2> +nand_cle = port:PC02<2> +nand_ce1 = port:PC03<2> +nand_ce0 = port:PC04<2> +nand_nre = port:PC05<2> +nand_rb0 = port:PC06<2> +nand_rb1 = port:PC07<2> +nand_d0 = port:PC08<2> +nand_d1 = port:PC09<2> +nand_d2 = port:PC10<2> +nand_d3 = port:PC11<2> +nand_d4 = port:PC12<2> +nand_d5 = port:PC13<2> +nand_d6 = port:PC14<2> +nand_d7 = port:PC15<2> +nand_wp = port:PC16<2> +nand_ce2 = port:PC17<2> +nand_ce3 = port:PC18<2> +nand_ce4 = +nand_ce5 = +nand_ce6 = +nand_ce7 = +nand_spi = port:PC23<3> +nand_ndqs = port:PC24<2> +good_block_ratio = 0 + +[disp_init] +disp_init_enable = 1 +disp_mode = 0 +screen0_output_type = 3 +screen0_output_mode = 4 +screen1_output_type = 2 +screen1_output_mode = 11 +fb0_framebuffer_num = 2 +fb0_format = 10 +fb0_pixel_sequence = 0 +fb0_scaler_mode_enable = 1 +fb1_framebuffer_num = 2 +fb1_format = 10 +fb1_pixel_sequence = 0 +fb1_scaler_mode_enable = 0 +lcd0_backlight = 197 +lcd1_backlight = 197 +lcd0_bright = 50 +lcd0_contrast = 50 +lcd0_saturation = 57 +lcd0_hue = 50 +lcd1_bright = 50 +lcd1_contrast = 50 +lcd1_saturation = 57 +lcd1_hue = 50 + +[lcd0_para] +lcd_used = 0 +lcd_x = 800 +lcd_y = 480 +lcd_dclk_freq = 33 +lcd_pwm_not_used = 0 +lcd_pwm_ch = 0 +lcd_pwm_freq = 10000 +lcd_pwm_pol = 0 +lcd_max_bright = 240 +lcd_min_bright = 64 +lcd_if = 0 +lcd_hbp = 46 +lcd_ht = 1055 +lcd_vbp = 23 +lcd_vt = 1050 +lcd_vspw = 0 +lcd_hspw = 0 +lcd_hv_if = 0 +lcd_hv_smode = 0 +lcd_hv_s888_if = 0 +lcd_hv_syuv_if = 0 +lcd_lvds_ch = 0 +lcd_lvds_mode = 0 +lcd_lvds_bitwidth = 0 +lcd_lvds_io_cross = 0 +lcd_cpu_if = 0 +lcd_frm = 0 +lcd_io_cfg0 = 268435456 +lcd_gamma_correction_en = 0 +lcd_gamma_tbl_0 = 0x0 +lcd_gamma_tbl_1 = 0x10101 +lcd_gamma_tbl_255 = 0xffffff +lcd_bl_en_used = 1 +lcd_bl_en = port:PH07<1><0><1> +lcd_power_used = 1 +lcd_power = port:PH08<1><0><1> +lcd_pwm_used = 1 +lcd_pwm = port:PB02<2><0> +lcdd0 = port:PD00<2><0> +lcdd1 = port:PD01<2><0> +lcdd2 = port:PD02<2><0> +lcdd3 = port:PD03<2><0> +lcdd4 = port:PD04<2><0> +lcdd5 = port:PD05<2><0> +lcdd6 = port:PD06<2><0> +lcdd7 = port:PD07<2><0> +lcdd8 = port:PD08<2><0> +lcdd9 = port:PD09<2><0> +lcdd10 = port:PD10<2><0> +lcdd11 = port:PD11<2><0> +lcdd12 = port:PD12<2><0> +lcdd13 = port:PD13<2><0> +lcdd14 = port:PD14<2><0> +lcdd15 = port:PD15<2><0> +lcdd16 = port:PD16<2><0> +lcdd17 = port:PD17<2><0> +lcdd18 = port:PD18<2><0> +lcdd19 = port:PD19<2><0> +lcdd20 = port:PD20<2><0> +lcdd21 = port:PD21<2><0> +lcdd22 = port:PD22<2><0> +lcdd23 = port:PD23<2><0> +lcdclk = port:PD24<2><0> +lcdde = port:PD25<2><0> +lcdhsync = port:PD26<2><0> +lcdvsync = port:PD27<2><0> + +[lcd1_para] +lcd_used = 0 +lcd_x = 0 +lcd_y = 0 +lcd_dclk_freq = 0 +lcd_pwm_not_used = 0 +lcd_pwm_ch = 1 +lcd_pwm_freq = 0 +lcd_pwm_pol = 0 +lcd_max_bright = 240 +lcd_min_bright = 64 +lcd_if = 0 +lcd_hbp = 0 +lcd_ht = 0 +lcd_vbp = 0 +lcd_vt = 0 +lcd_vspw = 0 +lcd_hspw = 0 +lcd_hv_if = 0 +lcd_hv_smode = 0 +lcd_hv_s888_if = 0 +lcd_hv_syuv_if = 0 +lcd_lvds_ch = 0 +lcd_lvds_mode = 0 +lcd_lvds_bitwidth = 0 +lcd_lvds_io_cross = 0 +lcd_cpu_if = 0 +lcd_frm = 0 +lcd_io_cfg0 = 0 +lcd_gamma_correction_en = 0 +lcd_gamma_tbl_0 = 0x0 +lcd_gamma_tbl_1 = 0x10101 +lcd_gamma_tbl_255 = 0xffffff +lcd_bl_en_used = 0 +lcd_bl_en = +lcd_power_used = 0 +lcd_power = +lcd_pwm_used = 1 +lcd_pwm = port:PI03<2><0> +lcd_gpio_0 = +lcd_gpio_1 = +lcd_gpio_2 = +lcd_gpio_3 = +lcdd0 = port:PH00<2><0> +lcdd1 = port:PH01<2><0> +lcdd2 = port:PH02<2><0> +lcdd3 = port:PH03<2><0> +lcdd4 = port:PH04<2><0> +lcdd5 = port:PH05<2><0> +lcdd6 = port:PH06<2><0> +lcdd7 = port:PH07<2><0> +lcdd8 = port:PH08<2><0> +lcdd9 = port:PH09<2><0> +lcdd10 = port:PH10<2><0> +lcdd11 = port:PH11<2><0> +lcdd12 = port:PH12<2><0> +lcdd13 = port:PH13<2><0> +lcdd14 = port:PH14<2><0> +lcdd15 = port:PH15<2><0> +lcdd16 = port:PH16<2><0> +lcdd17 = port:PH17<2><0> +lcdd18 = port:PH18<2><0> +lcdd19 = port:PH19<2><0> +lcdd20 = port:PH20<2><0> +lcdd21 = port:PH21<2><0> +lcdd22 = port:PH22<2><0> +lcdd23 = port:PH23<2><0> +lcdclk = port:PH24<2><0> +lcdde = port:PH25<2><0> +lcdhsync = port:PH26<2><0> +lcdvsync = port:PH27<2><0> + +[tv_out_dac_para] +dac_used = 0 +dac0_src = 4 +dac1_src = 5 +dac2_src = 6 +dac3_src = 0 + +[hdmi_para] +hdmi_used = 1 + +[csi0_para] +csi_used = 1 +csi_dev_qty = 1 +csi_stby_mode = 0 +csi_mname = "ov5640" +csi_twi_id = 1 +csi_twi_addr = 0x78 +csi_if = 0 +csi_vflip = 1 +csi_hflip = 0 +csi_iovdd = "axp20_pll" +csi_avdd = "" +csi_dvdd = "" +csi_vol_iovdd = 2800 +csi_vol_dvdd = +csi_vol_avdd = +csi_flash_pol = 0 +csi_facing = 0 +csi_pck = port:PE00<3> +csi_ck = port:PE01<3> +csi_hsync = port:PE02<3> +csi_vsync = port:PE03<3> +csi_d0 = port:PE04<3> +csi_d1 = port:PE05<3> +csi_d2 = port:PE06<3> +csi_d3 = port:PE07<3> +csi_d4 = port:PE08<3> +csi_d5 = port:PE09<3> +csi_d6 = port:PE10<3> +csi_d7 = port:PE11<3> +csi_reset = port:PH14<1><0> +csi_power_en = port:PH16<1><0> +csi_stby = port:PH19<1><0> + +[csi1_para] +csi_used = 0 +csi_dev_qty = 1 +csi_stby_mode = 0 +csi_mname = "gc0308" +csi_if = 0 +csi_iovdd = "axp20_pll" +csi_avdd = "" +csi_dvdd = "" +csi_vol_iovdd = 2800 +csi_vol_dvdd = +csi_vol_avdd = +csi_vflip = 0 +csi_hflip = 0 +csi_flash_pol = 0 +csi_facing = 1 +csi_twi_id = 1 +csi_twi_addr = 0x42 +csi_pck = port:PG00<3> +csi_ck = port:PG01<3> +csi_hsync = port:PG02<3> +csi_vsync = port:PG03<3> +csi_d0 = port:PG04<3> +csi_d1 = port:PG05<3> +csi_d2 = port:PG06<3> +csi_d3 = port:PG07<3> +csi_d4 = port:PG08<3> +csi_d5 = port:PG09<3> +csi_d6 = port:PG10<3> +csi_d7 = port:PG11<3> +csi_reset = port:PH13<1><0> +csi_power_en = port:PH16<1><0> +csi_stby = port:PH18<1><0> + +[camera_list_para] +camera_list_para_used = 1 +ov7670 = 0 +gc0308 = 0 +gt2005 = 0 +hi704 = 0 +sp0838 = 0 +mt9m112 = 0 +mt9m113 = 0 +ov2655 = 0 +hi253 = 0 +gc0307 = 0 +mt9d112 = 0 +ov5640 = 1 +gc2015 = 0 +ov2643 = 0 +gc0329 = 0 +gc0309 = 0 +tvp5150 = 0 +s5k4ec = 0 +ov5650_mv9335 = 0 +siv121d = 0 +gc2035 = 0 + +[tvout_para] +tvout_used = 0 +tvout_channel_num = 1 + +[tvin_para] +tvin_used = 0 +tvin_channel_num = 4 + +[sata_para] +sata_used = 1 +sata_power_en = + +[mmc0_para] +sdc_used = 1 +sdc_detmode = 1 +sdc_buswidth = 4 +sdc_clk = port:PF02<2><1><2> +sdc_cmd = port:PF03<2><1><2> +sdc_d0 = port:PF01<2><1><2> +sdc_d1 = port:PF00<2><1><2> +sdc_d2 = port:PF05<2><1><2> +sdc_d3 = port:PF04<2><1><2> +sdc_det = port:PH10<0><1> +sdc_use_wp = 0 +sdc_wp = +sdc_isio = 0 +sdc_regulator = "none" + +[mmc1_para] +sdc_used = 0 +sdc_detmode = 4 +sdc_buswidth = 4 +sdc_clk = port:PG00<2><1><2> +sdc_cmd = port:PG01<2><1><2> +sdc_d0 = port:PG02<2><1><2> +sdc_d1 = port:PG03<2><1><2> +sdc_d2 = port:PG04<2><1><2> +sdc_d3 = port:PG05<2><1><2> +sdc_det = +sdc_use_wp = 0 +sdc_wp = +sdc_isio = 0 +sdc_regulator = "none" + +[mmc2_para] +sdc_used = 0 +sdc_detmode = 3 +sdc_buswidth = 4 +sdc_cmd = port:PC06<3><1><2> +sdc_clk = port:PC07<3><1><2> +sdc_d0 = port:PC08<3><1><2> +sdc_d1 = port:PC09<3><1><2> +sdc_d2 = port:PC10<3><1><2> +sdc_d3 = port:PC11<3><1><2> +sdc_det = +sdc_use_wp = 0 +sdc_wp = +sdc_isio = 0 +sdc_regulator = "none" + +[mmc3_para] +sdc_used = 0 +sdc_detmode = 4 +sdc_buswidth = 4 +sdc_cmd = port:PI04<2><1><2> +sdc_clk = port:PI05<2><1><2> +sdc_d0 = port:PI06<2><1><2> +sdc_d1 = port:PI07<2><1><2> +sdc_d2 = port:PI08<2><1><2> +sdc_d3 = port:PI09<2><1><2> +sdc_det = +sdc_use_wp = 0 +sdc_wp = +sdc_isio = 1 +sdc_regulator = "none" + +[ms_para] +ms_used = 0 +ms_bs = port:PH06<5> +ms_clk = port:PH07<5> +ms_d0 = port:PH08<5> +ms_d1 = port:PH09<5> +ms_d2 = port:PH10<5> +ms_d3 = port:PH11<5> +ms_det = + +[smc_para] +smc_used = 0 +smc_rst = port:PH13<5> +smc_vppen = port:PH14<5> +smc_vppp = port:PH15<5> +smc_det = port:PH16<5> +smc_vccen = port:PH17<5> +smc_sck = port:PH18<5> +smc_sda = port:PH19<5> + +[ps2_0_para] +ps2_used = 0 +ps2_scl = port:PI20<2><1> +ps2_sda = port:PI21<2><1> + +[ps2_1_para] +ps2_used = 0 +ps2_scl = port:PI14<3><1> +ps2_sda = port:PI15<3><1> + +[can_para] +can_used = 0 +can_tx = port:PA16<3> +can_rx = port:PA17<3> + +[keypad_para] +kp_used = 0 +kp_in_size = 8 +kp_out_size = 8 +kp_in0 = port:PH08<4><1> +kp_in1 = port:PH09<4><1> +kp_in2 = port:PH10<4><1> +kp_in3 = port:PH11<4><1> +kp_in4 = port:PH14<4><1> +kp_in5 = port:PH15<4><1> +kp_in6 = port:PH16<4><1> +kp_in7 = port:PH17<4><1> +kp_out0 = port:PH18<4><1> +kp_out1 = port:PH19<4><1> +kp_out2 = port:PH22<4><1> +kp_out3 = port:PH23<4><1> +kp_out4 = port:PH24<4><1> +kp_out5 = port:PH25<4><1> +kp_out6 = port:PH26<4><1> +kp_out7 = port:PH27<4><1> + +[usbc0] +usb_used = 1 +usb_port_type = 2 +usb_detect_type = 0 +usb_id_gpio = port:PH04<0><1> +usb_det_vbus_gpio = "axp_ctrl" +usb_drv_vbus_gpio = port:PB09<1><0><0> +usb_ac_enable_gpio = port:PH05<1><0><0> +usb_restrict_gpio = 0 +usb_host_init_state = 0 +usb_restric_flag = 0 +usb_restric_voltage = 3550000 +usb_restric_capacity = 5 + +[usbc1] +usb_used = 1 +usb_port_type = 1 +usb_detect_type = 0 +usb_drv_vbus_gpio = port:PH06<1><0><0> +usb_restrict_gpio = +usb_host_init_state = 1 +usb_restric_flag = 0 + +[usbc2] +usb_used = 1 +usb_port_type = 1 +usb_detect_type = 0 +usb_drv_vbus_gpio = port:PH03<1><0><0> +usb_restrict_gpio = +usb_host_init_state = 1 +usb_restric_flag = 0 + +[usb_feature] +vendor_id = 6353 +mass_storage_id = 1 +adb_id = 2 +manufacturer_name = "USB Developer" +product_name = "Android" +serial_number = "20080411" + +[msc_feature] +vendor_name = "USB 2.0" +product_name = "USB Flash Driver" +release = 100 +luns = 3 + +[gsensor_para] +gsensor_used = 0 +gsensor_twi_id = 1 +gsensor_int1 = +gsensor_int2 = + +[gsensor_list_para] +gsensor_det_used = 0 +bma250 = 1 +mma8452 = 1 +mma7660 = 1 +mma865x = 1 +afa750 = 1 +lis3de_acc = 1 +lis3dh_acc = 1 +kxtik = 1 +dmard10 = 0 +dmard06 = 1 +mxc622x = 1 +fxos8700 = 1 +lsm303d = 1 + +[gps_para] +gps_used = 0 +gps_spi_id = 2 +gps_spi_cs_num = 0 +gps_lradc = 1 +gps_clk = port:PI00<2> +gps_sign = port:PI01<2> +gps_mag = port:PI02<2> +gps_vcc_en = port:PC22<1><0> +gps_osc_en = port:PI14<1><0> +gps_rx_en = port:PI15<1><0> + +[wifi_para] +wifi_used = 0 +wifi_sdc_id = 3 +wifi_usbc_id = 2 +wifi_usbc_type = 1 +wifi_mod_sel = 6 +wifi_power = "" +ap6xxx_wl_regon = port:PH09<1><0> +ap6xxx_wl_host_wake = port:PH10<0><0> +ap6xxx_bt_regon = port:PH18<1><0> +ap6xxx_bt_wake = port:PH24<1><0> +ap6xxx_bt_host_wake = port:PH25<0><0> +ap6xxx_lpo = port:PI12<4><1><1> + +[usb_wifi_para] +usb_wifi_used = 1 +usb_wifi_usbc_num = 2 + +[3g_para] +3g_used = 0 +3g_usbc_num = 2 +3g_uart_num = 0 +3g_pwr = +3g_wakeup = +3g_int = + +[gy_para] +gy_used = 0 +gy_twi_id = 1 +gy_twi_addr = 0 +gy_int1 = port:PH18<6><1> +gy_int2 = port:PH19<6><1> + +[ls_para] +ls_used = 0 +ls_twi_id = 1 +ls_twi_addr = 0 +ls_int = port:PH20<6><1> + +[compass_para] +compass_used = 0 +compass_twi_id = 1 +compass_twi_addr = 0 +compass_int = port:PI13<6><1> + +[bt_para] +bt_used = 0 +bt_uart_id = 2 +bt_wakeup = port:PI20<1> +bt_gpio = port:PI21<1> +bt_rst = port:PB05<1> + +[i2s_para] +i2s_used = 1 +i2s_channel = 2 +i2s_mclk = port:PB05<2><1> +i2s_bclk = port:PB06<2><1> +i2s_lrclk = port:PB07<2><1> +i2s_dout0 = port:PB08<2><1> +i2s_dout1 = +i2s_dout2 = +i2s_dout3 = +i2s_din = port:PB12<2><1> + +[spdif_para] +spdif_used = 0 +spdif_mclk = +spdif_dout = port:PB13<4><1> +spdif_din = + +[audio_para] +audio_used = 1 +capture_used = 1 +audio_pa_ctrl = port:PH15<1><1> + +[switch_para] +switch_used = 0 + +[leds_para] +leds_used = 1 +leds_num = 1 +leds_pin_1 = port:PH24<1><0> +leds_name_1 = "green:ph24:led1" +leds_default_1 = 1 +leds_trigger_1 = "mmc0" + +[ir_para] +ir_used = 1 +ir0_rx = port:PB04<2> + +[pmu_para] +pmu_used = 1 +pmu_twi_addr = 52 +pmu_twi_id = 0 +pmu_irq_id = 32 +pmu_battery_rdc = 100 +pmu_battery_cap = 3200 +pmu_init_chgcur = 300 +pmu_earlysuspend_chgcur = 600 +pmu_suspend_chgcur = 1000 +pmu_resume_chgcur = 300 +pmu_shutdown_chgcur = 1000 +pmu_init_chgvol = 4200 +pmu_init_chgend_rate = 15 +pmu_init_chg_enabled = 1 +pmu_init_adc_freq = 100 +pmu_init_adc_freqc = 100 +pmu_init_chg_pretime = 50 +pmu_init_chg_csttime = 720 +pmu_bat_para1 = 0 +pmu_bat_para2 = 0 +pmu_bat_para3 = 0 +pmu_bat_para4 = 0 +pmu_bat_para5 = 5 +pmu_bat_para6 = 8 +pmu_bat_para7 = 11 +pmu_bat_para8 = 22 +pmu_bat_para9 = 33 +pmu_bat_para10 = 43 +pmu_bat_para11 = 50 +pmu_bat_para12 = 59 +pmu_bat_para13 = 71 +pmu_bat_para14 = 83 +pmu_bat_para15 = 92 +pmu_bat_para16 = 100 +pmu_usbvol_limit = 1 +pmu_usbcur_limit = 0 +pmu_usbvol = 4000 +pmu_usbcur = 0 +pmu_usbvol_pc = 4400 +pmu_usbcur_pc = 500 +pmu_pwroff_vol = 3300 +pmu_pwron_vol = 2900 +pmu_pekoff_time = 4000 +pmu_pekoff_en = 1 +pmu_peklong_time = 1500 +pmu_pekon_time = 1000 +pmu_pwrok_time = 64 +pmu_pwrnoe_time = 2000 +pmu_intotp_en = 1 +pmu_backupen = 1 +pmu_used2 = 0 +pmu_adpdet = port:PH02<0> +pmu_init_chgcur2 = 400 +pmu_earlysuspend_chgcur2 = 600 +pmu_suspend_chgcur2 = 1200 +pmu_resume_chgcur2 = 400 +pmu_shutdown_chgcur2 = 1200 +pmu_suspendpwroff_vol = 3500 +pmu_batdeten = 1 + +[recovery_key] +key_min = 4 +key_max = 10 + +[dvfs_table] +max_freq = 912000000 +min_freq = 720000000 +LV_count = 7 +LV1_freq = 1008000000 +LV1_volt = 1450 +LV2_freq = 912000000 +LV2_volt = 1425 +LV3_freq = 864000000 +LV3_volt = 1350 +LV4_freq = 720000000 +LV4_volt = 1250 +LV5_freq = 528000000 +LV5_volt = 1150 +LV6_freq = 312000000 +LV6_volt = 1100 +LV7_freq = 144000000 +LV7_volt = 1050 + diff --git a/config/hostapd.conf.bananapi b/config/hostapd.conf.bananapi new file mode 100644 index 0000000000..3a4d346d0c --- /dev/null +++ b/config/hostapd.conf.bananapi @@ -0,0 +1,19 @@ +ssid=BANANA +interface=wlan0 +hw_mode=g +channel=1 +bridge=br0 + +logger_syslog=0 +logger_syslog_level=0 + +wmm_enabled=0 +wpa=2 +preamble=1 +wpa_psk=66eb31d2b48d19ba216f2e50c6831ee11be98e2fa3a8075e30b866f4a5ccda27 +wpa_passphrase=12345678 +wpa_key_mgmt=WPA-PSK +wpa_pairwise=TKIP +rsn_pairwise=CCMP +auth_algs=1 +macaddr_acl=0 \ No newline at end of file diff --git a/config/interfaces.bonding b/config/interfaces.bonding new file mode 100644 index 0000000000..3c291139ea --- /dev/null +++ b/config/interfaces.bonding @@ -0,0 +1,24 @@ +auto eth0 +iface eth0 inet manual + bond-master bond0 + bond-primary eth0 + bond-mode active-backup + +auto wlan0 +iface wlan0 inet manual + wpa-ssid your_SSID + wpa-psk xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + + # to generate proper encrypted key: wpa_passphrase your_SSID your_password + + bond-master bond0 + bond-primary eth0 + bond-mode active-backup + +# Define master +auto bond0 +iface bond0 inet dhcp + bond-slaves none + bond-primary eth0 + bond-mode active-backup + bond-miimon 100 diff --git a/config/interfaces.default b/config/interfaces.default new file mode 100644 index 0000000000..90f970e006 --- /dev/null +++ b/config/interfaces.default @@ -0,0 +1,23 @@ +# Wired adapter #1 +auto eth0 + iface eth0 inet dhcp +# hwaddress ether # if you want to set MAC manually +# pre-up /sbin/ifconfig eth0 mtu 3838 # setting MTU for DHCP, static just: mtu 3838 +# +# Wired adapter #2 +#auto eth1 +# iface eth1 inet dhcp +# hwaddress ether # if you want to set MAC manually +# pre-up /sbin/ifconfig eth0 mtu 3838 # setting MTU for DHCP, static just: mtu 3838 +# +# Wireless adapter #1 +#auto wlan0 +# allow-hotplug wlan0 +# iface wlan0 inet dhcp +# wpa-ssid SSID +# wpa-psk xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +# to generate proper encrypted key: wpa_passphrase yourSSID yourpassword +# +# Local loopback +auto lo + iface lo inet loopback \ No newline at end of file diff --git a/config/interfaces.hostapd b/config/interfaces.hostapd new file mode 100644 index 0000000000..7ffaae48ed --- /dev/null +++ b/config/interfaces.hostapd @@ -0,0 +1,12 @@ +auto lo br0 +iface lo inet loopback + +allow-hotplug eth0 +iface eth0 inet manual + +allow-hotplug wlan0 +iface wlan0 inet manual + +iface br0 inet dhcp +bridge_ports eth0 wlan0 +#hwaddress ether # will be added at first boot diff --git a/config/linux-sunxi.config b/config/linux-sunxi.config new file mode 100644 index 0000000000..1100caca5d --- /dev/null +++ b/config/linux-sunxi.config @@ -0,0 +1,3953 @@ +# +# Automatically generated file; DO NOT EDIT. +# Linux/arm 3.4.104 Kernel Configuration +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +# CONFIG_ARCH_USES_GETTIMEOFFSET is not set +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_KTIME_SCALAR=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_LOCKBREAK=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_ARCH_HAS_CPUFREQ=y +CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_NEED_MACH_IO_H=y +CONFIG_NEED_MACH_MEMORY_H=y +CONFIG_GENERIC_BUG=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_HAVE_IRQ_WORK=y +CONFIG_IRQ_WORK=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="" +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_XZ is not set +# CONFIG_KERNEL_LZO is not set +CONFIG_DEFAULT_HOSTNAME="(none)" +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +# CONFIG_FHANDLE is not set +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_AUDIT=y +# CONFIG_AUDITSYSCALL is not set +# CONFIG_AUDIT_LOGINUID_IMMUTABLE is not set +CONFIG_HAVE_GENERIC_HARDIRQS=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_DEBUG=y + +# +# RCU Subsystem +# +CONFIG_TREE_PREEMPT_RCU=y +CONFIG_PREEMPT_RCU=y +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +CONFIG_RCU_FAST_NO_HZ=y +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_RCU_BOOST is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=19 +CONFIG_CGROUPS=y +# CONFIG_CGROUP_DEBUG is not set +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CPUSETS=y +CONFIG_PROC_PID_CPUSET=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_RESOURCE_COUNTERS=y +CONFIG_CGROUP_MEM_RES_CTLR=y +CONFIG_CGROUP_MEM_RES_CTLR_SWAP=y +CONFIG_CGROUP_MEM_RES_CTLR_SWAP_ENABLED=y +CONFIG_CGROUP_MEM_RES_CTLR_KMEM=y +CONFIG_CGROUP_PERF=y +CONFIG_CGROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +CONFIG_CFS_BANDWIDTH=y +CONFIG_RT_GROUP_SCHED=y +CONFIG_BLK_CGROUP=y +# CONFIG_DEBUG_BLK_CGROUP is not set +# CONFIG_CHECKPOINT_RESTORE is not set +CONFIG_NAMESPACES=y +CONFIG_UTS_NS=y +CONFIG_IPC_NS=y +CONFIG_USER_NS=y +CONFIG_PID_NS=y +CONFIG_NET_NS=y +# CONFIG_SCHED_AUTOGROUP is not set +CONFIG_MM_OWNER=y +# CONFIG_SYSFS_DEPRECATED is not set +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +CONFIG_RD_XZ=y +CONFIG_RD_LZO=y +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_PANIC_TIMEOUT=0 +# CONFIG_EXPERT is not set +CONFIG_UID16=y +# CONFIG_SYSCTL_SYSCALL is not set +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +# CONFIG_EMBEDDED is not set +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +CONFIG_PERF_EVENTS=y +CONFIG_PERF_COUNTERS=y +# CONFIG_DEBUG_PERF_USE_VMALLOC is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +# CONFIG_COMPAT_BRK is not set +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_JUMP_LABEL=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_USE_GENERIC_SMP_HELPERS=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_HW_BREAKPOINT=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_STOP_MACHINE=y +CONFIG_BLOCK=y +CONFIG_LBDAF=y +CONFIG_BLK_DEV_BSG=y +CONFIG_BLK_DEV_BSGLIB=y +CONFIG_BLK_DEV_INTEGRITY=y +# CONFIG_BLK_DEV_THROTTLING is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +CONFIG_OSF_PARTITION=y +CONFIG_AMIGA_PARTITION=y +# CONFIG_ATARI_PARTITION is not set +CONFIG_MAC_PARTITION=y +CONFIG_MSDOS_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +# CONFIG_LDM_PARTITION is not set +CONFIG_SGI_PARTITION=y +# CONFIG_ULTRIX_PARTITION is not set +CONFIG_SUN_PARTITION=y +CONFIG_KARMA_PARTITION=y +CONFIG_EFI_PARTITION=y +# CONFIG_SYSV68_PARTITION is not set +CONFIG_SUNXI_NAND_PARTITION=y + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +CONFIG_CFQ_GROUP_IOSCHED=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +CONFIG_UNINLINE_SPIN_UNLOCK=y +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +# CONFIG_INLINE_READ_UNLOCK is not set +# CONFIG_INLINE_READ_UNLOCK_BH is not set +# CONFIG_INLINE_READ_UNLOCK_IRQ is not set +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +# CONFIG_INLINE_WRITE_UNLOCK is not set +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_FREEZER=y + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_VEXPRESS is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_BCMRING is not set +# CONFIG_ARCH_HIGHBANK is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CNS3XXX is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_PRIMA2 is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_MXS is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LPC32XX is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_TEGRA is not set +# CONFIG_ARCH_PICOXCELL is not set +# CONFIG_ARCH_SUN4I is not set +# CONFIG_ARCH_SUN5I is not set +CONFIG_ARCH_SUN7I=y +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_SHMOBILE is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C24XX is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5P64X0 is not set +# CONFIG_ARCH_S5PC100 is not set +# CONFIG_ARCH_S5PV210 is not set +# CONFIG_ARCH_EXYNOS is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_U8500 is not set +# CONFIG_ARCH_NOMADIK is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_PLAT_SPEAR is not set +# CONFIG_ARCH_VT8500 is not set +# CONFIG_ARCH_ZYNQ is not set +# CONFIG_GPIO_PCA953X is not set +CONFIG_KEYBOARD_GPIO_POLLED=m + +# +# System MMU +# + +# +# Allwinner's sunxi options +# +CONFIG_SW_DEBUG_UART=0 +CONFIG_SUNXI_MULTIPLATFORM=y +CONFIG_SUNXI_SCALING_MIN=60 +CONFIG_PLAT_SUNXI=y + +# +# Processor Type +# +CONFIG_CPU_V7=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +# CONFIG_ARM_LPAE is not set +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set +CONFIG_ARM_THUMB=y +# CONFIG_ARM_THUMBEE is not set +CONFIG_SWP_EMULATE=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_MIGHT_HAVE_CACHE_L2X0=y +# CONFIG_CACHE_L2X0 is not set +CONFIG_ARM_L1_CACHE_SHIFT_6=y +CONFIG_ARM_L1_CACHE_SHIFT=6 +CONFIG_ARM_DMA_MEM_BUFFERABLE=y +CONFIG_ARCH_HAS_BARRIERS=y +CONFIG_ARM_NR_BANKS=8 +CONFIG_CPU_HAS_PMU=y +CONFIG_MULTI_IRQ_HANDLER=y +# CONFIG_ARM_ERRATA_430973 is not set +# CONFIG_ARM_ERRATA_458693 is not set +# CONFIG_ARM_ERRATA_460075 is not set +# CONFIG_ARM_ERRATA_742230 is not set +# CONFIG_ARM_ERRATA_742231 is not set +# CONFIG_ARM_ERRATA_720789 is not set +# CONFIG_ARM_ERRATA_743622 is not set +# CONFIG_ARM_ERRATA_751472 is not set +# CONFIG_ARM_ERRATA_754322 is not set +# CONFIG_ARM_ERRATA_754327 is not set +# CONFIG_ARM_ERRATA_764369 is not set +# CONFIG_ARM_ERRATA_775420 is not set +CONFIG_ARM_GIC=y +# CONFIG_FIQ_DEBUGGER is not set + +# +# Bus support +# +CONFIG_ARM_AMBA=y +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_HAVE_SMP=y +CONFIG_SMP=y +CONFIG_SMP_ON_UP=y +CONFIG_ARM_CPU_TOPOLOGY=y +CONFIG_SCHED_MC=y +CONFIG_SCHED_SMT=y +CONFIG_HAVE_ARM_SCU=y +CONFIG_ARM_ARCH_TIMER=y +CONFIG_HAVE_ARM_TWD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_NR_CPUS=2 +CONFIG_HOTPLUG_CPU=y +CONFIG_LOCAL_TIMERS=y +CONFIG_ARCH_NR_GPIO=0 +# CONFIG_PREEMPT_NONE is not set +# CONFIG_PREEMPT_VOLUNTARY is not set +CONFIG_PREEMPT=y +CONFIG_PREEMPT_COUNT=y +CONFIG_HZ=300 +# CONFIG_THUMB2_KERNEL is not set +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +CONFIG_HAVE_ARCH_PFN_VALID=y +CONFIG_HIGHMEM=y +# CONFIG_HIGHPTE is not set +CONFIG_HW_PERF_EVENTS=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_COMPACTION=y +CONFIG_MIGRATION=y +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +CONFIG_KSM=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +# CONFIG_CLEANCACHE is not set +CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set +# CONFIG_SECCOMP is not set +# CONFIG_CC_STACKPROTECTOR is not set +# CONFIG_DEPRECATED_PARAM_STRUCT is not set +# CONFIG_ARM_FLUSH_CONSOLE_ON_RESTART is not set + +# +# Boot options +# +# CONFIG_USE_OF is not set +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_CMDLINE="console=ttyS0,115200 root=/dev/mmc0p1 rw init=/init loglevel=8" +CONFIG_CMDLINE_FROM_BOOTLOADER=y +# CONFIG_CMDLINE_EXTEND is not set +# CONFIG_CMDLINE_FORCE is not set +# CONFIG_XIP_KERNEL is not set +CONFIG_KEXEC=y +CONFIG_ATAGS_PROC=y +# CONFIG_CRASH_DUMP is not set +# CONFIG_AUTO_ZRELADDR is not set + +# +# CPU Power Management +# + +# +# CPU Frequency scaling +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_TABLE=y +CONFIG_CPU_FREQ_STAT=y +# CONFIG_CPU_FREQ_STAT_DETAILS is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_FANTASY is not set +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set +CONFIG_CPU_FREQ_GOV_USERSPACE=m +# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set +CONFIG_CPU_FREQ_GOV_INTERACTIVE=y +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set +# CONFIG_CPU_FREQ_GOV_FANTASY is not set +CONFIG_CPU_FREQ_USR_EVNT_NOTIFY=y +CONFIG_CPU_FREQ_DVFS=y + +# +# ARM CPU frequency scaling drivers +# +# CONFIG_ARM_EXYNOS4210_CPUFREQ is not set +# CONFIG_ARM_EXYNOS4X12_CPUFREQ is not set +# CONFIG_ARM_EXYNOS5250_CPUFREQ is not set +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_LADDER=y +CONFIG_CPU_IDLE_GOV_MENU=y +# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_VFP=y +CONFIG_VFPv3=y +CONFIG_NEON=y + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +# CONFIG_HAVE_AOUT is not set +CONFIG_BINFMT_MISC=y + +# +# Power management options +# +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +CONFIG_HAS_WAKELOCK=y +CONFIG_WAKELOCK=y +CONFIG_PM_SLEEP=y +CONFIG_PM_SLEEP_SMP=y +# CONFIG_PM_AUTOSLEEP is not set +# CONFIG_PM_WAKELOCKS is not set +CONFIG_PM_RUNTIME=y +CONFIG_PM=y +CONFIG_PM_DEBUG=y +CONFIG_PM_ADVANCED_DEBUG=y +# CONFIG_PM_TEST_SUSPEND is not set +CONFIG_CAN_PM_TRACE=y +# CONFIG_APM_EMULATION is not set +CONFIG_PM_CLK=y +CONFIG_CPU_PM=y +# CONFIG_SUSPEND_TIME is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARM_CPU_SUSPEND=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_UNIX=y +# CONFIG_UNIX_DIAG is not set +CONFIG_XFRM=y +CONFIG_XFRM_USER=y +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +CONFIG_XFRM_IPCOMP=y +CONFIG_NET_KEY=y +# CONFIG_NET_KEY_MIGRATE is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_FIB_TRIE_STATS=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_ROUTE_CLASSID=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_NET_IPIP=y +CONFIG_NET_IPGRE_DEMUX=m +CONFIG_NET_IPGRE=m +CONFIG_NET_IPGRE_BROADCAST=y +CONFIG_IP_MROUTE=y +CONFIG_IP_MROUTE_MULTIPLE_TABLES=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +CONFIG_ARPD=y +CONFIG_SYN_COOKIES=y +CONFIG_INET_AH=y +CONFIG_INET_ESP=y +CONFIG_INET_IPCOMP=y +CONFIG_INET_XFRM_TUNNEL=y +CONFIG_INET_TUNNEL=y +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +CONFIG_INET_LRO=y +CONFIG_INET_DIAG=m +CONFIG_INET_TCP_DIAG=m +CONFIG_INET_UDP_DIAG=m +CONFIG_TCP_CONG_ADVANCED=y +CONFIG_TCP_CONG_BIC=y +CONFIG_TCP_CONG_CUBIC=y +CONFIG_TCP_CONG_WESTWOOD=y +CONFIG_TCP_CONG_HTCP=y +CONFIG_TCP_CONG_HSTCP=y +CONFIG_TCP_CONG_HYBLA=y +CONFIG_TCP_CONG_VEGAS=y +CONFIG_TCP_CONG_SCALABLE=y +CONFIG_TCP_CONG_LP=y +CONFIG_TCP_CONG_VENO=y +CONFIG_TCP_CONG_YEAH=y +CONFIG_TCP_CONG_ILLINOIS=y +# CONFIG_DEFAULT_BIC is not set +CONFIG_DEFAULT_CUBIC=y +# CONFIG_DEFAULT_HTCP is not set +# CONFIG_DEFAULT_HYBLA is not set +# CONFIG_DEFAULT_VEGAS is not set +# CONFIG_DEFAULT_VENO is not set +# CONFIG_DEFAULT_WESTWOOD is not set +# CONFIG_DEFAULT_RENO is not set +CONFIG_DEFAULT_TCP_CONG="cubic" +CONFIG_TCP_MD5SIG=y +CONFIG_IPV6=y +CONFIG_IPV6_PRIVACY=y +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_ROUTE_INFO=y +CONFIG_IPV6_OPTIMISTIC_DAD=y +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_IPCOMP=m +CONFIG_IPV6_MIP6=m +CONFIG_INET6_XFRM_TUNNEL=m +CONFIG_INET6_TUNNEL=m +CONFIG_INET6_XFRM_MODE_TRANSPORT=m +CONFIG_INET6_XFRM_MODE_TUNNEL=m +CONFIG_INET6_XFRM_MODE_BEET=m +CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m +CONFIG_IPV6_SIT=m +CONFIG_IPV6_SIT_6RD=y +CONFIG_IPV6_NDISC_NODETYPE=y +CONFIG_IPV6_TUNNEL=m +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_IPV6_SUBTREES=y +CONFIG_IPV6_MROUTE=y +CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y +CONFIG_IPV6_PIMSM_V2=y +# CONFIG_ANDROID_PARANOID_NETWORK is not set +CONFIG_NET_ACTIVITY_STATS=y +CONFIG_NETWORK_SECMARK=y +CONFIG_NETWORK_PHY_TIMESTAMPING=y +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_ADVANCED=y +CONFIG_BRIDGE_NETFILTER=y + +# +# Core Netfilter Configuration +# +CONFIG_NETFILTER_NETLINK=m +CONFIG_NETFILTER_NETLINK_ACCT=m +CONFIG_NETFILTER_NETLINK_QUEUE=m +CONFIG_NETFILTER_NETLINK_LOG=m +CONFIG_NF_CONNTRACK=m +CONFIG_NF_CONNTRACK_MARK=y +CONFIG_NF_CONNTRACK_SECMARK=y +CONFIG_NF_CONNTRACK_ZONES=y +CONFIG_NF_CONNTRACK_PROCFS=y +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CONNTRACK_TIMEOUT=y +CONFIG_NF_CONNTRACK_TIMESTAMP=y +CONFIG_NF_CT_PROTO_DCCP=m +CONFIG_NF_CT_PROTO_GRE=m +CONFIG_NF_CT_PROTO_SCTP=m +CONFIG_NF_CT_PROTO_UDPLITE=m +CONFIG_NF_CONNTRACK_AMANDA=m +CONFIG_NF_CONNTRACK_FTP=m +CONFIG_NF_CONNTRACK_H323=m +CONFIG_NF_CONNTRACK_IRC=m +CONFIG_NF_CONNTRACK_BROADCAST=m +CONFIG_NF_CONNTRACK_NETBIOS_NS=m +CONFIG_NF_CONNTRACK_SNMP=m +CONFIG_NF_CONNTRACK_PPTP=m +CONFIG_NF_CONNTRACK_SANE=m +CONFIG_NF_CONNTRACK_SIP=m +CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NF_CT_NETLINK=m +CONFIG_NF_CT_NETLINK_TIMEOUT=m +CONFIG_NETFILTER_TPROXY=m +CONFIG_NETFILTER_XTABLES=m + +# +# Xtables combined modules +# +CONFIG_NETFILTER_XT_MARK=m +CONFIG_NETFILTER_XT_CONNMARK=m +CONFIG_NETFILTER_XT_SET=m + +# +# Xtables targets +# +CONFIG_NETFILTER_XT_TARGET_AUDIT=m +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m +CONFIG_NETFILTER_XT_TARGET_CT=m +CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HL=m +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m +CONFIG_NETFILTER_XT_TARGET_LED=m +CONFIG_NETFILTER_XT_TARGET_LOG=m +CONFIG_NETFILTER_XT_TARGET_MARK=m +CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_NOTRACK=m +CONFIG_NETFILTER_XT_TARGET_RATEEST=m +CONFIG_NETFILTER_XT_TARGET_TEE=m +CONFIG_NETFILTER_XT_TARGET_TPROXY=m +CONFIG_NETFILTER_XT_TARGET_TRACE=m +CONFIG_NETFILTER_XT_TARGET_SECMARK=m +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m + +# +# Xtables matches +# +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_CLUSTER=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_CPU=m +CONFIG_NETFILTER_XT_MATCH_DCCP=m +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m +CONFIG_NETFILTER_XT_MATCH_DSCP=m +CONFIG_NETFILTER_XT_MATCH_ECN=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_HL=m +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m +CONFIG_NETFILTER_XT_MATCH_IPVS=m +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_NFACCT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m +CONFIG_NETFILTER_XT_MATCH_OWNER=m +CONFIG_NETFILTER_XT_MATCH_POLICY=m +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +CONFIG_NETFILTER_XT_MATCH_QUOTA2=m +CONFIG_NETFILTER_XT_MATCH_RATEEST=m +CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +CONFIG_NETFILTER_XT_MATCH_SCTP=m +CONFIG_NETFILTER_XT_MATCH_SOCKET=m +CONFIG_NETFILTER_XT_MATCH_STATE=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_TIME=m +CONFIG_NETFILTER_XT_MATCH_U32=m +CONFIG_IP_SET=m +CONFIG_IP_SET_MAX=256 +CONFIG_IP_SET_BITMAP_IP=m +CONFIG_IP_SET_BITMAP_IPMAC=m +CONFIG_IP_SET_BITMAP_PORT=m +CONFIG_IP_SET_HASH_IP=m +CONFIG_IP_SET_HASH_IPPORT=m +CONFIG_IP_SET_HASH_IPPORTIP=m +CONFIG_IP_SET_HASH_IPPORTNET=m +CONFIG_IP_SET_HASH_NET=m +CONFIG_IP_SET_HASH_NETPORT=m +CONFIG_IP_SET_HASH_NETIFACE=m +CONFIG_IP_SET_LIST_SET=m +CONFIG_IP_VS=m +CONFIG_IP_VS_IPV6=y +# CONFIG_IP_VS_DEBUG is not set +CONFIG_IP_VS_TAB_BITS=12 + +# +# IPVS transport protocol load balancing support +# +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_PROTO_AH_ESP=y +CONFIG_IP_VS_PROTO_ESP=y +CONFIG_IP_VS_PROTO_AH=y +CONFIG_IP_VS_PROTO_SCTP=y + +# +# IPVS scheduler +# +CONFIG_IP_VS_RR=m +CONFIG_IP_VS_WRR=m +CONFIG_IP_VS_LC=m +CONFIG_IP_VS_WLC=m +CONFIG_IP_VS_LBLC=m +CONFIG_IP_VS_LBLCR=m +CONFIG_IP_VS_DH=m +CONFIG_IP_VS_SH=m +CONFIG_IP_VS_SED=m +CONFIG_IP_VS_NQ=m + +# +# IPVS SH scheduler +# +CONFIG_IP_VS_SH_TAB_BITS=8 + +# +# IPVS application helper +# +CONFIG_IP_VS_FTP=m +CONFIG_IP_VS_NFCT=y +CONFIG_IP_VS_PE_SIP=m + +# +# IP: Netfilter Configuration +# +CONFIG_NF_DEFRAG_IPV4=m +CONFIG_NF_CONNTRACK_IPV4=m +CONFIG_NF_CONNTRACK_PROC_COMPAT=y +CONFIG_IP_NF_QUEUE=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_RPFILTER=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_REJECT_SKERR=y +CONFIG_IP_NF_TARGET_ULOG=m +CONFIG_NF_NAT=m +CONFIG_NF_NAT_NEEDED=y +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_NF_NAT_SNMP_BASIC=m +CONFIG_NF_NAT_PROTO_DCCP=m +CONFIG_NF_NAT_PROTO_GRE=m +CONFIG_NF_NAT_PROTO_UDPLITE=m +CONFIG_NF_NAT_PROTO_SCTP=m +CONFIG_NF_NAT_FTP=m +CONFIG_NF_NAT_IRC=m +CONFIG_NF_NAT_TFTP=m +CONFIG_NF_NAT_AMANDA=m +CONFIG_NF_NAT_PPTP=m +CONFIG_NF_NAT_H323=m +CONFIG_NF_NAT_SIP=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_NF_RAW=m +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m + +# +# IPv6: Netfilter Configuration +# +CONFIG_NF_DEFRAG_IPV6=m +CONFIG_NF_CONNTRACK_IPV6=m +CONFIG_IP6_NF_QUEUE=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m +CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_HL=m +CONFIG_IP6_NF_MATCH_IPV6HEADER=m +CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_RPFILTER=m +CONFIG_IP6_NF_MATCH_RT=m +CONFIG_IP6_NF_TARGET_HL=m +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_TARGET_REJECT_SKERR=y +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_RAW=m +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_EBT_BROUTE=m +CONFIG_BRIDGE_EBT_T_FILTER=m +CONFIG_BRIDGE_EBT_T_NAT=m +CONFIG_BRIDGE_EBT_802_3=m +CONFIG_BRIDGE_EBT_AMONG=m +CONFIG_BRIDGE_EBT_ARP=m +CONFIG_BRIDGE_EBT_IP=m +CONFIG_BRIDGE_EBT_IP6=m +CONFIG_BRIDGE_EBT_LIMIT=m +CONFIG_BRIDGE_EBT_MARK=m +CONFIG_BRIDGE_EBT_PKTTYPE=m +CONFIG_BRIDGE_EBT_STP=m +CONFIG_BRIDGE_EBT_VLAN=m +CONFIG_BRIDGE_EBT_ARPREPLY=m +CONFIG_BRIDGE_EBT_DNAT=m +CONFIG_BRIDGE_EBT_MARK_T=m +CONFIG_BRIDGE_EBT_REDIRECT=m +CONFIG_BRIDGE_EBT_SNAT=m +CONFIG_BRIDGE_EBT_LOG=m +CONFIG_BRIDGE_EBT_ULOG=m +CONFIG_BRIDGE_EBT_NFLOG=m +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +CONFIG_L2TP=m +# CONFIG_L2TP_DEBUGFS is not set +CONFIG_L2TP_V3=y +CONFIG_L2TP_IP=m +CONFIG_L2TP_ETH=m +CONFIG_STP=m +CONFIG_GARP=m +CONFIG_BRIDGE=m +CONFIG_BRIDGE_IGMP_SNOOPING=y +# CONFIG_NET_DSA is not set +CONFIG_VLAN_8021Q=m +CONFIG_VLAN_8021Q_GVRP=y +# CONFIG_DECNET is not set +CONFIG_LLC=m +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set +CONFIG_DNS_RESOLVER=y +CONFIG_BATMAN_ADV=m +# CONFIG_BATMAN_ADV_DEBUG is not set +CONFIG_OPENVSWITCH=m +CONFIG_RPS=y +CONFIG_RFS_ACCEL=y +CONFIG_XPS=y +CONFIG_NETPRIO_CGROUP=m +CONFIG_BQL=y +CONFIG_HAVE_BPF_JIT=y +# CONFIG_BPF_JIT is not set + +# +# Network testing +# +CONFIG_NET_PKTGEN=m +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +CONFIG_IRDA=m + +# +# IrDA protocols +# +CONFIG_IRLAN=m +CONFIG_IRNET=m +CONFIG_IRCOMM=m +CONFIG_IRDA_ULTRA=y + +# +# IrDA options +# +# CONFIG_IRDA_CACHE_LAST_LSAP is not set +# CONFIG_IRDA_FAST_RR is not set +# CONFIG_IRDA_DEBUG is not set + +# +# Infrared-port device drivers +# + +# +# SIR device drivers +# +CONFIG_IRTTY_SIR=m + +# +# Dongle support +# +# CONFIG_DONGLE is not set +CONFIG_KINGSUN_DONGLE=m +CONFIG_KSDAZZLE_DONGLE=m +CONFIG_KS959_DONGLE=m + +# +# FIR device drivers +# +CONFIG_USB_IRDA=m +CONFIG_SIGMATEL_FIR=m +CONFIG_MCS_FIR=m +CONFIG_BT=m +CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=m +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=m + +# +# Bluetooth device drivers +# +CONFIG_BT_HCIBTUSB=m +CONFIG_BT_HCIBTSDIO=m +CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_H4=y +CONFIG_BT_HCIUART_BCSP=y +CONFIG_BT_HCIUART_ATH3K=y +CONFIG_BT_HCIUART_LL=y +CONFIG_BT_HCIBCM203X=m +CONFIG_BT_HCIBPA10X=m +CONFIG_BT_HCIBFUSB=m +# CONFIG_BT_HCIVHCI is not set +CONFIG_BT_MRVL=m +CONFIG_BT_MRVL_SDIO=m +CONFIG_BT_ATH3K=m +CONFIG_BT_WILINK=m +CONFIG_AF_RXRPC=m +# CONFIG_AF_RXRPC_DEBUG is not set +CONFIG_RXKAD=m +CONFIG_FIB_RULES=y +CONFIG_WIRELESS=y +CONFIG_WIRELESS_EXT=y +CONFIG_WEXT_CORE=y +CONFIG_WEXT_PROC=y +CONFIG_WEXT_SPY=y +CONFIG_WEXT_PRIV=y +CONFIG_CFG80211=y +# CONFIG_NL80211_TESTMODE is not set +CONFIG_CFG80211_DEVELOPER_WARNINGS=y +# CONFIG_CFG80211_REG_DEBUG is not set +CONFIG_CFG80211_DEFAULT_PS=y +# CONFIG_CFG80211_DEBUGFS is not set +# CONFIG_CFG80211_INTERNAL_REGDB is not set +CONFIG_CFG80211_WEXT=y +CONFIG_WIRELESS_EXT_SYSFS=y +CONFIG_LIB80211=m +CONFIG_LIB80211_CRYPT_WEP=m +CONFIG_LIB80211_CRYPT_CCMP=m +CONFIG_LIB80211_CRYPT_TKIP=m +# CONFIG_LIB80211_DEBUG is not set +CONFIG_CFG80211_ALLOW_RECONNECT=y +CONFIG_MAC80211=m +CONFIG_MAC80211_HAS_RC=y +CONFIG_MAC80211_RC_MINSTREL=y +CONFIG_MAC80211_RC_MINSTREL_HT=y +CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y +CONFIG_MAC80211_RC_DEFAULT="minstrel_ht" +CONFIG_MAC80211_MESH=y +CONFIG_MAC80211_LEDS=y +# CONFIG_MAC80211_DEBUGFS is not set +# CONFIG_MAC80211_DEBUG_MENU is not set +CONFIG_WIMAX=m +CONFIG_WIMAX_DEBUG_LEVEL=8 +CONFIG_RFKILL=y +CONFIG_RFKILL_PM=y +CONFIG_RFKILL_LEDS=y +CONFIG_RFKILL_INPUT=y +# CONFIG_RFKILL_REGULATOR is not set +# CONFIG_RFKILL_GPIO is not set +CONFIG_SUNXI_RFKILL=y +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set +# CONFIG_CEPH_LIB is not set +# CONFIG_NFC is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_FIRMWARE_IN_KERNEL is not set +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_GENERIC_CPU_DEVICES is not set +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_SPI=y +CONFIG_DMA_SHARED_BUFFER=y +# CONFIG_SYNC is not set +# CONFIG_CMA is not set +CONFIG_CONNECTOR=y +CONFIG_PROC_EVENTS=y +# CONFIG_MTD is not set +CONFIG_PARPORT=m +# CONFIG_PARPORT_PC is not set +# CONFIG_PARPORT_GSC is not set +# CONFIG_PARPORT_AX88796 is not set +CONFIG_PARPORT_1284=y +CONFIG_PARPORT_NOT_PC=y +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 +CONFIG_BLK_DEV_CRYPTOLOOP=y +CONFIG_BLK_DEV_DRBD=m +# CONFIG_DRBD_FAULT_INJECTION is not set +CONFIG_BLK_DEV_NBD=m +# CONFIG_BLK_DEV_OSD is not set +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=65536 +# CONFIG_BLK_DEV_XIP is not set +CONFIG_CDROM_PKTCDVD=m +CONFIG_CDROM_PKTCDVD_BUFFERS=8 +# CONFIG_CDROM_PKTCDVD_WCACHE is not set +CONFIG_ATA_OVER_ETH=m +# CONFIG_MG_DISK is not set +# CONFIG_BLK_DEV_RBD is not set +CONFIG_SUNXI_NAND=y +# CONFIG_SUNXI_NAND_COMPAT_DEV is not set +# CONFIG_SUNXI_NAND_TEST is not set + +# +# Misc devices +# +CONFIG_SENSORS_LIS3LV02D=m +# CONFIG_AD525X_DPOT is not set +# CONFIG_SUN4I_VIBRATOR is not set +CONFIG_SUNXI_DBGREG=m +# CONFIG_ATMEL_PWM is not set +CONFIG_SUNXI_PWM=y +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_APDS9802ALS is not set +# CONFIG_ISL29003 is not set +# CONFIG_ISL29020 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_SENSORS_BH1780 is not set +# CONFIG_SENSORS_BH1770 is not set +# CONFIG_SENSORS_APDS990X is not set +# CONFIG_HMC6352 is not set +# CONFIG_SENSORS_AK8975 is not set +# CONFIG_DS1682 is not set +CONFIG_TI_DAC7512=m +# CONFIG_UID_STAT is not set +# CONFIG_BMP085 is not set +# CONFIG_USB_SWITCH_FSA9480 is not set +# CONFIG_WL127X_RFKILL is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +CONFIG_EEPROM_AT24=m +CONFIG_EEPROM_AT25=m +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +CONFIG_EEPROM_93CX6=m +CONFIG_EEPROM_93XX46=m +CONFIG_IWMC3200TOP=m +# CONFIG_IWMC3200TOP_DEBUG is not set +# CONFIG_IWMC3200TOP_DEBUGFS is not set + +# +# Texas Instruments shared transport line discipline +# +CONFIG_TI_ST=m +CONFIG_SENSORS_LIS3_SPI=m +CONFIG_SENSORS_LIS3_I2C=m + +# +# Altera FPGA firmware download module +# +CONFIG_ALTERA_STAPL=m + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +CONFIG_SCSI_NETLINK=y +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +CONFIG_BLK_DEV_SR=y +CONFIG_BLK_DEV_SR_VENDOR=y +CONFIG_CHR_DEV_SG=m +# CONFIG_CHR_DEV_SCH is not set +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +CONFIG_SCSI_FC_ATTRS=m +CONFIG_SCSI_ISCSI_ATTRS=m +# CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +CONFIG_ISCSI_TCP=m +# CONFIG_ISCSI_BOOT_SYSFS is not set +CONFIG_LIBFC=m +CONFIG_LIBFCOE=m +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_DH is not set +CONFIG_SCSI_OSD_INITIATOR=m +CONFIG_SCSI_OSD_ULD=m +CONFIG_SCSI_OSD_DPRINT_SENSE=1 +# CONFIG_SCSI_OSD_DEBUG is not set +CONFIG_ATA=y +# CONFIG_ATA_NONSTANDARD is not set +CONFIG_ATA_VERBOSE_ERROR=y +# CONFIG_SATA_PMP is not set + +# +# Controllers with non-SFF native interface +# +# CONFIG_SATA_AHCI_PLATFORM is not set +CONFIG_SW_SATA_AHCI_PLATFORM=y +# CONFIG_ATA_SFF is not set +CONFIG_MD=y +CONFIG_BLK_DEV_MD=m +# CONFIG_MD_LINEAR is not set +# CONFIG_MD_RAID0 is not set +CONFIG_MD_RAID1=m +# CONFIG_MD_RAID10 is not set +CONFIG_MD_RAID456=m +# CONFIG_MULTICORE_RAID456 is not set +# CONFIG_MD_MULTIPATH is not set +# CONFIG_MD_FAULTY is not set +CONFIG_BLK_DEV_DM_BUILTIN=y +CONFIG_BLK_DEV_DM=y +CONFIG_DM_DEBUG=y +CONFIG_DM_BUFIO=m +CONFIG_DM_PERSISTENT_DATA=m +CONFIG_DM_CRYPT=y +CONFIG_DM_SNAPSHOT=y +CONFIG_DM_THIN_PROVISIONING=m +# CONFIG_DM_DEBUG_BLOCK_STACK_TRACING is not set +# CONFIG_DM_DEBUG_SPACE_MAPS is not set +CONFIG_DM_MIRROR=y +CONFIG_DM_RAID=m +CONFIG_DM_LOG_USERSPACE=m +CONFIG_DM_ZERO=y +CONFIG_DM_MULTIPATH=y +CONFIG_DM_MULTIPATH_QL=y +CONFIG_DM_MULTIPATH_ST=y +CONFIG_DM_DELAY=m +CONFIG_DM_UEVENT=y +# CONFIG_DM_FLAKEY is not set +CONFIG_DM_VERITY=m +# CONFIG_TARGET_CORE is not set +CONFIG_NETDEVICES=y +CONFIG_NET_CORE=y +CONFIG_BONDING=y +# CONFIG_DUMMY is not set +# CONFIG_EQUALIZER is not set +CONFIG_MII=y +# CONFIG_NET_TEAM is not set +CONFIG_MACVLAN=y +CONFIG_MACVTAP=y +CONFIG_NETCONSOLE=y +CONFIG_NETCONSOLE_DYNAMIC=y +CONFIG_NETPOLL=y +# CONFIG_NETPOLL_TRAP is not set +CONFIG_NET_POLL_CONTROLLER=y +CONFIG_TUN=m +CONFIG_VETH=y + +# +# CAIF transport drivers +# +CONFIG_ETHERNET=y +CONFIG_NET_VENDOR_BROADCOM=y +# CONFIG_B44 is not set +# CONFIG_NET_CALXEDA_XGMAC is not set +CONFIG_NET_VENDOR_CHELSIO=y +CONFIG_NET_VENDOR_CIRRUS=y +# CONFIG_CS89x0 is not set +# CONFIG_DM9000 is not set +# CONFIG_DNET is not set +CONFIG_NET_VENDOR_DLINK=y +# CONFIG_DE600 is not set +# CONFIG_DE620 is not set +CONFIG_NET_VENDOR_FARADAY=y +# CONFIG_FTMAC100 is not set +# CONFIG_FTGMAC100 is not set +CONFIG_NET_VENDOR_INTEL=y +CONFIG_NET_VENDOR_I825XX=y +CONFIG_NET_VENDOR_MARVELL=y +CONFIG_NET_VENDOR_MICREL=y +# CONFIG_KS8851 is not set +# CONFIG_KS8851_MLL is not set +CONFIG_NET_VENDOR_MICROCHIP=y +# CONFIG_ENC28J60 is not set +CONFIG_NET_VENDOR_NATSEMI=y +CONFIG_NET_VENDOR_8390=y +# CONFIG_AX88796 is not set +# CONFIG_ETHOC is not set +CONFIG_NET_VENDOR_SEEQ=y +# CONFIG_SEEQ8005 is not set +CONFIG_NET_VENDOR_SMSC=y +# CONFIG_SMC91X is not set +# CONFIG_SMC911X is not set +# CONFIG_SMSC911X is not set +CONFIG_NET_VENDOR_STMICRO=y +# CONFIG_STMMAC_ETH is not set +CONFIG_SUNXI_EMAC=y +CONFIG_SUNXI_GMAC=y +CONFIG_GMAC_SCRIPT_SYS=y +CONFIG_GMAC_CLK_SYS=y +CONFIG_GMAC_FOR_BANANAPI=y +CONFIG_GMAC_RING=y +# CONFIG_GMAC_CHAINED is not set +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +# CONFIG_AMD_PHY is not set +# CONFIG_MARVELL_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_MICREL_PHY is not set +# CONFIG_FIXED_PHY is not set +# CONFIG_MDIO_BITBANG is not set +CONFIG_MICREL_KS8995MA=m +CONFIG_PLIP=m +CONFIG_PPP=y +CONFIG_PPP_BSDCOMP=y +CONFIG_PPP_DEFLATE=y +CONFIG_PPP_FILTER=y +CONFIG_PPP_MPPE=y +# CONFIG_PPP_MULTILINK is not set +CONFIG_PPPOE=y +CONFIG_PPTP=m +CONFIG_PPPOL2TP=m +CONFIG_PPPOLAC=y +CONFIG_PPPOPNS=y +CONFIG_PPP_ASYNC=y +CONFIG_PPP_SYNC_TTY=y +CONFIG_SLIP=m +CONFIG_SLHC=y +CONFIG_SLIP_COMPRESSED=y +CONFIG_SLIP_SMART=y +CONFIG_SLIP_MODE_SLIP6=y + +# +# USB Network Adapters +# +CONFIG_USB_CATC=m +CONFIG_USB_KAWETH=m +CONFIG_USB_PEGASUS=m +CONFIG_USB_RTL8150=m +CONFIG_USB_USBNET=m +CONFIG_USB_NET_AX8817X=m +CONFIG_USB_NET_QF9700=m +CONFIG_USB_NET_CDCETHER=m +CONFIG_USB_NET_CDC_EEM=m +CONFIG_USB_NET_CDC_NCM=m +CONFIG_USB_NET_DM9601=m +CONFIG_USB_NET_SMSC75XX=m +CONFIG_USB_NET_SMSC95XX=m +# CONFIG_USB_NET_GL620A is not set +# CONFIG_USB_NET_NET1080 is not set +# CONFIG_USB_NET_PLUSB is not set +CONFIG_USB_NET_MCS7830=m +CONFIG_USB_NET_RNDIS_HOST=m +CONFIG_USB_NET_CDC_SUBSET=m +CONFIG_USB_ALI_M5632=y +CONFIG_USB_AN2720=y +CONFIG_USB_BELKIN=y +CONFIG_USB_ARMLINUX=y +CONFIG_USB_EPSON2888=y +CONFIG_USB_KC2190=y +CONFIG_USB_NET_ZAURUS=m +CONFIG_USB_NET_CX82310_ETH=m +CONFIG_USB_NET_KALMIA=m +CONFIG_USB_NET_QMI_WWAN=m +CONFIG_USB_HSO=m +CONFIG_USB_NET_INT51X1=m +CONFIG_USB_IPHETH=m +CONFIG_USB_SIERRA_NET=m +CONFIG_USB_VL600=m +CONFIG_WLAN=y +CONFIG_LIBERTAS_THINFIRM=m +# CONFIG_LIBERTAS_THINFIRM_DEBUG is not set +CONFIG_LIBERTAS_THINFIRM_USB=m +CONFIG_AT76C50X_USB=m +CONFIG_USB_ZD1201=m +CONFIG_USB_NET_RNDIS_WLAN=m +CONFIG_RTL8187=m +CONFIG_RTL8187_LEDS=y +# CONFIG_MAC80211_HWSIM is not set +# CONFIG_WIFI_CONTROL_FUNC is not set +CONFIG_ATH_COMMON=m +# CONFIG_ATH_DEBUG is not set +CONFIG_ATH9K_HW=m +CONFIG_ATH9K_COMMON=m +CONFIG_ATH9K_BTCOEX_SUPPORT=y +CONFIG_ATH9K=m +CONFIG_ATH9K_AHB=y +# CONFIG_ATH9K_DEBUGFS is not set +# CONFIG_ATH9K_LEGACY_RATE_CONTROL is not set +CONFIG_ATH9K_HTC=m +# CONFIG_ATH9K_HTC_DEBUGFS is not set +CONFIG_CARL9170=m +CONFIG_CARL9170_LEDS=y +CONFIG_CARL9170_WPC=y +CONFIG_ATH6KL=m +CONFIG_ATH6KL_SDIO=m +CONFIG_ATH6KL_USB=m +# CONFIG_ATH6KL_DEBUG is not set +# CONFIG_B43 is not set +# CONFIG_B43LEGACY is not set +CONFIG_BCMDHD=m +CONFIG_BCMDHD_FW_PATH="/lib/firmware/ap6210/fw_bcmxxxx.bin" +CONFIG_BCMDHD_NVRAM_PATH="/lib/firmware/ap6210/nvram_apxxxx.txt" +CONFIG_BCMDHD_OOB=y +# CONFIG_BCMDHD_SDIO_IRQ is not set +CONFIG_BRCMUTIL=m +CONFIG_BRCMFMAC=m +CONFIG_BRCMFMAC_SDIO=y +CONFIG_BRCMFMAC_USB=y +# CONFIG_BRCMDBG is not set +CONFIG_BCM4330=m +CONFIG_HOSTAP=m +CONFIG_HOSTAP_FIRMWARE=y +# CONFIG_HOSTAP_FIRMWARE_NVRAM is not set +CONFIG_IWM=m +# CONFIG_IWM_DEBUG is not set +CONFIG_LIBERTAS=m +CONFIG_LIBERTAS_USB=m +CONFIG_LIBERTAS_SDIO=m +CONFIG_LIBERTAS_SPI=m +# CONFIG_LIBERTAS_DEBUG is not set +# CONFIG_LIBERTAS_MESH is not set +CONFIG_P54_COMMON=m +CONFIG_P54_USB=m +CONFIG_P54_SPI=m +CONFIG_P54_SPI_DEFAULT_EEPROM=y +CONFIG_P54_LEDS=y +CONFIG_RT2X00=m +CONFIG_RT2500USB=m +CONFIG_RT73USB=m +CONFIG_RT2800USB=m +CONFIG_RT2800USB_RT33XX=y +CONFIG_RT2800USB_RT35XX=y +CONFIG_RT2800USB_RT53XX=y +CONFIG_RT2800USB_UNKNOWN=y +CONFIG_RT2800_LIB=m +CONFIG_RT2X00_LIB_USB=m +CONFIG_RT2X00_LIB=m +CONFIG_RT2X00_LIB_FIRMWARE=y +CONFIG_RT2X00_LIB_CRYPTO=y +CONFIG_RT2X00_LIB_LEDS=y +# CONFIG_RT2X00_DEBUG is not set +# CONFIG_RTL8192CU is not set +CONFIG_WL1251=m +CONFIG_WL1251_SPI=m +CONFIG_WL1251_SDIO=m +CONFIG_WL12XX_MENU=m +CONFIG_WL12XX=m +CONFIG_WL12XX_SPI=m +CONFIG_WL12XX_SDIO=m +CONFIG_WL12XX_PLATFORM_DATA=y +CONFIG_ZD1211RW=m +# CONFIG_ZD1211RW_DEBUG is not set +CONFIG_MWIFIEX=m +CONFIG_MWIFIEX_SDIO=m +CONFIG_RTL8192CU_SW=m +CONFIG_RTL8188EU=m +CONFIG_RTL8189ES=m +CONFIG_RTL8723AS=m +CONFIG_RTXX7X_SW=m + +# +# WiMAX Wireless Broadband devices +# +CONFIG_WIMAX_I2400M=m +CONFIG_WIMAX_I2400M_USB=m +CONFIG_WIMAX_I2400M_SDIO=m +CONFIG_WIMAX_IWMC3200_SDIO=y +CONFIG_WIMAX_I2400M_DEBUG_LEVEL=8 +# CONFIG_WAN is not set +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +CONFIG_INPUT_FF_MEMLESS=y +CONFIG_INPUT_POLLDEV=y +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +CONFIG_INPUT_JOYDEV=y +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set +CONFIG_INPUT_KEYRESET=y + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +CONFIG_KEYBOARD_ADP5588=m +CONFIG_KEYBOARD_ADP5589=m +CONFIG_KEYBOARD_ATKBD=y +CONFIG_KEYBOARD_QT1070=m +CONFIG_KEYBOARD_QT2160=m +CONFIG_KEYBOARD_LKKBD=m +CONFIG_KEYBOARD_GPIO=m +CONFIG_KEYBOARD_TCA6416=m +CONFIG_KEYBOARD_TCA8418=m +CONFIG_KEYBOARD_MATRIX=m +CONFIG_KEYBOARD_LM8323=m +CONFIG_KEYBOARD_MAX7359=m +CONFIG_KEYBOARD_MCS=m +CONFIG_KEYBOARD_MPR121=m +CONFIG_KEYBOARD_NEWTON=m +CONFIG_KEYBOARD_OPENCORES=m +CONFIG_KEYBOARD_SAMSUNG=m +CONFIG_KEYBOARD_STOWAWAY=m +CONFIG_KEYBOARD_SUNKBD=m +CONFIG_KEYBOARD_OMAP4=m +CONFIG_KEYBOARD_XTKBD=m +CONFIG_KEYBOARD_SUN4IKEYPAD=m +CONFIG_KEYBOARD_SUN4I_KEYBOARD=m +# CONFIG_KEYBOARD_SUN4I_KEYBOARD_FEX is not set +CONFIG_KEYBOARD_HV2605_KEYBOARD=y +CONFIG_IR_SUNXI=m +CONFIG_INPUT_MOUSE=y +# CONFIG_MOUSE_PS2 is not set +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_APPLETOUCH is not set +# CONFIG_MOUSE_BCM5974 is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_MOUSE_GPIO is not set +# CONFIG_MOUSE_SYNAPTICS_I2C is not set +CONFIG_MOUSE_SYNAPTICS_USB=m +CONFIG_INPUT_JOYSTICK=y +# CONFIG_JOYSTICK_ANALOG is not set +# CONFIG_JOYSTICK_A3D is not set +# CONFIG_JOYSTICK_ADI is not set +# CONFIG_JOYSTICK_COBRA is not set +# CONFIG_JOYSTICK_GF2K is not set +# CONFIG_JOYSTICK_GRIP is not set +# CONFIG_JOYSTICK_GRIP_MP is not set +# CONFIG_JOYSTICK_GUILLEMOT is not set +# CONFIG_JOYSTICK_INTERACT is not set +# CONFIG_JOYSTICK_SIDEWINDER is not set +# CONFIG_JOYSTICK_TMDC is not set +# CONFIG_JOYSTICK_IFORCE is not set +# CONFIG_JOYSTICK_WARRIOR is not set +# CONFIG_JOYSTICK_MAGELLAN is not set +# CONFIG_JOYSTICK_SPACEORB is not set +# CONFIG_JOYSTICK_SPACEBALL is not set +# CONFIG_JOYSTICK_STINGER is not set +# CONFIG_JOYSTICK_TWIDJOY is not set +# CONFIG_JOYSTICK_ZHENHUA is not set +CONFIG_JOYSTICK_DB9=m +CONFIG_JOYSTICK_GAMECON=m +CONFIG_JOYSTICK_TURBOGRAFX=m +# CONFIG_JOYSTICK_AS5011 is not set +# CONFIG_JOYSTICK_JOYDUMP is not set +CONFIG_JOYSTICK_XPAD=m +CONFIG_JOYSTICK_XPAD_FF=y +CONFIG_JOYSTICK_XPAD_LEDS=y +CONFIG_JOYSTICK_WALKERA0701=m +CONFIG_INPUT_TABLET=y +CONFIG_TABLET_USB_ACECAD=m +CONFIG_TABLET_USB_AIPTEK=m +CONFIG_TABLET_USB_GTCO=m +CONFIG_TABLET_USB_HANWANG=m +CONFIG_TABLET_USB_KBTAB=m +CONFIG_TABLET_USB_WACOM=m +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_ADS7846=m +CONFIG_TOUCHSCREEN_AD7877=m +CONFIG_TOUCHSCREEN_AD7879=m +CONFIG_TOUCHSCREEN_AD7879_I2C=m +CONFIG_TOUCHSCREEN_AD7879_SPI=m +CONFIG_TOUCHSCREEN_ATMEL_MXT=m +CONFIG_TOUCHSCREEN_AUO_PIXCIR=m +CONFIG_TOUCHSCREEN_BU21013=m +CONFIG_TOUCHSCREEN_CY8CTMG110=m +CONFIG_TOUCHSCREEN_CYTTSP_CORE=m +CONFIG_TOUCHSCREEN_CYTTSP_I2C=m +CONFIG_TOUCHSCREEN_CYTTSP_SPI=m +CONFIG_TOUCHSCREEN_DYNAPRO=m +CONFIG_TOUCHSCREEN_HAMPSHIRE=m +CONFIG_TOUCHSCREEN_EETI=m +# CONFIG_TOUCHSCREEN_EGALAX is not set +CONFIG_TOUCHSCREEN_FUJITSU=m +CONFIG_TOUCHSCREEN_ILI210X=m +CONFIG_TOUCHSCREEN_GUNZE=m +CONFIG_TOUCHSCREEN_ELO=m +CONFIG_TOUCHSCREEN_WACOM_W8001=m +CONFIG_TOUCHSCREEN_MAX11801=m +CONFIG_TOUCHSCREEN_MCS5000=m +CONFIG_TOUCHSCREEN_MTOUCH=m +CONFIG_TOUCHSCREEN_INEXIO=m +CONFIG_TOUCHSCREEN_MK712=m +CONFIG_TOUCHSCREEN_PENMOUNT=m +CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI=m +CONFIG_TOUCHSCREEN_TOUCHRIGHT=m +CONFIG_TOUCHSCREEN_TOUCHWIN=m +CONFIG_TOUCHSCREEN_PIXCIR=m +CONFIG_TOUCHSCREEN_USB_COMPOSITE=m +CONFIG_TOUCHSCREEN_USB_EGALAX=y +CONFIG_TOUCHSCREEN_USB_PANJIT=y +CONFIG_TOUCHSCREEN_USB_3M=y +CONFIG_TOUCHSCREEN_USB_ITM=y +CONFIG_TOUCHSCREEN_USB_ETURBO=y +CONFIG_TOUCHSCREEN_USB_GUNZE=y +CONFIG_TOUCHSCREEN_USB_DMC_TSC10=y +CONFIG_TOUCHSCREEN_USB_IRTOUCH=y +CONFIG_TOUCHSCREEN_USB_IDEALTEK=y +CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH=y +CONFIG_TOUCHSCREEN_USB_GOTOP=y +CONFIG_TOUCHSCREEN_USB_JASTEC=y +CONFIG_TOUCHSCREEN_USB_ELO=y +CONFIG_TOUCHSCREEN_USB_E2I=y +CONFIG_TOUCHSCREEN_USB_ZYTRONIC=y +CONFIG_TOUCHSCREEN_USB_ETT_TC45USB=y +CONFIG_TOUCHSCREEN_USB_NEXIO=y +CONFIG_TOUCHSCREEN_USB_EASYTOUCH=y +CONFIG_TOUCHSCREEN_TOUCHIT213=m +CONFIG_TOUCHSCREEN_TSC_SERIO=m +CONFIG_TOUCHSCREEN_TSC2005=m +CONFIG_TOUCHSCREEN_TSC2007=m +CONFIG_TOUCHSCREEN_W90X900=m +CONFIG_TOUCHSCREEN_ST1232=m +CONFIG_TOUCHSCREEN_TPS6507X=m +CONFIG_TOUCHSCREEN_GT801=m +CONFIG_TOUCHSCREEN_GT811=m +CONFIG_TOUCHSCREEN_GT818=m +CONFIG_TOUCHSCREEN_SUN4I_TS=m +CONFIG_TOUCHSCREEN_FT5X_TS=m +CONFIG_TOUCHSCREEN_ZT8031=m +# CONFIG_TOUCHSCREEN_COASIA is not set +CONFIG_INPUT_MISC=y +CONFIG_INPUT_AD714X=m +CONFIG_INPUT_AD714X_I2C=m +CONFIG_INPUT_AD714X_SPI=m +CONFIG_INPUT_BMA150=m +CONFIG_INPUT_MMA8450=m +CONFIG_INPUT_MPU3050=m +CONFIG_INPUT_GP2A=m +CONFIG_INPUT_GPIO_TILT_POLLED=m +CONFIG_INPUT_ATI_REMOTE2=m +CONFIG_INPUT_KEYCHORD=m +CONFIG_INPUT_KEYSPAN_REMOTE=m +CONFIG_INPUT_KXTJ9=m +CONFIG_INPUT_KXTJ9_POLLED_MODE=y +CONFIG_INPUT_POWERMATE=m +CONFIG_INPUT_YEALINK=m +CONFIG_INPUT_CM109=m +CONFIG_INPUT_UINPUT=m +CONFIG_INPUT_GPIO=m +CONFIG_INPUT_PCF8574=m +CONFIG_INPUT_GPIO_ROTARY_ENCODER=m +CONFIG_INPUT_ADXL34X=m +CONFIG_INPUT_ADXL34X_I2C=m +CONFIG_INPUT_ADXL34X_SPI=m +CONFIG_INPUT_CMA3000=m +CONFIG_INPUT_CMA3000_I2C=m + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_PARKBD is not set +# CONFIG_SERIO_AMBAKMI is not set +CONFIG_SERIO_LIBPS2=m +# CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_SERIO_PS2MULT is not set +# CONFIG_GAMEPORT is not set +CONFIG_GSENSOR=y +CONFIG_SENSORS_BMA250=m +CONFIG_MEMSIC_ECOMPASS=m +CONFIG_SENSORS_MXC622X=m + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_VT_CONSOLE_SLEEP=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_UNIX98_PTYS=y +CONFIG_DEVPTS_MULTIPLE_INSTANCES=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_N_GSM is not set +# CONFIG_TRACE_SINK is not set +CONFIG_DEVMEM=y +CONFIG_DEVKMEM=y + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_SUNXI=y +CONFIG_SERIAL_8250_NR_UARTS=8 +CONFIG_SERIAL_8250_RUNTIME_UARTS=8 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_AMBA_PL010 is not set +# CONFIG_SERIAL_AMBA_PL011 is not set +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX3107 is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_IFX6X60 is not set +# CONFIG_SERIAL_XILINX_PS_UART is not set +CONFIG_PRINTER=m +# CONFIG_LP_CONSOLE is not set +CONFIG_PPDEV=m +# CONFIG_HVC_DCC is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_DCC_TTY is not set +# CONFIG_RAMOOPS is not set +CONFIG_SUNXI_G2D=y +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_CHARDEV=y +# CONFIG_I2C_MUX is not set +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_ALGOBIT=m + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_DESIGNWARE_PLATFORM is not set +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_PXA_PCI is not set +# CONFIG_I2C_SIMTEC is not set +CONFIG_I2C_SUNXI=y +# CONFIG_SUNXI_IIC_PRINT_TRANSFER_INFO is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_PARPORT is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_ALTERA is not set +CONFIG_SPI_BITBANG=y +# CONFIG_SPI_BUTTERFLY is not set +CONFIG_SPI_GPIO=y +# CONFIG_SPI_LM70_LLP is not set +# CONFIG_SPI_OC_TINY is not set +# CONFIG_SPI_PL022 is not set +# CONFIG_SPI_PXA2XX_PCI is not set +CONFIG_SPI_SUN7I=y +CONFIG_SUN7I_SPI_NDMA=y +# CONFIG_SPI_XILINX is not set +# CONFIG_SPI_DESIGNWARE is not set + +# +# SPI Protocol Masters +# +CONFIG_SPI_SPIDEV=m +# CONFIG_SPI_TLE62X0 is not set +# CONFIG_HSI is not set + +# +# PPS support +# +CONFIG_PPS=m +# CONFIG_PPS_DEBUG is not set + +# +# PPS clients support +# +# CONFIG_PPS_CLIENT_KTIMER is not set +# CONFIG_PPS_CLIENT_LDISC is not set +# CONFIG_PPS_CLIENT_PARPORT is not set +# CONFIG_PPS_CLIENT_GPIO is not set + +# +# PPS generators support +# + +# +# PTP clock support +# +CONFIG_PTP_1588_CLOCK=m +# CONFIG_DP83640_PHY is not set +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_DEBUG_GPIO is not set +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO drivers: +# +# CONFIG_GPIO_GENERIC_PLATFORM is not set +# CONFIG_GPIO_PL061 is not set +CONFIG_GPIO_SUNXI=y + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_SX150X is not set +# CONFIG_GPIO_ADP5588 is not set + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MCP23S08 is not set +# CONFIG_GPIO_MC33880 is not set +# CONFIG_GPIO_74X164 is not set + +# +# AC97 GPIO expanders: +# + +# +# MODULbus GPIO expanders: +# +CONFIG_W1=m +CONFIG_W1_CON=y +CONFIG_W1_SUNXI=m + +# +# 1-wire Bus Masters +# +CONFIG_W1_MASTER_DS2490=m +CONFIG_W1_MASTER_DS2482=m +CONFIG_W1_MASTER_DS1WM=m +CONFIG_W1_MASTER_GPIO=m + +# +# 1-wire Slaves +# +CONFIG_W1_SLAVE_THERM=m +CONFIG_W1_SLAVE_SMEM=m +CONFIG_W1_SLAVE_DS2408=m +CONFIG_W1_SLAVE_DS2423=m +CONFIG_W1_SLAVE_DS2431=m +CONFIG_W1_SLAVE_DS2433=m +# CONFIG_W1_SLAVE_DS2433_CRC is not set +CONFIG_W1_SLAVE_DS2760=m +CONFIG_W1_SLAVE_DS2780=m +CONFIG_W1_SLAVE_DS2781=m +CONFIG_W1_SLAVE_BQ27000=m +CONFIG_POWER_SUPPLY=y +CONFIG_AW_AXP=y +# CONFIG_AW_AXP18 is not set +# CONFIG_AW_AXP19 is not set +CONFIG_AW_AXP20=y +CONFIG_AXP_CHARGEINIT=y +CONFIG_AXP_CHGCHANGE=y +CONFIG_AXP_HWMON=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +CONFIG_AXP152=y +# CONFIG_PDA_POWER is not set +# CONFIG_TEST_POWER is not set +# CONFIG_BATTERY_DS2760 is not set +# CONFIG_BATTERY_DS2780 is not set +# CONFIG_BATTERY_DS2781 is not set +# CONFIG_BATTERY_DS2782 is not set +# CONFIG_BATTERY_SBS is not set +# CONFIG_BATTERY_BQ27x00 is not set +# CONFIG_BATTERY_MAX17040 is not set +# CONFIG_BATTERY_MAX17042 is not set +# CONFIG_CHARGER_ISP1704 is not set +# CONFIG_CHARGER_MAX8903 is not set +# CONFIG_CHARGER_LP8727 is not set +# CONFIG_CHARGER_GPIO is not set +# CONFIG_CHARGER_MANAGER is not set +# CONFIG_CHARGER_SMB347 is not set +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Native drivers +# +# CONFIG_SENSORS_MMA7660 is not set +# CONFIG_SENSORS_AD7314 is not set +# CONFIG_SENSORS_AD7414 is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADCXX is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7411 is not set +# CONFIG_SENSORS_ADT7462 is not set +# CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_ASC7621 is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_DS620 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_G760A is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_GPIO_FAN is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_JC42 is not set +# CONFIG_SENSORS_LINEAGE is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM70 is not set +# CONFIG_SENSORS_LM73 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_LTC4151 is not set +# CONFIG_SENSORS_LTC4215 is not set +# CONFIG_SENSORS_LTC4245 is not set +# CONFIG_SENSORS_LTC4261 is not set +# CONFIG_SENSORS_LM95241 is not set +# CONFIG_SENSORS_LM95245 is not set +# CONFIG_SENSORS_MAX1111 is not set +# CONFIG_SENSORS_MAX16065 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX1668 is not set +# CONFIG_SENSORS_MAX6639 is not set +# CONFIG_SENSORS_MAX6642 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_MCP3021 is not set +# CONFIG_SENSORS_NTC_THERMISTOR is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_PMBUS is not set +# CONFIG_SENSORS_SHT15 is not set +# CONFIG_SENSORS_SHT21 is not set +# CONFIG_SENSORS_SMM665 is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_EMC1403 is not set +# CONFIG_SENSORS_EMC2103 is not set +# CONFIG_SENSORS_EMC6W201 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_SCH56XX_COMMON is not set +# CONFIG_SENSORS_SCH5627 is not set +# CONFIG_SENSORS_SCH5636 is not set +# CONFIG_SENSORS_ADS1015 is not set +# CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_ADS7871 is not set +# CONFIG_SENSORS_AMC6821 is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_TMP102 is not set +# CONFIG_SENSORS_TMP401 is not set +# CONFIG_SENSORS_TMP421 is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83795 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +# CONFIG_THERMAL is not set +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_CORE is not set +# CONFIG_WATCHDOG_NOWAYOUT is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_ARM_SP805_WATCHDOG is not set +# CONFIG_DW_WATCHDOG is not set +# CONFIG_MPCORE_WATCHDOG is not set +# CONFIG_MAX63XX_WATCHDOG is not set +CONFIG_SUNXI_WDT=y + +# +# USB-based Watchdog Cards +# +CONFIG_USBPCWATCHDOG=m +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +CONFIG_SSB=m +CONFIG_SSB_SDIOHOST_POSSIBLE=y +CONFIG_SSB_SDIOHOST=y +# CONFIG_SSB_DEBUG is not set +CONFIG_BCMA_POSSIBLE=y + +# +# Broadcom specific AMBA +# +# CONFIG_BCMA is not set + +# +# Multifunction device drivers +# +CONFIG_MFD_CORE=m +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_TPS6105X is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set +# CONFIG_MFD_TPS65217 is not set +# CONFIG_MFD_TPS6586X is not set +# CONFIG_MFD_TPS65910 is not set +# CONFIG_MFD_TPS65912_I2C is not set +# CONFIG_MFD_TPS65912_SPI is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_TWL6040_CORE is not set +# CONFIG_MFD_STMPE is not set +# CONFIG_MFD_TC3589X is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_DA9052_SPI is not set +# CONFIG_MFD_DA9052_I2C is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_S5M_CORE is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_MC13XXX is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_EZX_PCAP is not set +CONFIG_MFD_WL1273_CORE=m +# CONFIG_MFD_TPS65090 is not set +# CONFIG_MFD_AAT2870_CORE is not set +# CONFIG_MFD_RC5T583 is not set +CONFIG_REGULATOR=y +# CONFIG_REGULATOR_DEBUG is not set +# CONFIG_REGULATOR_DUMMY is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +# CONFIG_REGULATOR_GPIO is not set +# CONFIG_REGULATOR_AD5398 is not set +# CONFIG_REGULATOR_ISL6271A is not set +# CONFIG_REGULATOR_MAX1586 is not set +# CONFIG_REGULATOR_MAX8649 is not set +# CONFIG_REGULATOR_MAX8660 is not set +# CONFIG_REGULATOR_MAX8952 is not set +# CONFIG_REGULATOR_LP3971 is not set +# CONFIG_REGULATOR_LP3972 is not set +# CONFIG_REGULATOR_TPS62360 is not set +# CONFIG_REGULATOR_TPS65023 is not set +# CONFIG_REGULATOR_TPS6507X is not set +# CONFIG_REGULATOR_TPS6524X is not set +CONFIG_MEDIA_SUPPORT=y + +# +# Multimedia core support +# +CONFIG_MEDIA_CONTROLLER=y +CONFIG_VIDEO_DEV=y +CONFIG_VIDEO_V4L2_COMMON=y +CONFIG_VIDEO_V4L2_SUBDEV_API=y +CONFIG_DVB_CORE=m +CONFIG_DVB_NET=y +CONFIG_VIDEO_MEDIA=m + +# +# Multimedia drivers +# +CONFIG_RC_CORE=m +CONFIG_LIRC=m +CONFIG_RC_MAP=m +CONFIG_IR_NEC_DECODER=m +CONFIG_IR_RC5_DECODER=m +CONFIG_IR_RC6_DECODER=m +CONFIG_IR_JVC_DECODER=m +CONFIG_IR_SONY_DECODER=m +CONFIG_IR_RC5_SZ_DECODER=m +CONFIG_IR_SANYO_DECODER=m +CONFIG_IR_MCE_KBD_DECODER=m +CONFIG_IR_LIRC_CODEC=m +CONFIG_RC_ATI_REMOTE=m +CONFIG_IR_IMON=m +CONFIG_IR_MCEUSB=m +CONFIG_IR_REDRAT3=m +CONFIG_IR_STREAMZAP=m +# CONFIG_RC_LOOPBACK is not set +# CONFIG_IR_GPIO_CIR is not set +CONFIG_MEDIA_ATTACH=y +CONFIG_MEDIA_TUNER=m +# CONFIG_MEDIA_TUNER_CUSTOMISE is not set +CONFIG_MEDIA_TUNER_SIMPLE=m +CONFIG_MEDIA_TUNER_TDA8290=m +CONFIG_MEDIA_TUNER_TDA827X=m +CONFIG_MEDIA_TUNER_TDA18271=m +CONFIG_MEDIA_TUNER_TDA9887=m +CONFIG_MEDIA_TUNER_TEA5761=m +CONFIG_MEDIA_TUNER_TEA5767=m +CONFIG_MEDIA_TUNER_MT20XX=m +CONFIG_MEDIA_TUNER_MT2060=m +CONFIG_MEDIA_TUNER_MT2063=m +CONFIG_MEDIA_TUNER_MT2266=m +CONFIG_MEDIA_TUNER_QT1010=m +CONFIG_MEDIA_TUNER_XC2028=m +CONFIG_MEDIA_TUNER_XC5000=m +CONFIG_MEDIA_TUNER_XC4000=m +CONFIG_MEDIA_TUNER_MXL5005S=m +CONFIG_MEDIA_TUNER_MXL5007T=m +CONFIG_MEDIA_TUNER_MC44S803=m +CONFIG_MEDIA_TUNER_MAX2165=m +CONFIG_MEDIA_TUNER_TDA18218=m +CONFIG_MEDIA_TUNER_TDA18212=m +CONFIG_VIDEO_V4L2=y +CONFIG_VIDEOBUF_GEN=m +CONFIG_VIDEOBUF_VMALLOC=m +CONFIG_VIDEOBUF_DMA_CONTIG=m +CONFIG_VIDEOBUF_DVB=m +CONFIG_VIDEO_TVEEPROM=m +CONFIG_VIDEO_TUNER=m +CONFIG_VIDEOBUF2_CORE=m +CONFIG_VIDEOBUF2_MEMOPS=m +CONFIG_VIDEOBUF2_VMALLOC=m +CONFIG_VIDEO_CAPTURE_DRIVERS=y +# CONFIG_VIDEO_ADV_DEBUG is not set +# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set +CONFIG_VIDEO_HELPER_CHIPS_AUTO=y +CONFIG_VIDEO_IR_I2C=m + +# +# Audio decoders, processors and mixers +# +CONFIG_VIDEO_MSP3400=m +CONFIG_VIDEO_CS53L32A=m +CONFIG_VIDEO_WM8775=m + +# +# RDS decoders +# + +# +# Video decoders +# +CONFIG_VIDEO_SAA711X=m +CONFIG_VIDEO_TVP5150=m + +# +# Video and audio decoders +# +CONFIG_VIDEO_CX25840=m + +# +# MPEG video encoders +# +CONFIG_VIDEO_CX2341X=m + +# +# Video encoders +# + +# +# Camera sensor devices +# +CONFIG_VIDEO_MT9V011=m + +# +# Flash devices +# + +# +# Video improvement chips +# + +# +# Miscelaneous helper chips +# +# CONFIG_VIDEO_VIVI is not set +CONFIG_V4L_USB_DRIVERS=y +CONFIG_USB_VIDEO_CLASS=m +CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y +CONFIG_USB_GSPCA=m +CONFIG_USB_M5602=m +CONFIG_USB_STV06XX=m +CONFIG_USB_GL860=m +CONFIG_USB_GSPCA_BENQ=m +CONFIG_USB_GSPCA_CONEX=m +CONFIG_USB_GSPCA_CPIA1=m +CONFIG_USB_GSPCA_ETOMS=m +CONFIG_USB_GSPCA_FINEPIX=m +CONFIG_USB_GSPCA_JEILINJ=m +CONFIG_USB_GSPCA_JL2005BCD=m +CONFIG_USB_GSPCA_KINECT=m +CONFIG_USB_GSPCA_KONICA=m +CONFIG_USB_GSPCA_MARS=m +CONFIG_USB_GSPCA_MR97310A=m +CONFIG_USB_GSPCA_NW80X=m +CONFIG_USB_GSPCA_OV519=m +CONFIG_USB_GSPCA_OV534=m +CONFIG_USB_GSPCA_OV534_9=m +CONFIG_USB_GSPCA_PAC207=m +CONFIG_USB_GSPCA_PAC7302=m +CONFIG_USB_GSPCA_PAC7311=m +CONFIG_USB_GSPCA_SE401=m +CONFIG_USB_GSPCA_SN9C2028=m +CONFIG_USB_GSPCA_SN9C20X=m +CONFIG_USB_GSPCA_SONIXB=m +CONFIG_USB_GSPCA_SONIXJ=m +CONFIG_USB_GSPCA_SPCA500=m +CONFIG_USB_GSPCA_SPCA501=m +CONFIG_USB_GSPCA_SPCA505=m +CONFIG_USB_GSPCA_SPCA506=m +CONFIG_USB_GSPCA_SPCA508=m +CONFIG_USB_GSPCA_SPCA561=m +CONFIG_USB_GSPCA_SPCA1528=m +CONFIG_USB_GSPCA_SQ905=m +CONFIG_USB_GSPCA_SQ905C=m +CONFIG_USB_GSPCA_SQ930X=m +CONFIG_USB_GSPCA_STK014=m +CONFIG_USB_GSPCA_STV0680=m +CONFIG_USB_GSPCA_SUNPLUS=m +CONFIG_USB_GSPCA_T613=m +CONFIG_USB_GSPCA_TOPRO=m +CONFIG_USB_GSPCA_TV8532=m +CONFIG_USB_GSPCA_VC032X=m +CONFIG_USB_GSPCA_VICAM=m +CONFIG_USB_GSPCA_XIRLINK_CIT=m +CONFIG_USB_GSPCA_ZC3XX=m +CONFIG_VIDEO_PVRUSB2=m +CONFIG_VIDEO_PVRUSB2_SYSFS=y +CONFIG_VIDEO_PVRUSB2_DVB=y +# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set +CONFIG_VIDEO_HDPVR=m +CONFIG_VIDEO_EM28XX=m +CONFIG_VIDEO_EM28XX_ALSA=m +CONFIG_VIDEO_EM28XX_DVB=m +CONFIG_VIDEO_EM28XX_RC=y +CONFIG_VIDEO_TLG2300=m +CONFIG_VIDEO_CX231XX=m +CONFIG_VIDEO_CX231XX_RC=y +CONFIG_VIDEO_CX231XX_ALSA=m +CONFIG_VIDEO_CX231XX_DVB=m +CONFIG_VIDEO_TM6000=m +CONFIG_VIDEO_TM6000_ALSA=m +CONFIG_VIDEO_TM6000_DVB=m +CONFIG_VIDEO_USBVISION=m +CONFIG_USB_ET61X251=m +CONFIG_USB_SN9C102=m +CONFIG_USB_PWC=m +# CONFIG_USB_PWC_DEBUG is not set +CONFIG_USB_PWC_INPUT_EVDEV=y +# CONFIG_VIDEO_CPIA2 is not set +CONFIG_USB_ZR364XX=m +CONFIG_USB_STKWEBCAM=m +CONFIG_USB_S2255=m +# CONFIG_V4L_ISA_PARPORT_DRIVERS is not set +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_SOC_CAMERA=m +CONFIG_SOC_CAMERA_IMX074=m +CONFIG_SOC_CAMERA_MT9M001=m +CONFIG_SOC_CAMERA_MT9M111=m +CONFIG_SOC_CAMERA_MT9T031=m +CONFIG_SOC_CAMERA_MT9T112=m +CONFIG_SOC_CAMERA_MT9V022=m +CONFIG_SOC_CAMERA_RJ54N1=m +CONFIG_SOC_CAMERA_TW9910=m +CONFIG_SOC_CAMERA_PLATFORM=m +CONFIG_SOC_CAMERA_OV2640=m +CONFIG_SOC_CAMERA_OV5642=m +CONFIG_SOC_CAMERA_OV6650=m +CONFIG_SOC_CAMERA_OV772X=m +CONFIG_SOC_CAMERA_OV9640=m +CONFIG_SOC_CAMERA_OV9740=m +# CONFIG_VIDEO_SH_MOBILE_CSI2 is not set +# CONFIG_VIDEO_SH_MOBILE_CEU is not set +CONFIG_V4L_MEM2MEM_DRIVERS=y +# CONFIG_VIDEO_MEM2MEM_TESTDEV is not set +CONFIG_VIDEO_SUNXI_CEDAR=y +CONFIG_VIDEO_DECODER_SUNXI=y +CONFIG_VIDEO_AVS_COUNTER=y +CONFIG_VIDEO_CSI_SUN4I=y +CONFIG_CSI_DEV_SEL=m +CONFIG_CSI0_SUN4I=m +CONFIG_CSI1_SUN4I=m +CONFIG_CSI_OV7670=m +CONFIG_CSI_GT2005=m +CONFIG_CSI_GC0308=m +CONFIG_CSI_HI704=m +CONFIG_CSI_SP0838=m +CONFIG_CSI_MT9M112=m +CONFIG_CSI_MT9M113=m +CONFIG_CSI_OV2655=m +CONFIG_CSI_HI253=m +CONFIG_CSI_MT9D112=m +CONFIG_CSI_GC0307=m +CONFIG_CSI_OV5640=m +CONFIG_RADIO_ADAPTERS=y +CONFIG_RADIO_SI470X=y +CONFIG_USB_SI470X=m +CONFIG_I2C_SI470X=m +CONFIG_USB_MR800=m +CONFIG_USB_DSBR=m +CONFIG_I2C_SI4713=m +CONFIG_RADIO_SI4713=m +CONFIG_USB_KEENE=m +CONFIG_RADIO_TEA5764=m +CONFIG_RADIO_SAA7706H=m +CONFIG_RADIO_TEF6862=m +CONFIG_RADIO_WL1273=m + +# +# Texas Instruments WL128x FM driver (ST based) +# +# CONFIG_RADIO_WL128X is not set +CONFIG_AUDIO_ENGINE=y +CONFIG_ACE_CONFIG=y +CONFIG_PA_CONTROL=y +CONFIG_PA_CONFIG=y +CONFIG_DVB_MAX_ADAPTERS=8 +CONFIG_DVB_DYNAMIC_MINORS=y +CONFIG_DVB_CAPTURE_DRIVERS=y +CONFIG_TTPCI_EEPROM=m + +# +# Supported USB Adapters +# +CONFIG_DVB_USB=m +# CONFIG_DVB_USB_DEBUG is not set +CONFIG_DVB_USB_A800=m +CONFIG_DVB_USB_DIBUSB_MB=m +CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y +CONFIG_DVB_USB_DIBUSB_MC=m +CONFIG_DVB_USB_DIB0700=m +CONFIG_DVB_USB_UMT_010=m +CONFIG_DVB_USB_CXUSB=m +CONFIG_DVB_USB_M920X=m +CONFIG_DVB_USB_GL861=m +CONFIG_DVB_USB_AU6610=m +CONFIG_DVB_USB_DIGITV=m +CONFIG_DVB_USB_VP7045=m +CONFIG_DVB_USB_VP702X=m +CONFIG_DVB_USB_GP8PSK=m +CONFIG_DVB_USB_NOVA_T_USB2=m +CONFIG_DVB_USB_TTUSB2=m +CONFIG_DVB_USB_DTT200U=m +CONFIG_DVB_USB_OPERA1=m +CONFIG_DVB_USB_AF9005=m +CONFIG_DVB_USB_AF9005_REMOTE=m +CONFIG_DVB_USB_PCTV452E=m +CONFIG_DVB_USB_DW2102=m +CONFIG_DVB_USB_CINERGY_T2=m +CONFIG_DVB_USB_ANYSEE=m +CONFIG_DVB_USB_DTV5100=m +CONFIG_DVB_USB_AF9015=m +CONFIG_DVB_USB_CE6230=m +CONFIG_DVB_USB_FRIIO=m +CONFIG_DVB_USB_EC168=m +CONFIG_DVB_USB_AZ6007=m +CONFIG_DVB_USB_AZ6027=m +CONFIG_DVB_USB_LME2510=m +CONFIG_DVB_USB_TECHNISAT_USB2=m +CONFIG_DVB_USB_IT913X=m +CONFIG_DVB_USB_MXL111SF=m +CONFIG_DVB_USB_RTL28XXU=m +CONFIG_SMS_SIANO_MDTV=m + +# +# Siano module components +# +CONFIG_SMS_USB_DRV=m +CONFIG_SMS_SDIO_DRV=m + +# +# Supported FlexCopII (B2C2) Adapters +# +CONFIG_DVB_B2C2_FLEXCOP=m +CONFIG_DVB_B2C2_FLEXCOP_USB=m +# CONFIG_DVB_B2C2_FLEXCOP_DEBUG is not set + +# +# Supported DVB Frontends +# +# CONFIG_DVB_FE_CUSTOMISE is not set + +# +# Multistandard (satellite) frontends +# +CONFIG_DVB_STB0899=m +CONFIG_DVB_STB6100=m +CONFIG_DVB_STV090x=m +CONFIG_DVB_STV6110x=m + +# +# Multistandard (cable + terrestrial) frontends +# +CONFIG_DVB_DRXK=m +CONFIG_DVB_TDA18271C2DD=m + +# +# DVB-S (satellite) frontends +# +CONFIG_DVB_CX24123=m +CONFIG_DVB_MT312=m +CONFIG_DVB_ZL10039=m +CONFIG_DVB_S5H1420=m +CONFIG_DVB_STV0288=m +CONFIG_DVB_STB6000=m +CONFIG_DVB_STV0299=m +CONFIG_DVB_STV6110=m +CONFIG_DVB_STV0900=m +CONFIG_DVB_TDA10086=m +CONFIG_DVB_TUNER_ITD1000=m +CONFIG_DVB_TUNER_CX24113=m +CONFIG_DVB_TDA826X=m +CONFIG_DVB_CX24116=m +CONFIG_DVB_SI21XX=m +CONFIG_DVB_DS3000=m +CONFIG_DVB_TDA10071=m + +# +# DVB-T (terrestrial) frontends +# +CONFIG_DVB_CX22702=m +CONFIG_DVB_DRXD=m +CONFIG_DVB_TDA1004X=m +CONFIG_DVB_NXT6000=m +CONFIG_DVB_MT352=m +CONFIG_DVB_ZL10353=m +CONFIG_DVB_DIB3000MB=m +CONFIG_DVB_DIB3000MC=m +CONFIG_DVB_DIB7000M=m +CONFIG_DVB_DIB7000P=m +CONFIG_DVB_TDA10048=m +CONFIG_DVB_AF9013=m +CONFIG_DVB_EC100=m +CONFIG_DVB_CXD2820R=m +CONFIG_DVB_RTL2830=m + +# +# DVB-C (cable) frontends +# +CONFIG_DVB_TDA10023=m +CONFIG_DVB_STV0297=m + +# +# ATSC (North American/Korean Terrestrial/Cable DTV) frontends +# +CONFIG_DVB_NXT200X=m +CONFIG_DVB_BCM3510=m +CONFIG_DVB_LGDT330X=m +CONFIG_DVB_LGDT3305=m +CONFIG_DVB_S5H1409=m +CONFIG_DVB_S5H1411=m + +# +# ISDB-T (terrestrial) frontends +# +CONFIG_DVB_S921=m +CONFIG_DVB_DIB8000=m +CONFIG_DVB_MB86A20S=m + +# +# Digital terrestrial only tuners/PLL +# +CONFIG_DVB_PLL=m +CONFIG_DVB_TUNER_DIB0070=m +CONFIG_DVB_TUNER_DIB0090=m + +# +# SEC control devices for DVB-S +# +CONFIG_DVB_LNBP21=m +CONFIG_DVB_LNBP22=m +CONFIG_DVB_ISL6421=m +CONFIG_DVB_ISL6423=m +CONFIG_DVB_A8293=m +CONFIG_DVB_LGS8GXX=m +CONFIG_DVB_ATBM8830=m +CONFIG_DVB_IX2505V=m +CONFIG_DVB_IT913X_FE=m +CONFIG_DVB_M88RS2000=m + +# +# Tools to develop new frontends +# +# CONFIG_DVB_DUMMY_FE is not set + +# +# Graphics support +# +CONFIG_DRM=m +CONFIG_DRM_USB=m +CONFIG_DRM_KMS_HELPER=m +# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set + +# +# I2C encoder or helper chips +# +CONFIG_DRM_I2C_CH7006=m +CONFIG_DRM_I2C_SIL164=m +CONFIG_DRM_MALI=m +CONFIG_DRM_UDL=m +# CONFIG_ION is not set +CONFIG_MALI=m +CONFIG_MALI400=m +CONFIG_MALI400_DEBUG=y +CONFIG_MALI400_GPU_UTILIZATION=y +CONFIG_UMP=m +CONFIG_UMP_DEBUG=y +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +CONFIG_FB_SYS_FILLRECT=m +CONFIG_FB_SYS_COPYAREA=m +CONFIG_FB_SYS_IMAGEBLIT=m +# CONFIG_FB_FOREIGN_ENDIAN is not set +CONFIG_FB_SYS_FOPS=m +# CONFIG_FB_WMT_GE_ROPS is not set +CONFIG_FB_DEFERRED_IO=y +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +CONFIG_FB_MODE_HELPERS=y +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +CONFIG_FB_SUNXI=y +CONFIG_FB_SUNXI_RESERVED_MEM=y +CONFIG_FB_SUNXI_UMP=y +CONFIG_FB_SUNXI_LCD=y +CONFIG_FB_SUNXI_HDMI=y +CONFIG_HDMI_CEC=m +# CONFIG_FB_ARMCLCD is not set +# CONFIG_FB_UVESA is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_TMIO is not set +CONFIG_FB_SMSCUFX=m +CONFIG_FB_UDL=m +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_BROADSHEET is not set +# CONFIG_EXYNOS_VIDEO is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=m +# CONFIG_LCD_L4F00242T03 is not set +# CONFIG_LCD_LMS283GF05 is not set +# CONFIG_LCD_LTV350QV is not set +# CONFIG_LCD_TDO24M is not set +# CONFIG_LCD_VGG2432A4 is not set +# CONFIG_LCD_PLATFORM is not set +# CONFIG_LCD_S6E63M0 is not set +# CONFIG_LCD_LD9040 is not set +# CONFIG_LCD_AMS369FG06 is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=m +CONFIG_BACKLIGHT_GENERIC=m +# CONFIG_BACKLIGHT_ADP8860 is not set +# CONFIG_BACKLIGHT_ADP8870 is not set +# CONFIG_BACKLIGHT_LP855X is not set + +# +# Console display driver support +# +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +# CONFIG_LOGO is not set +CONFIG_SOUND=y +# CONFIG_SOUND_OSS_CORE is not set +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +CONFIG_SND_HWDEP=m +CONFIG_SND_RAWMIDI=m +CONFIG_SND_JACK=y +# CONFIG_SND_SEQUENCER is not set +# CONFIG_SND_MIXER_OSS is not set +# CONFIG_SND_PCM_OSS is not set +CONFIG_SND_HRTIMER=y +CONFIG_SND_DYNAMIC_MINORS=y +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set +CONFIG_SND_VMASTER=y +# CONFIG_SND_RAWMIDI_SEQ is not set +# CONFIG_SND_OPL3_LIB_SEQ is not set +# CONFIG_SND_OPL4_LIB_SEQ is not set +# CONFIG_SND_SBAWE_SEQ is not set +# CONFIG_SND_EMU10K1_SEQ is not set +CONFIG_SND_DRIVERS=y +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_ALOOP is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_MTS64 is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set +# CONFIG_SND_PORTMAN2X4 is not set +# CONFIG_SND_ARM is not set +CONFIG_SND_SPI=y +CONFIG_SND_USB=y +CONFIG_SND_USB_AUDIO=m +CONFIG_SND_USB_UA101=m +CONFIG_SND_USB_CAIAQ=m +CONFIG_SND_USB_CAIAQ_INPUT=y +CONFIG_SND_USB_6FIRE=m +CONFIG_SND_SOC=y +CONFIG_SOUND_SUNXI=y +CONFIG_SND_SUNXI_SOC_CODEC=y +CONFIG_SND_SUNXI_SOC_HDMIAUDIO=y +CONFIG_SND_SUNXI_SOC_SPDIF=y +CONFIG_SND_SUNXI_SOC_I2S_INTERFACE=y +CONFIG_SND_SOC_I2C_AND_SPI=y +# CONFIG_SND_SOC_ALL_CODECS is not set +# CONFIG_SOUND_PRIME is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HID_BATTERY_STRENGTH is not set +CONFIG_HIDRAW=y +# CONFIG_UHID is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +CONFIG_HID_PID=y +CONFIG_USB_HIDDEV=y + +# +# Special HID drivers +# +CONFIG_HID_A4TECH=y +CONFIG_HID_ACRUX=m +CONFIG_HID_ACRUX_FF=y +CONFIG_HID_APPLE=y +CONFIG_HID_BELKIN=y +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +CONFIG_HID_PRODIKEYS=m +CONFIG_HID_CYPRESS=y +CONFIG_HID_DRAGONRISE=m +CONFIG_DRAGONRISE_FF=y +CONFIG_HID_EMS_FF=m +CONFIG_HID_ELECOM=m +CONFIG_HID_EZKEY=y +CONFIG_HID_HOLTEK=m +CONFIG_HOLTEK_FF=y +CONFIG_HID_KEYTOUCH=m +CONFIG_HID_KYE=y +CONFIG_HID_UCLOGIC=m +CONFIG_HID_WALTOP=m +CONFIG_HID_GYRATION=m +CONFIG_HID_TWINHAN=m +CONFIG_HID_KENSINGTON=y +CONFIG_HID_LCPOWER=m +CONFIG_HID_LOGITECH=y +CONFIG_HID_LOGITECH_DJ=m +CONFIG_LOGITECH_FF=y +CONFIG_LOGIRUMBLEPAD2_FF=y +CONFIG_LOGIG940_FF=y +CONFIG_LOGIWHEELS_FF=y +# CONFIG_HID_MAGICMOUSE is not set +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +CONFIG_HID_MULTITOUCH=m +CONFIG_HID_NTRIG=m +CONFIG_HID_ORTEK=m +CONFIG_HID_PANTHERLORD=m +CONFIG_PANTHERLORD_FF=y +CONFIG_HID_PETALYNX=m +CONFIG_HID_PICOLCD=m +CONFIG_HID_PICOLCD_FB=y +CONFIG_HID_PICOLCD_BACKLIGHT=y +CONFIG_HID_PICOLCD_LCD=y +CONFIG_HID_PICOLCD_LEDS=y +CONFIG_HID_PRIMAX=m +CONFIG_HID_ROCCAT=m +CONFIG_HID_SAITEK=m +CONFIG_HID_SAMSUNG=m +CONFIG_HID_SONY=m +CONFIG_HID_SPEEDLINK=m +CONFIG_HID_SUNPLUS=m +CONFIG_HID_GREENASIA=m +CONFIG_GREENASIA_FF=y +CONFIG_HID_SMARTJOYPLUS=m +CONFIG_SMARTJOYPLUS_FF=y +CONFIG_HID_TIVO=m +CONFIG_HID_TOPSEED=m +CONFIG_HID_THRUSTMASTER=m +CONFIG_THRUSTMASTER_FF=y +CONFIG_HID_WACOM=m +# CONFIG_HID_WACOM_POWER_SUPPLY is not set +CONFIG_HID_WIIMOTE=m +CONFIG_HID_WIIMOTE_EXT=y +CONFIG_HID_ZEROPLUS=m +CONFIG_ZEROPLUS_FF=y +CONFIG_HID_ZYDACRON=m +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +# CONFIG_USB_ARCH_HAS_XHCI is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_COMMON=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +# CONFIG_USB_DEVICEFS is not set +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +CONFIG_USB_SUSPEND=y +CONFIG_USB_OTG=y +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_DWC3 is not set +CONFIG_USB_MON=y +CONFIG_USB_WUSB_CBAF=m +CONFIG_USB_WUSB_CBAF_DEBUG=y + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_HCD_PLATFORM is not set +# CONFIG_USB_EHCI_HCD_PLATFORM is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +# CONFIG_USB_U132_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +CONFIG_USB_SUNXI_EHCI=y +CONFIG_USB_SUNXI_OHCI=y +CONFIG_USB_SUNXI_COMMON=y +CONFIG_USB_SW_SUNXI_HCD0=y +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_RENESAS_USBHS is not set + +# +# USB Device Class drivers +# +CONFIG_USB_ACM=m +CONFIG_USB_PRINTER=m +CONFIG_USB_WDM=m +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +CONFIG_USB_STORAGE_REALTEK=y +CONFIG_REALTEK_AUTOPM=y +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +CONFIG_USB_STORAGE_ISD200=y +CONFIG_USB_STORAGE_USBAT=y +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +CONFIG_USB_STORAGE_ALAUDA=y +CONFIG_USB_STORAGE_ONETOUCH=y +CONFIG_USB_STORAGE_KARMA=y +CONFIG_USB_STORAGE_CYPRESS_ATACB=y +CONFIG_USB_STORAGE_ENE_UB6250=y +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +CONFIG_USB_MDC800=m +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +CONFIG_USB_USS720=m +CONFIG_USB_SERIAL=m +CONFIG_USB_EZUSB=y +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_AIRCABLE=m +CONFIG_USB_SERIAL_ARK3116=m +CONFIG_USB_SERIAL_BELKIN=m +CONFIG_USB_SERIAL_CH341=m +CONFIG_USB_SERIAL_WHITEHEAT=m +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m +CONFIG_USB_SERIAL_CP210X=m +CONFIG_USB_SERIAL_CYPRESS_M8=m +CONFIG_USB_SERIAL_EMPEG=m +CONFIG_USB_SERIAL_FTDI_SIO=m +CONFIG_USB_SERIAL_FUNSOFT=m +CONFIG_USB_SERIAL_VISOR=m +CONFIG_USB_SERIAL_IPAQ=m +CONFIG_USB_SERIAL_IR=m +CONFIG_USB_SERIAL_EDGEPORT=m +CONFIG_USB_SERIAL_EDGEPORT_TI=m +CONFIG_USB_SERIAL_F81232=m +CONFIG_USB_SERIAL_GARMIN=m +CONFIG_USB_SERIAL_IPW=m +CONFIG_USB_SERIAL_IUU=m +CONFIG_USB_SERIAL_KEYSPAN_PDA=m +CONFIG_USB_SERIAL_KEYSPAN=m +CONFIG_USB_SERIAL_KLSI=m +CONFIG_USB_SERIAL_KOBIL_SCT=m +CONFIG_USB_SERIAL_MCT_U232=m +CONFIG_USB_SERIAL_METRO=m +CONFIG_USB_SERIAL_MOS7720=m +CONFIG_USB_SERIAL_MOS7715_PARPORT=y +CONFIG_USB_SERIAL_MOS7840=m +CONFIG_USB_SERIAL_MOTOROLA=m +CONFIG_USB_SERIAL_NAVMAN=m +CONFIG_USB_SERIAL_PL2303=m +CONFIG_USB_SERIAL_OTI6858=m +CONFIG_USB_SERIAL_QCAUX=m +CONFIG_USB_SERIAL_QUALCOMM=m +CONFIG_USB_SERIAL_SPCP8X5=m +CONFIG_USB_SERIAL_HP4X=m +# CONFIG_USB_SERIAL_SAFE is not set +CONFIG_USB_SERIAL_SIEMENS_MPI=m +CONFIG_USB_SERIAL_SIERRAWIRELESS=m +CONFIG_USB_SERIAL_SYMBOL=m +CONFIG_USB_SERIAL_TI=m +CONFIG_USB_SERIAL_CYBERJACK=m +CONFIG_USB_SERIAL_XIRCOM=m +CONFIG_USB_SERIAL_WWAN=m +CONFIG_USB_SERIAL_OPTION=m +CONFIG_USB_SERIAL_OMNINET=m +CONFIG_USB_SERIAL_OPTICON=m +CONFIG_USB_SERIAL_VIVOPAY_SERIAL=m +# CONFIG_USB_SERIAL_ZIO is not set +CONFIG_USB_SERIAL_SSU100=m +# CONFIG_USB_SERIAL_DEBUG is not set + +# +# USB Miscellaneous drivers +# +CONFIG_USB_EMI62=m +CONFIG_USB_EMI26=m +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +CONFIG_USB_IDMOUSE=m +CONFIG_USB_FTDI_ELAN=m +CONFIG_USB_APPLEDISPLAY=m +CONFIG_USB_SISUSBVGA=m +CONFIG_USB_SISUSBVGA_CON=y +CONFIG_USB_LD=m +CONFIG_USB_TRANCEVIBRATOR=m +CONFIG_USB_IOWARRIOR=m +# CONFIG_USB_TEST is not set +CONFIG_USB_ISIGHTFW=m +# CONFIG_USB_YUREX is not set +CONFIG_USB_GADGET=y +# CONFIG_USB_GADGET_DEBUG is not set +# CONFIG_USB_GADGET_DEBUG_FILES is not set +# CONFIG_USB_GADGET_DEBUG_FS is not set +CONFIG_USB_GADGET_VBUS_DRAW=2 +CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 +# CONFIG_USB_FUSB300 is not set +# CONFIG_USB_R8A66597 is not set +# CONFIG_USB_MV_UDC is not set +# CONFIG_USB_M66592 is not set +# CONFIG_USB_NET2272 is not set +CONFIG_USB_SW_SUNXI_UDC0_SELECT=m +# CONFIG_USB_DUMMY_HCD is not set +CONFIG_USB_SW_SUNXI_UDC0=y +CONFIG_USB_GADGET_DUALSPEED=y +# CONFIG_USB_ZERO is not set +CONFIG_USB_AUDIO=m +# CONFIG_GADGET_UAC1 is not set +CONFIG_USB_ETH=m +CONFIG_USB_ETH_RNDIS=y +CONFIG_USB_ETH_EEM=y +CONFIG_USB_G_NCM=m +CONFIG_USB_GADGETFS=m +CONFIG_USB_FUNCTIONFS=m +CONFIG_USB_FUNCTIONFS_ETH=y +CONFIG_USB_FUNCTIONFS_RNDIS=y +CONFIG_USB_FUNCTIONFS_GENERIC=y +# CONFIG_USB_FILE_STORAGE is not set +CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_G_SERIAL=m +CONFIG_USB_MIDI_GADGET=m +CONFIG_USB_G_PRINTER=m +CONFIG_USB_CDC_COMPOSITE=m +CONFIG_USB_G_ACM_MS=m +CONFIG_USB_G_MULTI=m +CONFIG_USB_G_MULTI_RNDIS=y +CONFIG_USB_G_MULTI_CDC=y +CONFIG_USB_G_HID=m +CONFIG_USB_G_DBGP=m +# CONFIG_USB_G_DBGP_PRINTK is not set +CONFIG_USB_G_DBGP_SERIAL=y +CONFIG_USB_G_WEBCAM=m + +# +# OTG and related infrastructure +# +CONFIG_USB_OTG_UTILS=y +CONFIG_USB_OTG_WAKELOCK=y +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_ULPI is not set +# CONFIG_NOP_USB_XCEIV is not set +CONFIG_USB_SW_SUNXI_USB=y +CONFIG_USB_SW_SUNXI_USB_MANAGER=y +# CONFIG_USB_SW_SUNXI_USB0_HOST_ONLY is not set +CONFIG_USB_SW_SUNXI_USB0_OTG=y +# CONFIG_USB_SW_SUNXI_USB0_DEVICE_ONLY is not set +# CONFIG_USB_SW_SUNXI_USB0_NULL is not set +CONFIG_USB_SW_SUNXI_USB_DEBUG=y +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +CONFIG_MMC_UNSAFE_RESUME=y +# CONFIG_MMC_CLKGATE is not set +# CONFIG_MMC_EMBEDDED_SDIO is not set +CONFIG_MMC_PARANOID_SD_INIT=y + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_MINORS=8 +# CONFIG_MMC_BLOCK_BOUNCE is not set +# CONFIG_MMC_BLOCK_DEFERRED_RESUME is not set +CONFIG_SDIO_UART=m +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_ARMMMCI is not set +# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_SDHCI_PXAV3 is not set +# CONFIG_MMC_SDHCI_PXAV2 is not set +# CONFIG_MMC_DW is not set +CONFIG_MMC_SUNXI_NEW=y +# CONFIG_MMC_DEBUG_SUNXI is not set +CONFIG_MMC_PRE_DBGLVL_SUNXI=0 +# CONFIG_MMC_VUB300 is not set +CONFIG_MMC_USHC=m + +# +# MMC/SD/SDIO Card Power Management Drivers +# +CONFIG_MMC_SUNXI_POWER_CONTROL=y + +# +# SUNXI MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MEMSTICK is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y + +# +# LED drivers +# +CONFIG_LEDS_SUNXI=y +# CONFIG_LEDS_LM3530 is not set +# CONFIG_LEDS_PCA9532 is not set +CONFIG_LEDS_GPIO=y +# CONFIG_LEDS_LP3944 is not set +# CONFIG_LEDS_LP5521 is not set +# CONFIG_LEDS_LP5523 is not set +# CONFIG_LEDS_PCA955X is not set +# CONFIG_LEDS_PCA9633 is not set +# CONFIG_LEDS_DAC124S085 is not set +# CONFIG_LEDS_REGULATOR is not set +# CONFIG_LEDS_BD2802 is not set +# CONFIG_LEDS_LT3593 is not set +# CONFIG_LEDS_RENESAS_TPU is not set +# CONFIG_LEDS_TCA6507 is not set +# CONFIG_LEDS_OT200 is not set +CONFIG_LEDS_TRIGGERS=y + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_DISK=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_BACKLIGHT=y +CONFIG_LEDS_TRIGGER_CPU=y +CONFIG_LEDS_TRIGGER_GPIO=m +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y + +# +# iptables trigger is under Netfilter config (LED target) +# +# CONFIG_SWITCH is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_DS3232 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_ISL12022 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set +# CONFIG_RTC_DRV_EM3027 is not set +# CONFIG_RTC_DRV_RV3029C2 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T93 is not set +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_DS3234 is not set +# CONFIG_RTC_DRV_PCF2123 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +# CONFIG_RTC_DRV_PL030 is not set +# CONFIG_RTC_DRV_PL031 is not set +CONFIG_RTC_DRV_SUN4I=y +# CONFIG_DMADEVICES is not set +CONFIG_AUXDISPLAY=y +# CONFIG_UIO is not set + +# +# Virtio drivers +# +# CONFIG_VIRTIO_BALLOON is not set +# CONFIG_VIRTIO_MMIO is not set + +# +# Microsoft Hyper-V guest support +# +CONFIG_STAGING=y +CONFIG_USBIP_CORE=m +CONFIG_USBIP_VHCI_HCD=m +CONFIG_USBIP_HOST=m +# CONFIG_USBIP_DEBUG is not set +CONFIG_W35UND=m +CONFIG_PRISM2_USB=m +CONFIG_ECHO=m +# CONFIG_ASUS_OLED is not set +CONFIG_PANEL=m +CONFIG_PANEL_PARPORT=0 +CONFIG_PANEL_PROFILE=5 +# CONFIG_PANEL_CHANGE_MESSAGE is not set +CONFIG_RTLLIB=m +CONFIG_RTLLIB_CRYPTO_CCMP=m +CONFIG_RTLLIB_CRYPTO_TKIP=m +CONFIG_RTLLIB_CRYPTO_WEP=m +CONFIG_R8712U=m +CONFIG_RTS5139=m +# CONFIG_RTS5139_DEBUG is not set +# CONFIG_TRANZPORT is not set +CONFIG_LINE6_USB=m +# CONFIG_LINE6_USB_DEBUG is not set +# CONFIG_LINE6_USB_DUMP_CTRL is not set +# CONFIG_LINE6_USB_DUMP_MIDI is not set +# CONFIG_LINE6_USB_DUMP_PCM is not set +# CONFIG_LINE6_USB_RAW is not set +# CONFIG_LINE6_USB_IMPULSE_RESPONSE is not set +CONFIG_USB_SERIAL_QUATECH2=m +CONFIG_USB_SERIAL_QUATECH_USB2=m +# CONFIG_VT6656 is not set +CONFIG_IIO=m +# CONFIG_IIO_ST_HWMON is not set +# CONFIG_IIO_BUFFER is not set +# CONFIG_IIO_TRIGGER is not set + +# +# Accelerometers +# +# CONFIG_ADIS16201 is not set +# CONFIG_ADIS16203 is not set +# CONFIG_ADIS16204 is not set +# CONFIG_ADIS16209 is not set +# CONFIG_ADIS16220 is not set +# CONFIG_ADIS16240 is not set +# CONFIG_KXSD9 is not set +# CONFIG_LIS3L02DQ is not set + +# +# Analog to digital converters +# +# CONFIG_AD7291 is not set +# CONFIG_AD7298 is not set +# CONFIG_AD7606 is not set +# CONFIG_AD799X is not set +# CONFIG_AD7476 is not set +# CONFIG_AD7887 is not set +# CONFIG_AD7780 is not set +# CONFIG_AD7793 is not set +# CONFIG_AD7816 is not set +# CONFIG_AD7192 is not set +# CONFIG_ADT7310 is not set +# CONFIG_ADT7410 is not set +# CONFIG_AD7280 is not set +# CONFIG_MAX1363 is not set + +# +# Analog digital bi-direction converters +# +# CONFIG_ADT7316 is not set + +# +# Capacitance to digital converters +# +# CONFIG_AD7150 is not set +# CONFIG_AD7152 is not set +# CONFIG_AD7746 is not set + +# +# Digital to analog converters +# +# CONFIG_AD5064 is not set +# CONFIG_AD5360 is not set +# CONFIG_AD5380 is not set +# CONFIG_AD5421 is not set +# CONFIG_AD5624R_SPI is not set +# CONFIG_AD5446 is not set +# CONFIG_AD5504 is not set +# CONFIG_AD5764 is not set +# CONFIG_AD5791 is not set +# CONFIG_AD5686 is not set +# CONFIG_MAX517 is not set + +# +# Direct Digital Synthesis +# +# CONFIG_AD5930 is not set +# CONFIG_AD9832 is not set +# CONFIG_AD9834 is not set +# CONFIG_AD9850 is not set +# CONFIG_AD9852 is not set +# CONFIG_AD9910 is not set +# CONFIG_AD9951 is not set + +# +# Digital gyroscope sensors +# +# CONFIG_ADIS16060 is not set +# CONFIG_ADIS16080 is not set +# CONFIG_ADIS16130 is not set +# CONFIG_ADIS16260 is not set +# CONFIG_ADXRS450 is not set + +# +# Network Analyzer, Impedance Converters +# +# CONFIG_AD5933 is not set + +# +# Inertial measurement units +# +# CONFIG_ADIS16400 is not set + +# +# Light sensors +# +# CONFIG_SENSORS_ISL29018 is not set +# CONFIG_SENSORS_TSL2563 is not set +# CONFIG_TSL2583 is not set + +# +# Magnetometer sensors +# +# CONFIG_SENSORS_HMC5843 is not set + +# +# Active energy metering IC +# +# CONFIG_ADE7753 is not set +# CONFIG_ADE7754 is not set +# CONFIG_ADE7758 is not set +# CONFIG_ADE7759 is not set +# CONFIG_ADE7854 is not set + +# +# Resolver to digital converters +# +# CONFIG_AD2S90 is not set +# CONFIG_AD2S1200 is not set +# CONFIG_AD2S1210 is not set + +# +# Triggers - standalone +# +# CONFIG_IIO_SIMPLE_DUMMY is not set +CONFIG_FB_SM7XX=m +CONFIG_USB_ENESTORAGE=m +CONFIG_BCM_WIMAX=m +# CONFIG_FT1000 is not set + +# +# Speakup console speech +# +CONFIG_SPEAKUP=m +# CONFIG_SPEAKUP_SYNTH_ACNTSA is not set +# CONFIG_SPEAKUP_SYNTH_ACNTPC is not set +# CONFIG_SPEAKUP_SYNTH_APOLLO is not set +# CONFIG_SPEAKUP_SYNTH_AUDPTR is not set +# CONFIG_SPEAKUP_SYNTH_BNS is not set +# CONFIG_SPEAKUP_SYNTH_DECTLK is not set +# CONFIG_SPEAKUP_SYNTH_DECEXT is not set +# CONFIG_SPEAKUP_SYNTH_DECPC is not set +# CONFIG_SPEAKUP_SYNTH_DTLK is not set +# CONFIG_SPEAKUP_SYNTH_KEYPC is not set +# CONFIG_SPEAKUP_SYNTH_LTLK is not set +CONFIG_SPEAKUP_SYNTH_SOFT=m +# CONFIG_SPEAKUP_SYNTH_SPKOUT is not set +# CONFIG_SPEAKUP_SYNTH_TXPRT is not set +# CONFIG_SPEAKUP_SYNTH_DUMMY is not set +CONFIG_TOUCHSCREEN_CLEARPAD_TM1217=m +CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4=m +CONFIG_STAGING_MEDIA=y +CONFIG_DVB_AS102=m +CONFIG_EASYCAP=m +# CONFIG_EASYCAP_DEBUG is not set +CONFIG_LIRC_STAGING=y +CONFIG_LIRC_IGORPLUGUSB=m +CONFIG_LIRC_IMON=m +# CONFIG_LIRC_PARALLEL is not set +CONFIG_LIRC_SASEM=m +# CONFIG_LIRC_SERIAL is not set +# CONFIG_LIRC_SIR is not set +CONFIG_LIRC_TTUSBIR=m +CONFIG_LIRC_ZILOG=m +CONFIG_LIRC_GPIO=m +CONFIG_LIRC_SUNXI_RAW=m + +# +# Android +# +CONFIG_ANDROID=y +CONFIG_ANDROID_BINDER_IPC=y +CONFIG_ASHMEM=y +CONFIG_ANDROID_LOGGER=y +CONFIG_ANDROID_PERSISTENT_RAM=y +CONFIG_ANDROID_RAM_CONSOLE=y +# CONFIG_PERSISTENT_TRACER is not set +CONFIG_ANDROID_TIMED_OUTPUT=y +# CONFIG_ANDROID_TIMED_GPIO is not set +CONFIG_ANDROID_LOW_MEMORY_KILLER=y +CONFIG_ANDROID_LOW_MEMORY_KILLER_AUTODETECT_OOM_ADJ_VALUES=y +# CONFIG_ANDROID_SWITCH is not set +# CONFIG_ANDROID_INTF_ALARM_DEV is not set +# CONFIG_PHONE is not set +CONFIG_USB_WPAN_HCD=m +CONFIG_CLKDEV_LOOKUP=y + +# +# Hardware Spinlock drivers +# +CONFIG_IOMMU_SUPPORT=y + +# +# Remoteproc drivers (EXPERIMENTAL) +# + +# +# Rpmsg drivers (EXPERIMENTAL) +# +# CONFIG_VIRT_DRIVERS is not set +# CONFIG_PM_DEVFREQ is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +CONFIG_EXT3_DEFAULTS_TO_ORDERED=y +CONFIG_EXT3_FS_XATTR=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_XATTR=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +# CONFIG_EXT4_DEBUG is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_JBD2=y +# CONFIG_JBD2_DEBUG is not set +CONFIG_FS_MBCACHE=y +CONFIG_REISERFS_FS=y +# CONFIG_REISERFS_CHECK is not set +CONFIG_REISERFS_PROC_INFO=y +CONFIG_REISERFS_FS_XATTR=y +CONFIG_REISERFS_FS_POSIX_ACL=y +CONFIG_REISERFS_FS_SECURITY=y +# CONFIG_JFS_FS is not set +CONFIG_XFS_FS=y +CONFIG_XFS_QUOTA=y +CONFIG_XFS_POSIX_ACL=y +# CONFIG_XFS_RT is not set +# CONFIG_XFS_DEBUG is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FS_POSIX_ACL=y +CONFIG_EXPORTFS=y +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_FANOTIFY is not set +CONFIG_QUOTA=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +# CONFIG_PRINT_QUOTA_WARNING is not set +# CONFIG_QUOTA_DEBUG is not set +CONFIG_QUOTA_TREE=y +# CONFIG_QFMT_V1 is not set +CONFIG_QFMT_V2=y +CONFIG_QUOTACTL=y +CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=y +CONFIG_CUSE=y +CONFIG_GENERIC_ACL=y + +# +# Caches +# +CONFIG_FSCACHE=y +CONFIG_FSCACHE_STATS=y +# CONFIG_FSCACHE_HISTOGRAM is not set +# CONFIG_FSCACHE_DEBUG is not set +# CONFIG_FSCACHE_OBJECT_LIST is not set +CONFIG_CACHEFILES=y +# CONFIG_CACHEFILES_DEBUG is not set +# CONFIG_CACHEFILES_HISTOGRAM is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=y +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=y +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="ascii" +CONFIG_NTFS_FS=y +# CONFIG_NTFS_DEBUG is not set +CONFIG_NTFS_RW=y + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_TMPFS_XATTR=y +# CONFIG_HUGETLB_PAGE is not set +CONFIG_CONFIGFS_FS=y +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +CONFIG_ECRYPT_FS=y +# CONFIG_HFS_FS is not set +CONFIG_HFSPLUS_FS=y +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_LOGFS is not set +# CONFIG_CRAMFS is not set +CONFIG_SQUASHFS=m +# CONFIG_SQUASHFS_XATTR is not set +CONFIG_SQUASHFS_ZLIB=y +# CONFIG_SQUASHFS_LZO is not set +# CONFIG_SQUASHFS_XZ is not set +# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set +# CONFIG_SQUASHFS_EMBEDDED is not set +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX6FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_PSTORE is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +# CONFIG_EXOFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +# CONFIG_NFS_V4_1 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFS_FSCACHE is not set +# CONFIG_NFS_USE_LEGACY_DNS is not set +CONFIG_NFS_USE_KERNEL_DNS=y +CONFIG_NFSD=m +CONFIG_NFSD_V2_ACL=y +CONFIG_NFSD_V3=y +CONFIG_NFSD_V3_ACL=y +CONFIG_NFSD_V4=y +# CONFIG_NFSD_FAULT_INJECTION is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_ACL_SUPPORT=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +CONFIG_SUNRPC_GSS=y +CONFIG_RPCSEC_GSS_KRB5=m +# CONFIG_SUNRPC_DEBUG is not set +# CONFIG_CEPH_FS is not set +CONFIG_CIFS=y +# CONFIG_CIFS_STATS is not set +# CONFIG_CIFS_WEAK_PW_HASH is not set +CONFIG_CIFS_UPCALL=y +CONFIG_CIFS_XATTR=y +CONFIG_CIFS_POSIX=y +# CONFIG_CIFS_DEBUG2 is not set +CONFIG_CIFS_DFS_UPCALL=y +# CONFIG_CIFS_FSCACHE is not set +CONFIG_CIFS_ACL=y +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="utf8" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +CONFIG_NLS_CODEPAGE_936=y +CONFIG_NLS_CODEPAGE_950=y +CONFIG_NLS_CODEPAGE_932=y +CONFIG_NLS_CODEPAGE_949=y +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=y +# CONFIG_DLM is not set + +# +# Kernel hacking +# +CONFIG_PRINTK_TIME=y +CONFIG_DEFAULT_MESSAGE_LOGLEVEL=7 +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=2048 +CONFIG_MAGIC_SYSRQ=y +CONFIG_STRIP_ASM_SYMS=y +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_SECTION_MISMATCH is not set +CONFIG_DEBUG_KERNEL=y +CONFIG_DEBUG_SHIRQ=y +# CONFIG_LOCKUP_DETECTOR is not set +# CONFIG_HARDLOCKUP_DETECTOR_NMI is not set +# CONFIG_HARDLOCKUP_DETECTOR_OTHER_CPU is not set +# CONFIG_HARDLOCKUP_DETECTOR is not set +CONFIG_DETECT_HUNG_TASK=y +CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120 +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 +CONFIG_SCHED_DEBUG=y +CONFIG_SCHEDSTATS=y +CONFIG_TIMER_STATS=y +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +# CONFIG_DEBUG_KMEMLEAK is not set +CONFIG_DEBUG_PREEMPT=y +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_SPARSE_RCU_POINTER is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_ATOMIC_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +CONFIG_STACKTRACE=y +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_HIGHMEM is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_INFO_REDUCED is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_DEBUG_LIST=y +# CONFIG_TEST_LIST_SORT is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set +CONFIG_BOOT_PRINTK_DELAY=y +# CONFIG_RCU_TORTURE_TEST is not set +CONFIG_RCU_CPU_STALL_TIMEOUT=60 +CONFIG_RCU_CPU_STALL_VERBOSE=y +CONFIG_RCU_CPU_STALL_INFO=y +# CONFIG_RCU_TRACE is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +CONFIG_DEBUG_FORCE_WEAK_PER_CPU=y +# CONFIG_DEBUG_PER_CPU_MAPS is not set +# CONFIG_LKDTM is not set +# CONFIG_CPU_NOTIFIER_ERROR_INJECT is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_DEBUG_PAGEALLOC is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +CONFIG_DYNAMIC_DEBUG=y +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_ASYNC_RAID6_TEST is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +# CONFIG_TEST_KSTRTOX is not set +CONFIG_STRICT_DEVMEM=y +CONFIG_ARM_UNWIND=y +# CONFIG_DEBUG_USER is not set +# CONFIG_DEBUG_RODATA is not set +CONFIG_DEBUG_LL=y +CONFIG_DEBUG_LL_UART_NONE=y +# CONFIG_DEBUG_ICEDCC is not set +# CONFIG_DEBUG_SEMIHOSTING is not set +CONFIG_EARLY_PRINTK=y +# CONFIG_OC_ETM is not set + +# +# Security options +# +CONFIG_KEYS=y +# CONFIG_ENCRYPTED_KEYS is not set +# CONFIG_KEYS_DEBUG_PROC_KEYS is not set +# CONFIG_SECURITY_DMESG_RESTRICT is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_XOR_BLOCKS=m +CONFIG_ASYNC_CORE=m +CONFIG_ASYNC_MEMCPY=m +CONFIG_ASYNC_XOR=m +CONFIG_ASYNC_PQ=m +CONFIG_ASYNC_RAID6_RECOV=m +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_FIPS is not set +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=y +CONFIG_CRYPTO_PCOMP2=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_USER=m +# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set +CONFIG_CRYPTO_GF128MUL=y +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_PCRYPT is not set +CONFIG_CRYPTO_WORKQUEUE=y +CONFIG_CRYPTO_CRYPTD=m +CONFIG_CRYPTO_AUTHENC=y +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +CONFIG_CRYPTO_CCM=m +CONFIG_CRYPTO_GCM=m +CONFIG_CRYPTO_SEQIV=y + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CTR=m +CONFIG_CRYPTO_CTS=m +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_XTS=m + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_VMAC=m + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_GHASH=m +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_RMD128=m +CONFIG_CRYPTO_RMD160=m +CONFIG_CRYPTO_RMD256=m +CONFIG_CRYPTO_RMD320=m +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_WP512=m + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_ARC4=y +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_BLOWFISH_COMMON=m +CONFIG_CRYPTO_CAMELLIA=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_DES=y +CONFIG_CRYPTO_FCRYPT=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_SALSA20=m +CONFIG_CRYPTO_SEED=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_TWOFISH_COMMON=y + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_ZLIB=y +CONFIG_CRYPTO_LZO=y + +# +# Random Number Generation +# +CONFIG_CRYPTO_ANSI_CPRNG=m +CONFIG_CRYPTO_USER_API=m +CONFIG_CRYPTO_USER_API_HASH=m +CONFIG_CRYPTO_USER_API_SKCIPHER=m +CONFIG_CRYPTO_HW=y +CONFIG_CRYPTO_DEV_SUNXI_SS=m +CONFIG_CRYPTO_DEV_SUNXI_SS_PRNG=y +CONFIG_CRYPTO_DEV_SUNXI_SS_MD5=y +CONFIG_CRYPTO_DEV_SUNXI_SS_SHA1=y +CONFIG_CRYPTO_DEV_SUNXI_SS_AES=y +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_RAID6_PQ=m +CONFIG_BITREVERSE=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_IO=y +CONFIG_CRC_CCITT=y +CONFIG_CRC16=y +CONFIG_CRC_T10DIF=y +CONFIG_CRC_ITU_T=y +CONFIG_CRC32=y +# CONFIG_CRC32_SELFTEST is not set +CONFIG_CRC32_SLICEBY8=y +# CONFIG_CRC32_SLICEBY4 is not set +# CONFIG_CRC32_SARWATE is not set +# CONFIG_CRC32_BIT is not set +CONFIG_CRC7=m +CONFIG_LIBCRC32C=y +# CONFIG_CRC8 is not set +CONFIG_AUDIT_GENERIC=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_XZ_DEC=y +CONFIG_XZ_DEC_X86=y +CONFIG_XZ_DEC_POWERPC=y +CONFIG_XZ_DEC_IA64=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_SPARC=y +CONFIG_XZ_DEC_BCJ=y +# CONFIG_XZ_DEC_TEST is not set +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_DECOMPRESS_XZ=y +CONFIG_DECOMPRESS_LZO=y +CONFIG_REED_SOLOMON=y +CONFIG_REED_SOLOMON_ENC8=y +CONFIG_REED_SOLOMON_DEC8=y +CONFIG_TEXTSEARCH=y +CONFIG_TEXTSEARCH_KMP=m +CONFIG_TEXTSEARCH_BM=m +CONFIG_TEXTSEARCH_FSM=m +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_CPU_RMAP=y +CONFIG_DQL=y +CONFIG_NLATTR=y +CONFIG_LRU_CACHE=m +CONFIG_AVERAGE=y +# CONFIG_CORDIC is not set diff --git a/config/lirc.conf.bananapi b/config/lirc.conf.bananapi new file mode 100644 index 0000000000..d5fa33f8db --- /dev/null +++ b/config/lirc.conf.bananapi @@ -0,0 +1,64 @@ +# generated by devinput.sh +begin remote + name devinput + bits 16 + eps 30 + aeps 100 + pre_data_bits 16 + pre_data 0x0001 + post_data_bits 32 + post_data 0x00000001 + gap 132799 + toggle_bit 0 + + begin codes + POWER 87 + MUTE 92 + HELP 5 + PREFS 9 + FAVS 21 + R2C1 4 + R2C2 8 + R2C3 20 + VOLUME+ 255 + VOLUME- 93 + INFO 16 + MOUSE 17 + ZOOM+ 12 + ZOOM- 88 + R5C1 84 + R5C2 91 + R5C3 23 + MENU 22 + HOME 71 + BACK 79 + LEFT 6 + RIGHT 14 + UP 67 + DOWN 10 + OK 2 + STOP 19 + PLAY 80 + SEARCH 13 + REV 7 + FWD 3 + PREV 15 + NEXT 11 + RED 85 + GREEN 78 + YELLOW 73 + BLUE 72 + 1 26 + 2 1 + 3 69 + 4 89 + 5 77 + 6 64 + 7 82 + 8 83 + 9 65 + 0 90 + AUDIO 68 + SUBTITLE 70 + end codes +end remote diff --git a/config/modules.bananapi b/config/modules.bananapi new file mode 100644 index 0000000000..612a1137ab --- /dev/null +++ b/config/modules.bananapi @@ -0,0 +1,8 @@ +hci_uart +gpio_sunxi +rfcomm +hidp +sunxi_ss +sunxi-ir +bonding +spi_sun7i \ No newline at end of file diff --git a/config/uEnv.bananapi b/config/uEnv.bananapi new file mode 100644 index 0000000000..3825ceb85a --- /dev/null +++ b/config/uEnv.bananapi @@ -0,0 +1,5 @@ +console=ttyS0,115200 +root=/dev/mmcblk0p1 rootwait +extraargs=rootfstype=ext4 sunxi_ve_mem_reserve=0 sunxi_g2d_mem_reserve=0 sunxi_no_mali_mem_reserve sunxi_fb_mem_reserve=16 hdmi.audio=EDID:0 disp.screen0_output_mode=EDID:1280x720p60 panic=10 consoleblank=0 +script=bananapi.bin +kernel=uImage diff --git a/patch/bananagmac.patch b/patch/bananagmac.patch new file mode 100644 index 0000000000..5aace127b3 --- /dev/null +++ b/patch/bananagmac.patch @@ -0,0 +1,374 @@ +--- a/arch/arm/kernel/setup.c ++++ b/arch/arm/kernel/setup.c +@@ -31,7 +31,18 @@ + #include + #include + #include ++ ++#ifdef CONFIG_GMAC_FOR_BANANAPI ++#include ++#include ++#include + #include ++#include ++#include ++#include ++#endif ++ ++ + + #include + #include +@@ -1101,16 +1112,13 @@ + + seq_printf(m, "Hardware\t: %s\n", machine_name); + seq_printf(m, "Revision\t: %04x\n", system_rev); ++#ifdef CONFIG_GMAC_FOR_BANANAPI ++ seq_printf(m, "Serial\t\t: %08x%08x%08x%08x\n", readl(SW_VA_SID_IO_BASE+0x0C), ++ readl(SW_VA_SID_IO_BASE+0x08), readl(SW_VA_SID_IO_BASE+0x04), readl(SW_VA_SID_IO_BASE)); ++#else + seq_printf(m, "Serial\t\t: %08x%08x\n", + system_serial_high, system_serial_low); +- +- #define SW_VA_SID_IO_BASE 0xf1c23800 +- seq_printf(m, "Chipid\t\t: %08x-%08x-%08x-%08x\n", +- readl(SW_VA_SID_IO_BASE), +- readl(SW_VA_SID_IO_BASE + 0x4), +- readl(SW_VA_SID_IO_BASE + 0x8), +- readl(SW_VA_SID_IO_BASE + 0xc) +- ); ++#endif + return 0; + } + + +--- a/arch/arm/plat-sunxi/sys_config.c ++++ b/arch/arm/plat-sunxi/sys_config.c +@@ -145,6 +145,7 @@ + + return gpio_count; + } ++EXPORT_SYMBOL(script_parser_mainkey_get_gpio_count); //Fix the GAMC cannot build as module + + int script_parser_mainkey_get_gpio_cfg(char *main_name, void *gpio_cfg, int gpio_count) + { +@@ -179,6 +180,7 @@ + + return SCRIPT_PARSER_KEY_NOT_FIND; + } ++EXPORT_SYMBOL(script_parser_mainkey_get_gpio_cfg); //Fix the GAMC cannot build as module + + /* + * +--- a/drivers/net/ethernet/allwinner/gmac/sunxi_gmac.h ++++ b/drivers/net/ethernet/allwinner/gmac/sunxi_gmac.h +@@ -33,6 +33,9 @@ + #include "gmac_base.h" + + #define GMAC_RESOURCE_NAME "sunxi_gmac" ++#ifdef CONFIG_GMAC_FOR_BANANAPI ++ #define GMAC_PHY_POWER ++#endif + + enum rx_frame_status { /* IPC status */ + good_frame = 0, +@@ -132,7 +135,11 @@ + void __iomem *gpiobase; + #else + int gpio_cnt; ++#ifdef CONFIG_GMAC_FOR_BANANAPI ++ user_gpio_set_t *gpio_hd; ++#else + unsigned int gpio_handle; ++#endif + + #endif + #ifndef CONFIG_GMAC_CLK_SYS +@@ -163,6 +170,9 @@ + spinlock_t lock; + spinlock_t tx_lock; + struct gmac_plat_data *plat; ++#ifdef GMAC_PHY_POWER ++ u32 gpio_power_hd; ++#endif + //struct dma_features dma_cap; + }; + +--- a/drivers/net/ethernet/allwinner/gmac/Kconfig ++++ b/drivers/net/ethernet/allwinner/gmac/Kconfig +@@ -29,6 +29,13 @@ + If you want to use the system interface, select it. If not, the + driver will control the clock by ioremap. + ++config GMAC_FOR_BANANAPI ++ bool "modified gmac driver for Bananapi" ++ depends on SUNXI_GMAC ++ ---help--- ++ If you want to compile the firmware for Bananapi, you should select it. ++ The driver will be modified to be suit for the Bananapi' gmac. ++ + choice + prompt "Select the DMA TX/RX descriptor operating modes" + depends on SUNXI_GMAC +--- a/drivers/net/ethernet/allwinner/gmac/gmac_plat.c ++++ b/drivers/net/ethernet/allwinner/gmac/gmac_plat.c +@@ -34,6 +34,10 @@ + #include + #include + #include ++#ifdef CONFIG_GMAC_FOR_BANANAPI ++#include ++#include //Fix the GAMC cannot build as module ++#endif + + #include "sunxi_gmac.h" + +@@ -43,11 +47,64 @@ + int ret = 0; + + #ifndef CONFIG_GMAC_SCRIPT_SYS ++#ifdef CONFIG_GMAC_FOR_BANANAPI ++ int reg_value; ++ /* configure system io */ ++ if(priv->gpiobase){ ++ writel(0x22222222, priv->gpiobase + PA_CFG0); ++ ++ writel(0x22222222, priv->gpiobase + PA_CFG1); ++ ++ writel(0x00000022, priv->gpiobase + PA_CFG2); ++#else + if(priv->gpiobase){ + writel(0x55555555, priv->gpiobase + PA_CFG0); + writel(0x50555505, priv->gpiobase + PA_CFG1); + writel(0x00000005, priv->gpiobase + PA_CFG2); + } ++#endif ++#else ++#ifdef CONFIG_GMAC_FOR_BANANAPI ++ int i = 0; ++ int gpio_tmp; ++ ++ priv->gpio_cnt = script_parser_mainkey_get_gpio_count("gmac_para"); ++ priv->gpio_hd = kmalloc(sizeof(user_gpio_set_t)*priv->gpio_cnt, GFP_KERNEL); ++ printk("gmac_para gpio count is %d\n", priv->gpio_cnt); ++ script_parser_mainkey_get_gpio_cfg("gmac_para", priv->gpio_hd, priv->gpio_cnt); ++ for (i = 0; i < priv->gpio_cnt; i++){ ++ gpio_tmp = gpio_request_ex("gmac_para", priv->gpio_hd[i].gpio_name); ++ if (gpio_tmp){ ++ gpio_set_one_pin_status(gpio_tmp, &priv->gpio_hd[i], priv->gpio_hd[i].gpio_name, 1); ++ }else{ ++ printk("gpio_set_one_pin_status error\n"); ++ } ++ } ++#ifdef GMAC_PHY_POWER ++ priv->gpio_power_hd= gpio_request_ex("gmac_phy_power", "gmac_phy_power_en"); ++#endif ++gpio_err: ++ if(unlikely(ret)){ ++ gpio_free(priv->gpio_hd); ++ priv->gpio_hd = NULL; ++ priv->gpio_cnt = 0; ++ } ++#ifdef SUN7i_GMAC_FPGA ++ reg_value = readl(IO_ADDRESS(GPIO_BASE + 0x108)); ++ reg_value |= 0x1<<20; ++ writel(reg_value, IO_ADDRESS(GPIO_BASE + 0x108)); ++ ++ reg_value = readl(IO_ADDRESS(GPIO_BASE + 0x10c)); ++ reg_value &= ~(0x1<<29); ++ writel(reg_value, IO_ADDRESS(GPIO_BASE + 0x10c)); ++ ++ mdelay(200); ++ ++ reg_value = readl(IO_ADDRESS(GPIO_BASE + 0x10c)); ++ reg_value |= 0x1<<29; ++ writel(reg_value, IO_ADDRESS(GPIO_BASE + 0x10c)); ++#endif ++ + #else + priv->gpio_handle = gpio_request_ex("gmac_para", NULL); + if(!priv->gpio_handle) { +@@ -55,6 +112,7 @@ + ret = -1; + } + #endif ++#endif + return ret; + } + +@@ -177,8 +235,17 @@ + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + release_mem_region(res->start, resource_size(res)); + #else ++ #ifdef CONFIG_GMAC_FOR_BANANAPI ++ int i; ++ if (priv->gpio_hd){ ++ gpio_free(priv->gpio_hd); ++ priv->gpio_hd = NULL; ++ priv->gpio_cnt = 0; ++ } ++ #else + gpio_release(priv->gpio_handle, 0); + #endif ++#endif + + iounmap(priv->gmac_clk_reg); + +--- a/drivers/net/ethernet/allwinner/gmac/gmac_core.c ++++ b/drivers/net/ethernet/allwinner/gmac/gmac_core.c +@@ -38,7 +38,6 @@ + #include + + #include +-#include + #include + #include + +@@ -51,6 +50,10 @@ + #include "gmac_desc.h" + #include "gmac_ethtool.h" + ++#ifdef CONFIG_GMAC_FOR_BANANAPI ++#include ++#endif ++ + #undef GMAC_DEBUG + #ifdef GMAC_DEBUG + #define DBG(nlevel, klevel, fmt, args...) \ +@@ -79,7 +82,8 @@ + #define GMAC_ALIGN(x) L1_CACHE_ALIGN(x) + #define JUMBO_LEN 9000 + +-static char *mac_str = ":"; ++#define GMAC_MAC_ADDRESS "00:00:00:00:00:00" ++static char *mac_str = GMAC_MAC_ADDRESS; + module_param(mac_str, charp, S_IRUGO | S_IWUSR); + MODULE_PARM_DESC(mac_str, "MAC Address String.(xx:xx:xx:xx:xx:xx)"); + +@@ -217,6 +221,9 @@ + || phy_interface == PHY_INTERFACE_MODE_GMII) + priv_clk_reg |= 0x00000002; + ++#ifdef CONFIG_GMAC_FOR_BANANAPI ++ priv_clk_reg |= (0x00000003<<10); ++#endif + writel(priv_clk_reg, priv->gmac_clk_reg + GMAC_CLK_REG); + } + +@@ -773,21 +780,17 @@ + + static void gmac_check_ether_addr(struct gmac_priv *priv) + { ++ int i; ++ char *p = mac_str; + /* verify if the MAC address is valid, in case of failures it + * generates a random MAC address */ + if (!is_valid_ether_addr(priv->ndev->dev_addr)) { +- if (strlen(mac_str) == 17) { +- int i; +- char *p = mac_str; +- +- pr_info("gmac: use mac address from mac_str\n"); +- for (i=0; i<6; i++,p++) +- priv->ndev->dev_addr[i] = simple_strtoul(p, &p, 16); +- } +- ++#ifdef CONFIG_GMAC_FOR_BANANAPI ++ gmac_get_umac_addr((void __iomem *) ++ priv->ndev->base_addr, ++ priv->ndev->dev_addr, 0); + if (!is_valid_ether_addr(priv->ndev->dev_addr)) { + unsigned int reg_val; +- + reg_val = readl(SW_VA_SID_IO_BASE); + pr_info("gmac: use mac address from chipid\n"); + priv->ndev->dev_addr[0] = 0x02; /* Non OUI / registered MAC address */ +@@ -803,12 +806,47 @@ + pr_info("gmac: use random mac address\n"); + } + } +- } else { +- pr_info("gmac: use mac address from cmdline\n"); ++#else ++ if (!is_valid_ether_addr(priv->ndev->dev_addr)) { ++ for (i=0; i<6; i++,p++) ++ priv->ndev->dev_addr[i] = simple_strtoul(p, &p, 16); ++ } ++ ++ if (!is_valid_ether_addr(priv->ndev->dev_addr)) ++ random_ether_addr(priv->ndev->dev_addr); ++#endif ++ } ++ printk(KERN_WARNING "%s: device MAC address %pM\n", priv->ndev->name, ++ priv->ndev->dev_addr); ++} ++ ++#ifdef GMAC_PHY_POWER ++void gmac_phy_power_en(struct gmac_priv *priv) ++{ ++ if(!priv) return; ++ ++ if (priv->gpio_power_hd){ ++ printk("GMAC gpio_power_hd:gpio_direction_output\n"); ++ gpio_set_one_pin_io_status(priv->gpio_power_hd, 1, "gmac_phy_power_en");//set the gpio to output ++ gpio_write_one_pin_value(priv->gpio_power_hd, 1, "gmac_phy_power_en"); ++ mdelay(200); ++ } ++ ++ return; ++} ++ ++void gmac_phy_power_disable(struct gmac_priv *priv) ++{ ++ if(!priv) return; ++ ++ if (priv->gpio_power_hd){ ++ gpio_write_one_pin_value(priv->gpio_power_hd, 0, "gmac_phy_power_en"); + } + +- pr_info("gmac: device MAC address %pM\n", priv->ndev->dev_addr); ++ return; ++ + } ++#endif + + /** + * gmac_open - open entry point of the driver +@@ -824,9 +862,14 @@ + struct gmac_priv *priv = netdev_priv(ndev); + int ret; + +- gmac_clk_ctl(priv, 1); +- //gmac_check_ether_addr(priv); ++#ifdef GMAC_PHY_POWER ++ gmac_phy_power_en(priv); ++#endif + ++ gmac_clk_ctl(priv, 1); ++#ifdef GMAC_PHY_POWER ++ gmac_check_ether_addr(priv); ++#endif + /* MDIO bus Registration */ + ret = gmac_mdio_register(ndev); + if (ret < 0) { +@@ -964,6 +1007,10 @@ + gmac_mdio_unregister(ndev); + gmac_clk_ctl(priv, 0); + ++#ifdef GMAC_PHY_POWER ++ gmac_phy_power_disable(priv); ++#endif ++ + return 0; + } + +@@ -1742,6 +1789,9 @@ + + static void __exit gmac_remove(void) + { ++#ifdef CONFIG_GMAC_SCRIPT_SYS ++ script_parser_fetch("gmac_para", "gmac_used", &gmac_used, 1); ++#endif + if (gmac_used != 1) { + pr_info("gmac is disabled\n"); + return; diff --git a/patch/gpio.patch b/patch/gpio.patch new file mode 100644 index 0000000000..541b314c22 --- /dev/null +++ b/patch/gpio.patch @@ -0,0 +1,17 @@ +--- a/drivers/gpio/gpio-sunxi.c ++++ b/drivers/gpio/gpio-sunxi.c +@@ -182,11 +182,9 @@ static int sunxi_gpio_request(struct gpio_chip *chip, unsigned offset) + if ((offset > chip->ngpio - 1) || (offset < 0)) + return -EINVAL; + +- /* Set sysfs exported gpio name (example "gpio254_ph20") */ +- sprintf((char *)(chip->names[offset]), "gpio%d_p%c%d", +- offset+chip->base, +- 'a'+sgpio->data[offset].info.port-1, +- sgpio->data[offset].info.port_num); ++ /* Set sysfs exported gpio name (example "gpio254") */ ++ sprintf((char *)(chip->names[offset]), "gpio%d", ++ offset+chip->base); + + sgpio->data[offset].gpio_handler = gpio_request_ex("gpio_para", + sgpio->data[offset].pin_name); diff --git a/patch/small_lcd_drivers.patch b/patch/small_lcd_drivers.patch new file mode 100644 index 0000000000..6f04199b53 --- /dev/null +++ b/patch/small_lcd_drivers.patch @@ -0,0 +1,21 @@ +--- a/drivers/video/Makefile ++++ b/drivers/video/Makefile +@@ -4,6 +4,7 @@ + + # Each configuration option enables a list of files. + ++obj-y += fbtft/ + obj-$(CONFIG_VGASTATE) += vgastate.o + obj-y += fb_notify.o + obj-$(CONFIG_FB) += fb.o +--- a/drivers/video/Kconfig ++++ b/drivers/video/Kconfig +@@ -17,6 +17,8 @@ config SH_LCD_MIPI_DSI + + source "drivers/char/agp/Kconfig" + ++source "drivers/video/fbtft/Kconfig" ++ + source "drivers/gpu/vga/Kconfig" + + source "drivers/gpu/drm/Kconfig" diff --git a/patch/spi.patch b/patch/spi.patch new file mode 100644 index 0000000000..3fcc586e89 --- /dev/null +++ b/patch/spi.patch @@ -0,0 +1,2182 @@ +diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig +index c4fb46a..2f9c804 100644 +--- a/drivers/spi/Kconfig ++++ b/drivers/spi/Kconfig +@@ -381,6 +381,19 @@ config SUN5I_SPI_NDMA + This selects SPI DMA mode with DMA transfer + Y select NDMA mode and N select DDMA mode + ++config SPI_SUN7I ++ tristate "SUN7I SPI Controller" ++ depends on ARCH_SUN7I ++ help ++ Allwinner Soc SPI controller,present on SUN7I chips. ++ ++config SUN7I_SPI_NDMA ++ bool "SUN7I SPI Normal DMA mode select" ++ depends on SPI_SUN7I ++ help ++ This selects SPI DMA mode with DMA transfer ++ Y select NDMA mode and N select DDMA mode ++ + config SPI_TEGRA + tristate "Nvidia Tegra SPI controller" + depends on ARCH_TEGRA && TEGRA_SYSTEM_DMA +diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile +index a13913f..f26f012 100644 +--- a/drivers/spi/Makefile ++++ b/drivers/spi/Makefile +@@ -64,4 +64,4 @@ obj-$(CONFIG_SPI_TXX9) += spi-txx9.o + obj-$(CONFIG_SPI_XILINX) += spi-xilinx.o + obj-$(CONFIG_SPI_SUN4I) += spi_sunxi.o + obj-$(CONFIG_SPI_SUN5I) += spi_sunxi.o +- ++obj-$(CONFIG_SPI_SUN7I) += spi-sun7i.o +diff --git a/drivers/spi/spi-sun7i.c b/drivers/spi/spi-sun7i.c +new file mode 100644 +index 0000000..a9967b7 +--- /dev/null ++++ b/drivers/spi/spi-sun7i.c +@@ -0,0 +1,2142 @@ ++/* ++ * drivers/spi/spi-sun7i.c ++ * Copyright (C) 2012 - 2016 Reuuimlla Limited ++ * Pan Nan ++ * James Deng ++ * ++ * SUN7I SPI Controller Driver ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define SPI_DEBUG_LEVEL 2 ++ ++#if (SPI_DEBUG_LEVEL == 1) ++ #define spi_dbg(format,args...) do {} while (0) ++ #define spi_inf(format,args...) do {} while (0) ++ #define spi_err(format,args...) printk(KERN_ERR "[spi-err] "format,##args) ++#elif (SPI_DEBUG_LEVEL == 2) ++ #define spi_dbg(format,args...) do {} while (0) ++ #define spi_inf(format,args...) printk(KERN_INFO"[spi-inf] "format,##args) ++ #define spi_err(format,args...) printk(KERN_ERR "[spi-err] "format,##args) ++#elif (SPI_DEBUG_LEVEL == 3) ++ #define spi_dbg(format,args...) printk(KERN_INFO"[spi-dbg] "format,##args) ++ #define spi_inf(format,args...) printk(KERN_INFO"[spi-inf] "format,##args) ++ #define spi_err(format,args...) printk(KERN_ERR "[spi-err] "format,##args) ++#endif ++ ++enum spi_duplex_flag { ++ HALF_DUPLEX_RX, // half duplex read ++ HALF_DUPLEX_TX, // half duplex write ++ FULL_DUPLEX_RX_TX, // full duplex read and write ++ DUPLEX_NULL, ++}; ++ ++enum spi_dma_dir { ++ SPI_DMA_NULL = 0, ++ SPI_DMA_RDEV = 1, ++ SPI_DMA_WDEV = 2, ++}; ++ ++#define SYS_SPI_PIN ++#ifndef SYS_SPI_PIN ++static void* __iomem gpio_addr = NULL; ++ ++/* gpio base address */ ++#define _PIO_BASE_ADDRESS (0x01c20800) ++ ++/* gpio spi1 */ ++#define _Pn_CFG1(n) ( (n)*0x24 + 0x04 + gpio_addr ) ++#define _Pn_DRV1(n) ( (n)*0x24 + 0x14 + gpio_addr ) ++#define _Pn_PUL1(n) ( (n)*0x24 + 0x1C + gpio_addr ) ++#endif ++ ++struct sun7i_spi { ++ struct platform_device *pdev; ++ struct spi_master *master; /* kzalloc */ ++ void __iomem *base_addr; /* register */ ++ struct clk *hclk; /* ahb spi gating bit */ ++ struct clk *mclk; /* ahb spi gating bit */ ++ unsigned long gpio_hdle; ++ dma_chan_type_e dma_type; ++ int dma_id_tx; ++ int dma_id_rx; ++ dma_hdl_t dma_hdle_tx; ++ dma_hdl_t dma_hdle_rx; ++ enum spi_duplex_flag duplex_flag; ++ unsigned int irq; /* irq NO. */ ++ int busy; ++#define SPI_FREE (1<<0) ++#define SPI_SUSPND (1<<1) ++#define SPI_BUSY (1<<2) ++ int result; /* 0: succeed, -1: fail */ ++ struct workqueue_struct *workqueue; ++ struct work_struct work; ++ struct list_head queue; /* spi messages */ ++ spinlock_t lock; ++ struct completion done; /* wakup another spi transfer */ ++ /* keep select during one message */ ++ void (*cs_control)(struct spi_device *spi, bool on); ++ /* (1) enable cs1, cs_bitmap = SPI_CHIP_SELECT_CS1; ++ * (2) enable cs0&cs1,cs_bitmap = SPI_CHIP_SELECT_CS0|SPI_CHIP_SELECT_CS1; ++ */ ++#define SPI_CHIP_SELECT_CS0 (0x01) ++#define SPI_CHIP_SELECT_CS1 (0x02) ++ int cs_bitmap; /* cs0- 0x1, cs1-0x2, cs0 & cs1-0x3. */ ++}; ++ ++/* config chip select */ ++s32 spi_set_cs(u32 chipselect, void *base_addr) ++{ ++ u32 reg_val = readl(base_addr + SPI_CTL_REG); ++ ++ if (chipselect < 4) { ++ reg_val &= ~SPI_CTL_SS_MASK;/* SS-chip select, clear two bits */ ++ reg_val |= chipselect << SPI_SS_BIT_POS;/* set chip select */ ++ ++ writel(reg_val, base_addr + SPI_CTL_REG); ++ ++ return 0; ++ } else { ++ spi_err("%s: chip select set fail, cs = %d\n", __func__, chipselect); ++ return -1; ++ } ++} ++ ++/* select dma type */ ++s32 spi_sel_dma_type(u32 dma_type, void *base_addr) ++{ ++ u32 reg_val = readl(base_addr + SPI_CTL_REG); ++ ++ reg_val &= ~SPI_CTL_DMAMOD; ++ if (dma_type) { ++ reg_val |= 1 << 5; ++ } ++ writel(reg_val, base_addr + SPI_CTL_REG); ++ ++ return 0; ++} ++ ++/* config spi */ ++void spi_config(u32 master, u32 config, void *base_addr) ++{ ++ u32 reg_val = readl(base_addr + SPI_CTL_REG); ++ ++ /* 1. POL */ ++ if (config & SPI_POL_ACTIVE_) { ++ reg_val |= SPI_CTL_POL; ++ } else { ++ reg_val &= ~SPI_CTL_POL; /* default POL = 0 */ ++ } ++ ++ /*2. PHA */ ++ if (config & SPI_PHA_ACTIVE_) { ++ reg_val |= SPI_CTL_PHA; ++ } else { ++ reg_val &= ~SPI_CTL_PHA; /* default PHA = 0 */ ++ } ++ ++ /* 3. SSPOL, chip select signal polarity */ ++ if (config & SPI_CS_HIGH_ACTIVE_) { ++ reg_val &= ~SPI_CTL_SSPOL; ++ } else { ++ reg_val |= SPI_CTL_SSPOL; /* default SSPOL = 1,Low level effective */ ++ } ++ ++ /* 4. LMTF-LSB/MSB transfer first select */ ++ if (config & SPI_LSB_FIRST_ACTIVE_) { ++ reg_val |= SPI_CTL_LMTF; ++ } else { ++ reg_val &= ~SPI_CTL_LMTF; /* default LMTF = 0, MSB first */ ++ } ++ ++ /* master mode: set DDB,DHB,SMC,SSCTL */ ++ if (master == 1) { ++ /* 5. dummy burst type */ ++ if (config & SPI_DUMMY_ONE_ACTIVE_) { ++ reg_val |= SPI_CTL_DDB; ++ } else { ++ reg_val &= ~SPI_CTL_DDB; /* default DDB =0, ZERO */ ++ } ++ ++ /* 6. discard hash burst-DHB */ ++ if (config & SPI_RECEIVE_ALL_ACTIVE_) { ++ reg_val &= ~SPI_CTL_DHB; ++ } else { ++ reg_val |= SPI_CTL_DHB; /* default DHB =1, discard unused burst */ ++ } ++ ++ /* 7. set SMC = 1, SSCTL = 0, TPE = 1 */ ++ reg_val &= ~SPI_CTL_SSCTL; ++ reg_val |= SPI_CTL_T_PAUSE_EN; ++ } else { ++ /* tips for slave mode config */ ++ spi_inf("%s: slave mode configurate control register\n", __func__); ++ } ++ ++ writel(reg_val, base_addr + SPI_CTL_REG); ++} ++ ++/* restore reg data after transfer complete */ ++void spi_restore_state(u32 master, void *base_addr) ++{ ++ u32 reg_val = readl(base_addr + SPI_CTL_REG); ++ ++ /* ++ * config spi control register ++ * | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ++ * | DHB| DDB | SS | SMC | XCH |TFRST|RFRST|SSCTL| MSB | TBW |SSPOL| POL | PHA | MOD | EN | ++ * | 1 | 0 | 00 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | ++ */ ++ /* master mode */ ++ if (master) { ++ reg_val |= (SPI_CTL_DHB | SPI_CTL_SSPOL | SPI_CTL_POL | SPI_CTL_PHA | SPI_CTL_FUNC_MODE | SPI_CTL_EN); ++ ++ /* new bit,transmit pause enable,stop smart dummy when rxfifo full */ ++ reg_val |= SPI_CTL_T_PAUSE_EN; ++ ++ /* |SPI_CTL_TBW); //deleted SPI_CTL_TBW bit for aw1623, this bit is defined for dma mode select, 2011-5-26 19:55:32 */ ++ reg_val &= ~(SPI_CTL_DDB | SPI_CTL_SS_MASK | SPI_CTL_XCH | SPI_CTL_SSCTL | SPI_CTL_LMTF); ++ } else { /* slave mode */ ++ reg_val |= (SPI_CTL_SSPOL | SPI_CTL_POL | SPI_CTL_PHA || SPI_CTL_EN); ++ ++ /* |SPI_CTL_TBW); //deleted SPI_CTL_TBW bit for aw1623, this bit is defined for dma mode select, 2011-5-26 19:55:32 */ ++ reg_val &= ~(SPI_CTL_DHB | SPI_CTL_FUNC_MODE | SPI_CTL_DDB | SPI_CTL_SS_MASK | SPI_CTL_XCH | SPI_CTL_SSCTL | SPI_CTL_LMTF); ++ } ++ ++ spi_dbg("control register set default value: 0x%08x\n", reg_val); ++ writel(reg_val, base_addr + SPI_CTL_REG); ++} ++ ++/* set spi clock */ ++void spi_set_clk(u32 spi_clk, u32 ahb_clk, void *base_addr) ++{ ++ u32 reg_val = 0; ++ u32 N = 0; ++ u32 div_clk = (ahb_clk >> 1) / spi_clk; ++ ++ reg_val = readl(base_addr + SPI_CLK_RATE_REG); ++ ++ if (div_clk <= SPI_CLK_SCOPE) { ++ if (div_clk != 0) { ++ div_clk--; ++ } ++ ++ reg_val &= ~SPI_CLKCTL_CDR2; ++ reg_val |= (div_clk | SPI_CLKCTL_DRS); ++ } else { ++ while (1) { ++ if (div_clk == 1) { ++ break; ++ } ++ div_clk >>= 1; ++ N++; ++ }; ++ ++ reg_val &= ~(SPI_CLKCTL_CDR1 | SPI_CLKCTL_DRS); ++ reg_val |= (N << 8); ++ } ++ ++ writel(reg_val, base_addr + SPI_CLK_RATE_REG); ++} ++ ++/* start spi transfer */ ++void spi_start_xfer(void *base_addr) ++{ ++ u32 reg_val = readl(base_addr + SPI_CTL_REG); ++ reg_val |= SPI_CTL_XCH; ++ writel(reg_val, base_addr + SPI_CTL_REG); ++} ++ ++/* query tranfer is completed in smc mode */ ++u32 spi_query_xfer(void *base_addr) ++{ ++ u32 reg_val = readl(base_addr + SPI_CTL_REG); ++ return (reg_val & SPI_CTL_XCH); ++} ++ ++/* enable spi bus */ ++void spi_enable_bus(void *base_addr) ++{ ++ u32 reg_val = readl(base_addr + SPI_CTL_REG); ++ reg_val |= SPI_CTL_EN; ++ writel(reg_val, base_addr + SPI_CTL_REG); ++} ++ ++/* disbale spi bus */ ++void spi_disable_bus(void *base_addr) ++{ ++ u32 reg_val = readl(base_addr + SPI_CTL_REG); ++ reg_val &= ~SPI_CTL_EN; ++ writel(reg_val, base_addr + SPI_CTL_REG); ++} ++ ++/* set master mode */ ++void spi_set_master(void *base_addr) ++{ ++ u32 reg_val = readl(base_addr + SPI_CTL_REG); ++ reg_val |= SPI_CTL_FUNC_MODE; ++ writel(reg_val, base_addr + SPI_CTL_REG); ++} ++ ++/* set slave mode */ ++void spi_set_slave(void *base_addr) ++{ ++ u32 reg_val = readl(base_addr + SPI_CTL_REG); ++ reg_val &= ~SPI_CTL_FUNC_MODE; ++ writel(reg_val, base_addr + SPI_CTL_REG); ++} ++ ++/* disable irq type */ ++void spi_disable_irq(u32 bitmap, void *base_addr) ++{ ++ u32 reg_val = readl(base_addr + SPI_INT_CTL_REG); ++ bitmap &= SPI_INTEN_MASK; ++ reg_val &= ~bitmap; ++ writel(reg_val, base_addr + SPI_INT_CTL_REG); ++} ++ ++/* enable irq type */ ++void spi_enable_irq(u32 bitmap, void *base_addr) ++{ ++ u32 reg_val = readl(base_addr + SPI_INT_CTL_REG); ++ bitmap &= SPI_INTEN_MASK; ++ reg_val |= bitmap; ++ writel(reg_val, (base_addr + SPI_INT_CTL_REG)); ++} ++ ++/* disable dma irq */ ++void spi_disable_dma_irq(u32 bitmap, void *base_addr) ++{ ++ u32 reg_val = readl(base_addr + SPI_DMA_CTL_REG); ++ bitmap &= SPI_DRQEN_MASK; ++ reg_val &= ~bitmap; ++ writel(reg_val, base_addr + SPI_DMA_CTL_REG); ++} ++ ++/* enable dma irq */ ++void spi_enable_dma_irq(u32 bitmap, void *base_addr) ++{ ++ u32 reg_val = readl(base_addr + SPI_DMA_CTL_REG); ++ bitmap &= SPI_DRQEN_MASK; ++ reg_val |= bitmap; ++ writel(reg_val, base_addr + SPI_DMA_CTL_REG); ++} ++ ++/* query irq pending */ ++u32 spi_qry_irq_pending(void *base_addr) ++{ ++ return (SPI_STAT_MASK & readl(base_addr + SPI_STATUS_REG)); ++} ++ ++/* clear irq pending */ ++void spi_clr_irq_pending(u32 pending_bit, void *base_addr) ++{ ++ pending_bit &= SPI_STAT_MASK; ++ writel(pending_bit, base_addr + SPI_STATUS_REG); ++} ++ ++/* query txfifo bytes */ ++u32 spi_query_txfifo(void *base_addr) ++{ ++ u32 reg_val = (SPI_FIFO_TXCNT & readl(base_addr + SPI_FIFO_STA_REG)); ++ reg_val >>= SPI_TXCNT_BIT_POS; ++ return reg_val; ++} ++ ++/* query rxfifo bytes */ ++u32 spi_query_rxfifo(void *base_addr) ++{ ++ u32 reg_val = (SPI_FIFO_RXCNT & readl(base_addr + SPI_FIFO_STA_REG)); ++ reg_val >>= SPI_RXCNT_BIT_POS; ++ return reg_val; ++} ++ ++/* reset fifo */ ++void spi_reset_fifo(void *base_addr) ++{ ++ u32 reg_val = readl(base_addr + SPI_CTL_REG); ++ reg_val |= (SPI_CTL_RST_RXFIFO | SPI_CTL_RST_TXFIFO); ++ writel(reg_val, base_addr + SPI_CTL_REG); ++} ++ ++/* set transfer total length BC and transfer length WTC */ ++void spi_set_bc_wtc(u32 tx_len, u32 rx_len, void *base_addr) ++{ ++ u32 reg_val = readl(base_addr + SPI_BC_REG); ++ reg_val &= ~SPI_BC_BC_MASK; ++ reg_val |= (SPI_BC_BC_MASK & (tx_len + rx_len)); ++ writel(reg_val, base_addr + SPI_BC_REG); ++ spi_dbg("%s: bc: %u\n", __func__, readl(base_addr + SPI_BC_REG)); ++ ++ reg_val = readl(base_addr + SPI_TC_REG); ++ reg_val &= ~SPI_TC_WTC_MASK; ++ reg_val |= (SPI_TC_WTC_MASK & tx_len); ++ writel(reg_val, base_addr + SPI_TC_REG); ++ spi_dbg("%s: tc: %u\n", __func__, readl(base_addr + SPI_TC_REG)); ++} ++ ++/* set ss control */ ++void spi_ss_ctrl(void *base_addr, u32 on_off) ++{ ++ u32 reg_val = readl(base_addr + SPI_CTL_REG); ++ ++ on_off &= 0x1; ++ if (on_off) { ++ reg_val |= SPI_CTL_SS_CTRL; ++ } else { ++ reg_val &= ~SPI_CTL_SS_CTRL; ++ } ++ ++ writel(reg_val, base_addr + SPI_CTL_REG); ++} ++ ++/* set ss level */ ++void spi_ss_level(void *base_addr, u32 hi_lo) ++{ ++ u32 reg_val = readl(base_addr + SPI_CTL_REG); ++ ++ hi_lo &= 0x1; ++ if (hi_lo) { ++ reg_val |= SPI_CTL_SS_LEVEL; ++ } else { ++ reg_val &= ~SPI_CTL_SS_LEVEL; ++ } ++ ++ writel(reg_val, base_addr + SPI_CTL_REG); ++} ++ ++/* set wait clock counter */ ++void spi_set_waitclk_cnt(u32 waitclk_cnt, void *base_addr) ++{ ++ u32 reg_val = readl(base_addr + SPI_WAIT_REG); ++ reg_val &= ~SPI_WAIT_CLK_MASK; ++ waitclk_cnt &= SPI_WAIT_CLK_MASK; ++ reg_val |= waitclk_cnt; ++ writel(reg_val, base_addr + SPI_WAIT_REG); ++} ++ ++/* set sample delay in high speed mode */ ++void spi_set_sample_delay(u32 on_off, void *base_addr) ++{ ++ u32 reg_val = readl(base_addr + SPI_CTL_REG); ++ reg_val &= ~SPI_CTL_MASTER_SDC; ++ reg_val |= on_off; ++ writel(reg_val, base_addr + SPI_CTL_REG); ++} ++ ++/* keep unused burst */ ++void spi_clear_dhb(void *base_addr) ++{ ++ u32 reg_val = readl(base_addr + SPI_CTL_REG); ++ reg_val &= ~SPI_CTL_DHB; ++ writel(reg_val, base_addr + SPI_CTL_REG); ++} ++ ++static int sun7i_spi_get_cfg_csbitmap(int bus_num); ++ ++/* flush d-cache */ ++static void sun7i_spi_cleanflush_dcache_region(void *addr, __u32 len) ++{ ++ __cpuc_flush_dcache_area(addr, len/*len + (1 << 5) * 2 - 2*/); ++} ++ ++static char *spi_dma_rx[] = {"spi0_rx", "spi1_rx", "spi2_rx", "spi3_rx"}; ++static char *spi_dma_tx[] = {"spi0_tx", "spi1_tx", "spi2_tx", "spi3_tx"}; ++ ++static void sun7i_spi_dma_cb_rx(dma_hdl_t dma_hdl, void *parg) ++{ ++ struct sun7i_spi *aw_spi = (struct sun7i_spi *)parg; ++ unsigned long flags; ++ ++ spi_dbg("%s: spi%d dma read data callback\n", __func__, aw_spi->master->bus_num); ++ ++ spin_lock_irqsave(&aw_spi->lock, flags); ++ spi_disable_dma_irq(SPI_DRQEN_RR, aw_spi->base_addr); ++ spin_unlock_irqrestore(&aw_spi->lock, flags); ++} ++ ++static void sun7i_spi_dma_cb_tx(dma_hdl_t dma_hdl, void *parg) ++{ ++ struct sun7i_spi *aw_spi = (struct sun7i_spi *)parg; ++ unsigned long flags; ++ ++ spi_dbg("%s: spi%d dma write data callback\n", __func__, aw_spi->master->bus_num); ++ ++ spin_lock_irqsave(&aw_spi->lock, flags); ++ spi_disable_dma_irq(SPI_DRQEN_TE, aw_spi->base_addr); ++ spin_unlock_irqrestore(&aw_spi->lock, flags); ++} ++ ++/* request dma channel and set callback function */ ++static int sun7i_spi_prepare_dma(struct sun7i_spi *aw_spi, enum spi_dma_dir dma_dir) ++{ ++ int ret = 0; ++ int bus_num = aw_spi->master->bus_num; ++ dma_cb_t done_cb; ++ ++ spi_dbg("%s: enter\n", __func__); ++ if (SPI_DMA_RDEV == dma_dir) { ++ aw_spi->dma_hdle_rx = sw_dma_request(spi_dma_rx[bus_num], aw_spi->dma_type); ++ if (!aw_spi->dma_hdle_rx) { ++ spi_err("%s: spi%d request dma rx failed\n", __func__, bus_num); ++ return -EINVAL; ++ } ++ ++ done_cb.func = sun7i_spi_dma_cb_rx; ++ done_cb.parg = aw_spi; ++ ret = sw_dma_ctl(aw_spi->dma_hdle_rx, DMA_OP_SET_FD_CB, (void *)&done_cb); ++ } else if (SPI_DMA_WDEV == dma_dir) { ++ aw_spi->dma_hdle_tx = sw_dma_request(spi_dma_tx[bus_num], aw_spi->dma_type); ++ if (!aw_spi->dma_hdle_tx) { ++ spi_err("%s: spi%d request dma tx failed\n", __func__, bus_num); ++ return -EINVAL; ++ } ++ ++ done_cb.func = sun7i_spi_dma_cb_tx; ++ done_cb.parg = aw_spi; ++ ret = sw_dma_ctl(aw_spi->dma_hdle_tx, DMA_OP_SET_FD_CB, (void *)&done_cb); ++ } else { ++ return -1; ++ } ++ ++ return ret; ++} ++ ++static int sun7i_spi_config_dma(struct sun7i_spi *aw_spi, enum spi_dma_dir dma_dir, void *buf, unsigned int len) ++{ ++ int bus_num = aw_spi->master->bus_num; ++ unsigned char spi_rx_ndrq[] = {N_SRC_SPI0_RX, N_SRC_SPI1_RX, N_SRC_SPI2_RX, N_SRC_SPI3_RX}; ++ unsigned char spi_tx_ndrq[] = {N_DST_SPI0_TX, N_DST_SPI1_TX, N_DST_SPI3_TX, N_DST_SPI3_TX}; ++ unsigned char spi_rx_ddrq[] = {D_SRC_SPI0_RX, D_SRC_SPI1_RX, D_SRC_SPI2_RX, D_SRC_SPI3_RX}; ++ unsigned char spi_tx_ddrq[] = {D_DST_SPI0_TX, D_DST_SPI1_TX, D_DST_SPI3_TX, D_DST_SPI3_TX}; ++ unsigned long spi_phyaddr[] = {SPI0_BASE_ADDR, SPI1_BASE_ADDR, SPI2_BASE_ADDR, SPI3_BASE_ADDR}; /* physical address */ ++ dma_config_t spi_hw_conf; ++ dma_hdl_t dma_hdle; ++ u32 src_addr, dst_addr; ++ u32 security = SRC_SECU_DST_SECU; ++ ++ spi_dbg("%s: enter\n", __func__); ++ spi_hw_conf.xfer_type.src_data_width = DATA_WIDTH_8BIT; ++ spi_hw_conf.xfer_type.src_bst_len = DATA_BRST_1; ++ spi_hw_conf.xfer_type.dst_data_width = DATA_WIDTH_8BIT; ++ spi_hw_conf.xfer_type.dst_bst_len = DATA_BRST_1; ++ spi_hw_conf.bconti_mode = false; ++ spi_hw_conf.irq_spt = CHAN_IRQ_FD; ++ switch (aw_spi->dma_type) { ++ case CHAN_NORMAL: ++ if (SPI_DMA_RDEV == dma_dir) { ++ spi_hw_conf.address_type.src_addr_mode = NDMA_ADDR_NOCHANGE; ++ spi_hw_conf.address_type.dst_addr_mode = NDMA_ADDR_INCREMENT; ++ spi_hw_conf.src_drq_type = spi_rx_ndrq[bus_num]; ++ spi_hw_conf.dst_drq_type = N_DST_SDRAM; ++ } else if (SPI_DMA_WDEV == dma_dir) { ++ spi_hw_conf.address_type.src_addr_mode = NDMA_ADDR_INCREMENT; ++ spi_hw_conf.address_type.dst_addr_mode = NDMA_ADDR_NOCHANGE; ++ spi_hw_conf.src_drq_type = N_SRC_SDRAM; ++ spi_hw_conf.dst_drq_type = spi_tx_ndrq[bus_num]; ++ } else { ++ return -1; ++ } ++ break; ++ ++ case CHAN_DEDICATE: ++ if (SPI_DMA_RDEV == dma_dir) { ++ spi_hw_conf.address_type.src_addr_mode = DDMA_ADDR_IO; ++ spi_hw_conf.address_type.dst_addr_mode = DDMA_ADDR_LINEAR; ++ spi_hw_conf.src_drq_type = spi_rx_ddrq[bus_num]; ++ spi_hw_conf.dst_drq_type = D_DST_SDRAM; ++ } else if (SPI_DMA_WDEV == dma_dir) { ++ spi_hw_conf.address_type.src_addr_mode = DDMA_ADDR_LINEAR; ++ spi_hw_conf.address_type.dst_addr_mode = DDMA_ADDR_IO; ++ spi_hw_conf.src_drq_type = D_SRC_SDRAM; ++ spi_hw_conf.dst_drq_type = spi_tx_ddrq[bus_num]; ++ } else { ++ return -1; ++ } ++ break; ++ } ++ ++ if (SPI_DMA_RDEV == dma_dir) { ++ dma_hdle = aw_spi->dma_hdle_rx; ++ src_addr = spi_phyaddr[bus_num] + SPI_RXDATA_REG; ++ dst_addr = virt_to_phys(buf); ++ } else if (SPI_DMA_WDEV == dma_dir) { ++ dma_hdle = aw_spi->dma_hdle_tx; ++ src_addr = virt_to_phys(buf); ++ dst_addr = spi_phyaddr[bus_num] + SPI_TXDATA_REG; ++ } else { ++ return -1; ++ } ++ ++ /* set src, dst, drq type, configuration */ ++ if (sw_dma_config(dma_hdle, &spi_hw_conf)) { ++ spi_err("%s: spi%d config failed\n", __func__, bus_num); ++ return -1; ++ } ++ ++ if (sw_dma_ctl(dma_hdle, DMA_OP_SET_SECURITY, &security)) { ++ spi_err("%s: spi%d set dma SRC_SECU_DST_SECU failed\n", __func__, ++ bus_num); ++ return -1; ++ } ++ ++ if (CHAN_DEDICATE == aw_spi->dma_type) { ++ dma_para_t para = { ++ .src_wait_cyc = 0x07, ++ .src_blk_sz = 0x1f, ++ .dst_wait_cyc = 0x07, ++ .dst_blk_sz = 0x1f ++ }; ++ ++ if (sw_dma_ctl(dma_hdle, DMA_OP_SET_PARA_REG, ¶)) { ++ spi_err("%s: spi%d set dma para failed\n", __func__, bus_num); ++ return -1; ++ } ++ } ++ ++ /* 1. flush d-cache */ ++ sun7i_spi_cleanflush_dcache_region((void *)buf, len); ++ ++ /* 2. enqueue dma transfer */ ++ return sw_dma_enqueue(dma_hdle, src_addr, dst_addr, len); ++} ++ ++/* set dma start flag, if queue, it will auto restart to transfer next queue */ ++static int sun7i_spi_start_dma(struct sun7i_spi *aw_spi, enum spi_dma_dir dma_dir) ++{ ++ int ret = 0; ++ ++ spi_dbg("%s: enter\n", __func__); ++ if (SPI_DMA_RDEV == dma_dir) { ++ ret = sw_dma_ctl(aw_spi->dma_hdle_rx, DMA_OP_START, NULL); ++ } else if (SPI_DMA_WDEV == dma_dir) { ++ ret = sw_dma_ctl(aw_spi->dma_hdle_tx, DMA_OP_START, NULL); ++ } else { ++ return -1; ++ } ++ ++ return ret; ++} ++ ++/* release dma channel, and set queue status to idle. */ ++static int sun7i_spi_release_dma(struct sun7i_spi *aw_spi, enum spi_dma_dir dma_dir) ++{ ++ int ret = 0; ++ unsigned long flags; ++ ++ spi_dbg("%s: enter\n", __func__); ++ if (SPI_DMA_RDEV == dma_dir) { ++ spin_lock_irqsave(&aw_spi->lock, flags); ++ ret = sw_dma_ctl(aw_spi->dma_hdle_rx, DMA_OP_STOP, NULL); ++ ret += sw_dma_release(aw_spi->dma_hdle_rx); ++ aw_spi->dma_hdle_rx = NULL; ++ spin_unlock_irqrestore(&aw_spi->lock, flags); ++ } else if (SPI_DMA_WDEV == dma_dir) { ++ spin_lock_irqsave(&aw_spi->lock, flags); ++ ret = sw_dma_ctl(aw_spi->dma_hdle_tx, DMA_OP_STOP, NULL); ++ ret += sw_dma_release(aw_spi->dma_hdle_tx); ++ aw_spi->dma_hdle_tx = NULL; ++ spin_unlock_irqrestore(&aw_spi->lock, flags); ++ } else { ++ return -1; ++ } ++ ++ return ret; ++} ++ ++/* check the valid of cs id */ ++static int sun7i_spi_check_cs(int cs_id, struct sun7i_spi *aw_spi) ++{ ++ int ret = -1; ++ switch (cs_id) { ++ case 0: ++ ret = (aw_spi->cs_bitmap & SPI_CHIP_SELECT_CS0) ? 0 : -1; ++ break; ++ case 1: ++ ret = (aw_spi->cs_bitmap & SPI_CHIP_SELECT_CS1) ? 0 : -1; ++ break; ++ default: ++ spi_err("%s: spi%d chip select not support, cs = %d\n", ++ __func__, aw_spi->master->bus_num, cs_id); ++ break; ++ } ++ ++ return ret; ++} ++ ++/* spi device on or off control */ ++static void sun7i_spi_cs_control(struct spi_device *spi, bool on) ++{ ++ struct sun7i_spi *aw_spi = spi_master_get_devdata(spi->master); ++ unsigned int cs = 0; ++ if (aw_spi->cs_control) { ++ if (on) { ++ /* set active */ ++ cs = (spi->mode & SPI_CS_HIGH) ? 1 : 0; ++ } else { ++ /* set inactive */ ++ cs = (spi->mode & SPI_CS_HIGH) ? 0 : 1; ++ } ++ spi_ss_level(aw_spi->base_addr, cs); ++ } ++} ++ ++/* ++ * change the properties of spi device with spi transfer. ++ * every spi transfer must call this interface to update the master to the excute transfer ++ * set clock frequecy, bits per word, mode etc... ++ * return: >= 0 : succeed; < 0: failed. ++ */ ++static int sun7i_spi_xfer_setup(struct spi_device *spi, struct spi_transfer *t) ++{ ++ /* get at the setup function, the properties of spi device */ ++ struct sun7i_spi *aw_spi = spi_master_get_devdata(spi->master); ++ struct sun7i_spi_config *config = spi->controller_data; // allocate in the setup, and free in the cleanup ++ void *__iomem base_addr = aw_spi->base_addr; ++ ++ spi_dbg("%s: enter\n", __func__); ++ config->max_speed_hz = (t && t->speed_hz) ? t->speed_hz : spi->max_speed_hz; ++ config->bits_per_word = (t && t->bits_per_word) ? t->bits_per_word : spi->bits_per_word; ++ config->bits_per_word = ((config->bits_per_word + 7) / 8) * 8; ++ ++ if (config->bits_per_word != 8) { ++ spi_err("%s: spi%d just support 8bits per word\n", __func__, spi->master->bus_num); ++ return -EINVAL; ++ } ++ ++ if (spi->chip_select >= spi->master->num_chipselect) { ++ spi_err("%s: spi%d device's chip select = %d exceeds the master supported cs_num[%d] \n", ++ __func__, spi->master->bus_num, spi->chip_select, spi->master->num_chipselect); ++ return -EINVAL; ++ } ++ ++ /* check again board info */ ++ if (sun7i_spi_check_cs(spi->chip_select, aw_spi)) { ++ spi_err("%s: sun7i_spi_check_cs failed, spi_device cs =%d\n", __func__, spi->chip_select); ++ return -EINVAL; ++ } ++ ++ /* set cs */ ++ spi_set_cs(spi->chip_select, base_addr); ++ /* ++ * master: set spi module clock; ++ * set the default frequency 10MHz ++ */ ++ spi_set_master(base_addr); ++ if (config->max_speed_hz > SPI_MAX_FREQUENCY) { ++ return -EINVAL; ++ } ++ ++#ifndef CONFIG_AW_FPGA_PLATFORM ++ spi_set_clk(config->max_speed_hz, clk_get_rate(aw_spi->mclk), base_addr); ++#else ++ spi_set_clk(config->max_speed_hz, 24000000, base_addr); ++#endif ++ ++ /* ++ * master : set POL,PHA,SSOPL,LMTF,DDB,DHB; default: SSCTL=0,SMC=1,TBW=0. ++ * set bit width-default: 8 bits ++ */ ++ spi_config(1, spi->mode, base_addr); ++ ++ return 0; ++} ++ ++/* ++ * <= 64 : cpu ; > 64 : dma ++ * wait for done completion in this function, wakup in the irq hanlder ++ */ ++static int sun7i_spi_xfer(struct spi_device *spi, struct spi_transfer *t) ++{ ++ struct sun7i_spi *aw_spi = spi_master_get_devdata(spi->master); ++ void __iomem *base_addr = aw_spi->base_addr; ++ unsigned long flags = 0; ++ unsigned tx_len = t->len; ++ unsigned rx_len = t->len; ++ unsigned char *rx_buf = (unsigned char *)t->rx_buf; ++ unsigned char *tx_buf = (unsigned char *)t->tx_buf; ++ enum spi_dma_dir dma_dir = SPI_DMA_NULL; ++ int ret = 0; ++ ++ spi_dbg("%s: spi%d begin transfer, txbuf %p, rxbuf %p, len %d\n", ++ __func__, spi->master->bus_num, tx_buf, rx_buf, t->len); ++ ++ if ((!t->tx_buf && !t->rx_buf) || !t->len) { ++ spi_err("%s: spi%d invalid buffer or len\n", __func__, spi->master->bus_num); ++ return -EINVAL; ++ } ++ ++ /* write 1 to clear 0 */ ++ spi_clr_irq_pending(SPI_STAT_MASK, base_addr); ++ /* disable all DRQ */ ++ spi_disable_dma_irq(SPI_DRQEN_MASK, base_addr); ++ /* reset tx/rx fifo */ ++ spi_reset_fifo(base_addr); ++ ++ if (aw_spi->duplex_flag != DUPLEX_NULL) { ++ spi_err("%s: spi%d duplex flag not null\n", __func__, spi->master->bus_num); ++ return -EINVAL; ++ } ++ ++ /* set the Burst Counter and Write Transmit Counter, auto put dummy data into the txFIFO! */ ++ /* check if use full duplex or half duplex */ ++ if (tx_buf && rx_buf) { ++ spin_lock_irqsave(&aw_spi->lock, flags); ++ aw_spi->duplex_flag = FULL_DUPLEX_RX_TX; ++ spi_set_bc_wtc(tx_len, 0, base_addr); ++ spin_unlock_irqrestore(&aw_spi->lock, flags); ++ } else { ++ if (tx_buf) { ++ spin_lock_irqsave(&aw_spi->lock, flags); ++ aw_spi->duplex_flag = HALF_DUPLEX_TX; ++ spi_set_bc_wtc(tx_len, 0, base_addr); ++ spin_unlock_irqrestore(&aw_spi->lock, flags); ++ } else if (rx_buf) { ++ spin_lock_irqsave(&aw_spi->lock, flags); ++ aw_spi->duplex_flag = HALF_DUPLEX_RX; ++ spi_set_bc_wtc(0, rx_len, base_addr); ++ spin_unlock_irqrestore(&aw_spi->lock, flags); ++ } ++ } ++ ++ /* ++ * 1. Tx/Rx error irq, process in IRQ; ++ * 2. Transfer Complete Interrupt Enable ++ */ ++ spi_enable_irq(SPI_INTEN_TC | SPI_INTEN_ERR, base_addr); ++ ++ /* > 64 use DMA transfer, or use cpu */ ++ if (t->len > BULK_DATA_BOUNDARY) { ++ spi_sel_dma_type(aw_spi->dma_type, base_addr); ++ ++ switch (aw_spi->duplex_flag) { ++ case HALF_DUPLEX_RX: { ++ spi_enable_dma_irq(SPI_DRQEN_RR, base_addr); ++ ++ dma_dir |= SPI_DMA_RDEV; ++ ret = sun7i_spi_prepare_dma(aw_spi, SPI_DMA_RDEV); ++ if (ret < 0) { ++ spi_disable_dma_irq(SPI_DRQEN_RR, base_addr); ++ spi_disable_irq(SPI_INTEN_TC | SPI_INTEN_ERR, base_addr); ++ return -EINVAL; ++ } ++ ++ sun7i_spi_config_dma(aw_spi, SPI_DMA_RDEV, (void *)rx_buf, rx_len); ++ sun7i_spi_start_dma(aw_spi, SPI_DMA_RDEV); ++ ++ spi_start_xfer(base_addr); ++ break; ++ } ++ ++ case HALF_DUPLEX_TX: { ++ spi_start_xfer(base_addr); ++ spi_enable_dma_irq(SPI_DRQEN_TE, base_addr); ++ ++ dma_dir |= SPI_DMA_WDEV; ++ ret = sun7i_spi_prepare_dma(aw_spi, SPI_DMA_WDEV); ++ if (ret < 0) { ++ spi_disable_irq(SPI_INTEN_TC | SPI_INTEN_ERR, base_addr); ++ spi_disable_dma_irq(SPI_DRQEN_TE, base_addr); ++ return -EINVAL; ++ } ++ ++ sun7i_spi_config_dma(aw_spi, SPI_DMA_WDEV, (void *)tx_buf, tx_len); ++ sun7i_spi_start_dma(aw_spi, SPI_DMA_WDEV); ++ break; ++ } ++ ++ case FULL_DUPLEX_RX_TX: { ++ spi_enable_dma_irq(SPI_DRQEN_RR, base_addr); ++ ++ dma_dir |= SPI_DMA_RDEV; ++ ret = sun7i_spi_prepare_dma(aw_spi, SPI_DMA_RDEV); ++ if (ret < 0) { ++ spi_disable_dma_irq(SPI_DRQEN_RR, base_addr); ++ spi_disable_irq(SPI_INTEN_TC | SPI_INTEN_ERR, base_addr); ++ return -EINVAL; ++ } ++ ++ sun7i_spi_config_dma(aw_spi, SPI_DMA_RDEV, (void *)rx_buf, rx_len); ++ sun7i_spi_start_dma(aw_spi, SPI_DMA_RDEV); ++ ++ spi_start_xfer(base_addr); ++ spi_enable_dma_irq(SPI_DRQEN_TE, base_addr); ++ ++ dma_dir |= SPI_DMA_WDEV; ++ ret = sun7i_spi_prepare_dma(aw_spi, SPI_DMA_WDEV); ++ if (ret < 0) { ++ spi_disable_irq(SPI_INTEN_TC | SPI_INTEN_ERR, base_addr); ++ spi_disable_dma_irq(SPI_DRQEN_TE, base_addr); ++ return -EINVAL; ++ } ++ ++ sun7i_spi_config_dma(aw_spi, SPI_DMA_WDEV, (void *)tx_buf, tx_len); ++ sun7i_spi_start_dma(aw_spi, SPI_DMA_WDEV); ++ break; ++ } ++ ++ default: ++ return -1; ++ } ++ } else { ++ switch (aw_spi->duplex_flag) { ++ case HALF_DUPLEX_RX: { ++ unsigned int poll_time = 0x7ffff; ++ /* SMC=1,XCH trigger the transfer */ ++ spi_start_xfer(base_addr); ++ while (rx_len && (--poll_time > 0)) { ++ /* rxFIFO counter */ ++ if (spi_query_rxfifo(base_addr)) { ++ *rx_buf++ = readb(base_addr + SPI_RXDATA_REG); ++ --rx_len; ++ } ++ } ++ if (poll_time <= 0) { ++ spi_err("%s: spi%d cpu receive data time out\n", ++ __func__, spi->master->bus_num); ++ } ++ break; ++ } ++ case HALF_DUPLEX_TX: { ++ unsigned int poll_time = 0xfffff; ++ spi_start_xfer(base_addr); ++ ++ spin_lock_irqsave(&aw_spi->lock, flags); ++ for (; tx_len > 0; --tx_len) { ++ writeb(*tx_buf++, base_addr + SPI_TXDATA_REG); ++ } ++ spin_unlock_irqrestore(&aw_spi->lock, flags); ++ ++ while (spi_query_txfifo(base_addr) && (--poll_time > 0)); /* txFIFO counter */ ++ if (poll_time <= 0) { ++ spi_err("%s: spi%d cpu transfer data time out\n", ++ __func__, spi->master->bus_num); ++ } ++ break; ++ } ++ case FULL_DUPLEX_RX_TX: { ++ unsigned int poll_time_tx = 0xfffff; ++ unsigned int poll_time_rx = 0x7ffff; ++ ++ if ((rx_len == 0) || (tx_len == 0)) ++ return -EINVAL; ++ ++ spi_start_xfer(base_addr); ++ ++ spin_lock_irqsave(&aw_spi->lock, flags); ++ for (; tx_len > 0; --tx_len) { ++ writeb(*tx_buf++, base_addr + SPI_TXDATA_REG); ++ } ++ spin_unlock_irqrestore(&aw_spi->lock, flags); ++ ++ while (spi_query_txfifo(base_addr) && (--poll_time_tx > 0)); /* txFIFO counter */ ++ if (poll_time_tx <= 0) { ++ spi_err("%s: spi%d cpu transfer data time out\n", ++ __func__, spi->master->bus_num); ++ break; ++ } ++ ++ while (rx_len && (--poll_time_rx > 0)) { ++ /* rxFIFO counter */ ++ if (spi_query_rxfifo(base_addr)) { ++ *rx_buf++ = readb(base_addr + SPI_RXDATA_REG); ++ --rx_len; ++ } ++ } ++ if (poll_time_rx <= 0) { ++ spi_err("%s: spi%d cpu receive data time out\n", ++ __func__, spi->master->bus_num); ++ } ++ break; ++ } ++ default: ++ return -1; ++ } ++ } ++ ++ /* wait for xfer complete in the isr. */ ++ spi_dbg("%s: spi%d wait for xfer complete\n", __func__, spi->master->bus_num); ++ wait_for_completion(&aw_spi->done); ++ /* get the isr return code */ ++ if (aw_spi->result != 0) { ++ spi_err("%s: spi%d xfer failed\n", __func__, spi->master->bus_num); ++ ret = -1; ++ } ++ ++ /* release dma resource if neccessary */ ++ if (SPI_DMA_RDEV & dma_dir) { ++ sun7i_spi_release_dma(aw_spi, SPI_DMA_RDEV); ++ } ++ if (SPI_DMA_WDEV & dma_dir) { ++ sun7i_spi_release_dma(aw_spi, SPI_DMA_WDEV); ++ } ++ ++ if (aw_spi->duplex_flag != DUPLEX_NULL) { ++ aw_spi->duplex_flag = DUPLEX_NULL; ++ } ++ ++ return ret; ++} ++ ++/* spi core xfer process */ ++static void sun7i_spi_work(struct work_struct *work) ++{ ++ struct sun7i_spi *aw_spi = container_of(work, struct sun7i_spi, work); ++ spin_lock_irq(&aw_spi->lock); ++ aw_spi->busy = SPI_BUSY; ++ ++ spi_dbg("%s: enter\n", __func__); ++ /* ++ * get from messages queue, and then do with them, ++ * if message queue is empty ,then return and set status to free, ++ * otherwise process them. ++ */ ++ while (!list_empty(&aw_spi->queue)) { ++ struct spi_message *msg = NULL; ++ struct spi_device *spi = NULL; ++ struct spi_transfer *t = NULL; ++ unsigned int cs_change = 0; ++ int status; ++ /* get message from message queue in sun7i_spi. */ ++ msg = container_of(aw_spi->queue.next, struct spi_message, queue); ++ /* then delete from the message queue,now it is alone.*/ ++ list_del_init(&msg->queue); ++ spin_unlock_irq(&aw_spi->lock); ++ /* get spi device from this message */ ++ spi = msg->spi; ++ /* set default value,no need to change cs,keep select until spi transfer require to change cs. */ ++ cs_change = 1; ++ /* set message status to succeed. */ ++ status = -1; ++ /* search the spi transfer in this message, deal with it alone. */ ++ list_for_each_entry(t, &msg->transfers, transfer_list) { ++ if ((status == -1) || t->bits_per_word || t->speed_hz) { /* if spi transfer is zero,use spi device value. */ ++ status = sun7i_spi_xfer_setup(spi, t); /* set the value every spi transfer */ ++ if (status < 0) ++ break; /* fail, quit */ ++ spi_dbg("[spi-%d]: xfer setup \n", aw_spi->master->bus_num); ++ } ++ ++ /* first active the cs */ ++ if (cs_change) ++ aw_spi->cs_control(spi, 1); ++ /* update the new cs value */ ++ cs_change = t->cs_change; ++ ++ /* full duplex mode */ ++ if (t->rx_buf && t->tx_buf) ++ spi_clear_dhb(aw_spi->base_addr); ++ ++ /* ++ * do transfer ++ * > 64 : dma ; <= 64 : cpu ++ * wait for done completion in this function, wakup in the irq hanlder ++ */ ++ status = sun7i_spi_xfer(spi, t); ++ if (status) ++ break; /* fail quit, zero means succeed */ ++ ++ /* accmulate the value in the message */ ++ msg->actual_length += t->len; ++ /* may be need to delay */ ++ if (t->delay_usecs) ++ udelay(t->delay_usecs); ++ ++ /* if zero, keep active, otherwise deactived. */ ++ if (cs_change) ++ aw_spi->cs_control(spi, 0); ++ } ++ ++ /* ++ * spi message complete,succeed or failed ++ * return value ++ */ ++ msg->status = status; ++ /* wakup the uplayer caller,complete one message */ ++ msg->complete(msg->context); ++ /* fail or need to change cs */ ++ if (status || !cs_change) { ++ aw_spi->cs_control(spi, 0); ++ } ++ ++ /* restore default value. */ ++ //sun7i_spi_xfer_setup(spi, NULL); ++ spin_lock_irq(&aw_spi->lock); ++ } ++ ++ /* set spi to free */ ++ aw_spi->busy = SPI_FREE; ++ spin_unlock_irq(&aw_spi->lock); ++} ++ ++/* wake up the sleep thread, and give the result code */ ++static irqreturn_t sun7i_spi_handler(int irq, void *dev_id) ++{ ++ struct sun7i_spi *aw_spi = (struct sun7i_spi *)dev_id; ++ void *base_addr = aw_spi->base_addr; ++ ++ unsigned int status = spi_qry_irq_pending(base_addr); ++ spi_clr_irq_pending(status, base_addr); ++ ++ aw_spi->result = 0; /* assume succeed */ ++ /* master mode, Transfer Complete Interrupt */ ++ if (status & SPI_STAT_TC) { ++ spi_dbg("%s: spi%d TC comes, irq status = 0x%08x\n", ++ __func__, aw_spi->master->bus_num, status); ++ spi_disable_irq(SPI_STAT_TC | SPI_STAT_ERR, base_addr); ++ /* ++ * just check dma+callback receive, skip other condition. ++ * dma+callback receive: when TC comes, dma may be still not complete fetch data from rxFIFO. ++ * other receive: cpu or dma+poll, just skip this. ++ */ ++ if (aw_spi->dma_hdle_rx) { ++ unsigned int poll_time = 0xffff; ++ /* during poll, dma maybe complete rx, rx_dma_used is 0. then return.*/ ++ while (spi_query_rxfifo(base_addr) && (--poll_time > 0)); ++ if (poll_time <= 0) { ++ spi_err("%s: spi%d dma callback method, rx data time out in irq\n", ++ __func__, aw_spi->master->bus_num); ++ aw_spi->result = -1; ++ complete(&aw_spi->done); ++ return -1; ++ } else if (poll_time < 0xffff) { ++ spi_dbg("%s: spi%d rx irq comes first, dma last. wait = 0x%x\n", ++ __func__, aw_spi->master->bus_num, poll_time); ++ } ++ } ++ ++ /* wakup uplayer, by the sem */ ++ complete(&aw_spi->done); ++ return IRQ_HANDLED; ++ } ++ /* master mode: err */ ++ else if (status & SPI_STAT_ERR) { ++ spi_err("%s: spi%d ERR comes, irq status = 0x%08x\n", ++ __func__, aw_spi->master->bus_num, status); ++ /* error process, release dma in the workqueue,should not be here */ ++ spi_disable_irq(SPI_STAT_TC | SPI_STAT_ERR, base_addr); ++ spi_restore_state(1, base_addr); ++ aw_spi->result = -1; ++ complete(&aw_spi->done); ++ spi_err("%s: spi%d master mode error: txFIFO overflow/rxFIFO underrun or overflow\n", ++ __func__, aw_spi->master->bus_num); ++ return IRQ_HANDLED; ++ } ++ ++ spi_dbg("%s: spi%d NONE comes\n", __func__, aw_spi->master->bus_num); ++ return IRQ_NONE; ++} ++ ++/* interface 1 */ ++static int sun7i_spi_transfer(struct spi_device *spi, struct spi_message *msg) ++{ ++ struct sun7i_spi *aw_spi = spi_master_get_devdata(spi->master); ++ unsigned long flags; ++ msg->actual_length = 0; ++ msg->status = -EINPROGRESS; ++ ++ spi_dbg("%s: enter\n", __func__); ++ spin_lock_irqsave(&aw_spi->lock, flags); ++ /* add msg to the sun7i_spi queue */ ++ list_add_tail(&msg->queue, &aw_spi->queue); ++ /* add work to the workqueue,schedule the cpu. */ ++ queue_work(aw_spi->workqueue, &aw_spi->work); ++ spin_unlock_irqrestore(&aw_spi->lock, flags); ++ ++ /* return immediately and wait for completion in the uplayer caller. */ ++ return 0; ++} ++ ++/* interface 2, setup the frequency and default status */ ++static int sun7i_spi_setup(struct spi_device *spi) ++{ ++ struct sun7i_spi *aw_spi = spi_master_get_devdata(spi->master); ++ struct sun7i_spi_config *config = spi->controller_data; /* general is null. */ ++ unsigned long flags; ++ ++ spi_dbg("%s: enter\n", __func__); ++ /* just support 8 bits per word */ ++ if (spi->bits_per_word != 8) ++ return -EINVAL; ++ /* first check its valid,then set it as default select,finally set its */ ++ if (sun7i_spi_check_cs(spi->chip_select, aw_spi)) { ++ spi_err("%s: spi%d not support cs-%d \n", __func__, ++ spi->master->bus_num, spi->chip_select); ++ return -EINVAL; ++ } ++ ++ if (spi->max_speed_hz > SPI_MAX_FREQUENCY) ++ return -EINVAL; ++ ++ if (!config) { ++ config = kzalloc(sizeof * config, GFP_KERNEL); ++ if (!config) { ++ spi_err("%s: spi%d alloc memory for config failed\n", ++ __func__, spi->master->bus_num); ++ return -ENOMEM; ++ } ++ spi->controller_data = config; ++ } ++ ++ /* ++ * set the default vaule with spi device ++ * can change by every spi transfer ++ */ ++ config->bits_per_word = spi->bits_per_word; ++ config->max_speed_hz = spi->max_speed_hz; ++ config->mode = spi->mode; ++ ++ spin_lock_irqsave(&aw_spi->lock, flags); ++ /* if aw16xx spi is free, then deactived the spi device */ ++ if (aw_spi->busy & SPI_FREE) { ++ /* set chip select number */ ++ spi_set_cs(spi->chip_select, aw_spi->base_addr); ++ /* deactivate chip select */ ++ aw_spi->cs_control(spi, 0); ++ } ++ spin_unlock_irqrestore(&aw_spi->lock, flags); ++ ++ return 0; ++} ++ ++/* interface 3 */ ++static void sun7i_spi_cleanup(struct spi_device *spi) ++{ ++ if (spi->controller_data) { ++ kfree(spi->controller_data); ++ spi->controller_data = NULL; ++ } ++} ++ ++static int sun7i_spi_set_gpio(struct sun7i_spi *aw_spi, bool on) ++{ ++ if(on) { ++ if(aw_spi->master->bus_num == 0) { ++ aw_spi->gpio_hdle = gpio_request_ex("spi0_para", NULL); ++ if(!aw_spi->gpio_hdle) { ++ spi_err("spi0 request gpio fail!\n"); ++ return -1; ++ } ++ //hex_dump("gpio regs:", (void __iomem*)SW_VA_PORTC_IO_BASE, 0x200, 2); ++ } ++ else if(aw_spi->master->bus_num == 1) { ++ /** ++ * PI8 SPI1_CS0 ++ * PI9 SPI1_CS1 ++ * PI10 SPI1_CLK ++ * PI11 SPI1_MOSI ++ * PI12 SPI1_MISO ++ */ ++ #ifndef SYS_SPI_PIN ++ unsigned int reg_val = readl(_Pn_CFG1(8)); ++ /* set spi function */ ++ reg_val &= ~0x77777; ++ reg_val |= 0x22222; ++ writel(reg_val, _Pn_CFG1(8)); ++ /* set pull up */ ++ reg_val = readl(_Pn_PUL1(8)); ++ reg_val &= ~(0x3ff<<16); ++ reg_val |= (0x155<<16); ++ writel(reg_val, _Pn_PUL1(8)); ++ /* no need to set driver,default is driver 1. */ ++ #else ++ aw_spi->gpio_hdle = gpio_request_ex("spi1_para", NULL); ++ if(!aw_spi->gpio_hdle) { ++ spi_err("spi1 request gpio fail!\n"); ++ return -1; ++ } ++ #endif ++ } ++ else if(aw_spi->master->bus_num == 2) { ++ aw_spi->gpio_hdle = gpio_request_ex("spi2_para", NULL); ++ if(!aw_spi->gpio_hdle) { ++ spi_err("spi2 request gpio fail!\n"); ++ return -1; ++ } ++ } ++ ++ #ifdef AW1623_FPGA ++ { ++ #include ++ void __iomem* pi_cfg0 = (void __iomem*)(SW_VA_PORTC_IO_BASE+0x48); ++ u32 rval = readl(pi_cfg0) & (~(0x70777)); ++ writel(rval|(0x30333), pi_cfg0); ++ } ++ #endif ++ } ++ else { ++ if(aw_spi->master->bus_num == 0) { ++ gpio_release(aw_spi->gpio_hdle, 0); ++ } ++ else if(aw_spi->master->bus_num == 1) { ++ #ifndef SYS_SPI_PIN ++ unsigned int reg_val = readl(_Pn_CFG1(8)); ++ /* set default */ ++ reg_val &= ~0x77777; ++ writel(reg_val, _Pn_CFG1(8)); ++ #else ++ gpio_release(aw_spi->gpio_hdle, 0); ++ #endif ++ } ++ else if(aw_spi->master->bus_num == 2) { ++ gpio_release(aw_spi->gpio_hdle, 0); ++ } ++ } ++ return 0; ++} ++ ++static int sun7i_spi_set_mclk(struct sun7i_spi *aw_spi, u32 mod_clk) ++{ ++ struct clk *source_clock = NULL; ++ char *name = NULL; ++#ifdef CONFIG_AW_FPGA_PLATFORM ++// u32 source = 0; ++#elif defined CONFIG_AW_ASIC_PLATFORM ++// u32 source = 2; ++#endif ++ u32 source = 1; ++ int ret = 0; ++ ++ switch (source) { ++ case 0: ++ source_clock = clk_get(NULL, "hosc"); ++ name = "hosc"; ++ break; ++ case 1: ++ source_clock = clk_get(NULL, "sdram_pll_p"); ++ name = "sdram_pll_p"; ++ break; ++ case 2: ++ source_clock = clk_get(NULL, "sata_pll"); ++ name = "sata_pll"; ++ break; ++ default: ++ return -1; ++ } ++ ++ if (IS_ERR(source_clock)) { ++ ret = PTR_ERR(source_clock); ++ spi_err("%s: Unable to get spi%d source clock resource\n", ++ __func__, aw_spi->master->bus_num); ++ return -1; ++ } ++ ++ if (clk_set_parent(aw_spi->mclk, source_clock)) { ++ spi_err("%s: spi%d clk_set_parent failed\n", __func__, ++ aw_spi->master->bus_num); ++ ret = -1; ++ goto out; ++ } ++ ++ if (clk_set_rate(aw_spi->mclk, mod_clk)) { ++ spi_err("%s: spi%d clk_set_rate failed\n", __func__, ++ aw_spi->master->bus_num); ++ ret = -1; ++ goto out; ++ } ++ ++ spi_inf("%s: spi%d source = %s, src_clk = %u, mclk %u\n", ++ __func__, aw_spi->master->bus_num, name, ++ (unsigned)clk_get_rate(source_clock), (unsigned)clk_get_rate(aw_spi->mclk)); ++ ++ if (clk_enable(aw_spi->mclk)) { ++ spi_err("%s: spi%d couldn't enable module clock 'spi'\n", ++ __func__, aw_spi->master->bus_num); ++ ret = -EBUSY; ++ goto out; ++ } ++ ++ ret = 0; ++out: ++ clk_put(source_clock); ++ return ret; ++} ++ ++static int sun7i_spi_hw_init(struct sun7i_spi *aw_spi) ++{ ++ void *base_addr = aw_spi->base_addr; ++ unsigned long sclk_freq = 0; ++ char *mclk_name[] = {"spi0", "spi1", "spi2", "spi3"}; ++ ++ aw_spi->mclk = clk_get(&aw_spi->pdev->dev, mclk_name[aw_spi->pdev->id]); ++ if (IS_ERR(aw_spi->mclk)) { ++ spi_err("%s: spi%d unable to acquire module clock 'spi'\n", ++ __func__, aw_spi->master->bus_num); ++ return -1; ++ } ++ if (sun7i_spi_set_mclk(aw_spi, 100000000)) { ++ spi_err("%s: spi%d sun7i_spi_set_mclk 'spi'\n", ++ __func__, aw_spi->master->bus_num); ++ clk_put(aw_spi->mclk); ++ return -1; ++ } ++ ++ /* 1. enable the spi module */ ++ spi_enable_bus(base_addr); ++ ++ /* 2. set the default chip select */ ++ if (sun7i_spi_check_cs(0, aw_spi)) { ++ spi_set_cs(1, base_addr); ++ } else { ++ spi_set_cs(0, base_addr); ++ } ++ ++ /* ++ * 3. master: set spi module clock; ++ * 4. set the default frequency 10MHz ++ */ ++ spi_set_master(base_addr); ++ sclk_freq = clk_get_rate(aw_spi->mclk); ++ spi_set_clk(10000000, sclk_freq, base_addr); ++ ++ /* ++ * 5. master : set POL,PHA,SSOPL,LMTF,DDB,DHB; default: SSCTL=0,SMC=1,TBW=0. ++ * 6. set bit width-default: 8 bits ++ */ ++ spi_config(1, SPI_MODE_0, base_addr); ++ ++ /* 7. manual control the chip select */ ++ spi_ss_ctrl(base_addr, 1); ++ return 0; ++} ++ ++static int sun7i_spi_hw_exit(struct sun7i_spi *aw_spi) ++{ ++ /* disable the spi controller */ ++ spi_disable_bus(aw_spi->base_addr); ++ /* disable module clock */ ++ clk_disable(aw_spi->mclk); ++ clk_put(aw_spi->mclk); ++ ++ return 0; ++} ++ ++static int __init sun7i_spi_probe(struct platform_device *pdev) ++{ ++ struct resource *mem_res, *dma_res_rx, *dma_res_tx; ++ struct sun7i_spi *aw_spi; ++ struct sun7i_spi_platform_data *pdata; ++ struct spi_master *master; ++ int ret = 0, err = 0, irq; ++ int cs_bitmap = 0; ++ ++ if (pdev->id < 0) { ++ spi_err("%s: invalid platform device id: %d\n", __func__, pdev->id); ++ return -ENODEV; ++ } ++ ++ if (pdev->dev.platform_data == NULL) { ++ spi_err("%s: platform_data missing\n", __func__); ++ return -ENODEV; ++ } ++ ++ pdata = pdev->dev.platform_data; ++ if (!pdata->clk_name) { ++ spi_err("%s: platform data must initialize\n", __func__); ++ return -EINVAL; ++ } ++ ++ /* Check for availability of necessary resource */ ++ dma_res_rx = platform_get_resource(pdev, IORESOURCE_DMA, 0); ++ if (dma_res_rx == NULL) { ++ spi_err("%s: Unable to get spi DMA RX resource\n", __func__); ++ return -ENXIO; ++ } ++ ++ dma_res_tx = platform_get_resource(pdev, IORESOURCE_DMA, 1); ++ if (dma_res_tx == NULL) { ++ spi_err("%s: Unable to get spi DMA TX resource\n", __func__); ++ return -ENXIO; ++ } ++ ++ mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (mem_res == NULL) { ++ spi_err("%s: Unable to get spi MEM resource\n", __func__); ++ return -ENXIO; ++ } ++ ++ irq = platform_get_irq(pdev, 0); ++ if (irq < 0) { ++ spi_err("%s: NO SPI IRQ specified\n", __func__); ++ return -ENXIO; ++ } ++ ++ /* create spi master */ ++ master = spi_alloc_master(&pdev->dev, sizeof(struct sun7i_spi)); ++ if (master == NULL) { ++ spi_err("%s: Unable to allocate SPI Master\n", __func__); ++ return -ENOMEM; ++ } ++ ++ platform_set_drvdata(pdev, master); ++ aw_spi = spi_master_get_devdata(master); ++ memset(aw_spi, 0, sizeof(struct sun7i_spi)); ++ ++ aw_spi->master = master; ++ aw_spi->irq = irq; ++#ifdef CONFIG_SUN7I_SPI_NDMA ++ aw_spi->dma_type = CHAN_NORMAL; ++#else ++ aw_spi->dma_type = CHAN_DEDICATE; ++#endif ++ spi_inf("%s: spi%d dma type: %s\n", __func__, pdev->id, ++ aw_spi->dma_type == CHAN_NORMAL ? "normal" : "dedicate"); ++ aw_spi->dma_id_tx = dma_res_tx->start; ++ aw_spi->dma_id_rx = dma_res_rx->start; ++ aw_spi->dma_hdle_rx = 0; ++ aw_spi->dma_hdle_tx = 0; ++ aw_spi->cs_control = sun7i_spi_cs_control; ++ aw_spi->cs_bitmap = pdata->cs_bitmap; /* cs0-0x1; cs1-0x2; cs0&cs1-0x3. */ ++ aw_spi->busy = SPI_FREE; ++ aw_spi->duplex_flag = DUPLEX_NULL; ++ ++ master->bus_num = pdev->id; ++ master->setup = sun7i_spi_setup; ++ master->cleanup = sun7i_spi_cleanup; ++ master->transfer = sun7i_spi_transfer; ++ master->num_chipselect = pdata->num_cs; ++ /* the spi->mode bits understood by this driver: */ ++ master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST; ++ ++ /* update the cs bitmap */ ++ cs_bitmap = sun7i_spi_get_cfg_csbitmap(pdev->id); ++ if (cs_bitmap & 0x3) { ++ aw_spi->cs_bitmap = cs_bitmap & 0x3; ++ spi_inf("%s: spi%d cs bitmap: 0x%x\n", ++ __func__, master->bus_num, cs_bitmap); ++ } ++ ++ err = request_irq(aw_spi->irq, sun7i_spi_handler, IRQF_DISABLED, pdev->name, aw_spi); ++ if (err) { ++ spi_err("%s: Cannot claim IRQ\n", __func__); ++ goto err0; ++ } ++ ++ if (request_mem_region(mem_res->start, ++ resource_size(mem_res), pdev->name) == NULL) { ++ spi_err("%s: Req mem region failed\n", __func__); ++ ret = -ENXIO; ++ goto err1; ++ } ++ ++ aw_spi->base_addr = ioremap(mem_res->start, resource_size(mem_res)); ++ if (aw_spi->base_addr == NULL) { ++ spi_err("%s: Unable to remap IO\n", __func__); ++ ret = -ENXIO; ++ goto err2; ++ } ++ ++ /* Setup clocks */ ++ aw_spi->hclk = clk_get(&pdev->dev, pdata->clk_name); ++ if (IS_ERR(aw_spi->hclk)) { ++ spi_err("%s: Unable to get clock 'spi'\n", __func__); ++ ret = PTR_ERR(aw_spi->hclk); ++ goto err3; ++ } ++ ++ if (clk_enable(aw_spi->hclk)) { ++ spi_err("%s: Couldn't enable clock 'spi'\n", __func__); ++ ret = -EBUSY; ++ goto err4; ++ } ++ ++ aw_spi->workqueue = create_singlethread_workqueue(dev_name(master->dev.parent)); ++ if (aw_spi->workqueue == NULL) { ++ spi_err("%s: Unable to create workqueue\n", __func__); ++ ret = -ENOMEM; ++ goto err5; ++ } ++ ++ aw_spi->pdev = pdev; ++ ++ /* Setup Deufult Mode */ ++ sun7i_spi_hw_init(aw_spi); ++ ++#ifndef SYS_SPI_PIN ++ /* set gpio */ ++ gpio_addr = ioremap(_PIO_BASE_ADDRESS, 0x1000); ++#endif ++ sun7i_spi_set_gpio(aw_spi, 1); ++ ++ spin_lock_init(&aw_spi->lock); ++ init_completion(&aw_spi->done); ++ INIT_WORK(&aw_spi->work, sun7i_spi_work); /* banding the process handler */ ++ INIT_LIST_HEAD(&aw_spi->queue); ++ ++ if (spi_register_master(master)) { ++ spi_err("%s: Cannot register SPI master\n", __func__); ++ ret = -EBUSY; ++ goto err6; ++ } ++ ++ spi_inf("%s: reuuimlla's SoC SPI Driver loaded for Bus SPI%d with %d Slaves at most\n", ++ __func__, pdev->id, master->num_chipselect); ++ spi_inf("%s: spi%d driver probe succeed, base %p, irq %d, dma_id_rx %d, dma_id_tx %d\n", ++ __func__, master->bus_num, aw_spi->base_addr, aw_spi->irq, ++ aw_spi->dma_id_rx, aw_spi->dma_id_tx); ++ return 0; ++ ++err6: ++ destroy_workqueue(aw_spi->workqueue); ++err5: ++ iounmap((void *)aw_spi->base_addr); ++err4: ++err3: ++err2: ++ release_mem_region(mem_res->start, resource_size(mem_res)); ++err1: ++ free_irq(aw_spi->irq, aw_spi); ++err0: ++ platform_set_drvdata(pdev, NULL); ++ spi_master_put(master); ++ return ret; ++} ++ ++static int sun7i_spi_remove(struct platform_device *pdev) ++{ ++ struct spi_master *master = spi_master_get(platform_get_drvdata(pdev)); ++ struct sun7i_spi *aw_spi = spi_master_get_devdata(master); ++ struct resource *mem_res; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&aw_spi->lock, flags); ++ aw_spi->busy |= SPI_FREE; ++ spin_unlock_irqrestore(&aw_spi->lock, flags); ++ ++ while (aw_spi->busy & SPI_BUSY) { ++ spi_inf("%s: spi%d busy\n", __func__, master->bus_num); ++ msleep(10); ++ } ++ ++ sun7i_spi_hw_exit(aw_spi); ++ spi_unregister_master(master); ++ destroy_workqueue(aw_spi->workqueue); ++ ++ clk_disable(aw_spi->hclk); ++ clk_put(aw_spi->hclk); ++ ++ iounmap((void *) aw_spi->base_addr); ++ mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (mem_res != NULL) ++ release_mem_region(mem_res->start, resource_size(mem_res)); ++ ++ platform_set_drvdata(pdev, NULL); ++ spi_master_put(master); ++ ++ return 0; ++} ++ ++#ifdef CONFIG_PM ++static int sun7i_spi_suspend(struct platform_device *pdev, pm_message_t state) ++{ ++ struct spi_master *master = spi_master_get(platform_get_drvdata(pdev)); ++ struct sun7i_spi *aw_spi = spi_master_get_devdata(master); ++ unsigned long flags; ++ ++ spin_lock_irqsave(&aw_spi->lock, flags); ++ aw_spi->busy |= SPI_SUSPND; ++ spin_unlock_irqrestore(&aw_spi->lock, flags); ++ ++ while (aw_spi->busy & SPI_BUSY) { ++ spi_inf("%s: spi%d busy\n", __func__, master->bus_num); ++ msleep(10); ++ } ++ ++ /* Disable the clock */ ++ clk_disable(aw_spi->hclk); ++ ++ spi_inf("%s: spi%d suspend okay...\n", __func__, master->bus_num); ++ return 0; ++} ++ ++static int sun7i_spi_resume(struct platform_device *pdev) ++{ ++ struct spi_master *master = spi_master_get(platform_get_drvdata(pdev)); ++ struct sun7i_spi *aw_spi = spi_master_get_devdata(master); ++ unsigned long flags; ++ ++ /* Enable the clock */ ++ clk_enable(aw_spi->hclk); ++ sun7i_spi_hw_init(aw_spi); ++ ++ spin_lock_irqsave(&aw_spi->lock, flags); ++ aw_spi->busy = SPI_FREE; ++ spin_unlock_irqrestore(&aw_spi->lock, flags); ++ ++ spi_inf("%s: spi%d resume okay...\n", __func__, master->bus_num); ++ return 0; ++} ++#else ++#define sun7i_spi_suspend NULL ++#define sun7i_spi_resume NULL ++#endif /* CONFIG_PM */ ++ ++static struct platform_driver sun7i_spi_driver = { ++ .probe = sun7i_spi_probe, ++ .remove = sun7i_spi_remove, ++ .suspend = sun7i_spi_suspend, ++ .resume = sun7i_spi_resume, ++ .driver = { ++ .name = "sun7i-spi", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++/* spi resouce and platform data start */ ++struct sun7i_spi_platform_data sun7i_spi0_pdata = { ++ .cs_bitmap = 0x3, ++ .num_cs = 2, ++ .clk_name = "ahb_spi0", ++}; ++ ++static struct resource sun7i_spi0_resources[] = { ++ [0] = { ++ .start = SPI0_BASE_ADDR, ++ .end = SPI0_BASE_ADDR + 1024, ++ .flags = IORESOURCE_MEM, ++ }, ++#ifdef CONFIG_SUN7I_SPI_NDMA ++ [1] = { ++ .start = N_SRC_SPI0_RX, ++ .end = N_SRC_SPI0_RX, ++ .flags = IORESOURCE_DMA, ++ }, ++ [2] = { ++ .start = N_DST_SPI0_TX, ++ .end = N_DST_SPI0_TX, ++ .flags = IORESOURCE_DMA, ++ }, ++#else ++ [1] = { ++ .start = D_SRC_SPI0_RX, ++ .end = D_SRC_SPI0_RX, ++ .flags = IORESOURCE_DMA, ++ }, ++ [2] = { ++ .start = D_DST_SPI0_TX, ++ .end = D_DST_SPI0_TX, ++ .flags = IORESOURCE_DMA, ++ }, ++#endif ++ [3] = { ++ .start = SW_INT_IRQNO_SPI00, ++ .end = SW_INT_IRQNO_SPI00, ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++static struct platform_device sun7i_spi0_device = { ++ .name = "sun7i-spi", ++ .id = 0, ++ .num_resources = ARRAY_SIZE(sun7i_spi0_resources), ++ .resource = sun7i_spi0_resources, ++ .dev = { ++ .platform_data = &sun7i_spi0_pdata, ++ }, ++}; ++ ++struct sun7i_spi_platform_data sun7i_spi1_pdata = { ++ .cs_bitmap = 0x3, ++ .num_cs = 2, ++ .clk_name = "ahb_spi1", ++}; ++ ++static struct resource sun7i_spi1_resources[] = { ++ [0] = { ++ .start = SPI1_BASE_ADDR, ++ .end = SPI1_BASE_ADDR + 1024, ++ .flags = IORESOURCE_MEM, ++ }, ++#ifdef CONFIG_SUN7I_SPI_NDMA ++ [1] = { ++ .start = N_SRC_SPI1_RX, ++ .end = N_SRC_SPI1_RX, ++ .flags = IORESOURCE_DMA, ++ }, ++ [2] = { ++ .start = N_DST_SPI1_TX, ++ .end = N_DST_SPI1_TX, ++ .flags = IORESOURCE_DMA, ++ }, ++#else ++ [1] = { ++ .start = D_SRC_SPI1_RX, ++ .end = D_SRC_SPI1_RX, ++ .flags = IORESOURCE_DMA, ++ }, ++ [2] = { ++ .start = N_DST_SPI1_TX, ++ .end = N_DST_SPI1_TX, ++ .flags = IORESOURCE_DMA, ++ }, ++#endif ++ [3] = { ++ .start = SW_INT_IRQNO_SPI01, ++ .end = SW_INT_IRQNO_SPI01, ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++static struct platform_device sun7i_spi1_device = { ++ .name = "sun7i-spi", ++ .id = 1, ++ .num_resources = ARRAY_SIZE(sun7i_spi1_resources), ++ .resource = sun7i_spi1_resources, ++ .dev = { ++ .platform_data = &sun7i_spi1_pdata, ++ }, ++}; ++ ++static struct resource sun7i_spi2_resources[] = { ++ [0] = { ++ .start = SPI2_BASE_ADDR, ++ .end = SPI2_BASE_ADDR + 1024, ++ .flags = IORESOURCE_MEM, ++ }, ++#ifdef CONFIG_SUN7I_SPI_NDMA ++ [1] = { ++ .start = N_SRC_SPI2_RX, ++ .end = N_SRC_SPI2_RX, ++ .flags = IORESOURCE_DMA, ++ }, ++ [2] = { ++ .start = N_DST_SPI2_TX, ++ .end = N_DST_SPI2_TX, ++ .flags = IORESOURCE_DMA, ++ }, ++#else ++ [1] = { ++ .start = D_SRC_SPI2_RX, ++ .end = D_SRC_SPI2_RX, ++ .flags = IORESOURCE_DMA, ++ }, ++ [2] = { ++ .start = N_DST_SPI2_TX, ++ .end = N_DST_SPI2_TX, ++ .flags = IORESOURCE_DMA, ++ }, ++#endif ++ [3] = { ++ .start = SW_INT_IRQNO_SPI02, ++ .end = SW_INT_IRQNO_SPI02, ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++struct sun7i_spi_platform_data sun7i_spi2_pdata = { ++ .cs_bitmap = 0x3, ++ .num_cs = 2, ++ .clk_name = "ahb_spi2", ++}; ++ ++static struct platform_device sun7i_spi2_device = { ++ .name = "sun7i-spi", ++ .id = 2, ++ .num_resources = ARRAY_SIZE(sun7i_spi2_resources), ++ .resource = sun7i_spi2_resources, ++ .dev = { ++ .platform_data = &sun7i_spi2_pdata, ++ }, ++}; ++ ++static struct resource sun7i_spi3_resources[] = { ++ [0] = { ++ .start = SPI3_BASE_ADDR, ++ .end = SPI3_BASE_ADDR + 1024, ++ .flags = IORESOURCE_MEM, ++ }, ++#ifdef CONFIG_SUN7I_SPI_NDMA ++ [1] = { ++ .start = N_SRC_SPI3_RX, ++ .end = N_SRC_SPI3_RX, ++ .flags = IORESOURCE_DMA, ++ }, ++ [2] = { ++ .start = N_DST_SPI3_TX, ++ .end = N_DST_SPI3_TX, ++ .flags = IORESOURCE_DMA, ++ }, ++#else ++ [1] = { ++ .start = D_SRC_SPI3_RX, ++ .end = D_SRC_SPI3_RX, ++ .flags = IORESOURCE_DMA, ++ }, ++ [2] = { ++ .start = N_DST_SPI3_TX, ++ .end = N_DST_SPI3_TX, ++ .flags = IORESOURCE_DMA, ++ }, ++#endif ++ [3] = { ++ .start = SW_INT_IRQNO_SPI3, ++ .end = SW_INT_IRQNO_SPI3, ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++struct sun7i_spi_platform_data sun7i_spi3_pdata = { ++ .cs_bitmap = 0x3, ++ .num_cs = 2, ++ .clk_name = "ahb_spi3", ++}; ++ ++static struct platform_device sun7i_spi3_device = { ++ .name = "sun7i-spi", ++ .id = 3, ++ .num_resources = ARRAY_SIZE(sun7i_spi3_resources), ++ .resource = sun7i_spi3_resources, ++ .dev = { ++ .platform_data = &sun7i_spi3_pdata, ++ }, ++}; ++ ++static struct spi_board_info *spi_boards = NULL; ++static int sun7i_spi_register_spidev(void) ++{ ++ int spi_dev_num = 0; ++ int ret = 0; ++ int i = 0; ++ unsigned int irq_gpio = 0; ++ char spi_board_name[32] = {0}; ++ struct spi_board_info* board; ++ ++ ret = script_parser_fetch("spi_devices", "spi_dev_num", &spi_dev_num, sizeof(int)); ++ if(ret != SCRIPT_PARSER_OK){ ++ spi_err("Get spi devices number failed\n"); ++ return -1; ++ } ++ spi_inf("Found %d spi devices in config files\n", spi_dev_num); ++ ++ /* alloc spidev board information structure */ ++ spi_boards = (struct spi_board_info*)kzalloc(sizeof(struct spi_board_info) * spi_dev_num, GFP_KERNEL); ++ if (spi_boards == NULL) ++ { ++ spi_err("Alloc spi board information failed \n"); ++ return -1; ++ } ++ ++ spi_inf("%-10s %-16s %-16s %-8s %-4s %-4s\n", "boards num", "modalias", "max_spd_hz", "bus_num", "cs", "mode"); ++ for (i=0; imodalias, sizeof(char*)); ++ if(ret != SCRIPT_PARSER_OK) { ++ spi_err("Get spi devices modalias failed\n"); ++ goto fail; ++ } ++ ret = script_parser_fetch(spi_board_name, "max_speed_hz", (void*)&board->max_speed_hz, sizeof(int)); ++ if(ret != SCRIPT_PARSER_OK) { ++ spi_err("Get spi devices max_speed_hz failed\n"); ++ goto fail; ++ } ++ ret = script_parser_fetch(spi_board_name, "bus_num", (void*)&board->bus_num, sizeof(u16)); ++ if(ret != SCRIPT_PARSER_OK) { ++ spi_err("Get spi devices bus_num failed\n"); ++ goto fail; ++ } ++ ret = script_parser_fetch(spi_board_name, "chip_select", (void*)&board->chip_select, sizeof(u16)); ++ if(ret != SCRIPT_PARSER_OK) { ++ spi_err("Get spi devices chip_select failed\n"); ++ goto fail; ++ } ++ ret = script_parser_fetch(spi_board_name, "mode", (void*)&board->mode, sizeof(u8)); ++ if(ret != SCRIPT_PARSER_OK) { ++ spi_err("Get spi devices mode failed\n"); ++ goto fail; ++ } ++ ret = script_parser_fetch(spi_board_name, "irq_gpio", (void*)&irq_gpio, sizeof(unsigned int)); ++ if (ret != SCRIPT_PARSER_OK) { ++ spi_inf("%s irq gpio not used\n", spi_board_name); ++ board->irq = -1; ++ } else if(gpio_request(irq_gpio, spi_board_name) == 0) ++ board->irq = gpio_to_irq(irq_gpio); ++ /* ++ ret = script_parser_fetch(spi_board_name, "full_duplex", &board->full_duplex, sizeof(int)); ++ if(ret != SCRIPT_PARSER_OK) { ++ spi_err("Get spi devices full_duplex failed\n"); ++ goto fail; ++ } ++ ret = script_parser_fetch(spi_board_name, "manual_cs", &board->manual_cs, sizeof(int)); ++ if(ret != SCRIPT_PARSER_OK) { ++ spi_err("Get spi devices manual_cs failed\n"); ++ goto fail; ++ } ++ */ ++ spi_inf("%-10d %-16s %-16d %-8d %-4d 0x%-4d\n", i, board->modalias, board->max_speed_hz, board->bus_num, board->chip_select, board->mode); ++ } ++ ++ /* register boards */ ++ ret = spi_register_board_info(spi_boards, spi_dev_num); ++ if (ret) ++ { ++ spi_err("Register board information failed\n"); ++ goto fail; ++ } ++ return 0; ++fail: ++ if (spi_boards) ++ { ++ kfree(spi_boards); ++ spi_boards = NULL; ++ } ++ return -1; ++ ++} ++ ++static int sun7i_spi_get_cfg_csbitmap(int bus_num) ++{ ++ int value = 0; ++ int ret = 0; ++ char *main_name[] = {"spi0_para", "spi1_para", "spi2_para", "spi3_para"}; ++ char *sub_name = "spi_cs_bitmap"; ++ ret = script_parser_fetch(main_name[bus_num], sub_name, &value, sizeof(int)); ++ if(ret != SCRIPT_PARSER_OK){ ++ spi_err("get spi %d para failed, err code = %d \n", bus_num, ret); ++ return 0; ++ } ++ spi_inf("bus num = %d, spi used = %d \n", bus_num, value); ++ return value; ++ ++} ++ ++#ifdef CONFIG_SUN7I_SPI_NORFLASH ++#include ++#include ++ ++/*struct mtd_partition part = { ++ .name = "p1", ++ .size = 8388608, ++ .offset = 0, ++};*/ ++ ++static struct flash_platform_data at25df641_info = { ++ .name = "m25p80", ++ .parts = NULL, ++ .nr_parts = 0, ++ .type = "at25df641", ++}; ++ ++static struct spi_board_info norflash = { ++ .modalias = "m25p80", ++ .platform_data = &at25df641_info, ++ .mode = SPI_MODE_0, ++ .irq = 0, ++ .max_speed_hz = 10 * 1000 * 1000, ++ .bus_num = 0, ++ .chip_select = 0, ++}; ++ ++static void __init sun7i_spi_norflash(void) ++{ ++ if (spi_register_board_info(&norflash, 1)) { ++ spi_err("%s: Register norflash:%s information failed\n", ++ __func__, at25df641_info.type); ++ } else { ++ spi_inf("%s: Register norflash:%s information OK\n", ++ __func__, at25df641_info.type); ++ } ++} ++#else ++static void __init sun7i_spi_norflash(void) ++{} ++#endif /* CONFIG_SUN7I_SPI_NORFLASH */ ++ ++/* get configuration in the script */ ++#define SPI0_USED_MASK 0x1 ++#define SPI1_USED_MASK 0x2 ++#define SPI2_USED_MASK 0x4 ++#define SPI3_USED_MASK 0x8 ++static int spi_used = 0; ++ ++static int __init spi_sun7i_init(void) ++{ ++ int used = 0; ++ int i = 0; ++ int ret = 0; ++ char spi_para[16] = {0}; ++ ++ spi_dbg("sw spi init !!\n"); ++ spi_used = 0; ++ for (i=0; i<4; i++) ++ { ++ used = 0; ++ sprintf(spi_para, "spi%d_para", i); ++ ret = script_parser_fetch(spi_para, "spi_used", &used, sizeof(int)); ++ if (ret) ++ { ++ spi_err("sw spi init fetch spi%d uning configuration failed\n", i); ++ continue; ++ } ++ if (used) ++ spi_used |= 1 << i; ++ } ++ ++ ret = sun7i_spi_register_spidev(); ++ if (ret) ++ { ++ spi_err("register spi devices board info failed \n"); ++ } ++ ++// sun7i_spi_norflash(); ++ ++ if (spi_used & SPI0_USED_MASK) ++ platform_device_register(&sun7i_spi0_device); ++ if (spi_used & SPI1_USED_MASK) ++ platform_device_register(&sun7i_spi1_device); ++ if (spi_used & SPI2_USED_MASK) ++ platform_device_register(&sun7i_spi2_device); ++ if (spi_used & SPI3_USED_MASK) ++ platform_device_register(&sun7i_spi3_device); ++ ++ if (spi_used) ++ { ++ return platform_driver_register(&sun7i_spi_driver); ++ } ++ else ++ { ++ pr_warning("spi: cannot find any using configuration for \ ++ all 4 spi controllers, return directly!\n"); ++ return 0; ++ } ++} ++ ++static void __exit spi_sun7i_exit(void) ++{ ++ if (spi_used) ++ platform_driver_unregister(&sun7i_spi_driver); ++} ++ ++module_init(spi_sun7i_init); ++module_exit(spi_sun7i_exit); ++ ++MODULE_AUTHOR("pannan"); ++MODULE_DESCRIPTION("SUN7I SPI BUS Driver"); ++MODULE_ALIAS("platform:sun7i-spi"); ++MODULE_LICENSE("GPL");