diff --git a/patch/kernel/archive/rockchip64-6.14/dt/rk3588-cyber-aib.dts b/patch/kernel/archive/rockchip64-6.14/dt/rk3588-cyber-aib.dts index d2d5b60e88..3098d48b6f 100644 --- a/patch/kernel/archive/rockchip64-6.14/dt/rk3588-cyber-aib.dts +++ b/patch/kernel/archive/rockchip64-6.14/dt/rk3588-cyber-aib.dts @@ -301,7 +301,7 @@ }; }; -&hdptxphy_hdmi0 { +&hdptxphy0 { status = "okay"; }; diff --git a/patch/kernel/archive/rockchip64-6.14/dt/rk3588-hinlink-h88k.dts b/patch/kernel/archive/rockchip64-6.14/dt/rk3588-hinlink-h88k.dts index 2e07b85d56..fc9a7c8aac 100644 --- a/patch/kernel/archive/rockchip64-6.14/dt/rk3588-hinlink-h88k.dts +++ b/patch/kernel/archive/rockchip64-6.14/dt/rk3588-hinlink-h88k.dts @@ -292,7 +292,7 @@ }; -&hdptxphy_hdmi0 { +&hdptxphy0 { status = "okay"; }; diff --git a/patch/kernel/archive/rockchip64-6.14/dt/rk3588-rock-5b-plus.dts b/patch/kernel/archive/rockchip64-6.14/dt/rk3588-rock-5b-plus.dts index 67ede3557c..d0f9a961c6 100644 --- a/patch/kernel/archive/rockchip64-6.14/dt/rk3588-rock-5b-plus.dts +++ b/patch/kernel/archive/rockchip64-6.14/dt/rk3588-rock-5b-plus.dts @@ -216,7 +216,7 @@ }; }; -&hdptxphy_hdmi0 { +&hdptxphy0 { status = "okay"; }; diff --git a/patch/kernel/archive/rockchip64-6.14/dt/rk3588s-nanopi-m6.dts b/patch/kernel/archive/rockchip64-6.14/dt/rk3588s-nanopi-m6.dts index ee4e4f3bfa..30c10ce8d9 100644 --- a/patch/kernel/archive/rockchip64-6.14/dt/rk3588s-nanopi-m6.dts +++ b/patch/kernel/archive/rockchip64-6.14/dt/rk3588s-nanopi-m6.dts @@ -282,7 +282,7 @@ }; }; -&hdptxphy_hdmi0 { +&hdptxphy0 { status = "okay"; }; diff --git a/patch/kernel/archive/rockchip64-6.14/dt/rk3588s-youyeetoo-r1.dts b/patch/kernel/archive/rockchip64-6.14/dt/rk3588s-youyeetoo-r1.dts index 1446aa021c..2ce9b93f6f 100644 --- a/patch/kernel/archive/rockchip64-6.14/dt/rk3588s-youyeetoo-r1.dts +++ b/patch/kernel/archive/rockchip64-6.14/dt/rk3588s-youyeetoo-r1.dts @@ -835,7 +835,7 @@ cec-enable = "true"; }; -&hdptxphy_hdmi0 { +&hdptxphy0 { status = "okay"; }; diff --git a/patch/kernel/archive/rockchip64-6.14/rk3588-0131-vop2-hdmi0-disp-modes-support.patch b/patch/kernel/archive/rockchip64-6.14/rk3588-0131-vop2-hdmi0-disp-modes-support.patch index 190f2c81b8..c5f0cac410 100644 --- a/patch/kernel/archive/rockchip64-6.14/rk3588-0131-vop2-hdmi0-disp-modes-support.patch +++ b/patch/kernel/archive/rockchip64-6.14/rk3588-0131-vop2-hdmi0-disp-modes-support.patch @@ -115,7 +115,7 @@ index 111111111111..222222222222 100644 struct vop2_win win[]; }; -+#define VOP2_MAX_DCLK_RATE 600000 /* kHz */ ++#define VOP2_MAX_DCLK_RATE 600000000 + #define vop2_output_if_is_hdmi(x) ((x) == ROCKCHIP_VOP2_EP_HDMI0 || \ (x) == ROCKCHIP_VOP2_EP_HDMI1) @@ -138,7 +138,7 @@ index 111111111111..222222222222 100644 + * Switch to HDMI PHY PLL as DCLK source for display modes up + * to 4K@60Hz, if available, otherwise keep using the system CRU. + */ -+ if (vop2->pll_hdmiphy0 && mode->crtc_clock <= VOP2_MAX_DCLK_RATE) { ++ if (vop2->pll_hdmiphy0 && clock <= VOP2_MAX_DCLK_RATE) { + drm_for_each_encoder_mask(encoder, crtc->dev, crtc_state->encoder_mask) { + struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); + diff --git a/patch/kernel/archive/rockchip64-6.14/rk3588-0132-Fix-label-name-of-hdptxphy-for-RK3588.patch b/patch/kernel/archive/rockchip64-6.14/rk3588-0132-Fix-label-name-of-hdptxphy-for-RK3588.patch new file mode 100644 index 0000000000..dbb68ff515 --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.14/rk3588-0132-Fix-label-name-of-hdptxphy-for-RK3588.patch @@ -0,0 +1,318 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Damon Ding +Date: Thu, 6 Feb 2025 11:03:30 +0800 +Subject: arm64: dts: rockchip: Fix label name of hdptxphy for RK3588 + +The hdptxphy is a combo transmit-PHY for HDMI2.1 TMDS Link, FRL Link, DP +and eDP Link. Therefore, it is better to name it hdptxphy0 other than +hdptxphy_hdmi0, which will be referenced by both hdmi0 and edp0 nodes. + +Signed-off-by: Damon Ding +Link: https://lore.kernel.org/r/20250206030330.680424-3-damon.ding@rock-chips.com +[added armsom-sige7, where hdmi-support was added recently and also + the hdptxphy0-as-dclk source I just added] +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 6 +++--- + arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-evb.dts | 2 +- + arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-genbook.dts | 2 +- + arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts | 2 +- + arch/arm64/boot/dts/rockchip/rk3588-firefly-itx-3588j.dts | 2 +- + arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts | 2 +- + arch/arm64/boot/dts/rockchip/rk3588-h96-max-v58.dts | 2 +- + arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts | 2 +- + arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi | 2 +- + arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-max.dts | 2 +- + arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts | 2 +- + arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 2 +- + arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts | 2 +- + arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts | 2 +- + arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts | 2 +- + arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi | 2 +- + arch/arm64/boot/dts/rockchip/rk3588s-odroid-m2.dts | 2 +- + arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi | 2 +- + arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 2 +- + arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts | 2 +- + 20 files changed, 22 insertions(+), 22 deletions(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +index 111111111111..222222222222 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +@@ -1262,7 +1262,7 @@ vop: vop@fdd90000 { + <&cru DCLK_VOP2>, + <&cru DCLK_VOP3>, + <&cru PCLK_VOP_ROOT>, +- <&hdptxphy_hdmi0>; ++ <&hdptxphy0>; + clock-names = "aclk", + "hclk", + "dclk_vp0", +@@ -1387,7 +1387,7 @@ hdmi0: hdmi@fde80000 { + , + ; + interrupt-names = "avp", "cec", "earc", "main", "hpd"; +- phys = <&hdptxphy_hdmi0>; ++ phys = <&hdptxphy0>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd + &hdmim0_tx0_scl &hdmim0_tx0_sda>; +@@ -2809,7 +2809,7 @@ dmac2: dma-controller@fed10000 { + #dma-cells = <1>; + }; + +- hdptxphy_hdmi0: phy@fed60000 { ++ hdptxphy0: phy@fed60000 { + compatible = "rockchip,rk3588-hdptx-phy"; + reg = <0x0 0xfed60000 0x0 0x2000>; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>; +diff --git a/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-evb.dts b/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-evb.dts +index 111111111111..222222222222 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-evb.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-evb.dts +@@ -129,7 +129,7 @@ hdmi0_out_con: endpoint { + }; + }; + +-&hdptxphy_hdmi0 { ++&hdptxphy0 { + status = "okay"; + }; + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-genbook.dts b/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-genbook.dts +index 111111111111..222222222222 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-genbook.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-genbook.dts +@@ -166,7 +166,7 @@ hdmi0_out_con: endpoint { + }; + }; + +-&hdptxphy_hdmi0 { ++&hdptxphy0 { + status = "okay"; + }; + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts +index 111111111111..222222222222 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts +@@ -364,7 +364,7 @@ hdmi0_out_con: endpoint { + }; + }; + +-&hdptxphy_hdmi0 { ++&hdptxphy0 { + status = "okay"; + }; + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588-firefly-itx-3588j.dts b/arch/arm64/boot/dts/rockchip/rk3588-firefly-itx-3588j.dts +index 111111111111..222222222222 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588-firefly-itx-3588j.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-firefly-itx-3588j.dts +@@ -337,7 +337,7 @@ hdmi0_out_con: endpoint { + }; + }; + +-&hdptxphy_hdmi0 { ++&hdptxphy0 { + status = "okay"; + }; + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts b/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts +index 111111111111..222222222222 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts +@@ -335,7 +335,7 @@ hdmi0_out_con: endpoint { + }; + }; + +-&hdptxphy_hdmi0 { ++&hdptxphy0 { + status = "okay"; + }; + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588-h96-max-v58.dts b/arch/arm64/boot/dts/rockchip/rk3588-h96-max-v58.dts +index 111111111111..222222222222 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588-h96-max-v58.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-h96-max-v58.dts +@@ -207,7 +207,7 @@ hdmi0_out_con: endpoint { + }; + }; + +-&hdptxphy_hdmi0 { ++&hdptxphy0 { + status = "okay"; + }; + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts b/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts +index 111111111111..222222222222 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts +@@ -303,7 +303,7 @@ hdmi0_out_con: endpoint { + }; + }; + +-&hdptxphy_hdmi0 { ++&hdptxphy0 { + status = "okay"; + }; + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi +index 111111111111..222222222222 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi +@@ -360,7 +360,7 @@ hdmi0_out_con: endpoint { + }; + }; + +-&hdptxphy_hdmi0 { ++&hdptxphy0 { + status = "okay"; + }; + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-max.dts b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-max.dts +index 111111111111..222222222222 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-max.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-max.dts +@@ -39,7 +39,7 @@ hdmi0_out_con: endpoint { + }; + }; + +-&hdptxphy_hdmi0 { ++&hdptxphy0 { + status = "okay"; + }; + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts +index 111111111111..222222222222 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts +@@ -125,7 +125,7 @@ hdmi0_out_con: endpoint { + }; + }; + +-&hdptxphy_hdmi0 { ++&hdptxphy0 { + status = "okay"; + }; + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +index 111111111111..222222222222 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +@@ -220,7 +220,7 @@ hdmi0_out_con: endpoint { + }; + }; + +-&hdptxphy_hdmi0 { ++&hdptxphy0 { + status = "okay"; + }; + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts b/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts +index 111111111111..222222222222 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts +@@ -189,7 +189,7 @@ hdmi0_out_con: endpoint { + }; + }; + +-&hdptxphy_hdmi0 { ++&hdptxphy0 { + status = "okay"; + }; + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts b/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts +index 111111111111..222222222222 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts +@@ -236,7 +236,7 @@ hdmi0_out_con: endpoint { + }; + }; + +-&hdptxphy_hdmi0 { ++&hdptxphy0 { + status = "okay"; + }; + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts b/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts +index 111111111111..222222222222 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts +@@ -278,7 +278,7 @@ hdmi0_out_con: endpoint { + }; + }; + +-&hdptxphy_hdmi0 { ++&hdptxphy0 { + status = "okay"; + }; + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi +index 111111111111..222222222222 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi +@@ -251,7 +251,7 @@ hdmi0_out_con: endpoint { + }; + }; + +-&hdptxphy_hdmi0 { ++&hdptxphy0 { + status = "okay"; + }; + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-odroid-m2.dts b/arch/arm64/boot/dts/rockchip/rk3588s-odroid-m2.dts +index 111111111111..222222222222 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588s-odroid-m2.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588s-odroid-m2.dts +@@ -264,7 +264,7 @@ hdmi0_out_con: endpoint { + }; + }; + +-&hdptxphy_hdmi0 { ++&hdptxphy0 { + status = "okay"; + }; + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi +index 111111111111..222222222222 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi +@@ -197,7 +197,7 @@ hdmi0_out_con: endpoint { + }; + }; + +-&hdptxphy_hdmi0 { ++&hdptxphy0 { + status = "okay"; + }; + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts +index 111111111111..222222222222 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts +@@ -334,7 +334,7 @@ hdmi0_out_con: endpoint { + }; + }; + +-&hdptxphy_hdmi0 { ++&hdptxphy0 { + status = "okay"; + }; + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts +index 111111111111..222222222222 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts +@@ -278,7 +278,7 @@ hdmi0_out_con: endpoint { + }; + }; + +-&hdptxphy_hdmi0 { ++&hdptxphy0 { + status = "okay"; + }; + +-- +Armbian + diff --git a/patch/kernel/archive/rockchip64-6.14/rk3588-0133-vop2-hdmi1-disp-modes-support.patch b/patch/kernel/archive/rockchip64-6.14/rk3588-0133-vop2-hdmi1-disp-modes-support.patch new file mode 100644 index 0000000000..1a5cfc0c70 --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.14/rk3588-0133-vop2-hdmi1-disp-modes-support.patch @@ -0,0 +1,173 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Cristian Ciocaltea +Date: Sat, 15 Feb 2025 02:55:37 +0200 +Subject: drm/rockchip: vop2: Improve display modes handling on RK3588 HDMI1 + +The RK3588 specific implementation is currently quite limited in terms +of handling the full range of display modes supported by the connected +screens, e.g. 2560x1440@75Hz, 2048x1152@60Hz, 1024x768@60Hz are just a +few of them. + +Additionally, it doesn't cope well with non-integer refresh rates like +59.94, 29.97, 23.98, etc. + +Make use of HDMI1 PHY PLL as a more accurate DCLK source to handle +all display modes up to 4K@60Hz. + +Signed-off-by: Cristian Ciocaltea +--- + drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 26 +++++++++- + 1 file changed, 25 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +index 111111111111..222222222222 100644 +--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c ++++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +@@ -216,6 +216,7 @@ struct vop2 { + struct clk *aclk; + struct clk *pclk; + struct clk *pll_hdmiphy0; ++ struct clk *pll_hdmiphy1; + + /* optional internal rgb encoder */ + struct rockchip_rgb *rgb; +@@ -2270,11 +2271,14 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, + * Switch to HDMI PHY PLL as DCLK source for display modes up + * to 4K@60Hz, if available, otherwise keep using the system CRU. + */ +- if (vop2->pll_hdmiphy0 && clock <= VOP2_MAX_DCLK_RATE) { ++ if ((vop2->pll_hdmiphy0 || vop2->pll_hdmiphy1) && clock <= VOP2_MAX_DCLK_RATE) { + drm_for_each_encoder_mask(encoder, crtc->dev, crtc_state->encoder_mask) { + struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); + + if (rkencoder->crtc_endpoint_id == ROCKCHIP_VOP2_EP_HDMI0) { ++ if (!vop2->pll_hdmiphy0) ++ break; ++ + if (!vp->dclk_src) + vp->dclk_src = clk_get_parent(vp->dclk); + +@@ -2284,6 +2288,20 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, + "Could not switch to HDMI0 PHY PLL: %d\n", ret); + break; + } ++ ++ if (rkencoder->crtc_endpoint_id == ROCKCHIP_VOP2_EP_HDMI1) { ++ if (!vop2->pll_hdmiphy1) ++ break; ++ ++ if (!vp->dclk_src) ++ vp->dclk_src = clk_get_parent(vp->dclk); ++ ++ ret = clk_set_parent(vp->dclk, vop2->pll_hdmiphy1); ++ if (ret < 0) ++ drm_warn(vop2->drm, ++ "Could not switch to HDMI1 PHY PLL: %d\n", ret); ++ break; ++ } + } + } + +@@ -3733,6 +3751,12 @@ static int vop2_bind(struct device *dev, struct device *master, void *data) + return PTR_ERR(vop2->pll_hdmiphy0); + } + ++ vop2->pll_hdmiphy1 = devm_clk_get_optional(vop2->dev, "pll_hdmiphy1"); ++ if (IS_ERR(vop2->pll_hdmiphy1)) { ++ drm_err(vop2->drm, "failed to get pll_hdmiphy1\n"); ++ return PTR_ERR(vop2->pll_hdmiphy1); ++ } ++ + vop2->irq = platform_get_irq(pdev, 0); + if (vop2->irq < 0) { + drm_err(vop2->drm, "cannot find irq for vop2\n"); +-- +Armbian + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Cristian Ciocaltea +Date: Sat, 15 Feb 2025 02:55:38 +0200 +Subject: arm64: dts: rockchip: Enable HDMI1 PHY clk provider on RK3588 + +Since commit c4b09c562086 ("phy: phy-rockchip-samsung-hdptx: Add clock +provider support"), the HDMI PHY PLL can be used as an alternative and +more accurate pixel clock source for VOP2 to improve display modes +handling on RK3588 SoC. + +Add the missing #clock-cells property to allow using the clock provider +functionality of HDMI1 PHY. + +Signed-off-by: Cristian Ciocaltea +--- + arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi +index 111111111111..222222222222 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi +@@ -506,6 +506,7 @@ hdptxphy1: phy@fed70000 { + reg = <0x0 0xfed70000 0x0 0x2000>; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX1>; + clock-names = "ref", "apb"; ++ #clock-cells = <0>; + #phy-cells = <0>; + resets = <&cru SRST_HDPTX1>, <&cru SRST_P_HDPTX1>, + <&cru SRST_HDPTX1_INIT>, <&cru SRST_HDPTX1_CMN>, +-- +Armbian + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Cristian Ciocaltea +Date: Sat, 15 Feb 2025 02:55:39 +0200 +Subject: arm64: dts: rockchip: Add HDMI1 PHY PLL clock source to VOP2 on + RK3588 + +VOP2 on RK3588 is able to use the HDMI PHY PLL as an alternative and +more accurate pixel clock source to improve handling of display modes up +to 4K@60Hz on video ports 0, 1 and 2. + +The HDMI1 PHY PLL clock source cannot be added directly to vop node in +rk3588-base.dtsi, along with the HDMI0 related one, because HDMI1 is an +optional feature and its PHY node belongs to a separate (extra) DT file. + +Therefore, add the HDMI1 PHY PLL clock source to VOP2 by overwriting its +clocks & clock-names properties in the extra DT file. + +Signed-off-by: Cristian Ciocaltea +--- + arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi | 21 ++++++++++ + 1 file changed, 21 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi +index 111111111111..222222222222 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi +@@ -569,3 +569,24 @@ pcie30phy: phy@fee80000 { + status = "disabled"; + }; + }; ++ ++&vop { ++ clocks = <&cru ACLK_VOP>, ++ <&cru HCLK_VOP>, ++ <&cru DCLK_VOP0>, ++ <&cru DCLK_VOP1>, ++ <&cru DCLK_VOP2>, ++ <&cru DCLK_VOP3>, ++ <&cru PCLK_VOP_ROOT>, ++ <&hdptxphy0>, ++ <&hdptxphy1>; ++ clock-names = "aclk", ++ "hclk", ++ "dclk_vp0", ++ "dclk_vp1", ++ "dclk_vp2", ++ "dclk_vp3", ++ "pclk_vop", ++ "pll_hdmiphy0", ++ "pll_hdmiphy1"; ++}; +-- +Armbian + diff --git a/patch/kernel/archive/rockchip64-6.14/rk3588-0170-drm-rockchip-vop2-add-clocks-reset-support.patch b/patch/kernel/archive/rockchip64-6.14/rk3588-0170-drm-rockchip-vop2-add-clocks-reset-support.patch index ffc31dbbc1..f551867cd6 100644 --- a/patch/kernel/archive/rockchip64-6.14/rk3588-0170-drm-rockchip-vop2-add-clocks-reset-support.patch +++ b/patch/kernel/archive/rockchip64-6.14/rk3588-0170-drm-rockchip-vop2-add-clocks-reset-support.patch @@ -34,7 +34,7 @@ index 111111111111..222222222222 100644 struct clk *dclk; struct clk *dclk_src; unsigned int id; -@@ -2134,6 +2136,26 @@ static int us_to_vertical_line(struct drm_display_mode *mode, int us) +@@ -2135,6 +2137,26 @@ static int us_to_vertical_line(struct drm_display_mode *mode, int us) return us * mode->clock / mode->htotal / 1000; } @@ -61,7 +61,7 @@ index 111111111111..222222222222 100644 static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_state *state) { -@@ -2297,6 +2319,8 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, +@@ -2315,6 +2337,8 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, vop2_crtc_atomic_try_set_gamma(vop2, vp, crtc, crtc_state); @@ -70,7 +70,7 @@ index 111111111111..222222222222 100644 drm_crtc_vblank_on(crtc); vop2_unlock(vop2); -@@ -3254,6 +3278,12 @@ static int vop2_create_crtcs(struct vop2 *vop2) +@@ -3272,6 +3296,12 @@ static int vop2_create_crtcs(struct vop2 *vop2) vp->data = vp_data; snprintf(dclk_name, sizeof(dclk_name), "dclk_vp%d", vp->id); diff --git a/patch/kernel/archive/rockchip64-6.14/rk3588-1011-rock5b-hdmi1.patch b/patch/kernel/archive/rockchip64-6.14/rk3588-1011-rock5b-hdmi1.patch index 271e0fa572..116d439914 100644 --- a/patch/kernel/archive/rockchip64-6.14/rk3588-1011-rock5b-hdmi1.patch +++ b/patch/kernel/archive/rockchip64-6.14/rk3588-1011-rock5b-hdmi1.patch @@ -56,7 +56,7 @@ index 111111111111..222222222222 100644 + }; +}; + - &hdptxphy_hdmi0 { + &hdptxphy0 { status = "okay"; }; diff --git a/patch/kernel/archive/rockchip64-6.14/rk3588-1031-arm64-dts-rockchip-Add-HDMI-support-to-ArmSoM-Sige7.patch b/patch/kernel/archive/rockchip64-6.14/rk3588-1031-arm64-dts-rockchip-Add-HDMI-support-to-ArmSoM-Sige7.patch index 8ee172545f..2906ea40c5 100644 --- a/patch/kernel/archive/rockchip64-6.14/rk3588-1031-arm64-dts-rockchip-Add-HDMI-support-to-ArmSoM-Sige7.patch +++ b/patch/kernel/archive/rockchip64-6.14/rk3588-1031-arm64-dts-rockchip-Add-HDMI-support-to-ArmSoM-Sige7.patch @@ -33,7 +33,7 @@ index 111111111111..222222222222 100644 + }; +}; + -+&hdptxphy_hdmi0 { ++&hdptxphy0 { + status = "okay"; +}; + diff --git a/patch/kernel/archive/rockchip64-6.14/rk3588-1040-board-khadas-edge2-add-nodes.patch b/patch/kernel/archive/rockchip64-6.14/rk3588-1040-board-khadas-edge2-add-nodes.patch index 510b3e3a5a..be3c89e264 100644 --- a/patch/kernel/archive/rockchip64-6.14/rk3588-1040-board-khadas-edge2-add-nodes.patch +++ b/patch/kernel/archive/rockchip64-6.14/rk3588-1040-board-khadas-edge2-add-nodes.patch @@ -279,7 +279,7 @@ index 111111111111..222222222222 100644 + }; +}; + -+&hdptxphy_hdmi0 { ++&hdptxphy0 { + status = "okay"; +}; + diff --git a/patch/kernel/archive/rockchip64-6.14/rk3588-1071-arm64-dts-Add-missing-nodes-to-Orange-Pi-5-Plus.patch b/patch/kernel/archive/rockchip64-6.14/rk3588-1071-arm64-dts-Add-missing-nodes-to-Orange-Pi-5-Plus.patch index f273d5b1b5..e813522347 100644 --- a/patch/kernel/archive/rockchip64-6.14/rk3588-1071-arm64-dts-Add-missing-nodes-to-Orange-Pi-5-Plus.patch +++ b/patch/kernel/archive/rockchip64-6.14/rk3588-1071-arm64-dts-Add-missing-nodes-to-Orange-Pi-5-Plus.patch @@ -130,7 +130,7 @@ index 111111111111..222222222222 100644 + }; +}; + - &hdptxphy_hdmi0 { + &hdptxphy0 { status = "okay"; };