From 88464cc41251c76de4fc87e8da67d19ac7ce364c Mon Sep 17 00:00:00 2001 From: Jianfeng Liu Date: Sat, 19 Mar 2022 19:10:37 +0800 Subject: [PATCH] Radxa rock3a gpu support (#3547) * Refresh the vop2 patch from catalinii * add SCMI related config to support rk3568 gpu Co-authored-by: Jianfeng Liu --- config/kernel/linux-rk35xx-edge.config | 3 +- .../rk356x-drm-rockchip-VOP2-support.patch | 4594 +++++++---------- .../archive/rk35xx-5.16/rk356x-gpu-GPU.patch | 795 ++- .../archive/rk35xx-5.16/rk356x-usb3.patch | 10 - 4 files changed, 2532 insertions(+), 2870 deletions(-) diff --git a/config/kernel/linux-rk35xx-edge.config b/config/kernel/linux-rk35xx-edge.config index e29012da54..dc7fbf5600 100644 --- a/config/kernel/linux-rk35xx-edge.config +++ b/config/kernel/linux-rk35xx-edge.config @@ -2093,7 +2093,7 @@ CONFIG_CONNECTOR=m # # ARM System Control and Management Interface Protocol # -# CONFIG_ARM_SCMI_PROTOCOL is not set +CONFIG_ARM_SCMI_PROTOCOL=y # end of ARM System Control and Management Interface Protocol CONFIG_ARM_SCPI_PROTOCOL=y @@ -7447,6 +7447,7 @@ CONFIG_LMK04832=m # CONFIG_COMMON_CLK_MAX77686 is not set # CONFIG_COMMON_CLK_MAX9485 is not set CONFIG_COMMON_CLK_RK808=y +CONFIG_COMMON_CLK_SCMI=y CONFIG_COMMON_CLK_SCPI=y # CONFIG_COMMON_CLK_SI5341 is not set # CONFIG_COMMON_CLK_SI5351 is not set diff --git a/patch/kernel/archive/rk35xx-5.16/rk356x-drm-rockchip-VOP2-support.patch b/patch/kernel/archive/rk35xx-5.16/rk356x-drm-rockchip-VOP2-support.patch index cc85a29dcd..4c98eb18c5 100644 --- a/patch/kernel/archive/rk35xx-5.16/rk356x-drm-rockchip-VOP2-support.patch +++ b/patch/kernel/archive/rk35xx-5.16/rk356x-drm-rockchip-VOP2-support.patch @@ -1,323 +1,47 @@ -diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 830bdd5e9b7ce..8677c82716784 100644 ---- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -529,13 +529,6 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, - return ret; - } - -- ret = clk_prepare_enable(hdmi->vpll_clk); -- if (ret) { -- DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI vpll: %d\n", -- ret); -- return ret; -- } -- - hdmi->phy = devm_phy_optional_get(dev, "hdmi"); - if (IS_ERR(hdmi->phy)) { - ret = PTR_ERR(hdmi->phy); -@@ -544,6 +537,13 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, - return ret; - } - -+ ret = clk_prepare_enable(hdmi->vpll_clk); -+ if (ret) { -+ DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI vpll: %d\n", -+ ret); -+ return ret; -+ } -+ - drm_encoder_helper_add(encoder, &dw_hdmi_rockchip_encoder_helper_funcs); - drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS); - -diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 8677c82716784..e352e0404f772 100644 ---- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -69,7 +69,7 @@ struct rockchip_hdmi { - struct regmap *regmap; - struct drm_encoder encoder; - const struct rockchip_hdmi_chip_data *chip_data; -- struct clk *vpll_clk; -+ struct clk *ref_clk; - struct clk *grf_clk; - struct dw_hdmi *hdmi; - struct phy *phy; -@@ -196,14 +196,17 @@ static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi) - return PTR_ERR(hdmi->regmap); - } - -- hdmi->vpll_clk = devm_clk_get(hdmi->dev, "vpll"); -- if (PTR_ERR(hdmi->vpll_clk) == -ENOENT) { -- hdmi->vpll_clk = NULL; -- } else if (PTR_ERR(hdmi->vpll_clk) == -EPROBE_DEFER) { -+ hdmi->ref_clk = devm_clk_get(hdmi->dev, "ref"); -+ if (PTR_ERR(hdmi->ref_clk) == -ENOENT) -+ hdmi->ref_clk = devm_clk_get(hdmi->dev, "vpll"); -+ -+ if (PTR_ERR(hdmi->ref_clk) == -ENOENT) { -+ hdmi->ref_clk = NULL; -+ } else if (PTR_ERR(hdmi->ref_clk) == -EPROBE_DEFER) { - return -EPROBE_DEFER; -- } else if (IS_ERR(hdmi->vpll_clk)) { -- DRM_DEV_ERROR(hdmi->dev, "failed to get vpll clock\n"); -- return PTR_ERR(hdmi->vpll_clk); -+ } else if (IS_ERR(hdmi->ref_clk)) { -+ DRM_DEV_ERROR(hdmi->dev, "failed to get reference clock\n"); -+ return PTR_ERR(hdmi->ref_clk); - } - - hdmi->grf_clk = devm_clk_get(hdmi->dev, "grf"); -@@ -257,7 +260,7 @@ static void dw_hdmi_rockchip_encoder_mode_set(struct drm_encoder *encoder, - { - struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder); - -- clk_set_rate(hdmi->vpll_clk, adj_mode->clock * 1000); -+ clk_set_rate(hdmi->ref_clk, adj_mode->clock * 1000); - } - - static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder) -@@ -537,9 +540,9 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, - return ret; - } - -- ret = clk_prepare_enable(hdmi->vpll_clk); -+ ret = clk_prepare_enable(hdmi->ref_clk); - if (ret) { -- DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI vpll: %d\n", -+ DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI reference clock: %d\n", - ret); - return ret; - } -@@ -558,7 +561,7 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, - if (IS_ERR(hdmi->hdmi)) { - ret = PTR_ERR(hdmi->hdmi); - drm_encoder_cleanup(encoder); -- clk_disable_unprepare(hdmi->vpll_clk); -+ clk_disable_unprepare(hdmi->ref_clk); - } - - return ret; -@@ -570,7 +573,7 @@ static void dw_hdmi_rockchip_unbind(struct device *dev, struct device *master, - struct rockchip_hdmi *hdmi = dev_get_drvdata(dev); - - dw_hdmi_unbind(hdmi->hdmi); -- clk_disable_unprepare(hdmi->vpll_clk); -+ clk_disable_unprepare(hdmi->ref_clk); - } - - static const struct component_ops dw_hdmi_rockchip_ops = { -diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index e352e0404f772..262eef614cb12 100644 ---- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -50,6 +50,10 @@ - #define RK3399_GRF_SOC_CON20 0x6250 - #define RK3399_HDMI_LCDC_SEL BIT(6) - -+#define RK3568_GRF_VO_CON1 0x0364 -+#define RK3568_HDMI_SDAIN_MSK BIT(15) -+#define RK3568_HDMI_SCLIN_MSK BIT(14) -+ - #define HIWORD_UPDATE(val, mask) (val | (mask) << 16) - - /** -@@ -470,6 +474,19 @@ static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = { - .use_drm_infoframe = true, - }; - -+static struct rockchip_hdmi_chip_data rk3568_chip_data = { -+ .lcdsel_grf_reg = -1, -+}; -+ -+static const struct dw_hdmi_plat_data rk3568_hdmi_drv_data = { -+ .mode_valid = dw_hdmi_rockchip_mode_valid, -+ .mpll_cfg = rockchip_mpll_cfg, -+ .cur_ctr = rockchip_cur_ctr, -+ .phy_config = rockchip_phy_config, -+ .phy_data = &rk3568_chip_data, -+ .use_drm_infoframe = true, -+}; -+ - static const struct of_device_id dw_hdmi_rockchip_dt_ids[] = { - { .compatible = "rockchip,rk3228-dw-hdmi", - .data = &rk3228_hdmi_drv_data -@@ -483,6 +500,9 @@ static const struct of_device_id dw_hdmi_rockchip_dt_ids[] = { - { .compatible = "rockchip,rk3399-dw-hdmi", - .data = &rk3399_hdmi_drv_data - }, -+ { .compatible = "rockchip,rk3568-dw-hdmi", -+ .data = &rk3568_hdmi_drv_data -+ }, - {}, - }; - MODULE_DEVICE_TABLE(of, dw_hdmi_rockchip_dt_ids); -@@ -517,6 +537,9 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, - encoder = &hdmi->encoder; - - encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node); -+ -+ encoder->port = of_graph_get_port_by_id(dev->of_node, 0); -+ - /* - * If we failed to find the CRTC(s) which this encoder is - * supposed to be connected to, it's because the CRTC has -@@ -547,6 +570,14 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, - return ret; - } - -+ if (hdmi->chip_data == &rk3568_chip_data) { -+ regmap_write(hdmi->regmap, RK3568_GRF_VO_CON1, -+ HIWORD_UPDATE(RK3568_HDMI_SDAIN_MSK | -+ RK3568_HDMI_SCLIN_MSK, -+ RK3568_HDMI_SDAIN_MSK | -+ RK3568_HDMI_SCLIN_MSK)); -+ } -+ - drm_encoder_helper_add(encoder, &dw_hdmi_rockchip_encoder_helper_funcs); - drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS); - -diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 262eef614cb12..3d7c3f6fdf223 100644 ---- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -9,6 +9,7 @@ - #include - #include - #include -+#include - - #include - #include -@@ -76,6 +77,8 @@ struct rockchip_hdmi { - struct clk *ref_clk; - struct clk *grf_clk; - struct dw_hdmi *hdmi; -+ struct regulator *avdd_0v9; -+ struct regulator *avdd_1v8; - struct phy *phy; - }; - -@@ -223,6 +226,14 @@ static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi) - return PTR_ERR(hdmi->grf_clk); - } - -+ hdmi->avdd_0v9 = devm_regulator_get(hdmi->dev, "avdd-0v9"); -+ if (IS_ERR(hdmi->avdd_0v9)) -+ return PTR_ERR(hdmi->avdd_0v9); -+ -+ hdmi->avdd_1v8 = devm_regulator_get(hdmi->dev, "avdd-1v8"); -+ if (IS_ERR(hdmi->avdd_1v8)) -+ return PTR_ERR(hdmi->avdd_1v8); -+ - return 0; - } - -@@ -563,11 +574,23 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, - return ret; - } - -+ ret = regulator_enable(hdmi->avdd_0v9); -+ if (ret) { -+ DRM_DEV_ERROR(hdmi->dev, "failed to enable avdd0v9: %d\n", ret); -+ goto err_avdd_0v9; -+ } -+ -+ ret = regulator_enable(hdmi->avdd_1v8); -+ if (ret) { -+ DRM_DEV_ERROR(hdmi->dev, "failed to enable avdd1v8: %d\n", ret); -+ goto err_avdd_1v8; -+ } -+ - ret = clk_prepare_enable(hdmi->ref_clk); - if (ret) { - DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI reference clock: %d\n", - ret); -- return ret; -+ goto err_clk; - } - - if (hdmi->chip_data == &rk3568_chip_data) { -@@ -591,10 +614,19 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, - */ - if (IS_ERR(hdmi->hdmi)) { - ret = PTR_ERR(hdmi->hdmi); -- drm_encoder_cleanup(encoder); -- clk_disable_unprepare(hdmi->ref_clk); -+ goto err_bind; - } - -+ return 0; -+ -+err_bind: -+ clk_disable_unprepare(hdmi->ref_clk); -+ drm_encoder_cleanup(encoder); -+err_clk: -+ regulator_disable(hdmi->avdd_1v8); -+err_avdd_1v8: -+ regulator_disable(hdmi->avdd_0v9); -+err_avdd_0v9: - return ret; - } - -@@ -605,6 +637,9 @@ static void dw_hdmi_rockchip_unbind(struct device *dev, struct device *master, - - dw_hdmi_unbind(hdmi->hdmi); - clk_disable_unprepare(hdmi->ref_clk); -+ -+ regulator_disable(hdmi->avdd_1v8); -+ regulator_disable(hdmi->avdd_0v9); - } - - static const struct component_ops dw_hdmi_rockchip_ops = { -diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 3d7c3f6fdf223..b9928e622adf5 100644 ---- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -76,6 +76,7 @@ struct rockchip_hdmi { - const struct rockchip_hdmi_chip_data *chip_data; - struct clk *ref_clk; - struct clk *grf_clk; -+ struct clk *hclk_clk; - struct dw_hdmi *hdmi; - struct regulator *avdd_0v9; - struct regulator *avdd_1v8; -@@ -226,6 +227,16 @@ static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi) - return PTR_ERR(hdmi->grf_clk); - } - -+ hdmi->hclk_clk = devm_clk_get(hdmi->dev, "hclk"); -+ if (PTR_ERR(hdmi->hclk_clk) == -ENOENT) { -+ hdmi->hclk_clk = NULL; -+ } else if (PTR_ERR(hdmi->hclk_clk) == -EPROBE_DEFER) { -+ return -EPROBE_DEFER; -+ } else if (IS_ERR(hdmi->hclk_clk)) { -+ DRM_DEV_ERROR(hdmi->dev, "failed to get hclk_clk clock\n"); -+ return PTR_ERR(hdmi->hclk_clk); -+ } -+ - hdmi->avdd_0v9 = devm_regulator_get(hdmi->dev, "avdd-0v9"); - if (IS_ERR(hdmi->avdd_0v9)) - return PTR_ERR(hdmi->avdd_0v9); -@@ -593,6 +604,13 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, - goto err_clk; - } - -+ ret = clk_prepare_enable(hdmi->hclk_clk); -+ if (ret) { -+ DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI hclk clock: %d\n", -+ ret); -+ goto err_clk; -+ } -+ - if (hdmi->chip_data == &rk3568_chip_data) { - regmap_write(hdmi->regmap, RK3568_GRF_VO_CON1, - HIWORD_UPDATE(RK3568_HDMI_SDAIN_MSK | +From 42198d593e6b63ce1eb0106649ad2e0b8a1ea1d3 Mon Sep 17 00:00:00 2001 +From: Catalin Toda +Date: Thu, 24 Feb 2022 11:36:40 -0800 +Subject: [PATCH] drm/rockchip rk356x VOP2 support v6 + +--- + .../display/rockchip/rockchip,dw-hdmi.yaml | 53 +- + .../display/rockchip/rockchip-vop2.yaml | 140 + + arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 +- + .../boot/dts/rockchip/rk3566-quartz64-a.dts | 47 + + arch/arm64/boot/dts/rockchip/rk3566.dtsi | 4 + + .../boot/dts/rockchip/rk3568-evb1-v10.dts | 47 + + arch/arm64/boot/dts/rockchip/rk3568.dtsi | 4 + + arch/arm64/boot/dts/rockchip/rk356x.dtsi | 83 + + drivers/gpu/drm/rockchip/Kconfig | 14 + + drivers/gpu/drm/rockchip/Makefile | 4 +- + .../gpu/drm/rockchip/analogix_dp-rockchip.c | 32 +- + drivers/gpu/drm/rockchip/cdn-dp-core.c | 18 +- + drivers/gpu/drm/rockchip/cdn-dp-core.h | 2 +- + .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 17 +- + drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 294 +- + drivers/gpu/drm/rockchip/inno_hdmi.c | 32 +- + drivers/gpu/drm/rockchip/rk3066_hdmi.c | 34 +- + drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 3 +- + drivers/gpu/drm/rockchip/rockchip_drm_drv.h | 17 +- + drivers/gpu/drm/rockchip/rockchip_drm_fb.c | 2 + + drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 15 + + drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 2708 +++++++++++++++++ + drivers/gpu/drm/rockchip/rockchip_drm_vop2.h | 477 +++ + drivers/gpu/drm/rockchip/rockchip_lvds.c | 26 +- + drivers/gpu/drm/rockchip/rockchip_vop2_reg.c | 281 ++ + include/dt-bindings/soc/rockchip,vop2.h | 14 + + 26 files changed, 4175 insertions(+), 195 deletions(-) + create mode 100644 Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml + create mode 100644 drivers/gpu/drm/rockchip/rockchip_drm_vop2.c + create mode 100644 drivers/gpu/drm/rockchip/rockchip_drm_vop2.h + create mode 100644 drivers/gpu/drm/rockchip/rockchip_vop2_reg.c + create mode 100644 include/dt-bindings/soc/rockchip,vop2.h + diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml -index da3b889ad8fcd..45cae4f57a1c1 100644 +index da3b889ad8fc..fc26f1d4d001 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml -@@ -23,6 +23,7 @@ properties: +@@ -23,20 +23,34 @@ properties: - rockchip,rk3288-dw-hdmi - rockchip,rk3328-dw-hdmi - rockchip,rk3399-dw-hdmi @@ -325,234 +49,6 @@ index da3b889ad8fcd..45cae4f57a1c1 100644 reg-io-width: const: 4 -diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml -index 45cae4f57a1c1..6e09dd2ee05ac 100644 ---- a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml -+++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml -@@ -73,6 +73,7 @@ properties: - The unwedge pinctrl entry shall drive the DDC SDA line low. This is - intended to work around a hardware errata that can cause the DDC I2C - bus to be wedged. -+ minItems: 1 - items: - - const: default - - const: unwedge -From patchwork Mon Dec 20 11:06:16 2021 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Sascha Hauer -X-Patchwork-Id: 12687625 -Return-Path: - -X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on - aws-us-west-2-korg-lkml-1.web.codeaurora.org -Received: from bombadil.infradead.org (bombadil.infradead.org - [198.137.202.133]) - (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) - (No client certificate requested) - by smtp.lore.kernel.org (Postfix) with ESMTPS id 7D787C4332F - for ; - Mon, 20 Dec 2021 11:21:43 +0000 (UTC) -DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; - d=lists.infradead.org; s=bombadil.20210309; h=Sender: - Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: - List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: - Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: - Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: - List-Owner; bh=dPAqJXapcobg6sEdWol3+UOIIBgXZYUh6ue5+adn5MY=; b=QyVZSelYHNkM7g - GAOX659fBRm9mX0hK4dAGOQeENMZR5pJ60Ye9Kmw+wOarTbkL5dgtXWAu6cFJISjlv03Pe3QQKuNo - 9oaKPa5myV35GYXOcL/UNnN9lnGdnhketCZdvsXdhr/0FGNOBYb+eL4KdLMpYSt7mBKg3S+/iSh+u - BEaGRMRcXD+cR4/QReVjT33bACLC9Nsnf9vYKj73PcOGQ4n1ZDScswkbpyWk9E8HH2qHs7xSSQ+Vy - sIK576UWpqb3sgnRm62/JSvR9lFSA99n1+Tig9fMEIKI2HNpeAhOi5/kCCT04qHAMOSkf9mcLUmZB - f1OPbk3GvRCHsGpisD5A==; -Received: from localhost ([::1] helo=bombadil.infradead.org) - by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) - id 1mzGjb-001wBg-DV; Mon, 20 Dec 2021 11:21:39 +0000 -Received: from metis.ext.pengutronix.de ([85.220.165.71]) - by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) - id 1mzGVi-001oUQ-Er - for linux-rockchip@lists.infradead.org; Mon, 20 Dec 2021 11:07:19 +0000 -Received: from dude02.hi.pengutronix.de ([2001:67c:670:100:1d::28]) - by metis.ext.pengutronix.de with esmtps - (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) - (envelope-from ) - id 1mzGVH-0004x7-7m; Mon, 20 Dec 2021 12:06:51 +0100 -Received: from sha by dude02.hi.pengutronix.de with local (Exim 4.94.2) - (envelope-from ) - id 1mzGVA-00EmEJ-Kw; Mon, 20 Dec 2021 12:06:44 +0100 -From: Sascha Hauer -To: dri-devel@lists.freedesktop.org -Cc: linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, - devicetree@vger.kernel.org, kernel@pengutronix.de, - Andy Yan , - Benjamin Gaignard , - Michael Riesch , - Sandy Huang , - =?utf-8?q?Heiko_St=C3=BCbner?= , - Peter Geis , Sascha Hauer -Subject: [PATCH 08/22] dt-bindings: display: rockchip: dw-hdmi: use "ref" as - clock name -Date: Mon, 20 Dec 2021 12:06:16 +0100 -Message-Id: <20211220110630.3521121-9-s.hauer@pengutronix.de> -X-Mailer: git-send-email 2.30.2 -In-Reply-To: <20211220110630.3521121-1-s.hauer@pengutronix.de> -References: <20211220110630.3521121-1-s.hauer@pengutronix.de> -MIME-Version: 1.0 -X-SA-Exim-Connect-IP: 2001:67c:670:100:1d::28 -X-SA-Exim-Mail-From: sha@pengutronix.de -X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); - SAEximRunCond expanded to false -X-PTX-Original-Recipient: linux-rockchip@lists.infradead.org -X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 -X-CRM114-CacheID: sfid-20211220_030718_534274_9B6345AC -X-CRM114-Status: GOOD ( 10.57 ) -X-BeenThere: linux-rockchip@lists.infradead.org -X-Mailman-Version: 2.1.34 -Precedence: list -List-Id: Upstream kernel work for Rockchip platforms - -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Sender: "Linux-rockchip" -Errors-To: - linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org - -"vpll" is a misnomer. A clock input to a device should be named after -the usage in the device, not after the clock that drives it. On the -rk3568 the same clock is driven by the HPLL. -To fix that, this patch renames the vpll clock to ref clock. - -Signed-off-by: Sascha Hauer ---- - .../bindings/display/rockchip/rockchip,dw-hdmi.yaml | 7 ++++--- - 1 file changed, 4 insertions(+), 3 deletions(-) - -diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml -index 6e09dd2ee05ac..3b40219e3ea60 100644 ---- a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml -+++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml -@@ -47,11 +47,12 @@ properties: - - enum: - - cec - - grf -- - vpll -+ - ref - - enum: - - grf -- - vpll -- - const: vpll -+ - ref -+ - const: -+ - ref - - ddc-i2c-bus: - $ref: /schemas/types.yaml#/definitions/phandle -From patchwork Mon Dec 20 11:06:17 2021 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Sascha Hauer -X-Patchwork-Id: 12687591 -Return-Path: - -X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on - aws-us-west-2-korg-lkml-1.web.codeaurora.org -Received: from bombadil.infradead.org (bombadil.infradead.org - [198.137.202.133]) - (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) - (No client certificate requested) - by smtp.lore.kernel.org (Postfix) with ESMTPS id 28BBEC433F5 - for ; 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Mon, 20 Dec 2021 11:12:10 +0000 -Received: from metis.ext.pengutronix.de - ([2001:67c:670:201:290:27ff:fe1d:cc33]) - by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) - id 1mzGVQ-001oHz-4c - for linux-rockchip@lists.infradead.org; Mon, 20 Dec 2021 11:07:05 +0000 -Received: from dude02.hi.pengutronix.de ([2001:67c:670:100:1d::28]) - by metis.ext.pengutronix.de with esmtps - (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) - (envelope-from ) - id 1mzGVE-0004x8-DL; Mon, 20 Dec 2021 12:06:48 +0100 -Received: from sha by dude02.hi.pengutronix.de with local (Exim 4.94.2) - (envelope-from ) - id 1mzGVA-00EmEM-LY; Mon, 20 Dec 2021 12:06:44 +0100 -From: Sascha Hauer -To: dri-devel@lists.freedesktop.org -Cc: linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, - devicetree@vger.kernel.org, kernel@pengutronix.de, - Andy Yan , - Benjamin Gaignard , - Michael Riesch , - Sandy Huang , - =?utf-8?q?Heiko_St=C3=BCbner?= , - Peter Geis , Sascha Hauer -Subject: [PATCH 09/22] dt-bindings: display: rockchip: dw-hdmi: Add regulator - support -Date: Mon, 20 Dec 2021 12:06:17 +0100 -Message-Id: <20211220110630.3521121-10-s.hauer@pengutronix.de> -X-Mailer: git-send-email 2.30.2 -In-Reply-To: <20211220110630.3521121-1-s.hauer@pengutronix.de> -References: <20211220110630.3521121-1-s.hauer@pengutronix.de> -MIME-Version: 1.0 -X-SA-Exim-Connect-IP: 2001:67c:670:100:1d::28 -X-SA-Exim-Mail-From: sha@pengutronix.de -X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); - SAEximRunCond expanded to false -X-PTX-Original-Recipient: linux-rockchip@lists.infradead.org -X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 -X-CRM114-CacheID: sfid-20211220_030700_208701_F758DB20 -X-CRM114-Status: UNSURE ( 9.66 ) -X-CRM114-Notice: Please train this message. -X-BeenThere: linux-rockchip@lists.infradead.org -X-Mailman-Version: 2.1.34 -Precedence: list -List-Id: Upstream kernel work for Rockchip platforms - -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Sender: "Linux-rockchip" -Errors-To: - linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org - -Signed-off-by: Sascha Hauer ---- - .../bindings/display/rockchip/rockchip,dw-hdmi.yaml | 11 +++++++++++ - 1 file changed, 11 insertions(+) - -diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml -index 3b40219e3ea60..bf8618b26721a 100644 ---- a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml -+++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml -@@ -28,6 +28,17 @@ properties: - reg-io-width: - const: 4 + avdd-0v9-supply: + description: @@ -568,108 +64,6 @@ index 3b40219e3ea60..bf8618b26721a 100644 clocks: minItems: 2 items: -From patchwork Mon Dec 20 11:06:18 2021 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Sascha Hauer -X-Patchwork-Id: 12687537 -Return-Path: - -X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on - aws-us-west-2-korg-lkml-1.web.codeaurora.org -Received: from bombadil.infradead.org (bombadil.infradead.org - [198.137.202.133]) - (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) - (No client certificate requested) - by smtp.lore.kernel.org (Postfix) with ESMTPS id 0A241C433FE - for ; - Mon, 20 Dec 2021 11:10:07 +0000 (UTC) -DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; - d=lists.infradead.org; s=bombadil.20210309; h=Sender: - Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: - List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: - Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: - Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: - List-Owner; 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Mon, 20 Dec 2021 12:06:51 +0100 -Received: from sha by dude02.hi.pengutronix.de with local (Exim 4.94.2) - (envelope-from ) - id 1mzGVA-00EmEP-MA; Mon, 20 Dec 2021 12:06:44 +0100 -From: Sascha Hauer -To: dri-devel@lists.freedesktop.org -Cc: linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, - devicetree@vger.kernel.org, kernel@pengutronix.de, - Andy Yan , - Benjamin Gaignard , - Michael Riesch , - Sandy Huang , - =?utf-8?q?Heiko_St=C3=BCbner?= , - Peter Geis , Sascha Hauer -Subject: [PATCH 10/22] dt-bindings: display: rockchip: dw-hdmi: Add additional - clock -Date: Mon, 20 Dec 2021 12:06:18 +0100 -Message-Id: <20211220110630.3521121-11-s.hauer@pengutronix.de> -X-Mailer: git-send-email 2.30.2 -In-Reply-To: <20211220110630.3521121-1-s.hauer@pengutronix.de> -References: <20211220110630.3521121-1-s.hauer@pengutronix.de> -MIME-Version: 1.0 -X-SA-Exim-Connect-IP: 2001:67c:670:100:1d::28 -X-SA-Exim-Mail-From: sha@pengutronix.de -X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); - SAEximRunCond expanded to false -X-PTX-Original-Recipient: linux-rockchip@lists.infradead.org -X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 -X-CRM114-CacheID: sfid-20211220_030654_389202_A66FCD61 -X-CRM114-Status: GOOD ( 12.28 ) -X-BeenThere: linux-rockchip@lists.infradead.org -X-Mailman-Version: 2.1.34 -Precedence: list -List-Id: Upstream kernel work for Rockchip platforms - -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Sender: "Linux-rockchip" -Errors-To: - linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org - -The rk3568 HDMI has an additional clock that needs to be enabled for the -HDMI controller to work. The purpose of that clock is not clear. It is -named "hclk" in the downstream driver, so use the same name. - -Signed-off-by: Sascha Hauer ---- - .../bindings/display/rockchip/rockchip,dw-hdmi.yaml | 10 ++++++++-- - 1 file changed, 8 insertions(+), 2 deletions(-) - -diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml -index bf8618b26721a..a50ebf24b7f93 100644 ---- a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml -+++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml -@@ -44,11 +44,12 @@ properties: - items: - {} - {} - # The next three clocks are all optional, but shall be specified in this @@ -677,145 +71,84 @@ index bf8618b26721a..a50ebf24b7f93 100644 # order when present. - description: The HDMI CEC controller main clock - description: Power for GRF IO - - description: External clock for some HDMI PHY +- - description: External clock for some HDMI PHY ++ - description: External clock for some HDMI PHY (old clock name, deprecated) ++ - description: External clock for some HDMI PHY (new name) + - description: hclk clock-names: minItems: 2 -@@ -59,11 +60,16 @@ properties: +@@ -47,10 +61,18 @@ properties: - cec - grf - - ref + - vpll ++ - ref + - hclk - enum: - grf - - ref -- - const: + - vpll +- - const: vpll ++ - ref + - hclk + - enum: - - ref -+ - hclk -+ - const: ++ - vpll ++ - ref + - hclk ++ - const: hclk ddc-i2c-bus: $ref: /schemas/types.yaml#/definitions/phandle -From patchwork Mon Dec 20 11:06:19 2021 -Content-Type: text/plain; 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Mon, 20 Dec 2021 12:06:44 +0100 -From: Sascha Hauer -To: dri-devel@lists.freedesktop.org -Cc: linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, - devicetree@vger.kernel.org, kernel@pengutronix.de, - Andy Yan , - Benjamin Gaignard , - Michael Riesch , - Sandy Huang , - =?utf-8?q?Heiko_St=C3=BCbner?= , - Peter Geis , Sascha Hauer -Subject: [PATCH 11/22] dt-bindings: display: rockchip: Add binding for VOP2 -Date: Mon, 20 Dec 2021 12:06:19 +0100 -Message-Id: <20211220110630.3521121-12-s.hauer@pengutronix.de> -X-Mailer: git-send-email 2.30.2 -In-Reply-To: <20211220110630.3521121-1-s.hauer@pengutronix.de> -References: <20211220110630.3521121-1-s.hauer@pengutronix.de> -MIME-Version: 1.0 -X-SA-Exim-Connect-IP: 2001:67c:670:100:1d::28 -X-SA-Exim-Mail-From: sha@pengutronix.de -X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); - SAEximRunCond expanded to false -X-PTX-Original-Recipient: linux-rockchip@lists.infradead.org -X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 -X-CRM114-CacheID: sfid-20211220_110715_583359_1820B567 -X-CRM114-Status: GOOD ( 15.76 ) -X-BeenThere: linux-rockchip@lists.infradead.org -X-Mailman-Version: 2.1.34 -Precedence: list -List-Id: Upstream kernel work for Rockchip platforms - -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Sender: "Linux-rockchip" -Errors-To: - linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org - -The VOP2 is found on newer Rockchip SoCs like the rk3568 or the rk3566. -The binding differs slightly from the existing VOP binding, so add a new -binding file for it. - -Signed-off-by: Sascha Hauer ---- - .../display/rockchip/rockchip-vop2.yaml | 146 ++++++++++++++++++ - 1 file changed, 146 insertions(+) - create mode 100644 Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml - +@@ -72,6 +94,7 @@ properties: + The unwedge pinctrl entry shall drive the DDC SDA line low. This is + intended to work around a hardware errata that can cause the DDC I2C + bus to be wedged. ++ minItems: 1 + items: + - const: default + - const: unwedge +@@ -79,27 +102,21 @@ properties: + ports: + $ref: /schemas/graph.yaml#/properties/ports + +- properties: +- port: +- $ref: /schemas/graph.yaml#/$defs/port-base +- unevaluatedProperties: false ++ patternProperties: ++ "^port(@0)?$": ++ $ref: /schemas/graph.yaml#/properties/port + description: Input of the DWC HDMI TX +- + properties: ++ endpoint: ++ description: Connection to the VOP + endpoint@0: +- $ref: /schemas/graph.yaml#/properties/endpoint + description: Connection to the VOPB +- + endpoint@1: +- $ref: /schemas/graph.yaml#/properties/endpoint + description: Connection to the VOPL +- +- required: +- - endpoint@0 +- - endpoint@1 +- +- required: +- - port ++ properties: ++ port@1: ++ $ref: /schemas/graph.yaml#/properties/port ++ description: Output of the DWC HDMI TX + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml new file mode 100644 -index 0000000000000..df14d5aa85c85 +index 000000000000..655d9b327f7d --- /dev/null +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml -@@ -0,0 +1,146 @@ +@@ -0,0 +1,140 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- @@ -865,8 +198,8 @@ index 0000000000000..df14d5aa85c85 + + clock-names: + items: -+ - const: aclk_vop -+ - const: hclk_vop ++ - const: aclk ++ - const: hclk + - const: dclk_vp0 + - const: dclk_vp1 + - const: dclk_vp2 @@ -877,7 +210,7 @@ index 0000000000000..df14d5aa85c85 + Phandle to GRF regs used for misc control + + ports: -+ $ref: /schemas/graph.yaml#/properties/port ++ $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: @@ -890,17 +223,11 @@ index 0000000000000..df14d5aa85c85 + description: + Output endpoint of VP1 + -+ port@: ++ port@2: + $ref: /schemas/graph.yaml#/properties/port + description: + Output endpoint of VP2 + -+ assigned-clocks: true -+ -+ assigned-clock-rates: true -+ -+ assigned-clock-parents: true -+ + iommus: + maxItems: 1 + @@ -928,14 +255,15 @@ index 0000000000000..df14d5aa85c85 + vop: vop@fe040000 { + compatible = "rockchip,rk3568-vop"; + reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>; ++ reg-names = "regs", "gamma_lut"; + interrupts = ; + clocks = <&cru ACLK_VOP>, + <&cru HCLK_VOP>, + <&cru DCLK_VOP0>, + <&cru DCLK_VOP1>, + <&cru DCLK_VOP2>; -+ clock-names = "aclk_vop", -+ "hclk_vop", ++ clock-names = "aclk", ++ "hclk", + "dclk_vp0", + "dclk_vp1", + "dclk_vp2"; @@ -962,342 +290,97 @@ index 0000000000000..df14d5aa85c85 + }; + }; + }; -From patchwork Mon Dec 20 11:06:20 2021 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Sascha Hauer -X-Patchwork-Id: 12687627 -Return-Path: - -X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on - aws-us-west-2-korg-lkml-1.web.codeaurora.org -Received: from bombadil.infradead.org (bombadil.infradead.org - [198.137.202.133]) - (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) - (No client certificate requested) - by smtp.lore.kernel.org (Postfix) with ESMTPS id 1EA65C433F5 - for ; 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Mon, 20 Dec 2021 11:07:24 +0000 -Received: from dude02.hi.pengutronix.de ([2001:67c:670:100:1d::28]) - by metis.ext.pengutronix.de with esmtps - (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) - (envelope-from ) - id 1mzGVE-0004xB-DX; Mon, 20 Dec 2021 12:06:48 +0100 -Received: from sha by dude02.hi.pengutronix.de with local (Exim 4.94.2) - (envelope-from ) - id 1mzGVA-00EmEV-NS; Mon, 20 Dec 2021 12:06:44 +0100 -From: Sascha Hauer -To: dri-devel@lists.freedesktop.org -Cc: linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, - devicetree@vger.kernel.org, kernel@pengutronix.de, - Andy Yan , - Benjamin Gaignard , - Michael Riesch , - Sandy Huang , - =?utf-8?q?Heiko_St=C3=BCbner?= , - Peter Geis , Sascha Hauer -Subject: [PATCH 12/22] arm64: dts: rockchip: rk3399: reorder hmdi clocks -Date: Mon, 20 Dec 2021 12:06:20 +0100 -Message-Id: <20211220110630.3521121-13-s.hauer@pengutronix.de> -X-Mailer: git-send-email 2.30.2 -In-Reply-To: <20211220110630.3521121-1-s.hauer@pengutronix.de> -References: <20211220110630.3521121-1-s.hauer@pengutronix.de> -MIME-Version: 1.0 -X-SA-Exim-Connect-IP: 2001:67c:670:100:1d::28 -X-SA-Exim-Mail-From: sha@pengutronix.de -X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); - SAEximRunCond expanded to false -X-PTX-Original-Recipient: linux-rockchip@lists.infradead.org -X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 -X-CRM114-CacheID: sfid-20211220_110723_153685_D07DE51E -X-CRM114-Status: GOOD ( 10.45 ) -X-BeenThere: linux-rockchip@lists.infradead.org -X-Mailman-Version: 2.1.34 -Precedence: list -List-Id: Upstream kernel work for Rockchip platforms - -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Sender: "Linux-rockchip" -Errors-To: - linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org - -The binding specifies the clock order to "cec", "grf", "vpll". Reorder -the clocks accordingly. - -Signed-off-by: Sascha Hauer ---- - arch/arm64/boot/dts/rockchip/rk3399.dtsi | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -index d3cdf6f42a303..080457a68e3c7 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -@@ -1881,10 +1881,10 @@ hdmi: hdmi@ff940000 { - interrupts = ; - clocks = <&cru PCLK_HDMI_CTRL>, - <&cru SCLK_HDMI_SFR>, -- <&cru PLL_VPLL>, -+ <&cru SCLK_HDMI_CEC>, - <&cru PCLK_VIO_GRF>, -- <&cru SCLK_HDMI_CEC>; -- clock-names = "iahb", "isfr", "vpll", "grf", "cec"; -+ <&cru PLL_VPLL>; -+ clock-names = "iahb", "isfr", "cec", "grf", "vpll"; - power-domains = <&power RK3399_PD_HDCP>; - reg-io-width = <4>; - rockchip,grf = <&grf>; -From patchwork Mon Dec 20 11:06:21 2021 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Sascha Hauer -X-Patchwork-Id: 12687603 -Return-Path: - -X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on - aws-us-west-2-korg-lkml-1.web.codeaurora.org -Received: from bombadil.infradead.org (bombadil.infradead.org - [198.137.202.133]) - (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) - (No client certificate requested) - by smtp.lore.kernel.org (Postfix) with ESMTPS id 9D131C433F5 - for ; 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Mon, 20 Dec 2021 11:14:23 +0000 -Received: from metis.ext.pengutronix.de - ([2001:67c:670:201:290:27ff:fe1d:cc33]) - by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) - id 1mzGVS-001oJz-AQ - for linux-rockchip@lists.infradead.org; Mon, 20 Dec 2021 11:07:09 +0000 -Received: from dude02.hi.pengutronix.de ([2001:67c:670:100:1d::28]) - by metis.ext.pengutronix.de with esmtps - (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) - (envelope-from ) - id 1mzGVH-0004xC-7t; Mon, 20 Dec 2021 12:06:51 +0100 -Received: from sha by dude02.hi.pengutronix.de with local (Exim 4.94.2) - (envelope-from ) - id 1mzGVA-00EmEY-O0; Mon, 20 Dec 2021 12:06:44 +0100 -From: Sascha Hauer -To: dri-devel@lists.freedesktop.org -Cc: linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, - devicetree@vger.kernel.org, kernel@pengutronix.de, - Andy Yan , - Benjamin Gaignard , - Michael Riesch , - Sandy Huang , - =?utf-8?q?Heiko_St=C3=BCbner?= , - Peter Geis , Sascha Hauer -Subject: [PATCH 13/22] arm64: dts: rockchip: rk3399: rename HDMI ref clock to - 'ref' -Date: Mon, 20 Dec 2021 12:06:21 +0100 -Message-Id: <20211220110630.3521121-14-s.hauer@pengutronix.de> -X-Mailer: git-send-email 2.30.2 -In-Reply-To: <20211220110630.3521121-1-s.hauer@pengutronix.de> -References: <20211220110630.3521121-1-s.hauer@pengutronix.de> -MIME-Version: 1.0 -X-SA-Exim-Connect-IP: 2001:67c:670:100:1d::28 -X-SA-Exim-Mail-From: sha@pengutronix.de -X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); - SAEximRunCond expanded to false -X-PTX-Original-Recipient: linux-rockchip@lists.infradead.org -X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 -X-CRM114-CacheID: sfid-20211220_030702_396354_9A505BE5 -X-CRM114-Status: GOOD ( 12.24 ) -X-BeenThere: linux-rockchip@lists.infradead.org -X-Mailman-Version: 2.1.34 -Precedence: list -List-Id: Upstream kernel work for Rockchip platforms - -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Sender: "Linux-rockchip" -Errors-To: - linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org - -The reference clock for the HDMI controller has been renamed to 'ref', -the previous 'vpll' name is only left for compatibility in the driver. -Rename the clock to the new name. - -Signed-off-by: Sascha Hauer ---- - arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -index 080457a68e3c7..d0add619b0d22 100644 +index d3cdf6f42a30..426c4333bc7f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1884,7 +1884,7 @@ hdmi: hdmi@ff940000 { - <&cru SCLK_HDMI_CEC>, + <&cru PLL_VPLL>, <&cru PCLK_VIO_GRF>, - <&cru PLL_VPLL>; -- clock-names = "iahb", "isfr", "cec", "grf", "vpll"; + <&cru SCLK_HDMI_CEC>; +- clock-names = "iahb", "isfr", "vpll", "grf", "cec"; + clock-names = "iahb", "isfr", "cec", "grf", "ref"; power-domains = <&power RK3399_PD_HDCP>; reg-io-width = <4>; rockchip,grf = <&grf>; -From patchwork Mon Dec 20 11:06:22 2021 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Sascha Hauer -X-Patchwork-Id: 12687601 -Return-Path: - -X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on - aws-us-west-2-korg-lkml-1.web.codeaurora.org -Received: from bombadil.infradead.org (bombadil.infradead.org - [198.137.202.133]) - (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) - (No client certificate requested) - by smtp.lore.kernel.org (Postfix) with ESMTPS id D8D28C433EF - for ; - Mon, 20 Dec 2021 11:14:22 +0000 (UTC) -DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; - d=lists.infradead.org; s=bombadil.20210309; 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Mon, 20 Dec 2021 11:07:07 +0000 -Received: from dude02.hi.pengutronix.de ([2001:67c:670:100:1d::28]) - by metis.ext.pengutronix.de with esmtps - (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) - (envelope-from ) - id 1mzGVE-0004xD-DJ; Mon, 20 Dec 2021 12:06:48 +0100 -Received: from sha by dude02.hi.pengutronix.de with local (Exim 4.94.2) - (envelope-from ) - id 1mzGVA-00EmEb-Oi; Mon, 20 Dec 2021 12:06:44 +0100 -From: Sascha Hauer -To: dri-devel@lists.freedesktop.org -Cc: linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, - devicetree@vger.kernel.org, kernel@pengutronix.de, - Andy Yan , - Benjamin Gaignard , - Michael Riesch , - Sandy Huang , - =?utf-8?q?Heiko_St=C3=BCbner?= , - Peter Geis , Sascha Hauer -Subject: [PATCH 14/22] arm64: dts: rockchip: rk356x: Add VOP2 nodes -Date: Mon, 20 Dec 2021 12:06:22 +0100 -Message-Id: <20211220110630.3521121-15-s.hauer@pengutronix.de> -X-Mailer: git-send-email 2.30.2 -In-Reply-To: <20211220110630.3521121-1-s.hauer@pengutronix.de> -References: <20211220110630.3521121-1-s.hauer@pengutronix.de> -MIME-Version: 1.0 -X-SA-Exim-Connect-IP: 2001:67c:670:100:1d::28 -X-SA-Exim-Mail-From: sha@pengutronix.de -X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); - SAEximRunCond expanded to false -X-PTX-Original-Recipient: linux-rockchip@lists.infradead.org -X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 -X-CRM114-CacheID: sfid-20211220_030700_333528_4AD47181 -X-CRM114-Status: GOOD ( 16.00 ) -X-BeenThere: linux-rockchip@lists.infradead.org -X-Mailman-Version: 2.1.34 -Precedence: list -List-Id: Upstream kernel work for Rockchip platforms - -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Sender: "Linux-rockchip" -Errors-To: - linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org - -The VOP2 is the display output controller on the RK3568. Add the node -for it to the dtsi file along with the required display-subsystem node -and the iommu node. - -Signed-off-by: Sascha Hauer ---- - arch/arm64/boot/dts/rockchip/rk3566.dtsi | 4 ++ - arch/arm64/boot/dts/rockchip/rk3568.dtsi | 4 ++ - arch/arm64/boot/dts/rockchip/rk356x.dtsi | 50 ++++++++++++++++++++++++ - include/dt-bindings/soc/rockchip,vop2.h | 14 +++++++ - 4 files changed, 72 insertions(+) - create mode 100644 include/dt-bindings/soc/rockchip,vop2.h - +diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts +index 4d4b2a301b1a..d8640a9be12f 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts +@@ -4,6 +4,7 @@ + + #include + #include ++#include + #include "rk3566.dtsi" + + / { +@@ -35,6 +36,17 @@ fan: gpio_fan { + #cooling-cells = <2>; + }; + ++ hdmi-con { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi_con_in: endpoint { ++ remote-endpoint = <&hdmi_out_con>; ++ }; ++ }; ++ }; ++ + leds { + compatible = "gpio-leds"; + +@@ -205,6 +217,24 @@ &gmac1m0_clkinout + status = "okay"; + }; + ++&hdmi { ++ avdd-0v9-supply = <&vdda_0v9>; ++ avdd-1v8-supply = <&vcc_1v8>; ++ status = "okay"; ++}; ++ ++&hdmi_in { ++ hdmi_in_vp0: endpoint { ++ remote-endpoint = <&vp0_out_hdmi>; ++ }; ++}; ++ ++&hdmi_out { ++ hdmi_out_con: endpoint { ++ remote-endpoint = <&hdmi_con_in>; ++ }; ++}; ++ + &i2c0 { + status = "okay"; + +@@ -546,3 +576,20 @@ bluetooth { + &uart2 { + status = "okay"; + }; ++ ++&vop { ++ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; ++ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; ++ status = "okay"; ++}; ++ ++&vop_mmu { ++ status = "okay"; ++}; ++ ++&vp0 { ++ vp0_out_hdmi: endpoint@RK3568_VOP2_EP_HDMI { ++ reg = ; ++ remote-endpoint = <&hdmi_in_vp0>; ++ }; ++}; diff --git a/arch/arm64/boot/dts/rockchip/rk3566.dtsi b/arch/arm64/boot/dts/rockchip/rk3566.dtsi -index 3839eef5e4f76..595fa2562cb8e 100644 +index 3839eef5e4f7..595fa2562cb8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3566.dtsi @@ -18,3 +18,7 @@ power-domain@RK3568_PD_PIPE { @@ -1308,8 +391,84 @@ index 3839eef5e4f76..595fa2562cb8e 100644 +&vop { + compatible = "rockchip,rk3566-vop"; +}; +diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts +index 184e2aa2416a..cd4e01c7994c 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts +@@ -7,6 +7,7 @@ + /dts-v1/; + #include + #include ++#include + #include "rk3568.dtsi" + + / { +@@ -33,6 +34,17 @@ dc_12v: dc-12v { + regulator-max-microvolt = <12000000>; + }; + ++ hdmi-con { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi_con_in: endpoint { ++ remote-endpoint = <&hdmi_out_con>; ++ }; ++ }; ++ }; ++ + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; +@@ -106,6 +118,24 @@ &gmac1m1_rgmii_clk + status = "okay"; + }; + ++&hdmi { ++ avdd-0v9-supply = <&vdda0v9_image>; ++ avdd-1v8-supply = <&vcca1v8_image>; ++ status = "okay"; ++}; ++ ++&hdmi_in { ++ hdmi_in_vp0: endpoint { ++ remote-endpoint = <&vp0_out_hdmi>; ++ }; ++}; ++ ++&hdmi_out { ++ hdmi_out_con: endpoint { ++ remote-endpoint = <&hdmi_con_in>; ++ }; ++}; ++ + &i2c0 { + status = "okay"; + +@@ -390,3 +420,20 @@ &sdmmc0 { + &uart2 { + status = "okay"; + }; ++ ++&vop { ++ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; ++ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; ++ status = "okay"; ++}; ++ ++&vop_mmu { ++ status = "okay"; ++}; ++ ++&vp0 { ++ vp0_out_hdmi: endpoint@RK3568_VOP2_EP_HDMI { ++ reg = ; ++ remote-endpoint = <&hdmi_in_vp0>; ++ }; ++}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi -index 2fd313a295f8a..1e55efb6fcfde 100644 +index 2fd313a295f8..1e55efb6fcfd 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi @@ -95,3 +95,7 @@ power-domain@RK3568_PD_PIPE { @@ -1321,18 +480,10 @@ index 2fd313a295f8a..1e55efb6fcfde 100644 + compatible = "rockchip,rk3568-vop"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi -index 46d9552f60284..7c62ad921cf7b 100644 +index 46d9552f6028..cf62bce06695 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi -@@ -10,6 +10,7 @@ - #include - #include - #include -+#include - #include - - / { -@@ -125,6 +126,11 @@ opp-1800000000 { +@@ -125,6 +125,11 @@ opp-1800000000 { }; }; @@ -1344,15 +495,17 @@ index 46d9552f60284..7c62ad921cf7b 100644 firmware { scmi: scmi { compatible = "arm,scmi-smc"; -@@ -447,6 +453,50 @@ gmac1_mtl_tx_setup: tx-queues-config { +@@ -447,6 +452,84 @@ gmac1_mtl_tx_setup: tx-queues-config { }; }; + vop: vop@fe040000 { -+ reg = <0x0 0xfe040000 0x0 0x5000>; ++ reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>; ++ reg-names = "regs", "gamma_lut"; + interrupts = ; -+ clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>, <&cru DCLK_VOP0>, <&cru DCLK_VOP1>, <&cru DCLK_VOP2>; -+ clock-names = "aclk_vop", "hclk_vop", "dclk_vp0", "dclk_vp1", "dclk_vp2"; ++ clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>, <&cru DCLK_VOP0>, ++ <&cru DCLK_VOP1>, <&cru DCLK_VOP2>; ++ clock-names = "aclk", "hclk", "dclk_vp0", "dclk_vp1", "dclk_vp2"; + iommus = <&vop_mmu>; + power-domains = <&power RK3568_PD_VO>; + rockchip,grf = <&grf>; @@ -1392,152 +545,6 @@ index 46d9552f60284..7c62ad921cf7b 100644 + status = "disabled"; + }; + - qos_gpu: qos@fe128000 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe128000 0x0 0x20>; -diff --git a/include/dt-bindings/soc/rockchip,vop2.h b/include/dt-bindings/soc/rockchip,vop2.h -new file mode 100644 -index 0000000000000..0a87bc90564a7 ---- /dev/null -+++ b/include/dt-bindings/soc/rockchip,vop2.h -@@ -0,0 +1,14 @@ -+/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ -+ -+#ifndef __DT_BINDINGS_ROCKCHIP_VOP2_H -+#define __DT_BINDINGS_ROCKCHIP_VOP2_H -+ -+#define RK3568_VOP2_EP_RGB 0 -+#define RK3568_VOP2_EP_HDMI 1 -+#define RK3568_VOP2_EP_EDP 2 -+#define RK3568_VOP2_EP_MIPI0 3 -+#define RK3568_VOP2_EP_LVDS0 4 -+#define RK3568_VOP2_EP_MIPI1 5 -+#define RK3568_VOP2_EP_LVDS1 6 -+ -+#endif /* __DT_BINDINGS_ROCKCHIP_VOP2_H */ -From patchwork Mon Dec 20 11:06:23 2021 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Sascha Hauer -X-Patchwork-Id: 12687629 -Return-Path: - -X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on - aws-us-west-2-korg-lkml-1.web.codeaurora.org -Received: from bombadil.infradead.org (bombadil.infradead.org - [198.137.202.133]) - (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) - (No client certificate requested) - by smtp.lore.kernel.org (Postfix) with ESMTPS id 671DBC433F5 - for ; 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Mon, 20 Dec 2021 11:07:58 +0000 -Received: from dude02.hi.pengutronix.de ([2001:67c:670:100:1d::28]) - by metis.ext.pengutronix.de with esmtps - (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) - (envelope-from ) - id 1mzGVE-0004xE-DO; Mon, 20 Dec 2021 12:06:48 +0100 -Received: from sha by dude02.hi.pengutronix.de with local (Exim 4.94.2) - (envelope-from ) - id 1mzGVA-00EmEe-PK; Mon, 20 Dec 2021 12:06:44 +0100 -From: Sascha Hauer -To: dri-devel@lists.freedesktop.org -Cc: linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, - devicetree@vger.kernel.org, kernel@pengutronix.de, - Andy Yan , - Benjamin Gaignard , - Michael Riesch , - Sandy Huang , - =?utf-8?q?Heiko_St=C3=BCbner?= , - Peter Geis , Sascha Hauer -Subject: [PATCH 15/22] arm64: dts: rockchip: rk356x: Add HDMI nodes -Date: Mon, 20 Dec 2021 12:06:23 +0100 -Message-Id: <20211220110630.3521121-16-s.hauer@pengutronix.de> -X-Mailer: git-send-email 2.30.2 -In-Reply-To: <20211220110630.3521121-1-s.hauer@pengutronix.de> -References: <20211220110630.3521121-1-s.hauer@pengutronix.de> -MIME-Version: 1.0 -X-SA-Exim-Connect-IP: 2001:67c:670:100:1d::28 -X-SA-Exim-Mail-From: sha@pengutronix.de -X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); - SAEximRunCond expanded to false -X-PTX-Original-Recipient: linux-rockchip@lists.infradead.org -X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 -X-CRM114-CacheID: sfid-20211220_110715_699469_0B58CEC6 -X-CRM114-Status: GOOD ( 12.33 ) -X-BeenThere: linux-rockchip@lists.infradead.org -X-Mailman-Version: 2.1.34 -Precedence: list -List-Id: Upstream kernel work for Rockchip platforms - -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Sender: "Linux-rockchip" -Errors-To: - linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org - -Add support for the HDMI port found on RK3568. - -Signed-off-by: Sascha Hauer ---- - arch/arm64/boot/dts/rockchip/rk356x.dtsi | 37 +++++++++++++++++++++++- - 1 file changed, 36 insertions(+), 1 deletion(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi -index 7c62ad921cf7b..6d93b8fcee179 100644 ---- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi -@@ -10,7 +10,6 @@ - #include - #include - #include --#include - #include - - / { -@@ -497,6 +496,42 @@ vop_mmu: iommu@fe043e00 { - status = "disabled"; - }; - + hdmi: hdmi@fe0a0000 { + compatible = "rockchip,rk3568-dw-hdmi"; + reg = <0x0 0xfe0a0000 0x0 0x20000>; @@ -1562,14 +569,10 @@ index 7c62ad921cf7b..6d93b8fcee179 100644 + + hdmi_in: port@0 { + reg = <0>; -+ #address-cells = <1>; -+ #size-cells = <0>; + }; + + hdmi_out: port@1 { + reg = <1>; -+ #address-cells = <1>; -+ #size-cells = <0>; + }; + }; + }; @@ -1577,840 +580,11 @@ index 7c62ad921cf7b..6d93b8fcee179 100644 qos_gpu: qos@fe128000 { compatible = "rockchip,rk3568-qos", "syscon"; reg = <0x0 0xfe128000 0x0 0x20>; -From patchwork Mon Dec 20 11:06:24 2021 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Sascha Hauer -X-Patchwork-Id: 12687535 -Return-Path: - -X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on - aws-us-west-2-korg-lkml-1.web.codeaurora.org -Received: from bombadil.infradead.org (bombadil.infradead.org - [198.137.202.133]) - (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) - (No client certificate requested) - by smtp.lore.kernel.org (Postfix) with ESMTPS id CDFD2C433EF - for ; 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Mon, 20 Dec 2021 11:08:31 +0000 -Received: from metis.ext.pengutronix.de - ([2001:67c:670:201:290:27ff:fe1d:cc33]) - by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) - id 1mzGVI-001oAu-1Y - for linux-rockchip@lists.infradead.org; Mon, 20 Dec 2021 11:06:54 +0000 -Received: from dude02.hi.pengutronix.de ([2001:67c:670:100:1d::28]) - by metis.ext.pengutronix.de with esmtps - (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) - (envelope-from ) - id 1mzGVE-0004xF-DY; Mon, 20 Dec 2021 12:06:48 +0100 -Received: from sha by dude02.hi.pengutronix.de with local (Exim 4.94.2) - (envelope-from ) - id 1mzGVA-00EmEh-Ps; Mon, 20 Dec 2021 12:06:44 +0100 -From: Sascha Hauer -To: dri-devel@lists.freedesktop.org -Cc: linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, - devicetree@vger.kernel.org, kernel@pengutronix.de, - Andy Yan , - Benjamin Gaignard , - Michael Riesch , - Sandy Huang , - =?utf-8?q?Heiko_St=C3=BCbner?= , - Peter Geis , Sascha Hauer -Subject: [PATCH 16/22] arm64: dts: rockchip: rk3568-evb: Enable VOP2 and hdmi -Date: Mon, 20 Dec 2021 12:06:24 +0100 -Message-Id: <20211220110630.3521121-17-s.hauer@pengutronix.de> -X-Mailer: git-send-email 2.30.2 -In-Reply-To: <20211220110630.3521121-1-s.hauer@pengutronix.de> -References: <20211220110630.3521121-1-s.hauer@pengutronix.de> -MIME-Version: 1.0 -X-SA-Exim-Connect-IP: 2001:67c:670:100:1d::28 -X-SA-Exim-Mail-From: sha@pengutronix.de -X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); - SAEximRunCond expanded to false -X-PTX-Original-Recipient: linux-rockchip@lists.infradead.org -X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 -X-CRM114-CacheID: sfid-20211220_030652_125345_05F20D59 -X-CRM114-Status: GOOD ( 12.02 ) -X-BeenThere: linux-rockchip@lists.infradead.org -X-Mailman-Version: 2.1.34 -Precedence: list -List-Id: Upstream kernel work for Rockchip platforms - -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Sender: "Linux-rockchip" -Errors-To: - linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org - -This enabled the VOP2 display controller along with hdmi and the -required port routes which is enough to get a picture out of the -hdmi port of the board. - -Signed-off-by: Sascha Hauer ---- - .../boot/dts/rockchip/rk3568-evb1-v10.dts | 48 +++++++++++++++++++ - 1 file changed, 48 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts -index 184e2aa2416af..3fa0e654d7cf6 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts -@@ -7,6 +7,7 @@ - /dts-v1/; - #include - #include -+#include - #include "rk3568.dtsi" - - / { -@@ -33,6 +34,17 @@ dc_12v: dc-12v { - regulator-max-microvolt = <12000000>; - }; - -+ hdmi-con { -+ compatible = "hdmi-connector"; -+ type = "c"; -+ -+ port { -+ hdmi_con_in: endpoint { -+ remote-endpoint = <&hdmi_out_con>; -+ }; -+ }; -+ }; -+ - vcc3v3_sys: vcc3v3-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; -@@ -106,6 +118,12 @@ &gmac1m1_rgmii_clk - status = "okay"; - }; - -+&hdmi { -+ avdd-0v9-supply = <&vdda0v9_image>; -+ avdd-1v8-supply = <&vcca1v8_image>; -+ status = "okay"; -+}; -+ - &i2c0 { - status = "okay"; - -@@ -390,3 +408,33 @@ &sdmmc0 { - &uart2 { - status = "okay"; - }; -+ -+&vop { -+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; -+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; -+ status = "okay"; -+}; -+ -+&vop_mmu { -+ status = "okay"; -+}; -+ -+&hdmi_in { -+ hdmi_in_vp0: endpoint@0 { -+ reg = <0>; -+ remote-endpoint = <&vp0_out_hdmi>; -+ }; -+}; -+ -+&hdmi_out { -+ hdmi_out_con: endpoint { -+ remote-endpoint = <&hdmi_con_in>; -+ }; -+}; -+ -+&vp0 { -+ vp0_out_hdmi: endpoint@RK3568_VOP2_EP_HDMI { -+ reg = ; -+ remote-endpoint = <&hdmi_in_vp0>; -+ }; -+}; -From patchwork Mon Dec 20 11:06:25 2021 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Sascha Hauer -X-Patchwork-Id: 12687611 -Return-Path: - -X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on - aws-us-west-2-korg-lkml-1.web.codeaurora.org -Received: from bombadil.infradead.org (bombadil.infradead.org - [198.137.202.133]) - (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) - (No client certificate requested) - by smtp.lore.kernel.org (Postfix) with ESMTPS id B9015C433F5 - for ; - Mon, 20 Dec 2021 11:19:17 +0000 (UTC) -DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; - d=lists.infradead.org; s=bombadil.20210309; h=Sender: - Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: - List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: - Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: - Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: - List-Owner; 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Mon, 20 Dec 2021 12:06:51 +0100 -Received: from sha by dude02.hi.pengutronix.de with local (Exim 4.94.2) - (envelope-from ) - id 1mzGVA-00EmEk-QX; Mon, 20 Dec 2021 12:06:44 +0100 -From: Sascha Hauer -To: dri-devel@lists.freedesktop.org -Cc: linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, - devicetree@vger.kernel.org, kernel@pengutronix.de, - Andy Yan , - Benjamin Gaignard , - Michael Riesch , - Sandy Huang , - =?utf-8?q?Heiko_St=C3=BCbner?= , - Peter Geis , Sascha Hauer -Subject: [PATCH 17/22] arm64: dts: rockchip: enable vop2 and hdmi tx on - quartz64a -Date: Mon, 20 Dec 2021 12:06:25 +0100 -Message-Id: <20211220110630.3521121-18-s.hauer@pengutronix.de> -X-Mailer: git-send-email 2.30.2 -In-Reply-To: <20211220110630.3521121-1-s.hauer@pengutronix.de> -References: <20211220110630.3521121-1-s.hauer@pengutronix.de> -MIME-Version: 1.0 -X-SA-Exim-Connect-IP: 2001:67c:670:100:1d::28 -X-SA-Exim-Mail-From: sha@pengutronix.de -X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); - SAEximRunCond expanded to false -X-PTX-Original-Recipient: linux-rockchip@lists.infradead.org -X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 -X-CRM114-CacheID: sfid-20211220_030710_555253_6B9A03C5 -X-CRM114-Status: GOOD ( 11.67 ) -X-BeenThere: linux-rockchip@lists.infradead.org -X-Mailman-Version: 2.1.34 -Precedence: list -List-Id: Upstream kernel work for Rockchip platforms - -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Sender: "Linux-rockchip" -Errors-To: - linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org - -From: Michael Riesch - -Enable the RK356x Video Output Processor (VOP) 2 on the Pine64 -Quartz64 Model A. - -Signed-off-by: Michael Riesch -Signed-off-by: Sascha Hauer ---- - .../boot/dts/rockchip/rk3566-quartz64-a.dts | 48 +++++++++++++++++++ - 1 file changed, 48 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts -index 4d4b2a301b1a4..29748537cdbd0 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts -@@ -4,6 +4,7 @@ - - #include - #include -+#include - #include "rk3566.dtsi" - - / { -@@ -35,6 +36,17 @@ fan: gpio_fan { - #cooling-cells = <2>; - }; - -+ hdmi-con { -+ compatible = "hdmi-connector"; -+ type = "c"; -+ -+ port { -+ hdmi_con_in: endpoint { -+ remote-endpoint = <&hdmi_out_con>; -+ }; -+ }; -+ }; -+ - leds { - compatible = "gpio-leds"; - -@@ -205,6 +217,18 @@ &gmac1m0_clkinout - status = "okay"; - }; - -+&hdmi { -+ avdd-0v9-supply = <&vdda_0v9>; -+ avdd-1v8-supply = <&vcc_1v8>; -+ status = "okay"; -+}; -+ -+&hdmi_out { -+ hdmi_out_con: endpoint { -+ remote-endpoint = <&hdmi_con_in>; -+ }; -+}; -+ - &i2c0 { - status = "okay"; - -@@ -546,3 +570,27 @@ bluetooth { - &uart2 { - status = "okay"; - }; -+ -+&vop { -+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; -+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; -+ status = "okay"; -+}; -+ -+&vop_mmu { -+ status = "okay"; -+}; -+ -+&hdmi_in { -+ hdmi_in_vp0: endpoint@0 { -+ reg = <0>; -+ remote-endpoint = <&vp0_out_hdmi>; -+ }; -+}; -+ -+&vp0 { -+ vp0_out_hdmi: endpoint@RK3568_VOP2_EP_HDMI { -+ reg = ; -+ remote-endpoint = <&hdmi_in_vp0>; -+ }; -+}; -From patchwork Mon Dec 20 11:06:26 2021 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Sascha Hauer -X-Patchwork-Id: 12687543 -Return-Path: - -X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on - aws-us-west-2-korg-lkml-1.web.codeaurora.org -Received: from bombadil.infradead.org (bombadil.infradead.org - [198.137.202.133]) - (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) - (No client certificate requested) - by smtp.lore.kernel.org (Postfix) with ESMTPS id 88567C433F5 - for ; - Mon, 20 Dec 2021 11:10:11 +0000 (UTC) -DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; - d=lists.infradead.org; s=bombadil.20210309; h=Sender: - Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: - List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: - Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: - Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: - List-Owner; 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Mon, 20 Dec 2021 12:06:51 +0100 -Received: from sha by dude02.hi.pengutronix.de with local (Exim 4.94.2) - (envelope-from ) - id 1mzGVA-00EmEn-RE; Mon, 20 Dec 2021 12:06:44 +0100 -From: Sascha Hauer -To: dri-devel@lists.freedesktop.org -Cc: linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, - devicetree@vger.kernel.org, kernel@pengutronix.de, - Andy Yan , - Benjamin Gaignard , - Michael Riesch , - Sandy Huang , - =?utf-8?q?Heiko_St=C3=BCbner?= , - Peter Geis , Sascha Hauer -Subject: [PATCH 18/22] clk: rk3568: drop CLK_SET_RATE_PARENT from dclk_vop* -Date: Mon, 20 Dec 2021 12:06:26 +0100 -Message-Id: <20211220110630.3521121-19-s.hauer@pengutronix.de> -X-Mailer: git-send-email 2.30.2 -In-Reply-To: <20211220110630.3521121-1-s.hauer@pengutronix.de> -References: <20211220110630.3521121-1-s.hauer@pengutronix.de> -MIME-Version: 1.0 -X-SA-Exim-Connect-IP: 2001:67c:670:100:1d::28 -X-SA-Exim-Mail-From: sha@pengutronix.de -X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); - SAEximRunCond expanded to false -X-PTX-Original-Recipient: linux-rockchip@lists.infradead.org -X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 -X-CRM114-CacheID: sfid-20211220_030654_440482_4563C31D -X-CRM114-Status: GOOD ( 13.46 ) -X-BeenThere: linux-rockchip@lists.infradead.org -X-Mailman-Version: 2.1.34 -Precedence: list -List-Id: Upstream kernel work for Rockchip platforms - -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Sender: "Linux-rockchip" -Errors-To: - linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org - -The pixel clocks dclk_vop[012] can be clocked from hpll, vpll, gpll or -cpll. gpll and cpll also drive many other clocks, so changing the -dclk_vop[012] clocks could change these other clocks as well. Drop -CLK_SET_RATE_PARENT to fix that. With this change the VOP2 driver can -only adjust the pixel clocks with the divider between the PLL and the -dclk_vop[012] which means the user may have to adjust the PLL clock to a -suitable rate using the assigned-clock-rate device tree property. - -Signed-off-by: Sascha Hauer ---- - drivers/clk/rockchip/clk-rk3568.c | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - -diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c -index 69a9e8069a486..604a367bc498a 100644 ---- a/drivers/clk/rockchip/clk-rk3568.c -+++ b/drivers/clk/rockchip/clk-rk3568.c -@@ -1038,13 +1038,13 @@ static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = { - RK3568_CLKGATE_CON(20), 8, GFLAGS), - GATE(HCLK_VOP, "hclk_vop", "hclk_vo", 0, - RK3568_CLKGATE_CON(20), 9, GFLAGS), -- COMPOSITE(DCLK_VOP0, "dclk_vop0", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, -+ COMPOSITE(DCLK_VOP0, "dclk_vop0", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_NO_REPARENT, - RK3568_CLKSEL_CON(39), 10, 2, MFLAGS, 0, 8, DFLAGS, - RK3568_CLKGATE_CON(20), 10, GFLAGS), -- COMPOSITE(DCLK_VOP1, "dclk_vop1", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, -+ COMPOSITE(DCLK_VOP1, "dclk_vop1", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_NO_REPARENT, - RK3568_CLKSEL_CON(40), 10, 2, MFLAGS, 0, 8, DFLAGS, - RK3568_CLKGATE_CON(20), 11, GFLAGS), -- COMPOSITE(DCLK_VOP2, "dclk_vop2", hpll_vpll_gpll_cpll_p, 0, -+ COMPOSITE(DCLK_VOP2, "dclk_vop2", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_NO_REPARENT, - RK3568_CLKSEL_CON(41), 10, 2, MFLAGS, 0, 8, DFLAGS, - RK3568_CLKGATE_CON(20), 12, GFLAGS), - GATE(CLK_VOP_PWM, "clk_vop_pwm", "xin24m", 0, -From patchwork Mon Dec 20 11:06:27 2021 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 8bit -X-Patchwork-Submitter: Sascha Hauer -X-Patchwork-Id: 12687621 -Return-Path: - -X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on - aws-us-west-2-korg-lkml-1.web.codeaurora.org -Received: from bombadil.infradead.org (bombadil.infradead.org - [198.137.202.133]) - (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) - (No client certificate requested) - by smtp.lore.kernel.org (Postfix) with ESMTPS id 4A1D9C433EF - for ; - Mon, 20 Dec 2021 11:20:44 +0000 (UTC) -DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; - d=lists.infradead.org; s=bombadil.20210309; h=Sender: - Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: - List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: - Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: - Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: - List-Owner; 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Mon, 20 Dec 2021 12:06:44 +0100 -From: Sascha Hauer -To: dri-devel@lists.freedesktop.org -Cc: linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, - devicetree@vger.kernel.org, kernel@pengutronix.de, - Andy Yan , - Benjamin Gaignard , - Michael Riesch , - Sandy Huang , - =?utf-8?q?Heiko_St=C3=BCbner?= , - Peter Geis , Sascha Hauer -Subject: [PATCH 19/22] clk: rk3568: Add CLK_SET_RATE_PARENT to the HDMI - reference clock -Date: Mon, 20 Dec 2021 12:06:27 +0100 -Message-Id: <20211220110630.3521121-20-s.hauer@pengutronix.de> -X-Mailer: git-send-email 2.30.2 -In-Reply-To: <20211220110630.3521121-1-s.hauer@pengutronix.de> -References: <20211220110630.3521121-1-s.hauer@pengutronix.de> -MIME-Version: 1.0 -X-SA-Exim-Connect-IP: 2001:67c:670:100:1d::28 -X-SA-Exim-Mail-From: sha@pengutronix.de -X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); - SAEximRunCond expanded to false -X-PTX-Original-Recipient: linux-rockchip@lists.infradead.org -X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 -X-CRM114-CacheID: sfid-20211220_110713_894163_3C0C0EB3 -X-CRM114-Status: GOOD ( 15.63 ) -X-BeenThere: linux-rockchip@lists.infradead.org -X-Mailman-Version: 2.1.34 -Precedence: list -List-Id: Upstream kernel work for Rockchip platforms - -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Sender: "Linux-rockchip" -Errors-To: - linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org - -On the rk3568 we have this (simplified) situation: - - .--------. .-----. .---------. --| hpll |--.--| /n |----|dclk_vop0|- - `--------´ | `-----´ `---------´ - | .-----. .---------. - `--| /m |----|dclk_vop1|- - | `-----´ `---------´ - | .---------. - `-------------|hdmi_ref |- - `---------´ - -For the HDMI to work the HDMI reference clock needs to be the same as the -pixel clock which means the dividers have be set to one. The last patch removed -the CLK_SET_RATE_PARENT flag from the pixel clocks which means the hpll is not -changed on pixel clock changes. In order to allow the HDMI controller to -set a suitable PLL rate we now add the CLK_SET_RATE_PARENT flag to the -HDMI reference clock. With this the flow becomes: - -1) HDMI controller driver sets the rate to its pixel clock which means - hpll is set to the pixel clock -2) VOP2 driver sets dclk_vop[012] to the pixel clock. As this can't change - the hpll clock anymore this means only the divider is adjusted to the - desired value of dividing by one. - -Signed-off-by: Sascha Hauer ---- - drivers/clk/rockchip/clk-rk3568.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c -index 604a367bc498a..1fe78a58010ea 100644 ---- a/drivers/clk/rockchip/clk-rk3568.c -+++ b/drivers/clk/rockchip/clk-rk3568.c -@@ -1562,7 +1562,7 @@ static struct rockchip_clk_branch rk3568_clk_pmu_branches[] __initdata = { - RK3568_PMU_CLKGATE_CON(2), 14, GFLAGS), - GATE(XIN_OSC0_EDPPHY_G, "xin_osc0_edpphy_g", "xin24m", 0, - RK3568_PMU_CLKGATE_CON(2), 15, GFLAGS), -- MUX(CLK_HDMI_REF, "clk_hdmi_ref", clk_hdmi_ref_p, 0, -+ MUX(CLK_HDMI_REF, "clk_hdmi_ref", clk_hdmi_ref_p, CLK_SET_RATE_PARENT, - RK3568_PMU_CLKSEL_CON(8), 7, 1, MFLAGS), - }; - -From patchwork Mon Dec 20 11:06:28 2021 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Sascha Hauer -X-Patchwork-Id: 12687595 -Return-Path: - -X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on - aws-us-west-2-korg-lkml-1.web.codeaurora.org -Received: from bombadil.infradead.org (bombadil.infradead.org - [198.137.202.133]) - (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) - (No client certificate requested) - by smtp.lore.kernel.org (Postfix) with ESMTPS id 507B2C433EF - for ; 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Mon, 20 Dec 2021 11:07:05 +0000 -Received: from dude02.hi.pengutronix.de ([2001:67c:670:100:1d::28]) - by metis.ext.pengutronix.de with esmtps - (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) - (envelope-from ) - id 1mzGVH-0004xJ-BS; Mon, 20 Dec 2021 12:06:51 +0100 -Received: from sha by dude02.hi.pengutronix.de with local (Exim 4.94.2) - (envelope-from ) - id 1mzGVA-00EmEt-SW; Mon, 20 Dec 2021 12:06:44 +0100 -From: Sascha Hauer -To: dri-devel@lists.freedesktop.org -Cc: linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, - devicetree@vger.kernel.org, kernel@pengutronix.de, - Andy Yan , - Benjamin Gaignard , - Michael Riesch , - Sandy Huang , - =?utf-8?q?Heiko_St=C3=BCbner?= , - Peter Geis , Sascha Hauer -Subject: [PATCH 20/22] drm/encoder: Add of_graph port to struct drm_encoder -Date: Mon, 20 Dec 2021 12:06:28 +0100 -Message-Id: <20211220110630.3521121-21-s.hauer@pengutronix.de> -X-Mailer: git-send-email 2.30.2 -In-Reply-To: <20211220110630.3521121-1-s.hauer@pengutronix.de> -References: <20211220110630.3521121-1-s.hauer@pengutronix.de> -MIME-Version: 1.0 -X-SA-Exim-Connect-IP: 2001:67c:670:100:1d::28 -X-SA-Exim-Mail-From: sha@pengutronix.de -X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); - SAEximRunCond expanded to false -X-PTX-Original-Recipient: linux-rockchip@lists.infradead.org -X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 -X-CRM114-CacheID: sfid-20211220_110703_798471_E6CDC5BA -X-CRM114-Status: GOOD ( 11.42 ) -X-BeenThere: linux-rockchip@lists.infradead.org -X-Mailman-Version: 2.1.34 -Precedence: list -List-Id: Upstream kernel work for Rockchip platforms - -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Sender: "Linux-rockchip" -Errors-To: - linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org - -Add a device node to drm_encoder which corresponds with the port node -in the DT description of the encoder. This allows drivers to find the -of_graph link between a crtc and an encoder. - -Signed-off-by: Sascha Hauer ---- - include/drm/drm_encoder.h | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/include/drm/drm_encoder.h b/include/drm/drm_encoder.h -index 6e91a0280f31b..3acd054b1eb3e 100644 ---- a/include/drm/drm_encoder.h -+++ b/include/drm/drm_encoder.h -@@ -99,6 +99,8 @@ struct drm_encoder { - struct drm_device *dev; - struct list_head head; - -+ struct device_node *port; -+ - struct drm_mode_object base; - char *name; - /** -From patchwork Mon Dec 20 11:06:29 2021 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Sascha Hauer -X-Patchwork-Id: 12687539 -Return-Path: - -X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on - aws-us-west-2-korg-lkml-1.web.codeaurora.org -Received: from bombadil.infradead.org (bombadil.infradead.org - [198.137.202.133]) - (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) - (No client certificate requested) - by smtp.lore.kernel.org (Postfix) with ESMTPS id 1B3C4C433EF - for ; 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Mon, 20 Dec 2021 11:10:06 +0000 -Received: from metis.ext.pengutronix.de - ([2001:67c:670:201:290:27ff:fe1d:cc33]) - by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) - id 1mzGVK-001oDg-LU - for linux-rockchip@lists.infradead.org; Mon, 20 Dec 2021 11:06:58 +0000 -Received: from dude02.hi.pengutronix.de ([2001:67c:670:100:1d::28]) - by metis.ext.pengutronix.de with esmtps - (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) - (envelope-from ) - id 1mzGVH-0004xK-CJ; Mon, 20 Dec 2021 12:06:51 +0100 -Received: from sha by dude02.hi.pengutronix.de with local (Exim 4.94.2) - (envelope-from ) - id 1mzGVA-00EmEw-T4; Mon, 20 Dec 2021 12:06:44 +0100 -From: Sascha Hauer -To: dri-devel@lists.freedesktop.org -Cc: linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, - devicetree@vger.kernel.org, kernel@pengutronix.de, - Andy Yan , - Benjamin Gaignard , - Michael Riesch , - Sandy Huang , - =?utf-8?q?Heiko_St=C3=BCbner?= , - Peter Geis , Sascha Hauer -Subject: [PATCH 21/22] drm/rockchip: Make VOP driver optional -Date: Mon, 20 Dec 2021 12:06:29 +0100 -Message-Id: <20211220110630.3521121-22-s.hauer@pengutronix.de> -X-Mailer: git-send-email 2.30.2 -In-Reply-To: <20211220110630.3521121-1-s.hauer@pengutronix.de> -References: <20211220110630.3521121-1-s.hauer@pengutronix.de> -MIME-Version: 1.0 -X-SA-Exim-Connect-IP: 2001:67c:670:100:1d::28 -X-SA-Exim-Mail-From: sha@pengutronix.de -X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); - SAEximRunCond expanded to false -X-PTX-Original-Recipient: linux-rockchip@lists.infradead.org -X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 -X-CRM114-CacheID: sfid-20211220_030654_725855_55F01FB7 -X-CRM114-Status: GOOD ( 13.98 ) -X-BeenThere: linux-rockchip@lists.infradead.org -X-Mailman-Version: 2.1.34 -Precedence: list -List-Id: Upstream kernel work for Rockchip platforms - -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Sender: "Linux-rockchip" -Errors-To: - linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org - -With upcoming VOP2 support VOP won't be the only choice anymore, so make -the VOP driver optional. - -Signed-off-by: Sascha Hauer ---- - drivers/gpu/drm/rockchip/Kconfig | 8 ++++++++ - drivers/gpu/drm/rockchip/Makefile | 3 ++- - drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 2 +- - 3 files changed, 11 insertions(+), 2 deletions(-) - diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig -index 9f1ecefc39332..b9b156308460a 100644 +index 9f1ecefc3933..4ff0043f0ee7 100644 --- a/drivers/gpu/drm/rockchip/Kconfig +++ b/drivers/gpu/drm/rockchip/Kconfig -@@ -21,8 +21,16 @@ config DRM_ROCKCHIP +@@ -21,8 +21,22 @@ config DRM_ROCKCHIP if DRM_ROCKCHIP @@ -2421,169 +595,6 @@ index 9f1ecefc39332..b9b156308460a 100644 + This selects support for the VOP driver. You should enable it + on all older SoCs up to RK3399. + - config ROCKCHIP_ANALOGIX_DP - bool "Rockchip specific extensions for Analogix DP driver" -+ depends on ROCKCHIP_VOP - help - This selects support for Rockchip SoC specific extensions - for the Analogix Core DP driver. If you want to enable DP -diff --git a/drivers/gpu/drm/rockchip/Makefile b/drivers/gpu/drm/rockchip/Makefile -index 17a9e7eb2130d..cd6e7bb5ce9c5 100644 ---- a/drivers/gpu/drm/rockchip/Makefile -+++ b/drivers/gpu/drm/rockchip/Makefile -@@ -4,9 +4,10 @@ - # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher. - - rockchipdrm-y := rockchip_drm_drv.o rockchip_drm_fb.o \ -- rockchip_drm_gem.o rockchip_drm_vop.o rockchip_vop_reg.o -+ rockchip_drm_gem.o - rockchipdrm-$(CONFIG_DRM_FBDEV_EMULATION) += rockchip_drm_fbdev.o - -+rockchipdrm-$(CONFIG_ROCKCHIP_VOP) += rockchip_drm_vop.o rockchip_vop_reg.o - rockchipdrm-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o - rockchipdrm-$(CONFIG_ROCKCHIP_CDN_DP) += cdn-dp-core.o cdn-dp-reg.o - rockchipdrm-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o -diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c -index e4ebe60b3cc1a..64fa5fd62c01a 100644 ---- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c -@@ -473,7 +473,7 @@ static int __init rockchip_drm_init(void) - int ret; - - num_rockchip_sub_drivers = 0; -- ADD_ROCKCHIP_SUB_DRIVER(vop_platform_driver, CONFIG_DRM_ROCKCHIP); -+ ADD_ROCKCHIP_SUB_DRIVER(vop_platform_driver, CONFIG_ROCKCHIP_VOP); - ADD_ROCKCHIP_SUB_DRIVER(rockchip_lvds_driver, - CONFIG_ROCKCHIP_LVDS); - ADD_ROCKCHIP_SUB_DRIVER(rockchip_dp_driver, -From patchwork Mon Dec 20 11:06:30 2021 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Sascha Hauer -X-Patchwork-Id: 12687605 -Return-Path: - -X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on - aws-us-west-2-korg-lkml-1.web.codeaurora.org -Received: from bombadil.infradead.org (bombadil.infradead.org - [198.137.202.133]) - (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) - (No client certificate requested) - by smtp.lore.kernel.org (Postfix) with ESMTPS id B50DCC433EF - for ; - Mon, 20 Dec 2021 11:14:24 +0000 (UTC) -DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; - d=lists.infradead.org; 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Mon, 20 Dec 2021 11:07:08 +0000 -Received: from dude02.hi.pengutronix.de ([2001:67c:670:100:1d::28]) - by metis.ext.pengutronix.de with esmtps - (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) - (envelope-from ) - id 1mzGVH-0004xL-BS; Mon, 20 Dec 2021 12:06:51 +0100 -Received: from sha by dude02.hi.pengutronix.de with local (Exim 4.94.2) - (envelope-from ) - id 1mzGVA-00EmF0-U2; Mon, 20 Dec 2021 12:06:44 +0100 -From: Sascha Hauer -To: dri-devel@lists.freedesktop.org -Cc: linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, - devicetree@vger.kernel.org, kernel@pengutronix.de, - Andy Yan , - Benjamin Gaignard , - Michael Riesch , - Sandy Huang , - =?utf-8?q?Heiko_St=C3=BCbner?= , - Peter Geis , Sascha Hauer -Subject: [PATCH 22/22] drm: rockchip: Add VOP2 driver -Date: Mon, 20 Dec 2021 12:06:30 +0100 -Message-Id: <20211220110630.3521121-23-s.hauer@pengutronix.de> -X-Mailer: git-send-email 2.30.2 -In-Reply-To: <20211220110630.3521121-1-s.hauer@pengutronix.de> -References: <20211220110630.3521121-1-s.hauer@pengutronix.de> -MIME-Version: 1.0 -X-SA-Exim-Connect-IP: 2001:67c:670:100:1d::28 -X-SA-Exim-Mail-From: sha@pengutronix.de -X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); - SAEximRunCond expanded to false -X-PTX-Original-Recipient: linux-rockchip@lists.infradead.org -X-BeenThere: linux-rockchip@lists.infradead.org -X-Mailman-Version: 2.1.34 -Precedence: list -List-Id: Upstream kernel work for Rockchip platforms - -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Sender: "Linux-rockchip" -Errors-To: - linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org - -From: Andy Yan - -The VOP2 unit is found on Rockchip SoCs beginning with rk3566/rk3568. -It replaces the VOP unit found in the older Rockchip SoCs. - -This driver has been derived from the downstream Rockchip Kernel and -heavily modified: - -- All nonstandard DRM properties have been removed -- dropped struct vop2_plane_state and pass around less data between - functions -- Dropped all DRM_FORMAT_* not known on upstream -- rework register access to get rid of excessively used macros -- Drop all waiting for framesyncs - -The driver is tested with HDMI and MIPI-DSI display on a RK3568-EVB -board. Overlay support is tested with the modetest utility. AFBC support -on the cluster windows is tested with weston-simple-dmabuf-egl on -weston using the (yet to be upstreamed) panfrost driver support. - -Signed-off-by: Sascha Hauer -Reported-by: kernel test robot ---- - drivers/gpu/drm/rockchip/Kconfig | 6 + - drivers/gpu/drm/rockchip/Makefile | 1 + - drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 1 + - drivers/gpu/drm/rockchip/rockchip_drm_drv.h | 7 +- - drivers/gpu/drm/rockchip/rockchip_drm_fb.c | 2 + - drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 15 + - drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 2768 ++++++++++++++++++ - drivers/gpu/drm/rockchip/rockchip_drm_vop2.h | 480 +++ - drivers/gpu/drm/rockchip/rockchip_vop2_reg.c | 285 ++ - 9 files changed, 3564 insertions(+), 1 deletion(-) - create mode 100644 drivers/gpu/drm/rockchip/rockchip_drm_vop2.c - create mode 100644 drivers/gpu/drm/rockchip/rockchip_drm_vop2.h - create mode 100644 drivers/gpu/drm/rockchip/rockchip_vop2_reg.c - -diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig -index b9b156308460a..4ff0043f0ee70 100644 ---- a/drivers/gpu/drm/rockchip/Kconfig -+++ b/drivers/gpu/drm/rockchip/Kconfig -@@ -28,6 +28,12 @@ config ROCKCHIP_VOP - This selects support for the VOP driver. You should enable it - on all older SoCs up to RK3399. - +config ROCKCHIP_VOP2 + bool "Rockchip VOP2 driver" + help @@ -2592,33 +603,957 @@ index b9b156308460a..4ff0043f0ee70 100644 + config ROCKCHIP_ANALOGIX_DP bool "Rockchip specific extensions for Analogix DP driver" - depends on ROCKCHIP_VOP ++ depends on ROCKCHIP_VOP + help + This selects support for Rockchip SoC specific extensions + for the Analogix Core DP driver. If you want to enable DP diff --git a/drivers/gpu/drm/rockchip/Makefile b/drivers/gpu/drm/rockchip/Makefile -index cd6e7bb5ce9c5..29848caef5c21 100644 +index 17a9e7eb2130..75667a773113 100644 --- a/drivers/gpu/drm/rockchip/Makefile +++ b/drivers/gpu/drm/rockchip/Makefile -@@ -7,6 +7,7 @@ rockchipdrm-y := rockchip_drm_drv.o rockchip_drm_fb.o \ - rockchip_drm_gem.o +@@ -4,7 +4,9 @@ + # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher. + + rockchipdrm-y := rockchip_drm_drv.o rockchip_drm_fb.o \ +- rockchip_drm_gem.o rockchip_drm_vop.o rockchip_vop_reg.o ++ rockchip_drm_gem.o ++rockchipdrm-$(CONFIG_ROCKCHIP_VOP) += rockchip_drm_vop.o rockchip_vop_reg.o ++rockchipdrm-$(CONFIG_ROCKCHIP_VOP2) += rockchip_drm_vop2.o rockchip_vop2_reg.o rockchipdrm-$(CONFIG_DRM_FBDEV_EMULATION) += rockchip_drm_fbdev.o -+rockchipdrm-$(CONFIG_ROCKCHIP_VOP2) += rockchip_drm_vop2.o rockchip_vop2_reg.o - rockchipdrm-$(CONFIG_ROCKCHIP_VOP) += rockchip_drm_vop.o rockchip_vop_reg.o rockchipdrm-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o - rockchipdrm-$(CONFIG_ROCKCHIP_CDN_DP) += cdn-dp-core.o cdn-dp-reg.o +diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c +index 8abb5ac26807..bb33c6c217f7 100644 +--- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c ++++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c +@@ -40,8 +40,6 @@ + + #define PSR_WAIT_LINE_FLAG_TIMEOUT_MS 100 + +-#define to_dp(nm) container_of(nm, struct rockchip_dp_device, nm) +- + /** + * struct rockchip_dp_chip_data - splite the grf setting of kind of chips + * @lcdsel_grf_reg: grf register offset of lcdc select +@@ -59,7 +57,7 @@ struct rockchip_dp_chip_data { + struct rockchip_dp_device { + struct drm_device *drm_dev; + struct device *dev; +- struct drm_encoder encoder; ++ struct rockchip_encoder encoder; + struct drm_display_mode mode; + + struct clk *pclk; +@@ -73,6 +71,18 @@ struct rockchip_dp_device { + struct analogix_dp_plat_data plat_data; + }; + ++static struct rockchip_dp_device *encoder_to_dp(struct drm_encoder *encoder) ++{ ++ struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); ++ ++ return container_of(rkencoder, struct rockchip_dp_device, encoder); ++} ++ ++static struct rockchip_dp_device *pdata_encoder_to_dp(struct analogix_dp_plat_data *plat_data) ++{ ++ return container_of(plat_data, struct rockchip_dp_device, plat_data); ++} ++ + static int rockchip_dp_pre_init(struct rockchip_dp_device *dp) + { + reset_control_assert(dp->rst); +@@ -84,7 +94,7 @@ static int rockchip_dp_pre_init(struct rockchip_dp_device *dp) + + static int rockchip_dp_poweron_start(struct analogix_dp_plat_data *plat_data) + { +- struct rockchip_dp_device *dp = to_dp(plat_data); ++ struct rockchip_dp_device *dp = pdata_encoder_to_dp(plat_data); + int ret; + + ret = clk_prepare_enable(dp->pclk); +@@ -105,7 +115,7 @@ static int rockchip_dp_poweron_start(struct analogix_dp_plat_data *plat_data) + + static int rockchip_dp_powerdown(struct analogix_dp_plat_data *plat_data) + { +- struct rockchip_dp_device *dp = to_dp(plat_data); ++ struct rockchip_dp_device *dp = pdata_encoder_to_dp(plat_data); + + clk_disable_unprepare(dp->pclk); + +@@ -166,7 +176,7 @@ struct drm_crtc *rockchip_dp_drm_get_new_crtc(struct drm_encoder *encoder, + static void rockchip_dp_drm_encoder_enable(struct drm_encoder *encoder, + struct drm_atomic_state *state) + { +- struct rockchip_dp_device *dp = to_dp(encoder); ++ struct rockchip_dp_device *dp = encoder_to_dp(encoder); + struct drm_crtc *crtc; + struct drm_crtc_state *old_crtc_state; + int ret; +@@ -208,7 +218,7 @@ static void rockchip_dp_drm_encoder_enable(struct drm_encoder *encoder, + static void rockchip_dp_drm_encoder_disable(struct drm_encoder *encoder, + struct drm_atomic_state *state) + { +- struct rockchip_dp_device *dp = to_dp(encoder); ++ struct rockchip_dp_device *dp = encoder_to_dp(encoder); + struct drm_crtc *crtc; + struct drm_crtc_state *new_crtc_state = NULL; + int ret; +@@ -297,7 +307,7 @@ static int rockchip_dp_of_probe(struct rockchip_dp_device *dp) + + static int rockchip_dp_drm_create_encoder(struct rockchip_dp_device *dp) + { +- struct drm_encoder *encoder = &dp->encoder; ++ struct drm_encoder *encoder = &dp->encoder.encoder; + struct drm_device *drm_dev = dp->drm_dev; + struct device *dev = dp->dev; + int ret; +@@ -333,7 +343,7 @@ static int rockchip_dp_bind(struct device *dev, struct device *master, + return ret; + } + +- dp->plat_data.encoder = &dp->encoder; ++ dp->plat_data.encoder = &dp->encoder.encoder; + + ret = analogix_dp_bind(dp->adp, drm_dev); + if (ret) +@@ -341,7 +351,7 @@ static int rockchip_dp_bind(struct device *dev, struct device *master, + + return 0; + err_cleanup_encoder: +- dp->encoder.funcs->destroy(&dp->encoder); ++ dp->encoder.encoder.funcs->destroy(&dp->encoder.encoder); + return ret; + } + +@@ -351,7 +361,7 @@ static void rockchip_dp_unbind(struct device *dev, struct device *master, + struct rockchip_dp_device *dp = dev_get_drvdata(dev); + + analogix_dp_unbind(dp->adp); +- dp->encoder.funcs->destroy(&dp->encoder); ++ dp->encoder.encoder.funcs->destroy(&dp->encoder.encoder); + } + + static const struct component_ops rockchip_dp_component_ops = { +diff --git a/drivers/gpu/drm/rockchip/cdn-dp-core.c b/drivers/gpu/drm/rockchip/cdn-dp-core.c +index 16497c31d9f9..6ce1c1cdd9d6 100644 +--- a/drivers/gpu/drm/rockchip/cdn-dp-core.c ++++ b/drivers/gpu/drm/rockchip/cdn-dp-core.c +@@ -26,11 +26,17 @@ + #include "cdn-dp-reg.h" + #include "rockchip_drm_vop.h" + +-#define connector_to_dp(c) \ +- container_of(c, struct cdn_dp_device, connector) ++static inline struct cdn_dp_device *connector_to_dp(struct drm_connector *connector) ++{ ++ return container_of(connector, struct cdn_dp_device, connector); ++} + +-#define encoder_to_dp(c) \ +- container_of(c, struct cdn_dp_device, encoder) ++static inline struct cdn_dp_device *encoder_to_dp(struct drm_encoder *encoder) ++{ ++ struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); ++ ++ return container_of(rkencoder, struct cdn_dp_device, encoder); ++} + + #define GRF_SOC_CON9 0x6224 + #define DP_SEL_VOP_LIT BIT(12) +@@ -1022,7 +1028,7 @@ static int cdn_dp_bind(struct device *dev, struct device *master, void *data) + + INIT_WORK(&dp->event_work, cdn_dp_pd_event_work); + +- encoder = &dp->encoder; ++ encoder = &dp->encoder.encoder; + + encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev, + dev->of_node); +@@ -1087,7 +1093,7 @@ static int cdn_dp_bind(struct device *dev, struct device *master, void *data) + static void cdn_dp_unbind(struct device *dev, struct device *master, void *data) + { + struct cdn_dp_device *dp = dev_get_drvdata(dev); +- struct drm_encoder *encoder = &dp->encoder; ++ struct drm_encoder *encoder = &dp->encoder.encoder; + struct drm_connector *connector = &dp->connector; + + cancel_work_sync(&dp->event_work); +diff --git a/drivers/gpu/drm/rockchip/cdn-dp-core.h b/drivers/gpu/drm/rockchip/cdn-dp-core.h +index 81ac9b658a70..29539170d3b1 100644 +--- a/drivers/gpu/drm/rockchip/cdn-dp-core.h ++++ b/drivers/gpu/drm/rockchip/cdn-dp-core.h +@@ -65,7 +65,7 @@ struct cdn_dp_device { + struct device *dev; + struct drm_device *drm_dev; + struct drm_connector connector; +- struct drm_encoder encoder; ++ struct rockchip_encoder encoder; + struct drm_display_mode mode; + struct platform_device *audio_pdev; + struct work_struct event_work; +diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c +index 4ed7a6868197..110e83aad9bb 100644 +--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c ++++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c +@@ -181,8 +181,6 @@ + + #define HIWORD_UPDATE(val, mask) (val | (mask) << 16) + +-#define to_dsi(nm) container_of(nm, struct dw_mipi_dsi_rockchip, nm) +- + enum { + DW_DSI_USAGE_IDLE, + DW_DSI_USAGE_DSI, +@@ -236,7 +234,7 @@ struct rockchip_dw_dsi_chip_data { + + struct dw_mipi_dsi_rockchip { + struct device *dev; +- struct drm_encoder encoder; ++ struct rockchip_encoder encoder; + void __iomem *base; + + struct regmap *grf_regmap; +@@ -271,6 +269,13 @@ struct dw_mipi_dsi_rockchip { + bool dsi_bound; + }; + ++static struct dw_mipi_dsi_rockchip *to_dsi(struct drm_encoder *encoder) ++{ ++ struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); ++ ++ return container_of(rkencoder, struct dw_mipi_dsi_rockchip, encoder); ++} ++ + struct dphy_pll_parameter_map { + unsigned int max_mbps; + u8 hsfreqrange; +@@ -770,7 +775,7 @@ static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder) + int ret, mux; + + mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node, +- &dsi->encoder); ++ &dsi->encoder.encoder); + if (mux < 0) + return; + +@@ -801,7 +806,7 @@ dw_mipi_dsi_encoder_helper_funcs = { + static int rockchip_dsi_drm_create_encoder(struct dw_mipi_dsi_rockchip *dsi, + struct drm_device *drm_dev) + { +- struct drm_encoder *encoder = &dsi->encoder; ++ struct drm_encoder *encoder = &dsi->encoder.encoder; + int ret; + + encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev, +@@ -959,7 +964,7 @@ static int dw_mipi_dsi_rockchip_bind(struct device *dev, + goto out_pll_clk; + } + +- ret = dw_mipi_dsi_bind(dsi->dmd, &dsi->encoder); ++ ret = dw_mipi_dsi_bind(dsi->dmd, &dsi->encoder.encoder); + if (ret) { + DRM_DEV_ERROR(dev, "Failed to bind: %d\n", ret); + goto out_pll_clk; +diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +index 8677c8271678..2c9e3d82fbc6 100644 +--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c ++++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +@@ -9,6 +9,7 @@ + #include + #include + #include ++#include + + #include + #include +@@ -50,6 +51,10 @@ + #define RK3399_GRF_SOC_CON20 0x6250 + #define RK3399_HDMI_LCDC_SEL BIT(6) + ++#define RK3568_GRF_VO_CON1 0x0364 ++#define RK3568_HDMI_SDAIN_MSK BIT(15) ++#define RK3568_HDMI_SCLIN_MSK BIT(14) ++ + #define HIWORD_UPDATE(val, mask) (val | (mask) << 16) + + /** +@@ -67,92 +72,108 @@ struct rockchip_hdmi_chip_data { + struct rockchip_hdmi { + struct device *dev; + struct regmap *regmap; +- struct drm_encoder encoder; ++ struct rockchip_encoder encoder; + const struct rockchip_hdmi_chip_data *chip_data; +- struct clk *vpll_clk; ++ struct clk *ref_clk; + struct clk *grf_clk; ++ struct clk *hclk_clk; + struct dw_hdmi *hdmi; ++ struct regulator *avdd_0v9; ++ struct regulator *avdd_1v8; + struct phy *phy; + }; + +-#define to_rockchip_hdmi(x) container_of(x, struct rockchip_hdmi, x) ++static struct rockchip_hdmi *to_rockchip_hdmi(struct drm_encoder *encoder) ++{ ++ struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); ++ ++ return container_of(rkencoder, struct rockchip_hdmi, encoder); ++} + + static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = { + { +- 27000000, { +- { 0x00b3, 0x0000}, +- { 0x2153, 0x0000}, +- { 0x40f3, 0x0000} ++ 30666000, { ++ { 0x00b3, 0x0000 }, ++ { 0x2153, 0x0000 }, ++ { 0x40f3, 0x0000 }, ++ }, ++ }, { ++ 36800000, { ++ { 0x00b3, 0x0000 }, ++ { 0x2153, 0x0000 }, ++ { 0x40a2, 0x0001 }, + }, +- }, { +- 36000000, { +- { 0x00b3, 0x0000}, +- { 0x2153, 0x0000}, +- { 0x40f3, 0x0000} ++ }, { ++ 46000000, { ++ { 0x00b3, 0x0000 }, ++ { 0x2142, 0x0001 }, ++ { 0x40a2, 0x0001 }, + }, +- }, { +- 40000000, { +- { 0x00b3, 0x0000}, +- { 0x2153, 0x0000}, +- { 0x40f3, 0x0000} ++ }, { ++ 61333000, { ++ { 0x0072, 0x0001 }, ++ { 0x2142, 0x0001 }, ++ { 0x40a2, 0x0001 }, + }, +- }, { +- 54000000, { +- { 0x0072, 0x0001}, +- { 0x2142, 0x0001}, +- { 0x40a2, 0x0001}, ++ }, { ++ 73600000, { ++ { 0x0072, 0x0001 }, ++ { 0x2142, 0x0001 }, ++ { 0x4061, 0x0002 }, + }, +- }, { +- 65000000, { +- { 0x0072, 0x0001}, +- { 0x2142, 0x0001}, +- { 0x40a2, 0x0001}, ++ }, { ++ 92000000, { ++ { 0x0072, 0x0001 }, ++ { 0x2145, 0x0002 }, ++ { 0x4061, 0x0002 }, + }, +- }, { +- 66000000, { +- { 0x013e, 0x0003}, +- { 0x217e, 0x0002}, +- { 0x4061, 0x0002} ++ }, { ++ 122666000, { ++ { 0x0051, 0x0002 }, ++ { 0x2145, 0x0002 }, ++ { 0x4061, 0x0002 }, + }, +- }, { +- 74250000, { +- { 0x0072, 0x0001}, +- { 0x2145, 0x0002}, +- { 0x4061, 0x0002} ++ }, { ++ 147200000, { ++ { 0x0051, 0x0002 }, ++ { 0x2145, 0x0002 }, ++ { 0x4064, 0x0003 }, + }, +- }, { +- 83500000, { +- { 0x0072, 0x0001}, ++ }, { ++ 184000000, { ++ { 0x0051, 0x0002 }, ++ { 0x214c, 0x0003 }, ++ { 0x4064, 0x0003 }, + }, +- }, { +- 108000000, { +- { 0x0051, 0x0002}, +- { 0x2145, 0x0002}, +- { 0x4061, 0x0002} ++ }, { ++ 226666000, { ++ { 0x0040, 0x0003 }, ++ { 0x214c, 0x0003 }, ++ { 0x4064, 0x0003 }, + }, +- }, { +- 106500000, { +- { 0x0051, 0x0002}, +- { 0x2145, 0x0002}, +- { 0x4061, 0x0002} ++ }, { ++ 272000000, { ++ { 0x0040, 0x0003 }, ++ { 0x214c, 0x0003 }, ++ { 0x5a64, 0x0003 }, + }, +- }, { +- 146250000, { +- { 0x0051, 0x0002}, +- { 0x2145, 0x0002}, +- { 0x4061, 0x0002} ++ }, { ++ 340000000, { ++ { 0x0040, 0x0003 }, ++ { 0x3b4c, 0x0003 }, ++ { 0x5a64, 0x0003 }, + }, +- }, { +- 148500000, { +- { 0x0051, 0x0003}, +- { 0x214c, 0x0003}, +- { 0x4064, 0x0003} ++ }, { ++ 600000000, { ++ { 0x1a40, 0x0003 }, ++ { 0x3b4c, 0x0003 }, ++ { 0x5a64, 0x0003 }, + }, +- }, { ++ }, { + ~0UL, { +- { 0x00a0, 0x000a }, +- { 0x2001, 0x000f }, +- { 0x4002, 0x000f }, ++ { 0x0000, 0x0000 }, ++ { 0x0000, 0x0000 }, ++ { 0x0000, 0x0000 }, + }, + } + }; +@@ -160,20 +181,8 @@ static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = { + static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = { + /* pixelclk bpp8 bpp10 bpp12 */ + { +- 40000000, { 0x0018, 0x0018, 0x0018 }, +- }, { +- 65000000, { 0x0028, 0x0028, 0x0028 }, +- }, { +- 66000000, { 0x0038, 0x0038, 0x0038 }, +- }, { +- 74250000, { 0x0028, 0x0038, 0x0038 }, +- }, { +- 83500000, { 0x0028, 0x0038, 0x0038 }, +- }, { +- 146250000, { 0x0038, 0x0038, 0x0038 }, +- }, { +- 148500000, { 0x0000, 0x0038, 0x0038 }, +- }, { ++ 600000000, { 0x0000, 0x0000, 0x0000 }, ++ }, { + ~0UL, { 0x0000, 0x0000, 0x0000}, + } + }; +@@ -183,6 +192,7 @@ static const struct dw_hdmi_phy_config rockchip_phy_config[] = { + { 74250000, 0x8009, 0x0004, 0x0272}, + { 148500000, 0x802b, 0x0004, 0x028d}, + { 297000000, 0x8039, 0x0005, 0x028d}, ++ { 594000000, 0x8039, 0x0000, 0x019d}, + { ~0UL, 0x0000, 0x0000, 0x0000} + }; + +@@ -196,14 +206,17 @@ static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi) + return PTR_ERR(hdmi->regmap); + } + +- hdmi->vpll_clk = devm_clk_get(hdmi->dev, "vpll"); +- if (PTR_ERR(hdmi->vpll_clk) == -ENOENT) { +- hdmi->vpll_clk = NULL; +- } else if (PTR_ERR(hdmi->vpll_clk) == -EPROBE_DEFER) { ++ hdmi->ref_clk = devm_clk_get(hdmi->dev, "ref"); ++ if (PTR_ERR(hdmi->ref_clk) == -ENOENT) ++ hdmi->ref_clk = devm_clk_get(hdmi->dev, "vpll"); ++ ++ if (PTR_ERR(hdmi->ref_clk) == -ENOENT) { ++ hdmi->ref_clk = NULL; ++ } else if (PTR_ERR(hdmi->ref_clk) == -EPROBE_DEFER) { + return -EPROBE_DEFER; +- } else if (IS_ERR(hdmi->vpll_clk)) { +- DRM_DEV_ERROR(hdmi->dev, "failed to get vpll clock\n"); +- return PTR_ERR(hdmi->vpll_clk); ++ } else if (IS_ERR(hdmi->ref_clk)) { ++ DRM_DEV_ERROR(hdmi->dev, "failed to get reference clock\n"); ++ return PTR_ERR(hdmi->ref_clk); + } + + hdmi->grf_clk = devm_clk_get(hdmi->dev, "grf"); +@@ -216,27 +229,23 @@ static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi) + return PTR_ERR(hdmi->grf_clk); + } + +- return 0; +-} +- +-static enum drm_mode_status +-dw_hdmi_rockchip_mode_valid(struct dw_hdmi *hdmi, void *data, +- const struct drm_display_info *info, +- const struct drm_display_mode *mode) +-{ +- const struct dw_hdmi_mpll_config *mpll_cfg = rockchip_mpll_cfg; +- int pclk = mode->clock * 1000; +- bool valid = false; +- int i; +- +- for (i = 0; mpll_cfg[i].mpixelclock != (~0UL); i++) { +- if (pclk == mpll_cfg[i].mpixelclock) { +- valid = true; +- break; +- } ++ hdmi->hclk_clk = devm_clk_get_optional(hdmi->dev, "hclk"); ++ if (PTR_ERR(hdmi->hclk_clk) == -EPROBE_DEFER) { ++ return -EPROBE_DEFER; ++ } else if (IS_ERR(hdmi->hclk_clk)) { ++ DRM_DEV_ERROR(hdmi->dev, "failed to get hclk_clk clock\n"); ++ return PTR_ERR(hdmi->hclk_clk); + } + +- return (valid) ? MODE_OK : MODE_BAD; ++ hdmi->avdd_0v9 = devm_regulator_get(hdmi->dev, "avdd-0v9"); ++ if (IS_ERR(hdmi->avdd_0v9)) ++ return PTR_ERR(hdmi->avdd_0v9); ++ ++ hdmi->avdd_1v8 = devm_regulator_get(hdmi->dev, "avdd-1v8"); ++ if (IS_ERR(hdmi->avdd_1v8)) ++ return PTR_ERR(hdmi->avdd_1v8); ++ ++ return 0; + } + + static void dw_hdmi_rockchip_encoder_disable(struct drm_encoder *encoder) +@@ -257,7 +266,7 @@ static void dw_hdmi_rockchip_encoder_mode_set(struct drm_encoder *encoder, + { + struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder); + +- clk_set_rate(hdmi->vpll_clk, adj_mode->clock * 1000); ++ clk_set_rate(hdmi->ref_clk, adj_mode->clock * 1000); + } + + static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder) +@@ -404,7 +413,6 @@ static struct rockchip_hdmi_chip_data rk3228_chip_data = { + }; + + static const struct dw_hdmi_plat_data rk3228_hdmi_drv_data = { +- .mode_valid = dw_hdmi_rockchip_mode_valid, + .mpll_cfg = rockchip_mpll_cfg, + .cur_ctr = rockchip_cur_ctr, + .phy_config = rockchip_phy_config, +@@ -421,7 +429,6 @@ static struct rockchip_hdmi_chip_data rk3288_chip_data = { + }; + + static const struct dw_hdmi_plat_data rk3288_hdmi_drv_data = { +- .mode_valid = dw_hdmi_rockchip_mode_valid, + .mpll_cfg = rockchip_mpll_cfg, + .cur_ctr = rockchip_cur_ctr, + .phy_config = rockchip_phy_config, +@@ -441,7 +448,6 @@ static struct rockchip_hdmi_chip_data rk3328_chip_data = { + }; + + static const struct dw_hdmi_plat_data rk3328_hdmi_drv_data = { +- .mode_valid = dw_hdmi_rockchip_mode_valid, + .mpll_cfg = rockchip_mpll_cfg, + .cur_ctr = rockchip_cur_ctr, + .phy_config = rockchip_phy_config, +@@ -459,7 +465,6 @@ static struct rockchip_hdmi_chip_data rk3399_chip_data = { + }; + + static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = { +- .mode_valid = dw_hdmi_rockchip_mode_valid, + .mpll_cfg = rockchip_mpll_cfg, + .cur_ctr = rockchip_cur_ctr, + .phy_config = rockchip_phy_config, +@@ -467,6 +472,18 @@ static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = { + .use_drm_infoframe = true, + }; + ++static struct rockchip_hdmi_chip_data rk3568_chip_data = { ++ .lcdsel_grf_reg = -1, ++}; ++ ++static const struct dw_hdmi_plat_data rk3568_hdmi_drv_data = { ++ .mpll_cfg = rockchip_mpll_cfg, ++ .cur_ctr = rockchip_cur_ctr, ++ .phy_config = rockchip_phy_config, ++ .phy_data = &rk3568_chip_data, ++ .use_drm_infoframe = true, ++}; ++ + static const struct of_device_id dw_hdmi_rockchip_dt_ids[] = { + { .compatible = "rockchip,rk3228-dw-hdmi", + .data = &rk3228_hdmi_drv_data +@@ -480,6 +497,9 @@ static const struct of_device_id dw_hdmi_rockchip_dt_ids[] = { + { .compatible = "rockchip,rk3399-dw-hdmi", + .data = &rk3399_hdmi_drv_data + }, ++ { .compatible = "rockchip,rk3568-dw-hdmi", ++ .data = &rk3568_hdmi_drv_data ++ }, + {}, + }; + MODULE_DEVICE_TABLE(of, dw_hdmi_rockchip_dt_ids); +@@ -511,9 +531,12 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, + hdmi->dev = &pdev->dev; + hdmi->chip_data = plat_data->phy_data; + plat_data->phy_data = hdmi; +- encoder = &hdmi->encoder; ++ encoder = &hdmi->encoder.encoder; + + encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node); ++ ++ hdmi->encoder.port = of_graph_get_port_by_id(dev->of_node, 0); ++ + /* + * If we failed to find the CRTC(s) which this encoder is + * supposed to be connected to, it's because the CRTC has +@@ -537,11 +560,38 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, + return ret; + } + +- ret = clk_prepare_enable(hdmi->vpll_clk); ++ ret = regulator_enable(hdmi->avdd_0v9); ++ if (ret) { ++ DRM_DEV_ERROR(hdmi->dev, "failed to enable avdd0v9: %d\n", ret); ++ goto err_avdd_0v9; ++ } ++ ++ ret = regulator_enable(hdmi->avdd_1v8); ++ if (ret) { ++ DRM_DEV_ERROR(hdmi->dev, "failed to enable avdd1v8: %d\n", ret); ++ goto err_avdd_1v8; ++ } ++ ++ ret = clk_prepare_enable(hdmi->ref_clk); + if (ret) { +- DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI vpll: %d\n", ++ DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI reference clock: %d\n", + ret); +- return ret; ++ goto err_clk; ++ } ++ ++ ret = clk_prepare_enable(hdmi->hclk_clk); ++ if (ret) { ++ DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI hclk clock: %d\n", ++ ret); ++ goto err_clk; ++ } ++ ++ if (hdmi->chip_data == &rk3568_chip_data) { ++ regmap_write(hdmi->regmap, RK3568_GRF_VO_CON1, ++ HIWORD_UPDATE(RK3568_HDMI_SDAIN_MSK | ++ RK3568_HDMI_SCLIN_MSK, ++ RK3568_HDMI_SDAIN_MSK | ++ RK3568_HDMI_SCLIN_MSK)); + } + + drm_encoder_helper_add(encoder, &dw_hdmi_rockchip_encoder_helper_funcs); +@@ -557,10 +607,19 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, + */ + if (IS_ERR(hdmi->hdmi)) { + ret = PTR_ERR(hdmi->hdmi); +- drm_encoder_cleanup(encoder); +- clk_disable_unprepare(hdmi->vpll_clk); ++ goto err_bind; + } + ++ return 0; ++ ++err_bind: ++ clk_disable_unprepare(hdmi->ref_clk); ++ drm_encoder_cleanup(encoder); ++err_clk: ++ regulator_disable(hdmi->avdd_1v8); ++err_avdd_1v8: ++ regulator_disable(hdmi->avdd_0v9); ++err_avdd_0v9: + return ret; + } + +@@ -570,7 +629,10 @@ static void dw_hdmi_rockchip_unbind(struct device *dev, struct device *master, + struct rockchip_hdmi *hdmi = dev_get_drvdata(dev); + + dw_hdmi_unbind(hdmi->hdmi); +- clk_disable_unprepare(hdmi->vpll_clk); ++ clk_disable_unprepare(hdmi->ref_clk); ++ ++ regulator_disable(hdmi->avdd_1v8); ++ regulator_disable(hdmi->avdd_0v9); + } + + static const struct component_ops dw_hdmi_rockchip_ops = { +diff --git a/drivers/gpu/drm/rockchip/inno_hdmi.c b/drivers/gpu/drm/rockchip/inno_hdmi.c +index 046e8ec2a71c..0a4f72021d6a 100644 +--- a/drivers/gpu/drm/rockchip/inno_hdmi.c ++++ b/drivers/gpu/drm/rockchip/inno_hdmi.c +@@ -26,8 +26,6 @@ + + #include "inno_hdmi.h" + +-#define to_inno_hdmi(x) container_of(x, struct inno_hdmi, x) +- + struct hdmi_data_info { + int vic; + bool sink_is_hdmi; +@@ -56,7 +54,7 @@ struct inno_hdmi { + void __iomem *regs; + + struct drm_connector connector; +- struct drm_encoder encoder; ++ struct rockchip_encoder encoder; + + struct inno_hdmi_i2c *i2c; + struct i2c_adapter *ddc; +@@ -67,6 +65,18 @@ struct inno_hdmi { + struct drm_display_mode previous_mode; + }; + ++static struct inno_hdmi *encoder_to_inno_hdmi(struct drm_encoder *encoder) ++{ ++ struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); ++ ++ return container_of(rkencoder, struct inno_hdmi, encoder); ++} ++ ++static struct inno_hdmi *connector_to_inno_hdmi(struct drm_connector *connector) ++{ ++ return container_of(connector, struct inno_hdmi, connector); ++} ++ + enum { + CSC_ITU601_16_235_TO_RGB_0_255_8BIT, + CSC_ITU601_0_255_TO_RGB_0_255_8BIT, +@@ -483,7 +493,7 @@ static void inno_hdmi_encoder_mode_set(struct drm_encoder *encoder, + struct drm_display_mode *mode, + struct drm_display_mode *adj_mode) + { +- struct inno_hdmi *hdmi = to_inno_hdmi(encoder); ++ struct inno_hdmi *hdmi = encoder_to_inno_hdmi(encoder); + + inno_hdmi_setup(hdmi, adj_mode); + +@@ -493,14 +503,14 @@ static void inno_hdmi_encoder_mode_set(struct drm_encoder *encoder, + + static void inno_hdmi_encoder_enable(struct drm_encoder *encoder) + { +- struct inno_hdmi *hdmi = to_inno_hdmi(encoder); ++ struct inno_hdmi *hdmi = encoder_to_inno_hdmi(encoder); + + inno_hdmi_set_pwr_mode(hdmi, NORMAL); + } + + static void inno_hdmi_encoder_disable(struct drm_encoder *encoder) + { +- struct inno_hdmi *hdmi = to_inno_hdmi(encoder); ++ struct inno_hdmi *hdmi = encoder_to_inno_hdmi(encoder); + + inno_hdmi_set_pwr_mode(hdmi, LOWER_PWR); + } +@@ -536,7 +546,7 @@ static struct drm_encoder_helper_funcs inno_hdmi_encoder_helper_funcs = { + static enum drm_connector_status + inno_hdmi_connector_detect(struct drm_connector *connector, bool force) + { +- struct inno_hdmi *hdmi = to_inno_hdmi(connector); ++ struct inno_hdmi *hdmi = connector_to_inno_hdmi(connector); + + return (hdmi_readb(hdmi, HDMI_STATUS) & m_HOTPLUG) ? + connector_status_connected : connector_status_disconnected; +@@ -544,7 +554,7 @@ inno_hdmi_connector_detect(struct drm_connector *connector, bool force) + + static int inno_hdmi_connector_get_modes(struct drm_connector *connector) + { +- struct inno_hdmi *hdmi = to_inno_hdmi(connector); ++ struct inno_hdmi *hdmi = connector_to_inno_hdmi(connector); + struct edid *edid; + int ret = 0; + +@@ -599,7 +609,7 @@ static struct drm_connector_helper_funcs inno_hdmi_connector_helper_funcs = { + + static int inno_hdmi_register(struct drm_device *drm, struct inno_hdmi *hdmi) + { +- struct drm_encoder *encoder = &hdmi->encoder; ++ struct drm_encoder *encoder = &hdmi->encoder.encoder; + struct device *dev = hdmi->dev; + + encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node); +@@ -879,7 +889,7 @@ static int inno_hdmi_bind(struct device *dev, struct device *master, + return 0; + err_cleanup_hdmi: + hdmi->connector.funcs->destroy(&hdmi->connector); +- hdmi->encoder.funcs->destroy(&hdmi->encoder); ++ hdmi->encoder.encoder.funcs->destroy(&hdmi->encoder.encoder); + err_put_adapter: + i2c_put_adapter(hdmi->ddc); + err_disable_clk: +@@ -893,7 +903,7 @@ static void inno_hdmi_unbind(struct device *dev, struct device *master, + struct inno_hdmi *hdmi = dev_get_drvdata(dev); + + hdmi->connector.funcs->destroy(&hdmi->connector); +- hdmi->encoder.funcs->destroy(&hdmi->encoder); ++ hdmi->encoder.encoder.funcs->destroy(&hdmi->encoder.encoder); + + i2c_put_adapter(hdmi->ddc); + clk_disable_unprepare(hdmi->pclk); +diff --git a/drivers/gpu/drm/rockchip/rk3066_hdmi.c b/drivers/gpu/drm/rockchip/rk3066_hdmi.c +index 1c546c3a8998..319240c33dcc 100644 +--- a/drivers/gpu/drm/rockchip/rk3066_hdmi.c ++++ b/drivers/gpu/drm/rockchip/rk3066_hdmi.c +@@ -47,7 +47,7 @@ struct rk3066_hdmi { + void __iomem *regs; + + struct drm_connector connector; +- struct drm_encoder encoder; ++ struct rockchip_encoder encoder; + + struct rk3066_hdmi_i2c *i2c; + struct i2c_adapter *ddc; +@@ -58,7 +58,17 @@ struct rk3066_hdmi { + struct drm_display_mode previous_mode; + }; + +-#define to_rk3066_hdmi(x) container_of(x, struct rk3066_hdmi, x) ++static struct rk3066_hdmi *encoder_to_rk3066_hdmi(struct drm_encoder *encoder) ++{ ++ struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); ++ ++ return container_of(rkencoder, struct rk3066_hdmi, encoder); ++} ++ ++static struct rk3066_hdmi *connector_to_rk3066_hdmi(struct drm_connector *connector) ++{ ++ return container_of(connector, struct rk3066_hdmi, connector); ++} + + static inline u8 hdmi_readb(struct rk3066_hdmi *hdmi, u16 offset) + { +@@ -380,7 +390,7 @@ rk3066_hdmi_encoder_mode_set(struct drm_encoder *encoder, + struct drm_display_mode *mode, + struct drm_display_mode *adj_mode) + { +- struct rk3066_hdmi *hdmi = to_rk3066_hdmi(encoder); ++ struct rk3066_hdmi *hdmi = encoder_to_rk3066_hdmi(encoder); + + /* Store the display mode for plugin/DPMS poweron events. */ + memcpy(&hdmi->previous_mode, adj_mode, sizeof(hdmi->previous_mode)); +@@ -388,7 +398,7 @@ rk3066_hdmi_encoder_mode_set(struct drm_encoder *encoder, + + static void rk3066_hdmi_encoder_enable(struct drm_encoder *encoder) + { +- struct rk3066_hdmi *hdmi = to_rk3066_hdmi(encoder); ++ struct rk3066_hdmi *hdmi = encoder_to_rk3066_hdmi(encoder); + int mux, val; + + mux = drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, encoder); +@@ -407,7 +417,7 @@ static void rk3066_hdmi_encoder_enable(struct drm_encoder *encoder) + + static void rk3066_hdmi_encoder_disable(struct drm_encoder *encoder) + { +- struct rk3066_hdmi *hdmi = to_rk3066_hdmi(encoder); ++ struct rk3066_hdmi *hdmi = encoder_to_rk3066_hdmi(encoder); + + DRM_DEV_DEBUG(hdmi->dev, "hdmi encoder disable\n"); + +@@ -455,7 +465,7 @@ struct drm_encoder_helper_funcs rk3066_hdmi_encoder_helper_funcs = { + static enum drm_connector_status + rk3066_hdmi_connector_detect(struct drm_connector *connector, bool force) + { +- struct rk3066_hdmi *hdmi = to_rk3066_hdmi(connector); ++ struct rk3066_hdmi *hdmi = connector_to_rk3066_hdmi(connector); + + return (hdmi_readb(hdmi, HDMI_HPG_MENS_STA) & HDMI_HPG_IN_STATUS_HIGH) ? + connector_status_connected : connector_status_disconnected; +@@ -463,7 +473,7 @@ rk3066_hdmi_connector_detect(struct drm_connector *connector, bool force) + + static int rk3066_hdmi_connector_get_modes(struct drm_connector *connector) + { +- struct rk3066_hdmi *hdmi = to_rk3066_hdmi(connector); ++ struct rk3066_hdmi *hdmi = connector_to_rk3066_hdmi(connector); + struct edid *edid; + int ret = 0; + +@@ -496,9 +506,9 @@ rk3066_hdmi_connector_mode_valid(struct drm_connector *connector, + static struct drm_encoder * + rk3066_hdmi_connector_best_encoder(struct drm_connector *connector) + { +- struct rk3066_hdmi *hdmi = to_rk3066_hdmi(connector); ++ struct rk3066_hdmi *hdmi = connector_to_rk3066_hdmi(connector); + +- return &hdmi->encoder; ++ return &hdmi->encoder.encoder; + } + + static int +@@ -538,7 +548,7 @@ struct drm_connector_helper_funcs rk3066_hdmi_connector_helper_funcs = { + static int + rk3066_hdmi_register(struct drm_device *drm, struct rk3066_hdmi *hdmi) + { +- struct drm_encoder *encoder = &hdmi->encoder; ++ struct drm_encoder *encoder = &hdmi->encoder.encoder; + struct device *dev = hdmi->dev; + + encoder->possible_crtcs = +@@ -816,7 +826,7 @@ static int rk3066_hdmi_bind(struct device *dev, struct device *master, + + err_cleanup_hdmi: + hdmi->connector.funcs->destroy(&hdmi->connector); +- hdmi->encoder.funcs->destroy(&hdmi->encoder); ++ hdmi->encoder.encoder.funcs->destroy(&hdmi->encoder.encoder); + err_disable_i2c: + i2c_put_adapter(hdmi->ddc); + err_disable_hclk: +@@ -831,7 +841,7 @@ static void rk3066_hdmi_unbind(struct device *dev, struct device *master, + struct rk3066_hdmi *hdmi = dev_get_drvdata(dev); + + hdmi->connector.funcs->destroy(&hdmi->connector); +- hdmi->encoder.funcs->destroy(&hdmi->encoder); ++ hdmi->encoder.encoder.funcs->destroy(&hdmi->encoder.encoder); + + i2c_put_adapter(hdmi->ddc); + clk_disable_unprepare(hdmi->hclk); diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c -index 64fa5fd62c01a..2bd9acb265e5a 100644 +index e4ebe60b3cc1..2bd9acb265e5 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c -@@ -474,6 +474,7 @@ static int __init rockchip_drm_init(void) +@@ -473,7 +473,8 @@ static int __init rockchip_drm_init(void) + int ret; num_rockchip_sub_drivers = 0; - ADD_ROCKCHIP_SUB_DRIVER(vop_platform_driver, CONFIG_ROCKCHIP_VOP); +- ADD_ROCKCHIP_SUB_DRIVER(vop_platform_driver, CONFIG_DRM_ROCKCHIP); ++ ADD_ROCKCHIP_SUB_DRIVER(vop_platform_driver, CONFIG_ROCKCHIP_VOP); + ADD_ROCKCHIP_SUB_DRIVER(vop2_platform_driver, CONFIG_ROCKCHIP_VOP2); ADD_ROCKCHIP_SUB_DRIVER(rockchip_lvds_driver, CONFIG_ROCKCHIP_LVDS); ADD_ROCKCHIP_SUB_DRIVER(rockchip_dp_driver, diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h -index aa0909e8edf93..fd6994f21817e 100644 +index aa0909e8edf9..6e3ec9d8f250 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h @@ -18,7 +18,7 @@ @@ -2634,21 +1569,31 @@ index aa0909e8edf93..fd6994f21817e 100644 int output_bpc; int output_flags; bool enable_afbc; -+ uint32_t bus_format; ++ u32 bus_format; + u32 bus_flags; + int color_space; }; #define to_rockchip_crtc_state(s) \ container_of(s, struct rockchip_crtc_state, base) -@@ -65,4 +68,6 @@ extern struct platform_driver rockchip_dp_driver; +@@ -65,4 +68,16 @@ extern struct platform_driver rockchip_dp_driver; extern struct platform_driver rockchip_lvds_driver; extern struct platform_driver vop_platform_driver; extern struct platform_driver rk3066_hdmi_driver; +extern struct platform_driver vop2_platform_driver; ++ ++struct rockchip_encoder { ++ struct device_node *port; ++ struct drm_encoder encoder; ++}; ++ ++static inline struct rockchip_encoder *to_rockchip_encoder(struct drm_encoder *encoder) ++{ ++ return container_of(encoder, struct rockchip_encoder, encoder); ++} + #endif /* _ROCKCHIP_DRM_DRV_H_ */ diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_fb.c b/drivers/gpu/drm/rockchip/rockchip_drm_fb.c -index 3aa37e177667e..0d2cb4f3922b8 100644 +index 3aa37e177667..0d2cb4f3922b 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_fb.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_fb.c @@ -134,4 +134,6 @@ void rockchip_drm_mode_config_init(struct drm_device *dev) @@ -2659,7 +1604,7 @@ index 3aa37e177667e..0d2cb4f3922b8 100644 + dev->mode_config.normalize_zpos = true; } diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h -index 857d97cdc67c6..1e364d7b50e69 100644 +index 857d97cdc67c..1e364d7b50e6 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h @@ -54,9 +54,23 @@ struct vop_afbc { @@ -2694,44 +1639,43 @@ index 857d97cdc67c6..1e364d7b50e69 100644 #endif /* _ROCKCHIP_DRM_VOP_H */ diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c new file mode 100644 -index 0000000000000..7d39ba90061d1 +index 000000000000..394dd6c58368 --- /dev/null +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c -@@ -0,0 +1,2768 @@ +@@ -0,0 +1,2708 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * Author: Andy Yan + */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ ++#include ++#include ++#include ++#include +#include +#include ++#include +#include -+#include -+#include -+#include +#include +#include +#include ++#include +#include -+#include +#include -+#include -+#include +#include -+#include ++ ++#include ++#include ++#include ++#include ++#include +#include -+#include ++#include ++#include ++#include +#include ++ ++#include +#include + +#include "rockchip_drm_drv.h" @@ -2803,22 +1747,22 @@ index 0000000000000..7d39ba90061d1 +}; + +union vop2_alpha_ctrl { -+ uint32_t val; ++ u32 val; + struct { + /* [0:1] */ -+ uint32_t color_mode:1; -+ uint32_t alpha_mode:1; ++ u32 color_mode:1; ++ u32 alpha_mode:1; + /* [2:3] */ -+ uint32_t blend_mode:2; -+ uint32_t alpha_cal_mode:1; ++ u32 blend_mode:2; ++ u32 alpha_cal_mode:1; + /* [5:7] */ -+ uint32_t factor_mode:3; ++ u32 factor_mode:3; + /* [8:9] */ -+ uint32_t alpha_en:1; -+ uint32_t src_dst_swap:1; -+ uint32_t reserved:6; ++ u32 alpha_en:1; ++ u32 src_dst_swap:1; ++ u32 reserved:6; + /* [16:23] */ -+ uint32_t glb_alpha:8; ++ u32 glb_alpha:8; + } bits; +}; + @@ -2834,8 +1778,8 @@ index 0000000000000..7d39ba90061d1 + bool dst_premulti_en; + bool src_pixel_alpha_en; + bool dst_pixel_alpha_en; -+ uint16_t src_glb_alpha_value; -+ uint16_t dst_glb_alpha_value; ++ u16 src_glb_alpha_value; ++ u16 dst_glb_alpha_value; +}; + +struct vop2_win { @@ -2845,14 +1789,13 @@ index 0000000000000..7d39ba90061d1 + struct regmap_field *reg[VOP2_WIN_MAX_REG]; + + /** -+ * @win_id: graphic window id, a cluster maybe split into two ++ * @win_id: graphic window id, a cluster may be split into two + * graphics windows. + */ -+ uint8_t win_id; ++ u8 win_id; ++ u8 delay; ++ u32 offset; + -+ uint32_t offset; -+ -+ uint8_t delay; + enum drm_plane_type type; +}; + @@ -2860,21 +1803,21 @@ index 0000000000000..7d39ba90061d1 + struct drm_crtc crtc; + struct vop2 *vop2; + struct clk *dclk; -+ uint8_t id; ++ unsigned int id; + const struct vop2_video_port_regs *regs; + const struct vop2_video_port_data *data; + + struct completion dsp_hold_completion; + + /** -+ * @win_mask: Bitmask of wins attached to the video port; ++ * @win_mask: Bitmask of windows attached to the video port; + */ -+ uint32_t win_mask; ++ u32 win_mask; + + struct vop2_win *primary_plane; + struct drm_pending_vblank_event *event; + -+ int nlayers; ++ unsigned int nlayers; +}; + +struct vop2 { @@ -2883,11 +1826,11 @@ index 0000000000000..7d39ba90061d1 + struct vop2_video_port vps[ROCKCHIP_MAX_CRTC]; + + const struct vop2_data *data; -+ /* Number of win that registered as plane, -+ * maybe less than the total number of hardware -+ * win. ++ /* ++ * Number of windows that are registered as plane, may be less than the ++ * total number of hardware windows. + */ -+ uint32_t registered_num_wins; ++ u32 registered_num_wins; + + void __iomem *regs; + struct regmap *map; @@ -2895,11 +1838,9 @@ index 0000000000000..7d39ba90061d1 + struct regmap *grf; + + /* physical map length of vop2 register */ -+ uint32_t len; ++ u32 len; + + void __iomem *lut_regs; -+ /* one time only one process allowed to config the register */ -+ spinlock_t reg_lock; + + /* protects crtc enable/disable */ + struct mutex vop2_lock; @@ -2907,14 +1848,14 @@ index 0000000000000..7d39ba90061d1 + int irq; + + /* -+ * Some globle resource are shared between all -+ * the vidoe ports(crtcs), so we need a ref counter here. ++ * Some global resources are shared between all video ports(crtcs), so ++ * we need a ref counter here. + */ + unsigned int enable_count; + struct clk *hclk; + struct clk *aclk; + -+ /* must put at the end of the struct */ ++ /* must be put at the end of the struct */ + struct vop2_win win[]; +}; + @@ -2938,28 +1879,26 @@ index 0000000000000..7d39ba90061d1 + mutex_unlock(&vop2->vop2_lock); +} + -+static void vop2_writel(struct vop2 *vop2, uint32_t offset, uint32_t v) ++static void vop2_writel(struct vop2 *vop2, u32 offset, u32 v) +{ + regmap_write(vop2->map, offset, v); +} + -+static void vop2_vp_write(struct vop2_video_port *vp, uint32_t offset, -+ uint32_t v) ++static void vop2_vp_write(struct vop2_video_port *vp, u32 offset, u32 v) +{ + regmap_write(vp->vop2->map, vp->data->offset + offset, v); +} + -+static uint32_t vop2_readl(struct vop2 *vop2, uint32_t offset) ++static u32 vop2_readl(struct vop2 *vop2, u32 offset) +{ -+ uint32_t val; ++ u32 val; + + regmap_read(vop2->map, offset, &val); + + return val; +} + -+static void vop2_win_write(const struct vop2_win *win, unsigned int reg, -+ uint32_t v) ++static void vop2_win_write(const struct vop2_win *win, unsigned int reg, u32 v) +{ + regmap_field_write(win->reg[reg], v); +} @@ -2972,14 +1911,9 @@ index 0000000000000..7d39ba90061d1 +static void vop2_cfg_done(struct vop2_video_port *vp) +{ + struct vop2 *vop2 = vp->vop2; -+ uint32_t val; + -+ val = vop2_readl(vop2, RK3568_REG_CFG_DONE); -+ -+ val &= 0x7; -+ -+ vop2_writel(vop2, RK3568_REG_CFG_DONE, -+ val | BIT(vp->id) | RK3568_REG_CFG_DONE__GLB_CFG_DONE_EN); ++ regmap_set_bits(vop2->map, RK3568_REG_CFG_DONE, ++ BIT(vp->id) | RK3568_REG_CFG_DONE__GLB_CFG_DONE_EN); +} + +static void vop2_win_disable(struct vop2_win *win) @@ -2990,7 +1924,7 @@ index 0000000000000..7d39ba90061d1 + vop2_win_write(win, VOP2_WIN_CLUSTER_ENABLE, 0); +} + -+static enum vop2_data_format vop2_convert_format(uint32_t format) ++static enum vop2_data_format vop2_convert_format(u32 format) +{ + switch (format) { + case DRM_FORMAT_XRGB8888: @@ -3022,7 +1956,7 @@ index 0000000000000..7d39ba90061d1 + } +} + -+static enum vop2_afbc_format vop2_convert_afbc_format(uint32_t format) ++static enum vop2_afbc_format vop2_convert_afbc_format(u32 format) +{ + switch (format) { + case DRM_FORMAT_XRGB8888: @@ -3047,7 +1981,7 @@ index 0000000000000..7d39ba90061d1 + return VOP2_AFBC_FMT_INVALID; +} + -+static bool vop2_win_rb_swap(uint32_t format) ++static bool vop2_win_rb_swap(u32 format) +{ + switch (format) { + case DRM_FORMAT_XBGR8888: @@ -3060,7 +1994,7 @@ index 0000000000000..7d39ba90061d1 + } +} + -+static bool vop2_afbc_rb_swap(uint32_t format) ++static bool vop2_afbc_rb_swap(u32 format) +{ + switch (format) { + case DRM_FORMAT_NV24: @@ -3070,7 +2004,7 @@ index 0000000000000..7d39ba90061d1 + } +} + -+static bool vop2_afbc_uv_swap(uint32_t format) ++static bool vop2_afbc_uv_swap(u32 format) +{ + switch (format) { + case DRM_FORMAT_NV12: @@ -3081,7 +2015,7 @@ index 0000000000000..7d39ba90061d1 + } +} + -+static bool vop2_win_uv_swap(uint32_t format) ++static bool vop2_win_uv_swap(u32 format) +{ + switch (format) { + case DRM_FORMAT_NV12: @@ -3093,7 +2027,7 @@ index 0000000000000..7d39ba90061d1 + } +} + -+static bool vop2_win_dither_up(uint32_t format) ++static bool vop2_win_dither_up(u32 format) +{ + switch (format) { + case DRM_FORMAT_BGR565: @@ -3104,7 +2038,7 @@ index 0000000000000..7d39ba90061d1 + } +} + -+static bool vop2_output_uv_swap(uint32_t bus_format, uint32_t output_mode) ++static bool vop2_output_uv_swap(u32 bus_format, u32 output_mode) +{ + /* + * FIXME: @@ -3128,7 +2062,7 @@ index 0000000000000..7d39ba90061d1 + return false; +} + -+static bool is_yuv_output(uint32_t bus_format) ++static bool is_yuv_output(u32 bus_format) +{ + switch (bus_format) { + case MEDIA_BUS_FMT_YUV8_1X24: @@ -3158,13 +2092,14 @@ index 0000000000000..7d39ba90061d1 + + for (i = 0 ; i < plane->modifier_count; i++) + if (plane->modifiers[i] == modifier) -+ break; ++ return true; + -+ return (i < plane->modifier_count) ? true : false; ++ return false; + +} + -+static bool rockchip_vop2_mod_supported(struct drm_plane *plane, uint32_t format, u64 modifier) ++static bool rockchip_vop2_mod_supported(struct drm_plane *plane, u32 format, ++ u64 modifier) +{ + struct vop2_win *win = to_vop2_win(plane); + struct vop2 *vop2 = win->vop2; @@ -3176,7 +2111,8 @@ index 0000000000000..7d39ba90061d1 + return true; + + if (!rockchip_afbc(plane, modifier)) { -+ drm_err(vop2->drm, "Unsupported format modifier 0x%llx\n", modifier); ++ drm_err(vop2->drm, "Unsupported format modifier 0x%llx\n", ++ modifier); + + return false; + } @@ -3184,34 +2120,22 @@ index 0000000000000..7d39ba90061d1 + return vop2_convert_afbc_format(format) >= 0; +} + -+static int vop2_afbc_half_block_enable(struct drm_plane_state *pstate) -+{ -+ if ((pstate->rotation & DRM_MODE_ROTATE_270) || (pstate->rotation & DRM_MODE_ROTATE_90)) -+ return 0; -+ else -+ return 1; -+} -+ -+static uint32_t vop2_afbc_transform_offset(struct drm_plane_state *pstate, -+ bool afbc_half_block_en) ++static u32 vop2_afbc_transform_offset(struct drm_plane_state *pstate, ++ bool afbc_half_block_en) +{ + struct drm_rect *src = &pstate->src; + struct drm_framebuffer *fb = pstate->fb; -+ uint32_t bpp = fb->format->cpp[0] * 8; -+ uint32_t vir_width = (fb->pitches[0] << 3) / bpp; -+ uint32_t width = drm_rect_width(src) >> 16; -+ uint32_t height = drm_rect_height(src) >> 16; -+ uint32_t act_xoffset = src->x1 >> 16; -+ uint32_t act_yoffset = src->y1 >> 16; -+ uint32_t align16_crop = 0; -+ uint32_t align64_crop = 0; -+ uint32_t height_tmp = 0; -+ uint32_t transform_tmp = 0; -+ uint8_t transform_xoffset = 0; -+ uint8_t transform_yoffset = 0; -+ uint8_t top_crop = 0; -+ uint8_t top_crop_line_num = 0; -+ uint8_t bottom_crop_line_num = 0; ++ u32 bpp = fb->format->cpp[0] * 8; ++ u32 vir_width = (fb->pitches[0] << 3) / bpp; ++ u32 width = drm_rect_width(src) >> 16; ++ u32 height = drm_rect_height(src) >> 16; ++ u32 act_xoffset = src->x1 >> 16; ++ u32 act_yoffset = src->y1 >> 16; ++ u32 align16_crop = 0; ++ u32 align64_crop = 0; ++ u32 height_tmp; ++ u8 tx, ty; ++ u8 bottom_crop_line_num = 0; + + /* 16 pixel align */ + if (height & 0xf) @@ -3223,90 +2147,52 @@ index 0000000000000..7d39ba90061d1 + if (height_tmp & 0x3f) + align64_crop = 64 - (height_tmp & 0x3f); + -+ top_crop_line_num = top_crop << 2; -+ if (top_crop == 0) -+ bottom_crop_line_num = align16_crop + align64_crop; -+ else if (top_crop == 1) -+ bottom_crop_line_num = align16_crop + align64_crop + 12; -+ else if (top_crop == 2) -+ bottom_crop_line_num = align16_crop + align64_crop + 8; ++ bottom_crop_line_num = align16_crop + align64_crop; + + switch (pstate->rotation & -+ (DRM_MODE_REFLECT_X | -+ DRM_MODE_REFLECT_Y | -+ DRM_MODE_ROTATE_90 | -+ DRM_MODE_ROTATE_270)) { ++ (DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y | ++ DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270)) { + case DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y: -+ transform_tmp = act_xoffset + width; -+ transform_xoffset = 16 - (transform_tmp & 0xf); -+ transform_tmp = bottom_crop_line_num - act_yoffset; -+ -+ if (afbc_half_block_en) -+ transform_yoffset = transform_tmp & 0x7; -+ else -+ transform_yoffset = (transform_tmp & 0xf); -+ ++ tx = 16 - ((act_xoffset + width) & 0xf); ++ ty = bottom_crop_line_num - act_yoffset; + break; + case DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_90: -+ transform_tmp = bottom_crop_line_num - act_yoffset; -+ transform_xoffset = transform_tmp & 0xf; -+ transform_tmp = vir_width - width - act_xoffset; -+ transform_yoffset = transform_tmp & 0xf; ++ tx = bottom_crop_line_num - act_yoffset; ++ ty = vir_width - width - act_xoffset; + break; + case DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_270: -+ transform_tmp = top_crop_line_num + act_yoffset; -+ transform_xoffset = transform_tmp & 0xf; -+ transform_tmp = act_xoffset; -+ transform_yoffset = transform_tmp & 0xf; ++ tx = act_yoffset; ++ ty = act_xoffset; + break; + case DRM_MODE_REFLECT_X: -+ transform_tmp = act_xoffset + width; -+ transform_xoffset = 16 - (transform_tmp & 0xf); -+ transform_tmp = top_crop_line_num + act_yoffset; -+ -+ if (afbc_half_block_en) -+ transform_yoffset = transform_tmp & 0x7; -+ else -+ transform_yoffset = transform_tmp & 0xf; -+ ++ tx = 16 - ((act_xoffset + width) & 0xf); ++ ty = act_yoffset; + break; + case DRM_MODE_REFLECT_Y: -+ transform_tmp = act_xoffset; -+ transform_xoffset = transform_tmp & 0xf; -+ transform_tmp = bottom_crop_line_num - act_yoffset; -+ -+ if (afbc_half_block_en) -+ transform_yoffset = transform_tmp & 0x7; -+ else -+ transform_yoffset = transform_tmp & 0xf; -+ ++ tx = act_xoffset; ++ ty = bottom_crop_line_num - act_yoffset; + break; + case DRM_MODE_ROTATE_90: -+ transform_tmp = bottom_crop_line_num - act_yoffset; -+ transform_xoffset = transform_tmp & 0xf; -+ transform_tmp = act_xoffset; -+ transform_yoffset = transform_tmp & 0xf; ++ tx = bottom_crop_line_num - act_yoffset; ++ ty = act_xoffset; + break; + case DRM_MODE_ROTATE_270: -+ transform_tmp = top_crop_line_num + act_yoffset; -+ transform_xoffset = transform_tmp & 0xf; -+ transform_tmp = vir_width - width - act_xoffset; -+ transform_yoffset = transform_tmp & 0xf; ++ tx = act_yoffset; ++ ty = vir_width - width - act_xoffset; + break; + case 0: -+ transform_tmp = act_xoffset; -+ transform_xoffset = transform_tmp & 0xf; -+ transform_tmp = top_crop_line_num + act_yoffset; -+ -+ if (afbc_half_block_en) -+ transform_yoffset = transform_tmp & 0x7; -+ else -+ transform_yoffset = transform_tmp & 0xf; -+ ++ tx = act_xoffset; ++ ty = act_yoffset; + break; + } + -+ return (transform_xoffset & 0xf) | ((transform_yoffset & 0xf) << 16); ++ if (afbc_half_block_en) ++ ty &= 0x7f; ++ ++#define TRANSFORM_XOFFSET GENMASK(7, 0) ++#define TRANSFORM_YOFFSET GENMASK(23, 16) ++ return FIELD_PREP(TRANSFORM_XOFFSET, tx) | ++ FIELD_PREP(TRANSFORM_YOFFSET, ty); +} + +/* @@ -3318,83 +2204,59 @@ index 0000000000000..7d39ba90061d1 + * 2: half mode, for rotate_90/270 mode + * + */ -+static int vop2_get_cluster_lb_mode(struct vop2_win *win, struct drm_plane_state *pstate) ++static int vop2_get_cluster_lb_mode(struct vop2_win *win, ++ struct drm_plane_state *pstate) +{ -+ if ((pstate->rotation & DRM_MODE_ROTATE_270) || (pstate->rotation & DRM_MODE_ROTATE_90)) ++ if ((pstate->rotation & DRM_MODE_ROTATE_270) || ++ (pstate->rotation & DRM_MODE_ROTATE_90)) + return 2; + else + return 0; +} + -+/* -+ * bli_sd_factor = (src - 1) / (dst - 1) << 12; -+ * avg_sd_factor: -+ * bli_su_factor: -+ * bic_su_factor: -+ * = (src - 1) / (dst - 1) << 16; -+ * -+ * gt2 enable: dst get one line from two line of the src -+ * gt4 enable: dst get one line from four line of the src. -+ * -+ */ -+static uint16_t vop2_scale_factor(enum scale_mode mode, -+ int32_t filter_mode, -+ uint32_t src, uint32_t dst) ++static u16 vop2_scale_factor(u32 src, u32 dst) +{ -+ uint32_t fac; -+ int i; ++ u32 fac; ++ int shift; + -+ if (mode == SCALE_NONE) ++ if (src == dst) + return 0; + -+ /* -+ * A workaround to avoid zero div. -+ */ -+ if (dst == 1 || src == 1) { -+ dst++; -+ src++; -+ } ++ if (dst < 2) ++ return U16_MAX; + -+ if ((mode == SCALE_DOWN) && (filter_mode == VOP2_SCALE_DOWN_BIL)) { -+ fac = ((src - 1) << 12) / (dst - 1); -+ for (i = 0; i < 100; i++) { -+ if (fac * (dst - 1) >> 12 < (src - 1)) -+ break; -+ fac -= 1; -+ DRM_DEBUG("down fac cali: src:%d, dst:%d, fac:0x%x\n", src, dst, fac); -+ } -+ } else { -+ fac = ((src - 1) << 16) / (dst - 1); -+ for (i = 0; i < 100; i++) { -+ if (fac * (dst - 1) >> 16 < (src - 1)) -+ break; -+ fac -= 1; -+ DRM_DEBUG("up fac cali: src:%d, dst:%d, fac:0x%x\n", src, dst, fac); -+ } -+ } ++ if (src < 2) ++ return 0; ++ ++ if (src > dst) ++ shift = 12; ++ else ++ shift = 16; ++ ++ src--; ++ dst--; ++ ++ fac = DIV_ROUND_UP(src << shift, dst) - 1; ++ ++ if (fac > U16_MAX) ++ return U16_MAX; + + return fac; +} + +static void vop2_setup_scale(struct vop2 *vop2, const struct vop2_win *win, -+ uint32_t src_w, uint32_t src_h, uint32_t dst_w, -+ uint32_t dst_h, uint32_t pixel_format) ++ u32 src_w, u32 src_h, u32 dst_w, ++ u32 dst_h, u32 pixel_format) +{ + const struct drm_format_info *info; -+ uint16_t cbcr_src_w; -+ uint16_t cbcr_src_h; -+ uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; -+ uint16_t cbcr_hor_scl_mode, cbcr_ver_scl_mode; -+ uint16_t hscl_filter_mode, vscl_filter_mode; -+ uint8_t gt2 = 0; -+ uint8_t gt4 = 0; -+ uint32_t val; ++ u16 hor_scl_mode, ver_scl_mode; ++ u16 hscl_filter_mode, vscl_filter_mode; ++ u8 gt2 = 0; ++ u8 gt4 = 0; ++ u32 val; + + info = drm_format_info(pixel_format); + -+ cbcr_src_w = src_w / info->hsub; -+ cbcr_src_h = src_h / info->vsub; -+ + if (src_h >= (4 * dst_h)) { + gt4 = 1; + src_h >>= 2; @@ -3403,15 +2265,15 @@ index 0000000000000..7d39ba90061d1 + src_h >>= 1; + } + -+ yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); -+ yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); ++ hor_scl_mode = scl_get_scl_mode(src_w, dst_w); ++ ver_scl_mode = scl_get_scl_mode(src_h, dst_h); + -+ if (yrgb_hor_scl_mode == SCALE_UP) ++ if (hor_scl_mode == SCALE_UP) + hscl_filter_mode = VOP2_SCALE_UP_BIC; + else + hscl_filter_mode = VOP2_SCALE_DOWN_BIL; + -+ if (yrgb_ver_scl_mode == SCALE_UP) ++ if (ver_scl_mode == SCALE_UP) + vscl_filter_mode = VOP2_SCALE_UP_BIL; + else + vscl_filter_mode = VOP2_SCALE_DOWN_BIL; @@ -3421,25 +2283,23 @@ index 0000000000000..7d39ba90061d1 + * at scale down mode + */ + if (!(win->data->feature & WIN_FEATURE_AFBDC)) { -+ if ((yrgb_hor_scl_mode == SCALE_DOWN) && (dst_w & 0x1)) { ++ if ((hor_scl_mode == SCALE_DOWN) && (dst_w & 0x1)) { + drm_dbg(vop2->drm, "%s dst_w[%d] should align as 2 pixel\n", + win->data->name, dst_w); -+ dst_w += 1; ++ dst_w++; + } + } + -+ val = vop2_scale_factor(yrgb_hor_scl_mode, hscl_filter_mode, -+ src_w, dst_w); ++ val = vop2_scale_factor(src_w, dst_w); + vop2_win_write(win, VOP2_WIN_SCALE_YRGB_X, val); -+ val = vop2_scale_factor(yrgb_ver_scl_mode, vscl_filter_mode, -+ src_h, dst_h); ++ val = vop2_scale_factor(src_h, dst_h); + vop2_win_write(win, VOP2_WIN_SCALE_YRGB_Y, val); + + vop2_win_write(win, VOP2_WIN_VSD_YRGB_GT4, gt4); + vop2_win_write(win, VOP2_WIN_VSD_YRGB_GT2, gt2); + -+ vop2_win_write(win, VOP2_WIN_YRGB_HOR_SCL_MODE, yrgb_hor_scl_mode); -+ vop2_win_write(win, VOP2_WIN_YRGB_VER_SCL_MODE, yrgb_ver_scl_mode); ++ vop2_win_write(win, VOP2_WIN_YRGB_HOR_SCL_MODE, hor_scl_mode); ++ vop2_win_write(win, VOP2_WIN_YRGB_VER_SCL_MODE, ver_scl_mode); + + if (vop2_cluster_window(win)) + return; @@ -3448,33 +2308,32 @@ index 0000000000000..7d39ba90061d1 + vop2_win_write(win, VOP2_WIN_YRGB_VSCL_FILTER_MODE, vscl_filter_mode); + + if (info->is_yuv) { ++ src_w /= info->hsub; ++ src_h /= info->vsub; ++ + gt4 = gt2 = 0; + -+ if (cbcr_src_h >= (4 * dst_h)) ++ if (src_h >= (4 * dst_h)) { + gt4 = 1; -+ else if (cbcr_src_h >= (2 * dst_h)) ++ src_h >>= 2; ++ } else if (src_h >= (2 * dst_h)) { + gt2 = 1; ++ src_h >>= 1; ++ } + -+ if (gt4) -+ cbcr_src_h >>= 2; -+ else if (gt2) -+ cbcr_src_h >>= 1; ++ hor_scl_mode = scl_get_scl_mode(src_w, dst_w); ++ ver_scl_mode = scl_get_scl_mode(src_h, dst_h); + -+ cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w); -+ cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h); -+ -+ val = vop2_scale_factor(cbcr_hor_scl_mode, hscl_filter_mode, -+ cbcr_src_w, dst_w); ++ val = vop2_scale_factor(src_w, dst_w); + vop2_win_write(win, VOP2_WIN_SCALE_CBCR_X, val); + -+ val = vop2_scale_factor(cbcr_ver_scl_mode, vscl_filter_mode, -+ cbcr_src_h, dst_h); ++ val = vop2_scale_factor(src_h, dst_h); + vop2_win_write(win, VOP2_WIN_SCALE_CBCR_Y, val); + + vop2_win_write(win, VOP2_WIN_VSD_CBCR_GT4, gt4); + vop2_win_write(win, VOP2_WIN_VSD_CBCR_GT2, gt2); -+ vop2_win_write(win, VOP2_WIN_CBCR_HOR_SCL_MODE, cbcr_hor_scl_mode); -+ vop2_win_write(win, VOP2_WIN_CBCR_VER_SCL_MODE, cbcr_ver_scl_mode); ++ vop2_win_write(win, VOP2_WIN_CBCR_HOR_SCL_MODE, hor_scl_mode); ++ vop2_win_write(win, VOP2_WIN_CBCR_VER_SCL_MODE, ver_scl_mode); + vop2_win_write(win, VOP2_WIN_CBCR_HSCL_FILTER_MODE, hscl_filter_mode); + vop2_win_write(win, VOP2_WIN_CBCR_VSCL_FILTER_MODE, vscl_filter_mode); + } @@ -3546,17 +2405,17 @@ index 0000000000000..7d39ba90061d1 + int csc_mode; + + if (is_input_yuv && !is_output_yuv) { -+ y2r_en = 1; -+ r2y_en = 0; ++ y2r_en = true; ++ r2y_en = false; + csc_mode = vop2_convert_csc_mode(input_csc); + } else if (!is_input_yuv && is_output_yuv) { -+ y2r_en = 0; -+ r2y_en = 1; ++ y2r_en = false; ++ r2y_en = true; + csc_mode = vop2_convert_csc_mode(output_csc); + } else { -+ y2r_en = 0; -+ r2y_en = 0; -+ csc_mode = 0; ++ y2r_en = false; ++ r2y_en = false; ++ csc_mode = false; + } + + vop2_win_write(win, VOP2_WIN_Y2R_EN, y2r_en); @@ -3564,7 +2423,7 @@ index 0000000000000..7d39ba90061d1 + vop2_win_write(win, VOP2_WIN_CSC_MODE, csc_mode); +} + -+static void vop2_crtc_enable_irq(struct vop2_video_port *vp, uint32_t irq) ++static void vop2_crtc_enable_irq(struct vop2_video_port *vp, u32 irq) +{ + struct vop2 *vop2 = vp->vop2; + @@ -3572,7 +2431,7 @@ index 0000000000000..7d39ba90061d1 + vop2_writel(vop2, RK3568_VP_INT_EN(vp->id), irq << 16 | irq); +} + -+static void vop2_crtc_disable_irq(struct vop2_video_port *vp, uint32_t irq) ++static void vop2_crtc_disable_irq(struct vop2_video_port *vp, u32 irq) +{ + struct vop2 *vop2 = vp->vop2; + @@ -3605,7 +2464,6 @@ index 0000000000000..7d39ba90061d1 +static void vop2_enable(struct vop2 *vop2) +{ + int ret; -+ uint32_t v; + + ret = pm_runtime_get_sync(vop2->dev); + if (ret < 0) { @@ -3628,9 +2486,8 @@ index 0000000000000..7d39ba90061d1 + * Disable auto gating, this is a workaround to + * avoid display image shift when a window enabled. + */ -+ v = vop2_readl(vop2, RK3568_SYS_AUTO_GATING_CTRL); -+ v &= ~RK3568_SYS_AUTO_GATING_CTRL__AUTO_GATING_EN; -+ vop2_writel(vop2, RK3568_SYS_AUTO_GATING_CTRL, v); ++ regmap_clear_bits(vop2->map, RK3568_SYS_AUTO_GATING_CTRL, ++ RK3568_SYS_AUTO_GATING_CTRL__AUTO_GATING_EN); + + vop2_writel(vop2, RK3568_SYS0_INT_CLR, + VOP2_INT_BUS_ERRPR << 16 | VOP2_INT_BUS_ERRPR); @@ -3671,13 +2528,11 @@ index 0000000000000..7d39ba90061d1 + reinit_completion(&vp->dsp_hold_completion); + + vop2_crtc_enable_irq(vp, VP_INT_DSP_HOLD_VALID); -+ spin_lock(&vop2->reg_lock); + -+ vop2_writel(vop2, RK3568_VP_DSP_CTRL, 1); ++ vop2_vp_write(vp, RK3568_VP_DSP_CTRL, RK3568_VP_DSP_CTRL__STANDBY); + -+ spin_unlock(&vop2->reg_lock); -+ -+ ret = wait_for_completion_timeout(&vp->dsp_hold_completion, msecs_to_jiffies(50)); ++ ret = wait_for_completion_timeout(&vp->dsp_hold_completion, ++ msecs_to_jiffies(50)); + if (!ret) + drm_info(vop2->drm, "wait for vp%d dsp_hold timeout\n", vp->id); + @@ -3701,7 +2556,8 @@ index 0000000000000..7d39ba90061d1 + } +} + -+static int vop2_plane_atomic_check(struct drm_plane *plane, struct drm_atomic_state *astate) ++static int vop2_plane_atomic_check(struct drm_plane *plane, ++ struct drm_atomic_state *astate) +{ + struct drm_plane_state *pstate = drm_atomic_get_new_plane_state(astate, plane); + struct drm_framebuffer *fb = pstate->fb; @@ -3772,7 +2628,8 @@ index 0000000000000..7d39ba90061d1 + return 0; +} + -+static void vop2_plane_atomic_disable(struct drm_plane *plane, struct drm_atomic_state *state) ++static void vop2_plane_atomic_disable(struct drm_plane *plane, ++ struct drm_atomic_state *state) +{ + struct drm_plane_state *old_pstate = drm_atomic_get_old_plane_state(state, plane); + struct vop2_win *win = to_vop2_win(plane); @@ -3783,27 +2640,23 @@ index 0000000000000..7d39ba90061d1 + if (!old_pstate->crtc) + return; + -+ spin_lock(&vop2->reg_lock); -+ + vop2_win_disable(win); + vop2_win_write(win, VOP2_WIN_YUV_CLIP, 0); -+ -+ spin_unlock(&vop2->reg_lock); +} + +/* + * The color key is 10 bit, so all format should + * convert to 10 bit here. + */ -+static void vop2_plane_setup_color_key(struct drm_plane *plane, uint32_t color_key) ++static void vop2_plane_setup_color_key(struct drm_plane *plane, u32 color_key) +{ + struct drm_plane_state *pstate = plane->state; + struct drm_framebuffer *fb = pstate->fb; + struct vop2_win *win = to_vop2_win(plane); -+ uint32_t color_key_en = 0; -+ uint32_t r = 0; -+ uint32_t g = 0; -+ uint32_t b = 0; ++ u32 color_key_en = 0; ++ u32 r = 0; ++ u32 g = 0; ++ u32 b = 0; + + if (!(color_key & VOP2_COLOR_KEY_MASK) || fb->format->is_yuv) { + vop2_win_write(win, VOP2_WIN_COLOR_KEY_EN, 0); @@ -3841,7 +2694,8 @@ index 0000000000000..7d39ba90061d1 + vop2_win_write(win, VOP2_WIN_COLOR_KEY, (r << 20) | (g << 10) | b); +} + -+static void vop2_plane_atomic_update(struct drm_plane *plane, struct drm_atomic_state *state) ++static void vop2_plane_atomic_update(struct drm_plane *plane, ++ struct drm_atomic_state *state) +{ + struct drm_plane_state *pstate = plane->state; + struct drm_crtc *crtc = pstate->crtc; @@ -3850,21 +2704,20 @@ index 0000000000000..7d39ba90061d1 + struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode; + struct vop2 *vop2 = win->vop2; + struct drm_framebuffer *fb = pstate->fb; -+ uint32_t bpp = fb->format->cpp[0] * 8; -+ uint32_t actual_w, actual_h, dsp_w, dsp_h; -+ uint32_t act_info, dsp_info; -+ uint32_t format; -+ uint32_t afbc_format; -+ uint32_t rb_swap; -+ uint32_t uv_swap; ++ u32 bpp = fb->format->cpp[0] * 8; ++ u32 actual_w, actual_h, dsp_w, dsp_h; ++ u32 act_info, dsp_info; ++ u32 format; ++ u32 afbc_format; ++ u32 rb_swap; ++ u32 uv_swap; + struct drm_rect *src = &pstate->src; + struct drm_rect *dest = &pstate->dst; -+ uint32_t afbc_tile_num; -+ uint32_t afbc_half_block_en; -+ uint32_t transform_offset; ++ u32 afbc_tile_num; ++ u32 transform_offset; + bool dither_up; -+ bool xmirror = pstate->rotation & DRM_MODE_REFLECT_X; -+ bool ymirror = pstate->rotation & DRM_MODE_REFLECT_Y; ++ bool xmirror = pstate->rotation & DRM_MODE_REFLECT_X ? true : false; ++ bool ymirror = pstate->rotation & DRM_MODE_REFLECT_Y ? true : false; + bool rotate_270 = pstate->rotation & DRM_MODE_ROTATE_270; + bool rotate_90 = pstate->rotation & DRM_MODE_ROTATE_90; + struct rockchip_gem_object *rk_obj; @@ -3909,7 +2762,7 @@ index 0000000000000..7d39ba90061d1 + offset += (src->y1 >> 16) * fb->pitches[1] / vsub; + + if ((pstate->rotation & DRM_MODE_REFLECT_Y) && !afbc_en) -+ offset += fb->pitches[1] * ((pstate->src_h >> 16) - 2) / vsub; ++ offset += fb->pitches[1] * ((pstate->src_h >> 16) - 2) / vsub; + + rk_obj = to_rockchip_obj(fb->obj[0]); + uv_mst = rk_obj->dma_addr + offset + fb->offsets[1]; @@ -3945,13 +2798,14 @@ index 0000000000000..7d39ba90061d1 + */ + if (!(win->data->feature & WIN_FEATURE_AFBDC)) { + if (actual_w > dsp_w && (actual_w & 0xf) == 1) { -+ drm_err(vop2->drm, "vp%d %s act_w[%d] MODE 16 == 1\n", vp->id, win->data->name, actual_w); ++ drm_err(vop2->drm, "vp%d %s act_w[%d] MODE 16 == 1\n", ++ vp->id, win->data->name, actual_w); + actual_w -= 1; + } + } + + if (afbc_en && actual_w % 4) { -+ drm_err(vop2->drm, "vp%d %s actual_w[%d] should align as 4 pixel when enable afbc\n", ++ drm_err(vop2->drm, "vp%d %s actual_w[%d] not 4 pixel aligned\n", + vp->id, win->data->name, actual_w); + actual_w = ALIGN_DOWN(actual_w, 4); + } @@ -3961,7 +2815,6 @@ index 0000000000000..7d39ba90061d1 + + format = vop2_convert_format(fb->format->format); + -+ spin_lock(&vop2->reg_lock); + drm_dbg(vop2->drm, "vp%d update %s[%dx%d->%dx%d@%dx%d] fmt[%p4cc_%s] addr[%pad]\n", + vp->id, win->data->name, actual_w, actual_h, dsp_w, dsp_h, + dest->x1, dest->y1, @@ -3969,7 +2822,7 @@ index 0000000000000..7d39ba90061d1 + afbc_en ? "AFBC" : "", &yrgb_mst); + + if (afbc_en) { -+ uint32_t stride; ++ u32 stride; + + /* the afbc superblock is 16 x 16 */ + afbc_format = vop2_convert_afbc_format(fb->format->format); @@ -3986,8 +2839,8 @@ index 0000000000000..7d39ba90061d1 + */ + stride = (fb->pitches[0] << 3) / bpp; + if ((stride & 0x3f) && (xmirror || rotate_90 || rotate_270)) -+ drm_err(vop2->drm, "vp%d %s stride[%d] must align as 64 pixel when enable xmirror/rotate_90/rotate_270[0x%x]\n", -+ vp->id, win->data->name, stride, pstate->rotation); ++ drm_err(vop2->drm, "vp%d %s stride[%d] not 64 pixel aligened\n", ++ vp->id, win->data->name, stride); + + rb_swap = vop2_afbc_rb_swap(fb->format->format); + uv_swap = vop2_afbc_uv_swap(fb->format->format); @@ -4003,8 +2856,6 @@ index 0000000000000..7d39ba90061d1 + if (fb->format->is_yuv && (bpp == 10)) + format = VOP2_CLUSTER_YUV444_10; + -+ afbc_half_block_en = vop2_afbc_half_block_enable(pstate); -+ transform_offset = vop2_afbc_transform_offset(pstate, afbc_half_block_en); + if (vop2_cluster_window(win)) + vop2_win_write(win, VOP2_WIN_AFBC_ENABLE, 1); + vop2_win_write(win, VOP2_WIN_AFBC_FORMAT, afbc_format); @@ -4012,7 +2863,13 @@ index 0000000000000..7d39ba90061d1 + vop2_win_write(win, VOP2_WIN_AFBC_UV_SWAP, uv_swap); + vop2_win_write(win, VOP2_WIN_AFBC_AUTO_GATING_EN, 0); + vop2_win_write(win, VOP2_WIN_AFBC_BLOCK_SPLIT_EN, 0); -+ vop2_win_write(win, VOP2_WIN_AFBC_HALF_BLOCK_EN, afbc_half_block_en); ++ if (pstate->rotation & (DRM_MODE_ROTATE_270 | DRM_MODE_ROTATE_90)) { ++ vop2_win_write(win, VOP2_WIN_AFBC_HALF_BLOCK_EN, 0); ++ transform_offset = vop2_afbc_transform_offset(pstate, false); ++ } else { ++ vop2_win_write(win, VOP2_WIN_AFBC_HALF_BLOCK_EN, 1); ++ transform_offset = vop2_afbc_transform_offset(pstate, true); ++ } + vop2_win_write(win, VOP2_WIN_AFBC_HDR_PTR, yrgb_mst); + vop2_win_write(win, VOP2_WIN_AFBC_PIC_SIZE, act_info); + vop2_win_write(win, VOP2_WIN_AFBC_TRANSFORM_OFFSET, transform_offset); @@ -4070,8 +2927,6 @@ index 0000000000000..7d39ba90061d1 + vop2_win_write(win, VOP2_WIN_CLUSTER_LB_MODE, lb_mode); + vop2_win_write(win, VOP2_WIN_CLUSTER_ENABLE, 1); + } -+ -+ spin_unlock(&vop2->reg_lock); +} + +static const struct drm_plane_helper_funcs vop2_plane_helper_funcs = { @@ -4110,12 +2965,13 @@ index 0000000000000..7d39ba90061d1 + const struct drm_display_mode *mode, + struct drm_display_mode *adj_mode) +{ -+ drm_mode_set_crtcinfo(adj_mode, CRTC_INTERLACE_HALVE_V | CRTC_STEREO_DOUBLE); ++ drm_mode_set_crtcinfo(adj_mode, CRTC_INTERLACE_HALVE_V | ++ CRTC_STEREO_DOUBLE); + + return true; +} + -+static void vop2_dither_setup(struct drm_crtc *crtc, uint32_t *dsp_ctrl) ++static void vop2_dither_setup(struct drm_crtc *crtc, u32 *dsp_ctrl) +{ + struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state); + @@ -4147,18 +3003,18 @@ index 0000000000000..7d39ba90061d1 +static void vop2_post_config(struct drm_crtc *crtc) +{ + struct vop2_video_port *vp = to_vop2_video_port(crtc); -+ struct vop2 *vop2 = vp->vop2; + struct drm_display_mode *mode = &crtc->state->adjusted_mode; -+ uint16_t vtotal = mode->crtc_vtotal; -+ uint16_t hdisplay = mode->crtc_hdisplay; -+ uint16_t hact_st = mode->crtc_htotal - mode->crtc_hsync_start; -+ uint16_t vdisplay = mode->crtc_vdisplay; -+ uint16_t vact_st = mode->crtc_vtotal - mode->crtc_vsync_start; -+ uint32_t left_margin = 100, right_margin = 100, top_margin = 100, bottom_margin = 100; -+ uint16_t hsize = hdisplay * (left_margin + right_margin) / 200; -+ uint16_t vsize = vdisplay * (top_margin + bottom_margin) / 200; -+ uint16_t hact_end, vact_end; -+ uint32_t val; ++ u16 vtotal = mode->crtc_vtotal; ++ u16 hdisplay = mode->crtc_hdisplay; ++ u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start; ++ u16 vdisplay = mode->crtc_vdisplay; ++ u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start; ++ u32 left_margin = 100, right_margin = 100; ++ u32 top_margin = 100, bottom_margin = 100; ++ u16 hsize = hdisplay * (left_margin + right_margin) / 200; ++ u16 vsize = vdisplay * (top_margin + bottom_margin) / 200; ++ u16 hact_end, vact_end; ++ u32 val; + + vsize = rounddown(vsize, 2); + hsize = rounddown(hsize, 2); @@ -4181,11 +3037,11 @@ index 0000000000000..7d39ba90061d1 + val |= RK3568_VP_POST_SCL_CTRL__HSCALEDOWN; + if (vdisplay != vsize) + val |= RK3568_VP_POST_SCL_CTRL__VSCALEDOWN; -+ vop2_writel(vop2, RK3568_VP_POST_SCL_CTRL, val); ++ vop2_vp_write(vp, RK3568_VP_POST_SCL_CTRL, val); + + if (mode->flags & DRM_MODE_FLAG_INTERLACE) { -+ uint16_t vact_st_f1 = vtotal + vact_st + 1; -+ uint16_t vact_end_f1 = vact_st_f1 + vsize; ++ u16 vact_st_f1 = vtotal + vact_st + 1; ++ u16 vact_end_f1 = vact_st_f1 + vsize; + + val = vact_st_f1 << 16 | vact_end_f1; + vop2_vp_write(vp, RK3568_VP_POST_DSP_VACT_INFO_F1, val); @@ -4195,10 +3051,10 @@ index 0000000000000..7d39ba90061d1 +} + +static void rk3568_set_intf_mux(struct vop2_video_port *vp, int id, -+ uint32_t polflags) ++ u32 polflags) +{ + struct vop2 *vop2 = vp->vop2; -+ uint32_t die, dip; ++ u32 die, dip; + + die = vop2_readl(vop2, RK3568_DSP_IF_EN); + dip = vop2_readl(vop2, RK3568_DSP_IF_POL); @@ -4266,7 +3122,8 @@ index 0000000000000..7d39ba90061d1 + return us * mode->clock / mode->htotal / 1000; +} + -+static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_state *state) ++static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, ++ struct drm_atomic_state *state) +{ + struct vop2_video_port *vp = to_vop2_video_port(crtc); + struct vop2 *vop2 = vp->vop2; @@ -4276,20 +3133,20 @@ index 0000000000000..7d39ba90061d1 + struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state); + struct drm_display_mode *mode = &crtc->state->adjusted_mode; + unsigned long clock = mode->crtc_clock * 1000; -+ uint16_t hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; -+ uint16_t hdisplay = mode->crtc_hdisplay; -+ uint16_t htotal = mode->crtc_htotal; -+ uint16_t hact_st = mode->crtc_htotal - mode->crtc_hsync_start; -+ uint16_t hact_end = hact_st + hdisplay; -+ uint16_t vdisplay = mode->crtc_vdisplay; -+ uint16_t vtotal = mode->crtc_vtotal; -+ uint16_t vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; -+ uint16_t vact_st = mode->crtc_vtotal - mode->crtc_vsync_start; -+ uint16_t vact_end = vact_st + vdisplay; -+ uint8_t out_mode; -+ uint32_t dsp_ctrl = 0; ++ u16 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; ++ u16 hdisplay = mode->crtc_hdisplay; ++ u16 htotal = mode->crtc_htotal; ++ u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start; ++ u16 hact_end = hact_st + hdisplay; ++ u16 vdisplay = mode->crtc_vdisplay; ++ u16 vtotal = mode->crtc_vtotal; ++ u16 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; ++ u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start; ++ u16 vact_end = vact_st + vdisplay; ++ u8 out_mode; ++ u32 dsp_ctrl = 0; + int act_end; -+ uint32_t val, polflags; ++ u32 val, polflags; + int ret; + struct drm_encoder *encoder; + @@ -4322,9 +3179,10 @@ index 0000000000000..7d39ba90061d1 + polflags |= BIT(VSYNC_POSITIVE); + + drm_for_each_encoder_mask(encoder, crtc->dev, crtc_state->encoder_mask) { ++ struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); + struct device_node *node, *parent; + -+ parent = of_get_parent(encoder->port); ++ parent = of_get_parent(rkencoder->port); + + for_each_endpoint_of_node(parent, node) { + struct device_node *crtc_port = of_graph_get_remote_port(node); @@ -4375,8 +3233,8 @@ index 0000000000000..7d39ba90061d1 + vop2_vp_write(vp, RK3568_VP_DSP_VACT_ST_END, val); + + if (mode->flags & DRM_MODE_FLAG_INTERLACE) { -+ uint16_t vact_st_f1 = vtotal + vact_st + 1; -+ uint16_t vact_end_f1 = vact_st_f1 + vdisplay; ++ u16 vact_st_f1 = vtotal + vact_st + 1; ++ u16 vact_end_f1 = vact_st_f1 + vdisplay; + + val = vact_st_f1 << 16 | vact_end_f1; + vop2_vp_write(vp, RK3568_VP_DSP_VACT_ST_END_F1, val); @@ -4434,7 +3292,7 @@ index 0000000000000..7d39ba90061d1 + return 0; +} + -+static bool is_opaque(uint16_t alpha) ++static bool is_opaque(u16 alpha) +{ + return (alpha >> 8) == 0xff; +} @@ -4444,8 +3302,10 @@ index 0000000000000..7d39ba90061d1 +{ + int src_glb_alpha_en = is_opaque(alpha_config->src_glb_alpha_value) ? 0 : 1; + int dst_glb_alpha_en = is_opaque(alpha_config->dst_glb_alpha_value) ? 0 : 1; -+ int src_color_mode = alpha_config->src_premulti_en ? ALPHA_SRC_PRE_MUL : ALPHA_SRC_NO_PRE_MUL; -+ int dst_color_mode = alpha_config->dst_premulti_en ? ALPHA_SRC_PRE_MUL : ALPHA_SRC_NO_PRE_MUL; ++ int src_color_mode = alpha_config->src_premulti_en ? ++ ALPHA_SRC_PRE_MUL : ALPHA_SRC_NO_PRE_MUL; ++ int dst_color_mode = alpha_config->dst_premulti_en ? ++ ALPHA_SRC_PRE_MUL : ALPHA_SRC_NO_PRE_MUL; + + alpha->src_color_ctrl.val = 0; + alpha->dst_color_ctrl.val = 0; @@ -4496,7 +3356,7 @@ index 0000000000000..7d39ba90061d1 + alpha->dst_alpha_ctrl.bits.factor_mode = ALPHA_SRC_INVERSE; +} + -+static int vop2_find_start_mixer_id_for_vp(struct vop2 *vop2, uint8_t port_id) ++static int vop2_find_start_mixer_id_for_vp(struct vop2 *vop2, u8 port_id) +{ + struct vop2_video_port *vp; + int used_layer = 0; @@ -4512,12 +3372,12 @@ index 0000000000000..7d39ba90061d1 + +static void vop2_setup_cluster_alpha(struct vop2 *vop2, struct vop2_win *main_win) +{ -+ uint32_t offset = (main_win->data->phys_id * 0x10); ++ u32 offset = (main_win->data->phys_id * 0x10); + struct vop2_alpha_config alpha_config; + struct vop2_alpha alpha; + struct drm_plane_state *bottom_win_pstate; + bool src_pixel_alpha_en = false; -+ uint16_t src_glb_alpha_val, dst_glb_alpha_val; ++ u16 src_glb_alpha_val, dst_glb_alpha_val; + bool premulti_en = false; + bool swap = false; + @@ -4558,9 +3418,9 @@ index 0000000000000..7d39ba90061d1 + int pixel_alpha_en; + int premulti_en, gpremulti_en = 0; + int mixer_id; -+ uint32_t offset; ++ u32 offset; + bool bottom_layer_alpha_en = false; -+ uint32_t dst_global_alpha = DRM_BLEND_ALPHA_OPAQUE; ++ u32 dst_global_alpha = DRM_BLEND_ALPHA_OPAQUE; + + mixer_id = vop2_find_start_mixer_id_for_vp(vop2, vp->id); + alpha_config.dst_pixel_alpha_en = true; /* alpha value need transfer to next mix */ @@ -4655,21 +3515,18 @@ index 0000000000000..7d39ba90061d1 + } +} + -+#define NR_VPS 3 -+#define NR_MIXERS 6 -+ +static void vop2_setup_layer_mixer(struct vop2_video_port *vp) +{ + struct vop2 *vop2 = vp->vop2; + struct drm_plane *plane; -+ uint32_t layer_sel = 0; -+ uint32_t port_sel; -+ int nlayer, ofs; ++ u32 layer_sel = 0; ++ u32 port_sel; ++ unsigned int nlayer, ofs; + struct drm_display_mode *adjusted_mode; -+ uint16_t hsync_len; -+ uint16_t hdisplay; -+ uint32_t bg_dly; -+ uint32_t pre_scan_dly; ++ u16 hsync_len; ++ u16 hdisplay; ++ u32 bg_dly; ++ u32 pre_scan_dly; + int i; + struct vop2_video_port *vp0 = &vop2->vps[0]; + struct vop2_video_port *vp1 = &vop2->vps[1]; @@ -4765,10 +3622,10 @@ index 0000000000000..7d39ba90061d1 +{ + struct vop2_win *win; + int i = 0; -+ uint32_t cdly = 0, sdly = 0; ++ u32 cdly = 0, sdly = 0; + + for (i = 0; i < vop2->data->win_size; i++) { -+ uint32_t dly; ++ u32 dly; + + win = &vop2->win[i]; + dly = win->delay; @@ -4801,7 +3658,8 @@ index 0000000000000..7d39ba90061d1 + vop2_writel(vop2, RK3568_SMART_DLY_NUM, sdly); +} + -+static void vop2_crtc_atomic_begin(struct drm_crtc *crtc, struct drm_atomic_state *state) ++static void vop2_crtc_atomic_begin(struct drm_crtc *crtc, ++ struct drm_atomic_state *state) +{ + struct vop2_video_port *vp = to_vop2_video_port(crtc); + struct vop2 *vop2 = vp->vop2; @@ -4828,17 +3686,13 @@ index 0000000000000..7d39ba90061d1 + vop2_setup_dly_for_windows(vop2); +} + -+static void vop2_crtc_atomic_flush(struct drm_crtc *crtc, struct drm_atomic_state *state) ++static void vop2_crtc_atomic_flush(struct drm_crtc *crtc, ++ struct drm_atomic_state *state) +{ + struct vop2_video_port *vp = to_vop2_video_port(crtc); -+ struct vop2 *vop2 = vp->vop2; -+ -+ spin_lock(&vop2->reg_lock); + + vop2_post_config(crtc); + -+ spin_unlock(&vop2->reg_lock); -+ + vop2_cfg_done(vp); + + spin_lock_irq(&crtc->dev->event_lock); @@ -4917,7 +3771,7 @@ index 0000000000000..7d39ba90061d1 +{ + struct vop2 *vop2 = data; + const struct vop2_data *vop2_data = vop2->data; -+ uint32_t axi_irqs[VOP2_SYS_AXI_BUS_NUM]; ++ u32 axi_irqs[VOP2_SYS_AXI_BUS_NUM]; + int ret = IRQ_NONE; + int i; + @@ -4931,7 +3785,7 @@ index 0000000000000..7d39ba90061d1 + for (i = 0; i < vop2_data->nr_vps; i++) { + struct vop2_video_port *vp = &vop2->vps[i]; + struct drm_crtc *crtc = &vp->crtc; -+ uint32_t irqs; ++ u32 irqs; + + irqs = vop2_readl(vop2, RK3568_VP_INT_STATUS(vp->id)); + vop2_writel(vop2, RK3568_VP_INT_CLR(vp->id), irqs << 16 | irqs); @@ -4942,19 +3796,18 @@ index 0000000000000..7d39ba90061d1 + } + + if (irqs & VP_INT_FS_FIELD) { -+ unsigned long flags; -+ + drm_crtc_handle_vblank(crtc); -+ spin_lock_irqsave(&crtc->dev->event_lock, flags); ++ spin_lock(&crtc->dev->event_lock); + if (vp->event) { -+ uint32_t val = vop2_readl(vop2, RK3568_REG_CFG_DONE); ++ u32 val = vop2_readl(vop2, RK3568_REG_CFG_DONE); ++ + if (!(val & BIT(vp->id))) { + drm_crtc_send_vblank_event(crtc, vp->event); + vp->event = NULL; + drm_crtc_vblank_put(crtc); + } + } -+ spin_unlock_irqrestore(&crtc->dev->event_lock, flags); ++ spin_unlock(&crtc->dev->event_lock); + + ret = IRQ_HANDLED; + } @@ -4984,16 +3837,20 @@ index 0000000000000..7d39ba90061d1 + return ret; +} + -+static int vop2_plane_init(struct vop2 *vop2, struct vop2_win *win, unsigned long possible_crtcs) ++static int vop2_plane_init(struct vop2 *vop2, struct vop2_win *win, ++ unsigned long possible_crtcs) +{ + const struct vop2_win_data *win_data = win->data; -+ unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) | BIT(DRM_MODE_BLEND_PREMULTI) | ++ unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) | ++ BIT(DRM_MODE_BLEND_PREMULTI) | + BIT(DRM_MODE_BLEND_COVERAGE); + int ret; + + ret = drm_universal_plane_init(vop2->drm, &win->base, possible_crtcs, -+ &vop2_plane_funcs, win_data->formats, win_data->nformats, -+ win_data->format_modifiers, win->type, win_data->name); ++ &vop2_plane_funcs, win_data->formats, ++ win_data->nformats, ++ win_data->format_modifiers, ++ win->type, win_data->name); + if (ret) { + drm_err(vop2->drm, "failed to initialize plane %d\n", ret); + return ret; @@ -5031,6 +3888,8 @@ index 0000000000000..7d39ba90061d1 + return NULL; +} + ++#define NR_LAYERS 6 ++ +static int vop2_create_crtc(struct vop2 *vop2) +{ + const struct vop2_data *vop2_data = vop2->data; @@ -5039,7 +3898,7 @@ index 0000000000000..7d39ba90061d1 + struct drm_plane *plane; + struct device_node *port; + struct vop2_video_port *vp; -+ uint32_t possible_crtcs; ++ u32 possible_crtcs; + int i, nvp, nvps = 0; + int ret; + @@ -5064,7 +3923,7 @@ index 0000000000000..7d39ba90061d1 + + np = of_graph_get_remote_node(dev->of_node, i, -1); + if (!np) { -+ printk("%s: No remote for vp%d\n", __func__, i); ++ drm_dbg(vop2->drm, "%s: No remote for vp%d\n", __func__, i); + continue; + } + of_node_put(np); @@ -5103,7 +3962,8 @@ index 0000000000000..7d39ba90061d1 + ret = vop2_plane_init(vop2, win, possible_crtcs); + + if (ret) { -+ drm_err(vop2->drm, "failed to init plane %s: %d\n", win->data->name, ret); ++ drm_err(vop2->drm, "failed to init plane %s: %d\n", ++ win->data->name, ret); + return ret; + } + } @@ -5116,7 +3976,8 @@ index 0000000000000..7d39ba90061d1 + + plane = &vp->primary_plane->base; + -+ ret = drm_crtc_init_with_planes(drm, &vp->crtc, plane, NULL, &vop2_crtc_funcs, ++ ret = drm_crtc_init_with_planes(drm, &vp->crtc, plane, NULL, ++ &vop2_crtc_funcs, + "video_port%d", vp->id); + if (ret) { + drm_err(vop2->drm, "crtc init for video_port%d failed\n", i); @@ -5130,8 +3991,9 @@ index 0000000000000..7d39ba90061d1 + + for (i = 0; i < vop2->data->nr_vps; i++) { + struct vop2_video_port *vp = &vop2->vps[i]; ++ + if (vp->crtc.port) -+ vp->nlayers = NR_MIXERS / nvps; ++ vp->nlayers = NR_LAYERS / nvps; + } + + return 0; @@ -5148,152 +4010,176 @@ index 0000000000000..7d39ba90061d1 + drm_crtc_cleanup(crtc); +} + ++static struct reg_field vop2_cluster_regs[VOP2_WIN_MAX_REG] = { ++ [VOP2_WIN_ENABLE] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 0, 0), ++ [VOP2_WIN_FORMAT] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 1, 5), ++ [VOP2_WIN_RB_SWAP] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 14, 14), ++ [VOP2_WIN_DITHER_UP] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 18, 18), ++ [VOP2_WIN_ACT_INFO] = REG_FIELD(RK3568_CLUSTER_WIN_ACT_INFO, 0, 31), ++ [VOP2_WIN_DSP_INFO] = REG_FIELD(RK3568_CLUSTER_WIN_DSP_INFO, 0, 31), ++ [VOP2_WIN_DSP_ST] = REG_FIELD(RK3568_CLUSTER_WIN_DSP_ST, 0, 31), ++ [VOP2_WIN_YRGB_MST] = REG_FIELD(RK3568_CLUSTER_WIN_YRGB_MST, 0, 31), ++ [VOP2_WIN_UV_MST] = REG_FIELD(RK3568_CLUSTER_WIN_CBR_MST, 0, 31), ++ [VOP2_WIN_YUV_CLIP] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 19, 19), ++ [VOP2_WIN_YRGB_VIR] = REG_FIELD(RK3568_CLUSTER_WIN_VIR, 0, 15), ++ [VOP2_WIN_UV_VIR] = REG_FIELD(RK3568_CLUSTER_WIN_VIR, 16, 31), ++ [VOP2_WIN_Y2R_EN] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 8, 8), ++ [VOP2_WIN_R2Y_EN] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 9, 9), ++ [VOP2_WIN_CSC_MODE] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 10, 11), ++ ++ /* Scale */ ++ [VOP2_WIN_SCALE_YRGB_X] = REG_FIELD(RK3568_CLUSTER_WIN_SCL_FACTOR_YRGB, 0, 15), ++ [VOP2_WIN_SCALE_YRGB_Y] = REG_FIELD(RK3568_CLUSTER_WIN_SCL_FACTOR_YRGB, 16, 31), ++ [VOP2_WIN_YRGB_VER_SCL_MODE] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 14, 15), ++ [VOP2_WIN_YRGB_HOR_SCL_MODE] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 12, 13), ++ [VOP2_WIN_BIC_COE_SEL] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 2, 3), ++ [VOP2_WIN_VSD_YRGB_GT2] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 28, 28), ++ [VOP2_WIN_VSD_YRGB_GT4] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 29, 29), ++ ++ /* cluster regs */ ++ [VOP2_WIN_AFBC_ENABLE] = REG_FIELD(RK3568_CLUSTER_CTRL, 1, 1), ++ [VOP2_WIN_CLUSTER_ENABLE] = REG_FIELD(RK3568_CLUSTER_CTRL, 0, 0), ++ [VOP2_WIN_CLUSTER_LB_MODE] = REG_FIELD(RK3568_CLUSTER_CTRL, 4, 7), ++ ++ /* afbc regs */ ++ [VOP2_WIN_AFBC_FORMAT] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 2, 6), ++ [VOP2_WIN_AFBC_RB_SWAP] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 9, 9), ++ [VOP2_WIN_AFBC_UV_SWAP] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 10, 10), ++ [VOP2_WIN_AFBC_AUTO_GATING_EN] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_OUTPUT_CTRL, 4, 4), ++ [VOP2_WIN_AFBC_HALF_BLOCK_EN] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 7, 7), ++ [VOP2_WIN_AFBC_BLOCK_SPLIT_EN] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 8, 8), ++ [VOP2_WIN_AFBC_HDR_PTR] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_HDR_PTR, 0, 31), ++ [VOP2_WIN_AFBC_PIC_SIZE] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_PIC_SIZE, 0, 31), ++ [VOP2_WIN_AFBC_PIC_VIR_WIDTH] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_VIR_WIDTH, 0, 15), ++ [VOP2_WIN_AFBC_TILE_NUM] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_VIR_WIDTH, 16, 31), ++ [VOP2_WIN_AFBC_PIC_OFFSET] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_PIC_OFFSET, 0, 31), ++ [VOP2_WIN_AFBC_DSP_OFFSET] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_DSP_OFFSET, 0, 31), ++ [VOP2_WIN_AFBC_TRANSFORM_OFFSET] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_TRANSFORM_OFFSET, 0, 31), ++ [VOP2_WIN_AFBC_ROTATE_90] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE, 0, 0), ++ [VOP2_WIN_AFBC_ROTATE_270] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE, 1, 1), ++ [VOP2_WIN_XMIRROR] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE, 2, 2), ++ [VOP2_WIN_YMIRROR] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE, 3, 3), ++ [VOP2_WIN_UV_SWAP] = { .reg = 0xffffffff }, ++ [VOP2_WIN_COLOR_KEY] = { .reg = 0xffffffff }, ++ [VOP2_WIN_COLOR_KEY_EN] = { .reg = 0xffffffff }, ++ [VOP2_WIN_SCALE_CBCR_X] = { .reg = 0xffffffff }, ++ [VOP2_WIN_SCALE_CBCR_Y] = { .reg = 0xffffffff }, ++ [VOP2_WIN_YRGB_HSCL_FILTER_MODE] = { .reg = 0xffffffff }, ++ [VOP2_WIN_YRGB_VSCL_FILTER_MODE] = { .reg = 0xffffffff }, ++ [VOP2_WIN_CBCR_VER_SCL_MODE] = { .reg = 0xffffffff }, ++ [VOP2_WIN_CBCR_HSCL_FILTER_MODE] = { .reg = 0xffffffff }, ++ [VOP2_WIN_CBCR_HOR_SCL_MODE] = { .reg = 0xffffffff }, ++ [VOP2_WIN_CBCR_VSCL_FILTER_MODE] = { .reg = 0xffffffff }, ++ [VOP2_WIN_VSD_CBCR_GT2] = { .reg = 0xffffffff }, ++ [VOP2_WIN_VSD_CBCR_GT4] = { .reg = 0xffffffff }, ++}; ++ +static int vop2_cluster_init(struct vop2_win *win) +{ + struct vop2 *vop2 = win->vop2; -+ int i; -+ struct reg_field vop2_cluster_regs[VOP2_WIN_MAX_REG] = { -+ [VOP2_WIN_ENABLE] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 0, 0), -+ [VOP2_WIN_FORMAT] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 1, 5), -+ [VOP2_WIN_RB_SWAP] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 14, 14), -+ [VOP2_WIN_DITHER_UP] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 18, 18), -+ [VOP2_WIN_ACT_INFO] = REG_FIELD(RK3568_CLUSTER_WIN_ACT_INFO, 0, 31), -+ [VOP2_WIN_DSP_INFO] = REG_FIELD(RK3568_CLUSTER_WIN_DSP_INFO, 0, 31), -+ [VOP2_WIN_DSP_ST] = REG_FIELD(RK3568_CLUSTER_WIN_DSP_ST, 0, 31), -+ [VOP2_WIN_YRGB_MST] = REG_FIELD(RK3568_CLUSTER_WIN_YRGB_MST, 0, 31), -+ [VOP2_WIN_UV_MST] = REG_FIELD(RK3568_CLUSTER_WIN_CBR_MST, 0, 31), -+ [VOP2_WIN_YUV_CLIP] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 19, 19), -+ [VOP2_WIN_YRGB_VIR] = REG_FIELD(RK3568_CLUSTER_WIN_VIR, 0, 15), -+ [VOP2_WIN_UV_VIR] = REG_FIELD(RK3568_CLUSTER_WIN_VIR, 16, 31), -+ [VOP2_WIN_Y2R_EN] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 8, 8), -+ [VOP2_WIN_R2Y_EN] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 9, 9), -+ [VOP2_WIN_CSC_MODE] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 10, 11), ++ struct reg_field *cluster_regs; ++ int ret, i; + -+ /* Scale */ -+ [VOP2_WIN_SCALE_YRGB_X] = REG_FIELD(RK3568_CLUSTER_WIN_SCL_FACTOR_YRGB, 0, 15), -+ [VOP2_WIN_SCALE_YRGB_Y] = REG_FIELD(RK3568_CLUSTER_WIN_SCL_FACTOR_YRGB, 16, 31), -+ [VOP2_WIN_YRGB_VER_SCL_MODE] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 14, 15), -+ [VOP2_WIN_YRGB_HOR_SCL_MODE] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 12, 13), -+ [VOP2_WIN_BIC_COE_SEL] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 2, 3), -+ [VOP2_WIN_VSD_YRGB_GT2] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 28, 28), -+ [VOP2_WIN_VSD_YRGB_GT4] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 29, 29), -+ -+ /* cluster regs */ -+ [VOP2_WIN_AFBC_ENABLE] = REG_FIELD(RK3568_CLUSTER_CTRL, 1, 1), -+ [VOP2_WIN_CLUSTER_ENABLE] = REG_FIELD(RK3568_CLUSTER_CTRL, 0, 0), -+ [VOP2_WIN_CLUSTER_LB_MODE] = REG_FIELD(RK3568_CLUSTER_CTRL, 4, 7), -+ -+ /* afbc regs */ -+ [VOP2_WIN_AFBC_FORMAT] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 2, 6), -+ [VOP2_WIN_AFBC_RB_SWAP] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 9, 9), -+ [VOP2_WIN_AFBC_UV_SWAP] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 10, 10), -+ [VOP2_WIN_AFBC_AUTO_GATING_EN] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_OUTPUT_CTRL, 4, 4), -+ [VOP2_WIN_AFBC_HALF_BLOCK_EN] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 7, 7), -+ [VOP2_WIN_AFBC_BLOCK_SPLIT_EN] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 8, 8), -+ [VOP2_WIN_AFBC_HDR_PTR] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_HDR_PTR, 0, 31), -+ [VOP2_WIN_AFBC_PIC_SIZE] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_PIC_SIZE, 0, 31), -+ [VOP2_WIN_AFBC_PIC_VIR_WIDTH] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_VIR_WIDTH, 0, 15), -+ [VOP2_WIN_AFBC_TILE_NUM] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_VIR_WIDTH, 16, 31), -+ [VOP2_WIN_AFBC_PIC_OFFSET] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_PIC_OFFSET, 0, 31), -+ [VOP2_WIN_AFBC_DSP_OFFSET] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_DSP_OFFSET, 0, 31), -+ [VOP2_WIN_AFBC_TRANSFORM_OFFSET] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_TRANSFORM_OFFSET, 0, 31), -+ [VOP2_WIN_AFBC_ROTATE_90] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE, 0, 0), -+ [VOP2_WIN_AFBC_ROTATE_270] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE, 1, 1), -+ [VOP2_WIN_XMIRROR] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE, 2, 2), -+ [VOP2_WIN_YMIRROR] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE, 3, 3), -+ [VOP2_WIN_UV_SWAP] = { .reg = 0xffffffff }, -+ [VOP2_WIN_COLOR_KEY] = { .reg = 0xffffffff }, -+ [VOP2_WIN_COLOR_KEY_EN] = { .reg = 0xffffffff }, -+ [VOP2_WIN_SCALE_CBCR_X] = { .reg = 0xffffffff }, -+ [VOP2_WIN_SCALE_CBCR_Y] = { .reg = 0xffffffff }, -+ [VOP2_WIN_YRGB_HSCL_FILTER_MODE] = { .reg = 0xffffffff }, -+ [VOP2_WIN_YRGB_VSCL_FILTER_MODE] = { .reg = 0xffffffff }, -+ [VOP2_WIN_CBCR_VER_SCL_MODE] = { .reg = 0xffffffff }, -+ [VOP2_WIN_CBCR_HSCL_FILTER_MODE] = { .reg = 0xffffffff }, -+ [VOP2_WIN_CBCR_HOR_SCL_MODE] = { .reg = 0xffffffff }, -+ [VOP2_WIN_CBCR_VSCL_FILTER_MODE] = { .reg = 0xffffffff }, -+ [VOP2_WIN_VSD_CBCR_GT2] = { .reg = 0xffffffff }, -+ [VOP2_WIN_VSD_CBCR_GT4] = { .reg = 0xffffffff }, -+ }; ++ cluster_regs = kmemdup(vop2_cluster_regs, sizeof(vop2_cluster_regs), ++ GFP_KERNEL); ++ if (!cluster_regs) ++ return -ENOMEM; + + for (i = 0; i < ARRAY_SIZE(vop2_cluster_regs); i++) -+ vop2_cluster_regs[i].reg += win->offset; ++ if (cluster_regs[i].reg != 0xffffffff) ++ cluster_regs[i].reg += win->offset; + -+ return devm_regmap_field_bulk_alloc(vop2->dev, vop2->map, win->reg, -+ vop2_cluster_regs, ++ ret = devm_regmap_field_bulk_alloc(vop2->dev, vop2->map, win->reg, ++ cluster_regs, + ARRAY_SIZE(vop2_cluster_regs)); ++ ++ kfree(cluster_regs); ++ ++ return ret; ++}; ++ ++static struct reg_field vop2_esmart_regs[VOP2_WIN_MAX_REG] = { ++ [VOP2_WIN_ENABLE] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 0, 0), ++ [VOP2_WIN_FORMAT] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 1, 5), ++ [VOP2_WIN_DITHER_UP] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 12, 12), ++ [VOP2_WIN_RB_SWAP] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 14, 14), ++ [VOP2_WIN_UV_SWAP] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 16, 16), ++ [VOP2_WIN_ACT_INFO] = REG_FIELD(RK3568_SMART_REGION0_ACT_INFO, 0, 31), ++ [VOP2_WIN_DSP_INFO] = REG_FIELD(RK3568_SMART_REGION0_DSP_INFO, 0, 31), ++ [VOP2_WIN_DSP_ST] = REG_FIELD(RK3568_SMART_REGION0_DSP_ST, 0, 28), ++ [VOP2_WIN_YRGB_MST] = REG_FIELD(RK3568_SMART_REGION0_YRGB_MST, 0, 31), ++ [VOP2_WIN_UV_MST] = REG_FIELD(RK3568_SMART_REGION0_CBR_MST, 0, 31), ++ [VOP2_WIN_YUV_CLIP] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 17, 17), ++ [VOP2_WIN_YRGB_VIR] = REG_FIELD(RK3568_SMART_REGION0_VIR, 0, 15), ++ [VOP2_WIN_UV_VIR] = REG_FIELD(RK3568_SMART_REGION0_VIR, 16, 31), ++ [VOP2_WIN_Y2R_EN] = REG_FIELD(RK3568_SMART_CTRL0, 0, 0), ++ [VOP2_WIN_R2Y_EN] = REG_FIELD(RK3568_SMART_CTRL0, 1, 1), ++ [VOP2_WIN_CSC_MODE] = REG_FIELD(RK3568_SMART_CTRL0, 2, 3), ++ [VOP2_WIN_YMIRROR] = REG_FIELD(RK3568_SMART_CTRL1, 31, 31), ++ [VOP2_WIN_COLOR_KEY] = REG_FIELD(RK3568_SMART_COLOR_KEY_CTRL, 0, 29), ++ [VOP2_WIN_COLOR_KEY_EN] = REG_FIELD(RK3568_SMART_COLOR_KEY_CTRL, 31, 31), ++ ++ /* Scale */ ++ [VOP2_WIN_SCALE_YRGB_X] = REG_FIELD(RK3568_SMART_REGION0_SCL_FACTOR_YRGB, 0, 15), ++ [VOP2_WIN_SCALE_YRGB_Y] = REG_FIELD(RK3568_SMART_REGION0_SCL_FACTOR_YRGB, 16, 31), ++ [VOP2_WIN_SCALE_CBCR_X] = REG_FIELD(RK3568_SMART_REGION0_SCL_FACTOR_CBR, 0, 15), ++ [VOP2_WIN_SCALE_CBCR_Y] = REG_FIELD(RK3568_SMART_REGION0_SCL_FACTOR_CBR, 16, 31), ++ [VOP2_WIN_YRGB_HOR_SCL_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 0, 1), ++ [VOP2_WIN_YRGB_HSCL_FILTER_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 2, 3), ++ [VOP2_WIN_YRGB_VER_SCL_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 4, 5), ++ [VOP2_WIN_YRGB_VSCL_FILTER_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 6, 7), ++ [VOP2_WIN_CBCR_HOR_SCL_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 8, 9), ++ [VOP2_WIN_CBCR_HSCL_FILTER_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 10, 11), ++ [VOP2_WIN_CBCR_VER_SCL_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 12, 13), ++ [VOP2_WIN_CBCR_VSCL_FILTER_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 14, 15), ++ [VOP2_WIN_BIC_COE_SEL] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 16, 17), ++ [VOP2_WIN_VSD_YRGB_GT2] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 8, 8), ++ [VOP2_WIN_VSD_YRGB_GT4] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 9, 9), ++ [VOP2_WIN_VSD_CBCR_GT2] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 10, 10), ++ [VOP2_WIN_VSD_CBCR_GT4] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 11, 11), ++ [VOP2_WIN_XMIRROR] = { .reg = 0xffffffff }, ++ [VOP2_WIN_CLUSTER_ENABLE] = { .reg = 0xffffffff }, ++ [VOP2_WIN_AFBC_ENABLE] = { .reg = 0xffffffff }, ++ [VOP2_WIN_CLUSTER_LB_MODE] = { .reg = 0xffffffff }, ++ [VOP2_WIN_AFBC_FORMAT] = { .reg = 0xffffffff }, ++ [VOP2_WIN_AFBC_RB_SWAP] = { .reg = 0xffffffff }, ++ [VOP2_WIN_AFBC_UV_SWAP] = { .reg = 0xffffffff }, ++ [VOP2_WIN_AFBC_AUTO_GATING_EN] = { .reg = 0xffffffff }, ++ [VOP2_WIN_AFBC_BLOCK_SPLIT_EN] = { .reg = 0xffffffff }, ++ [VOP2_WIN_AFBC_PIC_VIR_WIDTH] = { .reg = 0xffffffff }, ++ [VOP2_WIN_AFBC_TILE_NUM] = { .reg = 0xffffffff }, ++ [VOP2_WIN_AFBC_PIC_OFFSET] = { .reg = 0xffffffff }, ++ [VOP2_WIN_AFBC_PIC_SIZE] = { .reg = 0xffffffff }, ++ [VOP2_WIN_AFBC_DSP_OFFSET] = { .reg = 0xffffffff }, ++ [VOP2_WIN_AFBC_TRANSFORM_OFFSET] = { .reg = 0xffffffff }, ++ [VOP2_WIN_AFBC_HDR_PTR] = { .reg = 0xffffffff }, ++ [VOP2_WIN_AFBC_HALF_BLOCK_EN] = { .reg = 0xffffffff }, ++ [VOP2_WIN_AFBC_ROTATE_270] = { .reg = 0xffffffff }, ++ [VOP2_WIN_AFBC_ROTATE_90] = { .reg = 0xffffffff }, +}; + +static int vop2_esmart_init(struct vop2_win *win) +{ + struct vop2 *vop2 = win->vop2; -+ int i; -+ struct reg_field vop2_esmart_regs[VOP2_WIN_MAX_REG] = { -+ [VOP2_WIN_ENABLE] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 0, 0), -+ [VOP2_WIN_FORMAT] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 1, 5), -+ [VOP2_WIN_DITHER_UP] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 12, 12), -+ [VOP2_WIN_RB_SWAP] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 14, 14), -+ [VOP2_WIN_UV_SWAP] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 16, 16), -+ [VOP2_WIN_ACT_INFO] = REG_FIELD(RK3568_SMART_REGION0_ACT_INFO, 0, 31), -+ [VOP2_WIN_DSP_INFO] = REG_FIELD(RK3568_SMART_REGION0_DSP_INFO, 0, 31), -+ [VOP2_WIN_DSP_ST] = REG_FIELD(RK3568_SMART_REGION0_DSP_ST, 0, 28), -+ [VOP2_WIN_YRGB_MST] = REG_FIELD(RK3568_SMART_REGION0_YRGB_MST, 0, 31), -+ [VOP2_WIN_UV_MST] = REG_FIELD(RK3568_SMART_REGION0_CBR_MST, 0, 31), -+ [VOP2_WIN_YUV_CLIP] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 17, 17), -+ [VOP2_WIN_YRGB_VIR] = REG_FIELD(RK3568_SMART_REGION0_VIR, 0, 15), -+ [VOP2_WIN_UV_VIR] = REG_FIELD(RK3568_SMART_REGION0_VIR, 16, 31), -+ [VOP2_WIN_Y2R_EN] = REG_FIELD(RK3568_SMART_CTRL0, 0, 0), -+ [VOP2_WIN_R2Y_EN] = REG_FIELD(RK3568_SMART_CTRL0, 1, 1), -+ [VOP2_WIN_CSC_MODE] = REG_FIELD(RK3568_SMART_CTRL0, 2, 3), -+ [VOP2_WIN_YMIRROR] = REG_FIELD(RK3568_SMART_CTRL1, 31, 31), -+ [VOP2_WIN_COLOR_KEY] = REG_FIELD(RK3568_SMART_COLOR_KEY_CTRL, 0, 29), -+ [VOP2_WIN_COLOR_KEY_EN] = REG_FIELD(RK3568_SMART_COLOR_KEY_CTRL, 31, 31), ++ struct reg_field *esmart_regs; ++ int ret, i; + -+ /* Scale */ -+ [VOP2_WIN_SCALE_YRGB_X] = REG_FIELD(RK3568_SMART_REGION0_SCL_FACTOR_YRGB, 0, 15), -+ [VOP2_WIN_SCALE_YRGB_Y] = REG_FIELD(RK3568_SMART_REGION0_SCL_FACTOR_YRGB, 16, 31), -+ [VOP2_WIN_SCALE_CBCR_X] = REG_FIELD(RK3568_SMART_REGION0_SCL_FACTOR_CBR, 0, 15), -+ [VOP2_WIN_SCALE_CBCR_Y] = REG_FIELD(RK3568_SMART_REGION0_SCL_FACTOR_CBR, 16, 31), -+ [VOP2_WIN_YRGB_HOR_SCL_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 0, 1), -+ [VOP2_WIN_YRGB_HSCL_FILTER_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 2, 3), -+ [VOP2_WIN_YRGB_VER_SCL_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 4, 5), -+ [VOP2_WIN_YRGB_VSCL_FILTER_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 6, 7), -+ [VOP2_WIN_CBCR_HOR_SCL_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 8, 9), -+ [VOP2_WIN_CBCR_HSCL_FILTER_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 10, 11), -+ [VOP2_WIN_CBCR_VER_SCL_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 12, 13), -+ [VOP2_WIN_CBCR_VSCL_FILTER_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 14, 15), -+ [VOP2_WIN_BIC_COE_SEL] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 16, 17), -+ [VOP2_WIN_VSD_YRGB_GT2] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 8, 8), -+ [VOP2_WIN_VSD_YRGB_GT4] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 9, 9), -+ [VOP2_WIN_VSD_CBCR_GT2] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 10, 10), -+ [VOP2_WIN_VSD_CBCR_GT4] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 11, 11), -+ [VOP2_WIN_XMIRROR] = { .reg = 0xffffffff }, -+ [VOP2_WIN_CLUSTER_ENABLE] = { .reg = 0xffffffff }, -+ [VOP2_WIN_AFBC_ENABLE] = { .reg = 0xffffffff }, -+ [VOP2_WIN_CLUSTER_LB_MODE] = { .reg = 0xffffffff }, -+ [VOP2_WIN_AFBC_FORMAT] = { .reg = 0xffffffff }, -+ [VOP2_WIN_AFBC_RB_SWAP] = { .reg = 0xffffffff }, -+ [VOP2_WIN_AFBC_UV_SWAP] = { .reg = 0xffffffff }, -+ [VOP2_WIN_AFBC_AUTO_GATING_EN] = { .reg = 0xffffffff }, -+ [VOP2_WIN_AFBC_BLOCK_SPLIT_EN] = { .reg = 0xffffffff }, -+ [VOP2_WIN_AFBC_PIC_VIR_WIDTH] = { .reg = 0xffffffff }, -+ [VOP2_WIN_AFBC_TILE_NUM] = { .reg = 0xffffffff }, -+ [VOP2_WIN_AFBC_PIC_OFFSET] = { .reg = 0xffffffff }, -+ [VOP2_WIN_AFBC_PIC_SIZE] = { .reg = 0xffffffff }, -+ [VOP2_WIN_AFBC_DSP_OFFSET] = { .reg = 0xffffffff }, -+ [VOP2_WIN_AFBC_TRANSFORM_OFFSET] = { .reg = 0xffffffff }, -+ [VOP2_WIN_AFBC_HDR_PTR] = { .reg = 0xffffffff }, -+ [VOP2_WIN_AFBC_HALF_BLOCK_EN] = { .reg = 0xffffffff }, -+ [VOP2_WIN_AFBC_ROTATE_270] = { .reg = 0xffffffff }, -+ [VOP2_WIN_AFBC_ROTATE_90] = { .reg = 0xffffffff }, -+ }; ++ esmart_regs = kmemdup(vop2_esmart_regs, sizeof(vop2_esmart_regs), ++ GFP_KERNEL); ++ if (!esmart_regs) ++ return -ENOMEM; + + for (i = 0; i < ARRAY_SIZE(vop2_esmart_regs); i++) -+ vop2_esmart_regs[i].reg += win->offset; ++ if (esmart_regs[i].reg != 0xffffffff) ++ esmart_regs[i].reg += win->offset; + -+ return devm_regmap_field_bulk_alloc(vop2->dev, vop2->map, win->reg, -+ vop2_esmart_regs, ++ ret = devm_regmap_field_bulk_alloc(vop2->dev, vop2->map, win->reg, ++ esmart_regs, + ARRAY_SIZE(vop2_esmart_regs)); ++ ++ kfree(esmart_regs); ++ ++ return ret; +}; + +static int vop2_win_init(struct vop2 *vop2) @@ -5401,13 +4287,13 @@ index 0000000000000..7d39ba90061d1 + + vop2->grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,grf"); + -+ vop2->hclk = devm_clk_get(vop2->dev, "hclk_vop"); ++ vop2->hclk = devm_clk_get(vop2->dev, "hclk"); + if (IS_ERR(vop2->hclk)) { + drm_err(vop2->drm, "failed to get hclk source\n"); + return PTR_ERR(vop2->hclk); + } + -+ vop2->aclk = devm_clk_get(vop2->dev, "aclk_vop"); ++ vop2->aclk = devm_clk_get(vop2->dev, "aclk"); + if (IS_ERR(vop2->aclk)) { + drm_err(vop2->drm, "failed to get aclk source\n"); + return PTR_ERR(vop2->aclk); @@ -5419,7 +4305,6 @@ index 0000000000000..7d39ba90061d1 + return vop2->irq; + } + -+ spin_lock_init(&vop2->reg_lock); + mutex_init(&vop2->vop2_lock); + + ret = devm_request_irq(dev, vop2->irq, vop2_isr, IRQF_SHARED, dev_name(dev), vop2); @@ -5468,10 +4353,10 @@ index 0000000000000..7d39ba90061d1 +EXPORT_SYMBOL_GPL(vop2_component_ops); diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h new file mode 100644 -index 0000000000000..bb5677ff00e93 +index 000000000000..c727093a06d6 --- /dev/null +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h -@@ -0,0 +1,480 @@ +@@ -0,0 +1,477 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd @@ -5585,43 +4470,40 @@ index 0000000000000..bb5677ff00e93 + +struct vop2_win_data { + const char *name; -+ uint8_t phys_id; ++ unsigned int phys_id; + -+ uint32_t base; ++ u32 base; + enum drm_plane_type type; + -+ uint32_t nformats; -+ const uint32_t *formats; ++ u32 nformats; ++ const u32 *formats; + const uint64_t *format_modifiers; + const unsigned int supported_rotations; + + /** + * @layer_sel_id: defined by register OVERLAY_LAYER_SEL of VOP2 + */ -+ int layer_sel_id; ++ unsigned int layer_sel_id; + uint64_t feature; + + unsigned int max_upscale_factor; + unsigned int max_downscale_factor; -+ const uint8_t dly[VOP2_DLY_MODE_MAX]; ++ const u8 dly[VOP2_DLY_MODE_MAX]; +}; + +struct vop2_video_port_data { -+ char id; -+ uint32_t feature; -+ uint16_t gamma_lut_len; -+ uint16_t cubic_lut_len; ++ unsigned int id; ++ u32 feature; ++ u16 gamma_lut_len; ++ u16 cubic_lut_len; + struct vop_rect max_output; + const u8 pre_scan_max_dly[4]; + const struct vop2_video_port_regs *regs; -+ int offset; ++ unsigned int offset; +}; + +struct vop2_data { -+ uint8_t nr_vps; -+ uint8_t nr_mixers; -+ uint8_t nr_layers; -+ uint8_t nr_gammas; ++ u8 nr_vps; + const struct vop2_ctrl *ctrl; + const struct vop2_win_data *win; + const struct vop2_video_port_data *vp; @@ -5952,12 +4834,75 @@ index 0000000000000..bb5677ff00e93 +extern const struct component_ops vop2_component_ops; + +#endif /* _ROCKCHIP_DRM_VOP2_H */ +diff --git a/drivers/gpu/drm/rockchip/rockchip_lvds.c b/drivers/gpu/drm/rockchip/rockchip_lvds.c +index be74c87a8be4..4ced073c6b06 100644 +--- a/drivers/gpu/drm/rockchip/rockchip_lvds.c ++++ b/drivers/gpu/drm/rockchip/rockchip_lvds.c +@@ -36,12 +36,6 @@ + + struct rockchip_lvds; + +-#define connector_to_lvds(c) \ +- container_of(c, struct rockchip_lvds, connector) +- +-#define encoder_to_lvds(c) \ +- container_of(c, struct rockchip_lvds, encoder) +- + /** + * struct rockchip_lvds_soc_data - rockchip lvds Soc private data + * @probe: LVDS platform probe function +@@ -65,10 +59,22 @@ struct rockchip_lvds { + struct drm_panel *panel; + struct drm_bridge *bridge; + struct drm_connector connector; +- struct drm_encoder encoder; ++ struct rockchip_encoder encoder; + struct dev_pin_info *pins; + }; + ++static inline struct rockchip_lvds *connector_to_lvds(struct drm_connector *connector) ++{ ++ return container_of(connector, struct rockchip_lvds, connector); ++} ++ ++static inline struct rockchip_lvds *encoder_to_lvds(struct drm_encoder *encoder) ++{ ++ struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); ++ ++ return container_of(rkencoder, struct rockchip_lvds, encoder); ++} ++ + static inline void rk3288_writel(struct rockchip_lvds *lvds, u32 offset, + u32 val) + { +@@ -599,7 +605,7 @@ static int rockchip_lvds_bind(struct device *dev, struct device *master, + goto err_put_remote; + } + +- encoder = &lvds->encoder; ++ encoder = &lvds->encoder.encoder; + encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev, + dev->of_node); + +@@ -674,10 +680,10 @@ static void rockchip_lvds_unbind(struct device *dev, struct device *master, + const struct drm_encoder_helper_funcs *encoder_funcs; + + encoder_funcs = lvds->soc_data->helper_funcs; +- encoder_funcs->disable(&lvds->encoder); ++ encoder_funcs->disable(&lvds->encoder.encoder); + pm_runtime_disable(dev); + drm_connector_cleanup(&lvds->connector); +- drm_encoder_cleanup(&lvds->encoder); ++ drm_encoder_cleanup(&lvds->encoder.encoder); + } + + static const struct component_ops rockchip_lvds_component_ops = { diff --git a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c new file mode 100644 -index 0000000000000..2376e63d9478f +index 000000000000..9bf0637bf8e2 --- /dev/null +++ b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c -@@ -0,0 +1,285 @@ +@@ -0,0 +1,281 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) Rockchip Electronics Co.Ltd @@ -6187,8 +5132,6 @@ index 0000000000000..2376e63d9478f + +static const struct vop2_data rk3566_vop = { + .nr_vps = 3, -+ .nr_mixers = 5, -+ .nr_gammas = 1, + .max_input = { 4096, 2304 }, + .max_output = { 4096, 2304 }, + .vp = rk3568_vop_video_ports, @@ -6199,8 +5142,6 @@ index 0000000000000..2376e63d9478f + +static const struct vop2_data rk3568_vop = { + .nr_vps = 3, -+ .nr_mixers = 5, -+ .nr_gammas = 1, + .max_input = { 4096, 2304 }, + .max_output = { 4096, 2304 }, + .vp = rk3568_vop_video_ports, @@ -6243,3 +5184,26 @@ index 0000000000000..2376e63d9478f + .of_match_table = of_match_ptr(vop2_dt_match), + }, +}; +diff --git a/include/dt-bindings/soc/rockchip,vop2.h b/include/dt-bindings/soc/rockchip,vop2.h +new file mode 100644 +index 000000000000..0a87bc90564a +--- /dev/null ++++ b/include/dt-bindings/soc/rockchip,vop2.h +@@ -0,0 +1,14 @@ ++/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ ++ ++#ifndef __DT_BINDINGS_ROCKCHIP_VOP2_H ++#define __DT_BINDINGS_ROCKCHIP_VOP2_H ++ ++#define RK3568_VOP2_EP_RGB 0 ++#define RK3568_VOP2_EP_HDMI 1 ++#define RK3568_VOP2_EP_EDP 2 ++#define RK3568_VOP2_EP_MIPI0 3 ++#define RK3568_VOP2_EP_LVDS0 4 ++#define RK3568_VOP2_EP_MIPI1 5 ++#define RK3568_VOP2_EP_LVDS1 6 ++ ++#endif /* __DT_BINDINGS_ROCKCHIP_VOP2_H */ +-- +2.30.2 + diff --git a/patch/kernel/archive/rk35xx-5.16/rk356x-gpu-GPU.patch b/patch/kernel/archive/rk35xx-5.16/rk356x-gpu-GPU.patch index e238f4ea3c..f64431b80e 100644 --- a/patch/kernel/archive/rk35xx-5.16/rk356x-gpu-GPU.patch +++ b/patch/kernel/archive/rk35xx-5.16/rk356x-gpu-GPU.patch @@ -1,37 +1,157 @@ -Commit b681af0bc1cc ("drm: panfrost: add optional bus_clock") -added an optional bus_clock to support Allwinner H6 T-720 GPU. -Increase the max clock items in the dt-binding to reflect this. +From patchwork Wed Feb 9 21:55:45 2022 +Content-Type: text/plain; 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Signed-off-by: Alex Bee +[move the changes to the SoC section] +Signed-off-by: Michael Riesch --- - .../bindings/gpu/arm,mali-bifrost.yaml | 20 ++++++++++++++++++- - 1 file changed, 19 insertions(+), 1 deletion(-) + .../devicetree/bindings/gpu/arm,mali-bifrost.yaml | 15 +++++++++++++++ + 1 file changed, 15 insertions(+) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml -index 6f98dd55fb4c..2849a7a97d73 100644 +index 63a08f3f321d..4d6bfae0653c 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml -@@ -39,7 +39,14 @@ properties: - - const: gpu - - clocks: -- maxItems: 1 -+ minItems: 1 -+ maxItems: 2 -+ -+ clock-names: -+ minItems: 1 -+ items: -+ - const: core -+ - const: bus - - mali-supply: true - -@@ -118,6 +125,17 @@ allOf: +@@ -159,6 +159,21 @@ allOf: power-domains: maxItems: 1 sram-supply: false @@ -44,12 +164,152 @@ index 6f98dd55fb4c..2849a7a97d73 100644 + properties: + clocks: + minItems: 2 ++ clock-names: ++ items: ++ - const: gpu ++ - const: bus + required: + - clock-names examples: - | +From patchwork Wed Feb 9 21:55:46 2022 +Content-Type: text/plain; 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}; @@ -110,25 +371,24 @@ index 46d9552f6028..3b314ccd6c94 100644 + }; + }; + - firmware { - scmi: scmi { - compatible = "arm,scmi-smc"; -@@ -386,6 +420,22 @@ power-domain@RK3568_PD_RKVENC { + pmu { + compatible = "arm,cortex-a55-pmu"; + interrupts = , +@@ -444,6 +478,21 @@ power-domain@RK3568_PD_RKVENC { }; }; + gpu: gpu@fde60000 { + compatible = "rockchip,rk3568-mali", "arm,mali-bifrost"; + reg = <0x0 0xfde60000 0x0 0x4000>; -+ + interrupts = , + , + ; + interrupt-names = "job", "mmu", "gpu"; + clocks = <&scmi_clk 1>, <&cru CLK_GPU>; -+ clock-names = "core", "bus"; -+ operating-points-v2 = <&gpu_opp_table>; ++ clock-names = "gpu", "bus"; + #cooling-cells = <2>; ++ operating-points-v2 = <&gpu_opp_table>; + power-domains = <&power RK3568_PD_GPU>; + status = "disabled"; + }; @@ -137,21 +397,159 @@ index 46d9552f6028..3b314ccd6c94 100644 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xfe000000 0x0 0x4000>; +From patchwork Wed Feb 9 21:55:47 2022 +Content-Type: text/plain; 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This adds the +cooling map and trip points for it to make use of its contribution as +a cooling device. Signed-off-by: Alex Bee +Signed-off-by: Michael Riesch --- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 27 ++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi -index 3b314ccd6c94..a67c279c164d 100644 +index 50bbea862a6a..37194d735028 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi -@@ -960,6 +960,33 @@ gpu_thermal: gpu-thermal { +@@ -1093,6 +1093,33 @@ gpu_thermal: gpu-thermal { polling-delay = <1000>; /* milliseconds */ thermal-sensors = <&tsadc 1>; @@ -186,6 +584,141 @@ index 3b314ccd6c94..a67c279c164d 100644 }; +From patchwork Wed Feb 9 21:55:48 2022 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Michael Riesch +X-Patchwork-Id: 12740948 +Return-Path: + +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +Received: from bombadil.infradead.org (bombadil.infradead.org + [198.137.202.133]) + (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) + (No client certificate requested) + by smtp.lore.kernel.org (Postfix) with ESMTPS id 92174C433FE + for ; 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Signed-off-by: Ezequiel Garcia Signed-off-by: Alex Bee +Signed-off-by: Michael Riesch --- arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts -index 4d4b2a301b1a..625489c60622 100644 +index 3e65465ac7d5..b048db6cff3a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts -@@ -205,6 +205,11 @@ &gmac1m0_clkinout +@@ -221,6 +221,11 @@ &gmac1m0_clkinout status = "okay"; }; @@ -213,3 +747,176 @@ index 4d4b2a301b1a..625489c60622 100644 &i2c0 { status = "okay"; + +From patchwork Wed Feb 9 21:55:49 2022 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Michael Riesch +X-Patchwork-Id: 12740949 +Return-Path: + +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +Received: from bombadil.infradead.org (bombadil.infradead.org + [198.137.202.133]) + (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) + (No client certificate requested) + by smtp.lore.kernel.org (Postfix) with ESMTPS id 80D52C433EF + for ; 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+ }; + ++&gpu { ++ mali-supply = <&vdd_gpu>; ++ status = "okay"; ++}; ++ + &i2c0 { + status = "okay"; + +@@ -462,6 +467,12 @@ &sdmmc0 { + status = "okay"; + }; + ++&tsadc { ++ rockchip,hw-tshut-mode = <1>; ++ rockchip,hw-tshut-polarity = <0>; ++ status = "okay"; ++}; ++ + &uart2 { + status = "okay"; + }; diff --git a/patch/kernel/archive/rk35xx-5.16/rk356x-usb3.patch b/patch/kernel/archive/rk35xx-5.16/rk356x-usb3.patch index 5b3106157b..607374bf70 100644 --- a/patch/kernel/archive/rk35xx-5.16/rk356x-usb3.patch +++ b/patch/kernel/archive/rk35xx-5.16/rk356x-usb3.patch @@ -107,16 +107,6 @@ pinctrl-0 = <&uart0_xfer>; pinctrl-names = "default"; reg-io-width = <4>; -@@ -573,7 +681,8 @@ - }; - - vop: vop@fe040000 { -- reg = <0x0 0xfe040000 0x0 0x5000>; -+ reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>; -+ reg-names = "regs", "gamma_lut"; - interrupts = ; - clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>, <&cru DCLK_VOP0>, <&cru DCLK_VOP1>, <&cru DCLK_VOP2>; - clock-names = "aclk_vop", "hclk_vop", "dclk_vp0", "dclk_vp1", "dclk_vp2"; @@ -770,6 +879,61 @@ qos_vop_m1: qos@fe1a8100 { compatible = "rockchip,rk3568-qos", "syscon";