diff --git a/boards.sh b/boards.sh index db7b3b6e54..c5e3c47f5d 100644 --- a/boards.sh +++ b/boards.sh @@ -130,8 +130,9 @@ install_board_specific (){ cp $SRC/lib/config/boot-odroid.ini $DEST/cache/sdcard/boot/boot.ini else cp $SRC/lib/config/boot.cmd $DEST/cache/sdcard/boot/boot.cmd - # orangepipc temp exception - [[ $LINUXFAMILY == "sun8i" ]] && sed -i '1s/^/setenv machid 1029\n/' $DEST/cache/sdcard/boot/boot.cmd + # orangepi h3 temp exceptions + [[ $LINUXFAMILY == "sun8i" ]] && sed -i '1s/^/gpio set PA15\nsetenv machid 1029\nsetenv bootm_boot_mode sec\n/' $DEST/cache/sdcard/boot/boot.cmd + [[ $BOARD == orangepip* ]] && sed -i '1s/^/gpio set PG11\n/' $DEST/cache/sdcard/boot/boot.cmd # let's prepare for old kernel too chroot $DEST/cache/sdcard /bin/bash -c \ "ln -s /boot/bin/$BOARD.bin /boot/script.bin >/dev/null 2>&1 || cp /boot/bin/$BOARD.bin /boot/script.bin" @@ -256,4 +257,4 @@ install_kernel (){ # add our linux firmwares to cache image unzip -q $SRC/lib/bin/linux-firmware.zip -d $DEST/cache/sdcard/lib/firmware -} \ No newline at end of file +} diff --git a/config/linux-sun8i-default.config b/config/linux-sun8i-default.config index 72981ef273..82fc07faf3 100644 --- a/config/linux-sun8i-default.config +++ b/config/linux-sun8i-default.config @@ -2248,6 +2248,7 @@ CONFIG_IR_LIRC_CODEC=y # CONFIG_IR_STREAMZAP is not set # CONFIG_RC_LOOPBACK is not set # CONFIG_IR_GPIO_CIR is not set +CONFIG_IR_SUNXI=m # CONFIG_MEDIA_ATTACH is not set CONFIG_MEDIA_TUNER=m CONFIG_MEDIA_TUNER_CUSTOMISE=y diff --git a/configuration.sh b/configuration.sh index 5b277e032b..07491b6ce7 100644 --- a/configuration.sh +++ b/configuration.sh @@ -250,7 +250,7 @@ #description H3 quad core 512Mb SoC #build 3wip LINUXFAMILY="sun8i" - BOOTCONFIG="orangepi_pc_defconfig" + BOOTCONFIG="orangepi_one_defconfig" MODULES="gpio_sunxi w1-sunxi w1-gpio w1-therm" MODULES_NEXT="" CPUMIN="648000" @@ -380,7 +380,11 @@ KERNEL_DEV_SOURCE="linux-vanilla" # U-boot UBOOT_DEFAULT="git://git.denx.de/u-boot.git" - UBOOT_DEFAULT_BRANCH="v"$(git ls-remote git://git.denx.de/u-boot.git | grep -v rc | grep -v "\^" | tail -1 | cut -d "v" -f 2) + if [[ $LINUXFAMILY == sun8i ]]; then + UBOOT_DEFAULT_BRANCH="v2016.03-rc2" + else + UBOOT_DEFAULT_BRANCH="v"$(git ls-remote git://git.denx.de/u-boot.git | grep -v rc | grep -v "\^" | tail -1 | cut -d "v" -f 2) + fi UBOOT_DEFAULT_SOURCE="u-boot" UBOOT_NEXT=$UBOOT_DEFAULT UBOOT_NEXT_BRANCH=$UBOOT_DEFAULT_BRANCH diff --git a/patch/kernel/sun8i-default/0007-fbdev-fixes.patch b/patch/kernel/sun8i-default/0007-fbdev-fixes.patch new file mode 100644 index 0000000000..439d7aa4f7 --- /dev/null +++ b/patch/kernel/sun8i-default/0007-fbdev-fixes.patch @@ -0,0 +1,106 @@ +diff -Nur a/drivers/video/sunxi/disp2/disp/dev_fb.c b/drivers/video/sunxi/disp2/disp/dev_fb.c +--- a/drivers/video/sunxi/disp2/disp/dev_fb.c 2016-01-05 19:45:42.000000000 +0100 ++++ b/drivers/video/sunxi/disp2/disp/dev_fb.c 2016-02-16 18:24:35.505409579 +0100 +@@ -41,9 +41,6 @@ + + extern disp_drv_info g_disp_drv; + +-#define FBHANDTOID(handle) ((handle) - 100) +-#define FBIDTOHAND(ID) ((ID) + 100) +- + static struct __fb_addr_para g_fb_addr; + + s32 sunxi_get_fb_addr_para(struct __fb_addr_para *fb_addr_para) +@@ -535,8 +532,6 @@ + + for(sel = 0; sel < num_screens; sel++) { + if(sel==g_fbi.fb_mode[info->node]) { +- u32 buffer_num = 1; +- u32 y_offset = 0; + s32 chan = g_fbi.layer_hdl[info->node][0]; + s32 layer_id = g_fbi.layer_hdl[info->node][1]; + disp_layer_config config; +@@ -550,10 +545,10 @@ + __wrn("fb %d, get_layer_config(%d,%d,%d) fail\n", info->node, sel, chan, layer_id); + return -1; + } +- config.info.fb.crop.x = ((long long)var->xoffset) << 32; +- config.info.fb.crop.y = ((unsigned long long)(var->yoffset + y_offset)) << 32;; +- config.info.fb.crop.width = ((long long)var->xres) << 32; +- config.info.fb.crop.height = ((long long)(var->yres / buffer_num)) << 32; ++ config.info.fb.crop.x = ((long long)(var->xoffset)) << 32; ++ config.info.fb.crop.y = ((long long)(var->yoffset)) << 32; ++ config.info.fb.crop.width = ((long long)(var->xres)) << 32; ++ config.info.fb.crop.height = ((long long)(var->yres)) << 32; + if(0 != mgr->set_layer_config(mgr, &config, 1)) { + __wrn("fb %d, set_layer_config(%d,%d,%d) fail\n", info->node, sel, chan, layer_id); + return -1; +@@ -615,25 +610,25 @@ + if(sel==g_fbi.fb_mode[info->node]) { + struct fb_var_screeninfo *var = &info->var; + struct fb_fix_screeninfo * fix = &info->fix; +- u32 buffer_num = 1; +- u32 y_offset = 0; + s32 chan = g_fbi.layer_hdl[info->node][0]; + s32 layer_id = g_fbi.layer_hdl[info->node][1]; + disp_layer_config config; + struct disp_manager *mgr = g_disp_drv.mgr[sel]; + +- if(mgr && mgr->get_layer_config && mgr->set_layer_config) { ++ if(mgr && mgr->get_layer_config) { + config.channel = chan; + config.layer_id = layer_id; + mgr->get_layer_config(mgr, &config, 1); + } + + var_to_disp_fb(&(config.info.fb), var, fix); +- config.info.fb.crop.x = var->xoffset; +- config.info.fb.crop.y = var->yoffset + y_offset; +- config.info.fb.crop.width = var->xres; +- config.info.fb.crop.height = var->yres / buffer_num; +- if(mgr && mgr->get_layer_config && mgr->set_layer_config) ++ config.info.fb.crop.x = ((long long)(var->xoffset)) << 32; ++ config.info.fb.crop.y = ((long long)(var->yoffset)) << 32; ++ config.info.fb.crop.width = ((long long)(var->xres)) << 32; ++ config.info.fb.crop.height = ((long long)(var->yres)) << 32; ++ config.info.screen_win.width = var->xres; ++ config.info.screen_win.height = var->yres; ++ if(mgr && mgr->set_layer_config) + mgr->set_layer_config(mgr, &config, 1); + } + } +@@ -1136,7 +1131,7 @@ + + for(sel = 0; sel < num_screens; sel++) { + if(sel == fb_para->fb_mode) { +- u32 y_offset = 0, src_width = xres, src_height = yres; ++ u32 src_width = xres, src_height = yres; + disp_video_timings tt; + struct disp_manager *mgr = NULL; + mgr = g_disp_drv.mgr[sel]; +@@ -1170,13 +1165,13 @@ + Fb_map_kernel_logo(sel, info); + } + config.info.screen_win.width = (0 == fb_para->output_width)? src_width:fb_para->output_width; +- config.info.screen_win.height = (0 == fb_para->output_height)? src_width:fb_para->output_height; ++ config.info.screen_win.height = (0 == fb_para->output_height)? src_height:fb_para->output_height; + + config.info.mode = LAYER_MODE_BUFFER; + config.info.alpha_mode = 1; + config.info.alpha_value = 0xff; +- config.info.fb.crop.x = ((long long)0) << 32; +- config.info.fb.crop.y = ((long long)y_offset) << 32; ++ config.info.fb.crop.x = 0LL; ++ config.info.fb.crop.y = 0LL; + config.info.fb.crop.width = ((long long)src_width) << 32; + config.info.fb.crop.height = ((long long)src_height) << 32; + config.info.screen_win.x = 0; +@@ -1401,7 +1396,7 @@ + + for(fb_id=0; fb_id ++ * Copyright (C) 2014 Alexander Bersenev ++ * ++ * Backported by: ++ * Copyright (C) 2016 Jernej Skrabec ++ * ++ * Based on sun5i-ir.c: ++ * Copyright (C) 2007-2012 Daniel Wang ++ * Allwinner Technology Co., Ltd. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#define IR0_BASE (void __iomem *)(0xf1f02000) ++ ++#define SUNXI_IR_DEV "sunxi-ir" ++ ++#ifndef GENMASK ++#define GENMASK(h, l) \ ++ (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) ++#endif ++ ++/* Registers */ ++/* IR Control */ ++#define SUNXI_IR_CTL_REG 0x00 ++/* Global Enable */ ++#define REG_CTL_GEN BIT(0) ++/* RX block enable */ ++#define REG_CTL_RXEN BIT(1) ++/* CIR mode */ ++#define REG_CTL_MD (BIT(4) | BIT(5)) ++ ++/* Rx Config */ ++#define SUNXI_IR_RXCTL_REG 0x10 ++/* Pulse Polarity Invert flag */ ++#define REG_RXCTL_RPPI BIT(2) ++ ++/* Rx Data */ ++#define SUNXI_IR_RXFIFO_REG 0x20 ++ ++/* Rx Interrupt Enable */ ++#define SUNXI_IR_RXINT_REG 0x2C ++/* Rx FIFO Overflow */ ++#define REG_RXINT_ROI_EN BIT(0) ++/* Rx Packet End */ ++#define REG_RXINT_RPEI_EN BIT(1) ++/* Rx FIFO Data Available */ ++#define REG_RXINT_RAI_EN BIT(4) ++ ++/* Rx FIFO available byte level */ ++#define REG_RXINT_RAL(val) ((val) << 8) ++ ++/* Rx Interrupt Status */ ++#define SUNXI_IR_RXSTA_REG 0x30 ++/* RX FIFO Get Available Counter */ ++#define REG_RXSTA_GET_AC(val) (((val) >> 8) & (ir->fifo_size * 2 - 1)) ++/* Clear all interrupt status value */ ++#define REG_RXSTA_CLEARALL 0xff ++ ++/* IR Sample Config */ ++#define SUNXI_IR_CIR_REG 0x34 ++/* CIR_REG register noise threshold */ ++#define REG_CIR_NTHR(val) (((val) << 2) & (GENMASK(7, 2))) ++/* CIR_REG register idle threshold */ ++#define REG_CIR_ITHR(val) (((val) << 8) & (GENMASK(15, 8))) ++ ++/* Required frequency for IR0 or IR1 clock in CIR mode */ ++#define SUNXI_IR_BASE_CLK 8000000 ++/* Frequency after IR internal divider */ ++#define SUNXI_IR_CLK (SUNXI_IR_BASE_CLK / 64) ++/* Sample period in ns */ ++#define SUNXI_IR_SAMPLE (1000000000ul / SUNXI_IR_CLK) ++/* Noise threshold in samples */ ++#define SUNXI_IR_RXNOISE 1 ++/* Idle Threshold in samples */ ++#define SUNXI_IR_RXIDLE 20 ++/* Time after which device stops sending data in ms */ ++#define SUNXI_IR_TIMEOUT 120 ++ ++ ++struct sunxi_ir { ++ spinlock_t ir_lock; ++ struct rc_dev *rc; ++ void __iomem *base; ++ int fifo_size; ++ struct clk *clk; ++ struct clk *apb_clk; ++ struct pinctrl *pinctrl; ++}; ++ ++static char ir_dev_name[] = "s_cir0"; ++ ++struct sunxi_ir *ir; ++ ++static irqreturn_t sunxi_ir_irq(int irqno, void *dev_id) ++{ ++ unsigned long status; ++ unsigned char dt; ++ unsigned int cnt, rc; ++ DEFINE_IR_RAW_EVENT(rawir); ++ ++ spin_lock(&ir->ir_lock); ++ ++ status = sunxi_smc_readl(ir->base + SUNXI_IR_RXSTA_REG); ++ ++ /* clean all pending statuses */ ++ sunxi_smc_writel(status | REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG); ++ ++ if (status & (REG_RXINT_RAI_EN | REG_RXINT_RPEI_EN)) { ++ /* How many messages in fifo */ ++ rc = REG_RXSTA_GET_AC(status); ++ /* Sanity check */ ++ rc = rc > ir->fifo_size ? ir->fifo_size : rc; ++ /* If we have data */ ++ for (cnt = 0; cnt < rc; cnt++) { ++ /* for each bit in fifo */ ++ dt = (unsigned char)(sunxi_smc_readl(ir->base + SUNXI_IR_RXFIFO_REG)); ++ rawir.pulse = (dt & 0x80) != 0; ++ rawir.duration = ((dt & 0x7f) + 1) * SUNXI_IR_SAMPLE; ++ ir_raw_event_store_with_filter(ir->rc, &rawir); ++ } ++ } ++ ++ if (status & REG_RXINT_ROI_EN) { ++ ir_raw_event_reset(ir->rc); ++ } else if (status & REG_RXINT_RPEI_EN) { ++ ir_raw_event_set_idle(ir->rc, true); ++ ir_raw_event_handle(ir->rc); ++ } ++ ++ spin_unlock(&ir->ir_lock); ++ ++ return IRQ_HANDLED; ++} ++ ++static int __init ir_rx_init(void) ++{ ++ int ret = 0; ++ unsigned long tmp = 0; ++ ++ ir = kzalloc(sizeof(struct sunxi_ir), GFP_KERNEL); ++ if (!ir) ++ return -ENOMEM; ++ ++ ir->fifo_size = 64; ++ ++ spin_lock_init(&ir->ir_lock); ++ ++ /* Clock */ ++ ir->apb_clk = clk_get(NULL, HOSC_CLK); ++ if (IS_ERR(ir->apb_clk)) { ++ pr_err("failed to get a apb clock.\n"); ++ return PTR_ERR(ir->apb_clk); ++ } ++ ir->clk = clk_get(NULL, "cpurcir"); ++ if (IS_ERR(ir->clk)) { ++ pr_err("failed to get a ir clock.\n"); ++ return PTR_ERR(ir->clk); ++ } ++ ++ if(clk_set_parent(ir->clk, ir->apb_clk)) { ++ pr_err("%s: set ir_clk parent to ir_clk_source failed!\n", __func__); ++ } ++ ++ ret = clk_set_rate(ir->clk, SUNXI_IR_BASE_CLK); ++ if (ret) { ++ pr_err("set ir base clock failed!\n"); ++ goto exit_reset_assert; ++ } ++ ++ if (clk_prepare_enable(ir->apb_clk)) { ++ pr_err("try to enable apb_ir_clk failed\n"); ++ ret = -EINVAL; ++ goto exit_reset_assert; ++ } ++ ++ if (clk_prepare_enable(ir->clk)) { ++ pr_err("try to enable ir_clk failed\n"); ++ ret = -EINVAL; ++ goto exit_clkdisable_apb_clk; ++ } ++ ++ /* IO */ ++ ir->base = IR0_BASE; ++ if (IS_ERR(ir->base)) { ++ pr_err("failed to map registers\n"); ++ ret = PTR_ERR(ir->base); ++ goto exit_clkdisable_clk; ++ } ++ ++ ir->rc = rc_allocate_device(); ++ if (!ir->rc) { ++ pr_err("failed to allocate device\n"); ++ ret = -ENOMEM; ++ goto exit_clkdisable_clk; ++ } ++ ++ ir->rc->priv = ir; ++ ir->rc->input_name = SUNXI_IR_DEV; ++ ir->rc->input_phys = "sunxi-ir/input1"; ++ ir->rc->input_id.bustype = BUS_HOST; ++ ir->rc->input_id.vendor = 0x0001; ++ ir->rc->input_id.product = 0x0001; ++ ir->rc->input_id.version = 0x0100; ++ ir->rc->map_name = RC_MAP_EMPTY; ++ ir->rc->driver_type = RC_DRIVER_IR_RAW; ++ ir->rc->allowed_protos = RC_TYPE_ALL; ++ ir->rc->rx_resolution = SUNXI_IR_SAMPLE; ++ ir->rc->timeout = MS_TO_NS(SUNXI_IR_TIMEOUT); ++ ir->rc->driver_name = SUNXI_IR_DEV; ++ ++ ret = rc_register_device(ir->rc); ++ if (ret) { ++ pr_err("failed to register rc device\n"); ++ goto exit_free_dev; ++ } ++ ++ /* pin config */ ++ ir->rc->dev.init_name = &ir_dev_name[0]; ++ ir->pinctrl = devm_pinctrl_get_select_default(&ir->rc->dev); ++ if (IS_ERR_OR_NULL(ir->pinctrl)) { ++ pr_err("%s: config ir rx pin err.\n", __func__); ++ goto exit_free_dev; ++ } ++ ++ ret = request_irq(SUNXI_IRQ_R_CIR_RX, sunxi_ir_irq, 0, SUNXI_IR_DEV, ir); ++ if (ret) { ++ pr_err("failed request irq\n"); ++ goto exit_free_pinctrl; ++ } ++ ++ /* Enable CIR Mode */ ++ sunxi_smc_writel(REG_CTL_MD, ir->base+SUNXI_IR_CTL_REG); ++ ++ /* Set noise threshold and idle threshold */ ++ sunxi_smc_writel(REG_CIR_NTHR(SUNXI_IR_RXNOISE)|REG_CIR_ITHR(SUNXI_IR_RXIDLE), ++ ir->base + SUNXI_IR_CIR_REG); ++ ++ /* Invert Input Signal */ ++ sunxi_smc_writel(REG_RXCTL_RPPI, ir->base + SUNXI_IR_RXCTL_REG); ++ ++ /* Clear All Rx Interrupt Status */ ++ sunxi_smc_writel(REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG); ++ ++ /* ++ * Enable IRQ on overflow, packet end, FIFO available with trigger ++ * level ++ */ ++ sunxi_smc_writel(REG_RXINT_ROI_EN | REG_RXINT_RPEI_EN | ++ REG_RXINT_RAI_EN | REG_RXINT_RAL(ir->fifo_size / 2 - 1), ++ ir->base + SUNXI_IR_RXINT_REG); ++ ++ /* Enable IR Module */ ++ tmp = sunxi_smc_readl(ir->base + SUNXI_IR_CTL_REG); ++ sunxi_smc_writel(tmp | REG_CTL_GEN | REG_CTL_RXEN, ir->base + SUNXI_IR_CTL_REG); ++ ++ return 0; ++ ++exit_free_pinctrl: ++ devm_pinctrl_put(ir->pinctrl); ++exit_free_dev: ++ rc_free_device(ir->rc); ++exit_clkdisable_clk: ++ clk_disable_unprepare(ir->clk); ++exit_clkdisable_apb_clk: ++ clk_disable_unprepare(ir->apb_clk); ++exit_reset_assert: ++ ++ return ret; ++} ++ ++static void __exit ir_rx_exit(void) ++{ ++ unsigned long flags; ++ ++ clk_disable_unprepare(ir->clk); ++ clk_disable_unprepare(ir->apb_clk); ++ ++ spin_lock_irqsave(&ir->ir_lock, flags); ++ /* disable IR IRQ */ ++ sunxi_smc_writel(0, ir->base + SUNXI_IR_RXINT_REG); ++ /* clear All Rx Interrupt Status */ ++ sunxi_smc_writel(REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG); ++ /* disable IR */ ++ sunxi_smc_writel(0, ir->base + SUNXI_IR_CTL_REG); ++ spin_unlock_irqrestore(&ir->ir_lock, flags); ++ ++ free_irq(SUNXI_IRQ_R_CIR_RX, ir); ++ ++ devm_pinctrl_put(ir->pinctrl); ++ ++ rc_unregister_device(ir->rc); ++} ++ ++ ++module_init(ir_rx_init); ++module_exit(ir_rx_exit); ++ ++MODULE_DESCRIPTION("Allwinner sunXi IR controller driver"); ++MODULE_AUTHOR("Alexsey Shestacov "); ++MODULE_LICENSE("GPL"); diff --git a/patch/u-boot/u-boot-dev/sy8106a.patch.disabled b/patch/u-boot/u-boot-default/u-boot-00-sunxi-power-add-support-for-sy8106a-driver.patch similarity index 100% rename from patch/u-boot/u-boot-dev/sy8106a.patch.disabled rename to patch/u-boot/u-boot-default/u-boot-00-sunxi-power-add-support-for-sy8106a-driver.patch diff --git a/patch/u-boot/u-boot-default/u-boot-01-add-h3-gpio-support.patch b/patch/u-boot/u-boot-default/u-boot-01-add-h3-gpio-support.patch new file mode 100644 index 0000000000..8bfdec1ee9 --- /dev/null +++ b/patch/u-boot/u-boot-default/u-boot-01-add-h3-gpio-support.patch @@ -0,0 +1,11 @@ +diff -Nur a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c +--- a/drivers/gpio/sunxi_gpio.c 2016-02-15 22:44:30.000000000 +0100 ++++ b/drivers/gpio/sunxi_gpio.c 2016-02-18 18:46:07.723851155 +0100 +@@ -316,6 +316,7 @@ + { .compatible = "allwinner,sun7i-a20-pinctrl" }, + { .compatible = "allwinner,sun8i-a23-pinctrl" }, + { .compatible = "allwinner,sun8i-a33-pinctrl" }, ++ { .compatible = "allwinner,sun8i-h3-pinctrl" }, + { .compatible = "allwinner,sun9i-a80-pinctrl" }, + { .compatible = "allwinner,sun6i-a31-r-pinctrl" }, + { .compatible = "allwinner,sun8i-a23-r-pinctrl" }, diff --git a/patch/u-boot/u-boot-default/u-boot-99-opi-change-build-settings.patch b/patch/u-boot/u-boot-default/u-boot-99-opi-change-build-settings.patch new file mode 100644 index 0000000000..9036ed914b --- /dev/null +++ b/patch/u-boot/u-boot-default/u-boot-99-opi-change-build-settings.patch @@ -0,0 +1,48 @@ +diff -Nur a/configs/orangepi_one_defconfig b/configs/orangepi_one_defconfig +--- a/configs/orangepi_one_defconfig 1970-01-01 01:00:00.000000000 +0100 ++++ b/configs/orangepi_one_defconfig 2016-02-19 00:58:31.007705977 +0100 +@@ -0,0 +1,17 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_SUNXI=y ++CONFIG_MACH_SUN8I_H3=y ++CONFIG_DRAM_CLK=624 ++CONFIG_DRAM_ZQ=3881979 ++CONFIG_DRAM_ODT_EN=y ++# CONFIG_VIDEO is not set ++CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-pc" ++# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_SPL=y ++# CONFIG_CMD_IMLS is not set ++# CONFIG_CMD_FLASH is not set ++# CONFIG_CMD_FPGA is not set ++CONFIG_CMD_GPIO=y ++CONFIG_DM=y ++CONFIG_DM_GPIO=y ++CONFIG_SUNXI_NO_PMIC=y +diff -Nur a/configs/orangepi_pc_defconfig b/configs/orangepi_pc_defconfig +--- a/configs/orangepi_pc_defconfig 2016-02-18 17:59:46.843681159 +0100 ++++ b/configs/orangepi_pc_defconfig 2016-02-19 00:58:41.071856141 +0100 +@@ -12,3 +12,5 @@ + # CONFIG_CMD_FLASH is not set + # CONFIG_CMD_FPGA is not set + CONFIG_CMD_GPIO=y ++CONFIG_DM=y ++CONFIG_DM_GPIO=y +diff -Nur a/configs/orangepi_plus_defconfig b/configs/orangepi_plus_defconfig +--- a/configs/orangepi_plus_defconfig 2016-02-15 22:44:30.000000000 +0100 ++++ b/configs/orangepi_plus_defconfig 2016-02-19 00:59:04.440204776 +0100 +@@ -1,7 +1,7 @@ + CONFIG_ARM=y + CONFIG_ARCH_SUNXI=y + CONFIG_MACH_SUN8I_H3=y +-CONFIG_DRAM_CLK=672 ++CONFIG_DRAM_CLK=624 + CONFIG_DRAM_ZQ=3881979 + CONFIG_DRAM_ODT_EN=y + # CONFIG_VIDEO is not set +@@ -12,3 +12,5 @@ + # CONFIG_CMD_FLASH is not set + # CONFIG_CMD_FPGA is not set + CONFIG_CMD_GPIO=y ++CONFIG_DM=y ++CONFIG_DM_GPIO=y