From 78a4dd5d00c0cddd6212d6aabf00698e770cd600 Mon Sep 17 00:00:00 2001 From: Martin Ayotte Date: Sun, 24 Jul 2016 14:04:20 -0400 Subject: [PATCH] add SPI pins/SoC + rename patch --- .../add_missing_UARTs_I2Cs_SPI_for-H3.patch | 184 ++++++++++++++++++ 1 file changed, 184 insertions(+) create mode 100644 patch/kernel/sun8i-dev/add_missing_UARTs_I2Cs_SPI_for-H3.patch diff --git a/patch/kernel/sun8i-dev/add_missing_UARTs_I2Cs_SPI_for-H3.patch b/patch/kernel/sun8i-dev/add_missing_UARTs_I2Cs_SPI_for-H3.patch new file mode 100644 index 0000000000..240aa9bdd9 --- /dev/null +++ b/patch/kernel/sun8i-dev/add_missing_UARTs_I2Cs_SPI_for-H3.patch @@ -0,0 +1,184 @@ +diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi +index 8e7d38c..106204e 100644 +--- a/arch/arm/boot/dts/sun8i-h3.dtsi ++++ b/arch/arm/boot/dts/sun8i-h3.dtsi +@@ -48,6 +48,11 @@ + / { + interrupt-parent = <&gic>; + ++ aliases { ++ spi0 = &spi0; ++ spi1 = &spi1; ++ }; ++ + cpus { + #address-cells = <1>; + #size-cells = <0>; +@@ -291,6 +296,22 @@ + "mmc2_sample"; + }; + ++ spi0_clk: clk@01c200a0 { ++ #clock-cells = <0>; ++ compatible = "allwinner,sun4i-a10-mod0-clk"; ++ reg = <0x01c200a0 0x4>; ++ clocks = <&osc24M>, <&pll6 0>; ++ clock-output-names = "spi0"; ++ }; ++ ++ spi1_clk: clk@01c200a4 { ++ #clock-cells = <0>; ++ compatible = "allwinner,sun4i-a10-mod0-clk"; ++ reg = <0x01c200a4 0x4>; ++ clocks = <&osc24M>, <&pll6 0>; ++ clock-output-names = "spi1"; ++ }; ++ + usb_clk: clk@01c200cc { + #clock-cells = <1>; + #reset-cells = <1>; +@@ -541,6 +562,76 @@ + allwinner,pull = ; + }; + ++ uart1_pins_a: uart1@0 { ++ allwinner,pins = "PG6", "PG7"; ++ allwinner,function = "uart1"; ++ allwinner,drive = ; ++ allwinner,pull = ; ++ }; ++ ++ uart2_pins_a: uart2@0 { ++ allwinner,pins = "PA0", "PA1"; ++ allwinner,function = "uart2"; ++ allwinner,drive = ; ++ allwinner,pull = ; ++ }; ++ ++ uart3_pins_a: uart3@0 { ++ allwinner,pins = "PA13", "PA14"; ++ allwinner,function = "uart3"; ++ allwinner,drive = ; ++ allwinner,pull = ; ++ }; ++ ++ i2c0_pins_a: i2c0@0 { ++ allwinner,pins = "PA11", "PA12"; ++ allwinner,function = "i2c0"; ++ allwinner,drive = ; ++ allwinner,pull = ; ++ }; ++ ++ i2c1_pins_a: i2c1@0 { ++ allwinner,pins = "PA18", "PA19"; ++ allwinner,function = "i2c1"; ++ allwinner,drive = ; ++ allwinner,pull = ; ++ }; ++ ++ i2c2_pins_a: i2c2@0 { ++ allwinner,pins = "PE12", "PE13"; ++ allwinner,function = "i2c2"; ++ allwinner,drive = ; ++ allwinner,pull = ; ++ }; ++ ++ spi0_pins_a: spi0@0 { ++ allwinner,pins = "PC0", "PC1", "PC2"; ++ allwinner,function = "spi0"; ++ allwinner,drive = ; ++ allwinner,pull = ; ++ }; ++ ++ spi0_cs0_pins_a: spi0_cs0@0 { ++ allwinner,pins = "PC3"; ++ allwinner,function = "spi0"; ++ allwinner,drive = ; ++ allwinner,pull = ; ++ }; ++ ++ spi1_pins_a: spi1@0 { ++ allwinner,pins = "PA15", "PA16", "PA14"; ++ allwinner,function = "spi1"; ++ allwinner,drive = ; ++ allwinner,pull = ; ++ }; ++ ++ spi1_cs0_pins_a: spi1_cs0@0 { ++ allwinner,pins = "PA13"; ++ allwinner,function = "spi1"; ++ allwinner,drive = ; ++ allwinner,pull = ; ++ }; ++ + mmc0_pins_a: mmc0@0 { + allwinner,pins = "PF0", "PF1", "PF2", "PF3", + "PF4", "PF5"; +@@ -699,6 +790,67 @@ + status = "disabled"; + }; + ++ i2c0: i2c@01c2ac00 { ++ compatible = "allwinner,sun6i-a31-i2c"; ++ reg = <0x01c2ac00 0x400>; ++ interrupts = ; ++ clocks = <&bus_gates 96>; ++ resets = <&apb2_rst 0>; ++ status = "disabled"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ ++ i2c1: i2c@01c2b000 { ++ compatible = "allwinner,sun6i-a31-i2c"; ++ reg = <0x01c2b000 0x400>; ++ interrupts = ; ++ clocks = <&bus_gates 97>; ++ resets = <&apb2_rst 1>; ++ status = "disabled"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ ++ i2c2: i2c@01c2b400 { ++ compatible = "allwinner,sun6i-a31-i2c"; ++ reg = <0x01c2b400 0x400>; ++ interrupts = ; ++ clocks = <&bus_gates 98>; ++ resets = <&apb2_rst 2>; ++ status = "disabled"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ ++ spi0: spi@01c68000 { ++ compatible = "allwinner,sun6i-a31-spi"; ++ reg = <0x01c68000 0x1000>; ++ interrupts = ; ++ clocks = <&bus_gates 20>, <&spi0_clk>; ++ clock-names = "ahb", "mod"; ++ dmas = <&dma 23>, <&dma 23>; ++ dma-names = "rx", "tx"; ++ resets = <&ahb_rst 20>; ++ status = "disabled"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ ++ spi1: spi@01c69000 { ++ compatible = "allwinner,sun6i-a31-spi"; ++ reg = <0x01c69000 0x1000>; ++ interrupts = ; ++ clocks = <&bus_gates 21>, <&spi1_clk>; ++ clock-names = "ahb", "mod"; ++ dmas = <&dma 24>, <&dma 24>; ++ dma-names = "rx", "tx"; ++ resets = <&ahb_rst 21>; ++ status = "disabled"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ + gic: interrupt-controller@01c81000 { + compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; + reg = <0x01c81000 0x1000>,