From 74b1acddf75e47c66bca3144766aea13ecde1a0f Mon Sep 17 00:00:00 2001 From: zador-blood-stained Date: Wed, 1 Nov 2017 17:59:03 +0300 Subject: [PATCH] Pull parts of Helios4 support from #812 --- config/boards/helios4.wip | 19 + config/kernel/linux-mvebu-default.config | 6 +- ...ebu-Add-limited-PWM-support.patch.disabled | 488 ++++++++++++++++++ ...perties-to-.dtsi-armada-38x.patch.disabled | 62 +++ .../92-libata-add-ledtrig-support.patch | 179 +++++++ .../93-Enable-ATA-port-LED-trigger.patch | 37 ++ .../95-helios4-device-tree.patch | 387 ++++++++++++++ ...dtb-file-for-backwards-compatibility.patch | 2 +- 8 files changed, 1177 insertions(+), 3 deletions(-) create mode 100644 config/boards/helios4.wip create mode 100644 patch/kernel/mvebu-default/90-gpio-mvebu-Add-limited-PWM-support.patch.disabled create mode 100644 patch/kernel/mvebu-default/91-ARM-dts-mvebu-Add-PWM-properties-to-.dtsi-armada-38x.patch.disabled create mode 100644 patch/kernel/mvebu-default/92-libata-add-ledtrig-support.patch create mode 100644 patch/kernel/mvebu-default/93-Enable-ATA-port-LED-trigger.patch create mode 100644 patch/kernel/mvebu-default/95-helios4-device-tree.patch diff --git a/config/boards/helios4.wip b/config/boards/helios4.wip new file mode 100644 index 0000000000..6a5c1c1ac8 --- /dev/null +++ b/config/boards/helios4.wip @@ -0,0 +1,19 @@ +# Marvell Armada 388 2GB-ECC 4xSATA 2xUSB3.0 1xGBE +BOARD_NAME="Helios4" +LINUXFAMILY="mvebu" +BOOTCONFIG="armada_38x_helios4_config" +MODULES="mv_cesa" +BUILD_DESKTOP="no" +# +KERNEL_TARGET="default" +CLI_TARGET="" + +CLI_BETA_TARGET="" +# +RECOMMENDED="" +# +BOARDRATING="" +CHIP="https://kobol.io/helios4" +REVIEW="" +HARDWARE="https://wiki.kobol.io" +FORUMS="https://forum.armbian.com/forum/11-other-boards/" diff --git a/config/kernel/linux-mvebu-default.config b/config/kernel/linux-mvebu-default.config index 6ccd3fc775..5020060826 100644 --- a/config/kernel/linux-mvebu-default.config +++ b/config/kernel/linux-mvebu-default.config @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm 4.4.91 Kernel Configuration +# Linux/arm 4.4.95 Kernel Configuration # CONFIG_ARM=y CONFIG_ARM_HAS_SG_CHAIN=y @@ -1933,6 +1933,8 @@ CONFIG_SCSI_OSD_DPRINT_SENSE=1 CONFIG_ATA=y # CONFIG_ATA_NONSTANDARD is not set # CONFIG_ATA_VERBOSE_ERROR is not set +CONFIG_ARCH_WANT_LIBATA_LEDS=y +CONFIG_ATA_LEDS=y CONFIG_SATA_PMP=y # @@ -3004,7 +3006,7 @@ CONFIG_SENSORS_GPIO_FAN=m # CONFIG_SENSORS_LM63 is not set # CONFIG_SENSORS_LM70 is not set # CONFIG_SENSORS_LM73 is not set -# CONFIG_SENSORS_LM75 is not set +CONFIG_SENSORS_LM75=m # CONFIG_SENSORS_LM77 is not set # CONFIG_SENSORS_LM78 is not set # CONFIG_SENSORS_LM80 is not set diff --git a/patch/kernel/mvebu-default/90-gpio-mvebu-Add-limited-PWM-support.patch.disabled b/patch/kernel/mvebu-default/90-gpio-mvebu-Add-limited-PWM-support.patch.disabled new file mode 100644 index 0000000000..045c82886e --- /dev/null +++ b/patch/kernel/mvebu-default/90-gpio-mvebu-Add-limited-PWM-support.patch.disabled @@ -0,0 +1,488 @@ +From 65bce3cd01230b283915be86196f5e1318c18dd6 Mon Sep 17 00:00:00 2001 +From: aprayoga +Date: Sun, 3 Sep 2017 15:59:11 +0800 +Subject: gpio: mvebu: Add limited PWM support + +backported from https://patchwork.kernel.org/patch/9681399/ + +* Remove atomic PWM API portion as this is not supported on LK4.4 +and use https://patchwork.ozlabs.org/patch/739591/ instead. +--- + .../devicetree/bindings/gpio/gpio-mvebu.txt | 31 +++ + MAINTAINERS | 2 + + drivers/gpio/gpio-mvebu.c | 309 ++++++++++++++++++++- + 3 files changed, 328 insertions(+), 14 deletions(-) + +diff --git a/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt +index 6b76891..b6cdcb2 100644 +--- a/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt ++++ b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt +@@ -46,6 +46,23 @@ Optional: + The base of CP0 bank0 should be 20 (after AP-806 pins) the base of CP0 bank1 should be + 52 (after AP-806, and CP0 bank0 pins) + ++Optional properties: ++ ++In order to use the gpio lines in PWM mode, some additional optional ++properties are required. Only Armada 370 and XP support these properties. ++ ++- reg: an additional register set is needed, for the GPIO Blink ++ Counter on/off registers. ++ ++- reg-names: Must contain an entry "pwm" corresponding to the ++ additional register range needed for pwm operation. ++ ++- #pwm-cells: Should be two. The first cell is the pin number. The ++ second cell is reserved for flags and should be set to 0, so it has a ++ known value. It then becomes possible to use it in the future. ++ ++- clocks: Must be a phandle to the clock for the gpio controller. ++ + Example: + + gpio0: gpio@d0018100 { +@@ -59,3 +76,17 @@ Example: + #interrupt-cells = <2>; + interrupts = <16>, <17>, <18>, <19>; + }; ++ ++ gpio1: gpio@18140 { ++ compatible = "marvell,armada-370-xp-gpio"; ++ reg = <0x18140 0x40>, <0x181c8 0x08>; ++ reg-names = "gpio", "pwm"; ++ ngpios = <17>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ #pwm-cells = <2>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ interrupts = <87>, <88>, <89>; ++ clocks = <&coreclk 0>; ++ }; +diff --git a/MAINTAINERS b/MAINTAINERS +index 7008b0d..d272aca 100644 +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -8635,6 +8635,8 @@ F: include/linux/pwm.h + F: drivers/pwm/ + F: drivers/video/backlight/pwm_bl.c + F: include/linux/pwm_backlight.h ++F: drivers/gpio/gpio-mvebu.c ++F: Documentation/devicetree/bindings/gpio/gpio-mvebu.txt + + PXA2xx/PXA3xx SUPPORT + M: Daniel Mack +diff --git a/drivers/gpio/gpio-mvebu.c b/drivers/gpio/gpio-mvebu.c +index ffea532..8775123 100644 +--- a/drivers/gpio/gpio-mvebu.c ++++ b/drivers/gpio/gpio-mvebu.c +@@ -42,29 +42,43 @@ + #include + #include + #include ++#include + #include + #include + #include ++#include ++ ++#include "gpiolib.h" + + /* + * GPIO unit register offsets. + */ +-#define GPIO_OUT_OFF 0x0000 +-#define GPIO_IO_CONF_OFF 0x0004 +-#define GPIO_BLINK_EN_OFF 0x0008 +-#define GPIO_IN_POL_OFF 0x000c +-#define GPIO_DATA_IN_OFF 0x0010 +-#define GPIO_EDGE_CAUSE_OFF 0x0014 +-#define GPIO_EDGE_MASK_OFF 0x0018 +-#define GPIO_LEVEL_MASK_OFF 0x001c ++#define GPIO_OUT_OFF 0x0000 ++#define GPIO_IO_CONF_OFF 0x0004 ++#define GPIO_BLINK_EN_OFF 0x0008 ++#define GPIO_IN_POL_OFF 0x000c ++#define GPIO_DATA_IN_OFF 0x0010 ++#define GPIO_EDGE_CAUSE_OFF 0x0014 ++#define GPIO_EDGE_MASK_OFF 0x0018 ++#define GPIO_LEVEL_MASK_OFF 0x001c ++#define GPIO_BLINK_CNT_SELECT_OFF 0x0020 ++ ++/* ++ * PWM register offsets. ++ */ ++#define PWM_BLINK_ON_DURATION_OFF 0x0 ++#define PWM_BLINK_OFF_DURATION_OFF 0x4 ++ + + /* The MV78200 has per-CPU registers for edge mask and level mask */ + #define GPIO_EDGE_MASK_MV78200_OFF(cpu) ((cpu) ? 0x30 : 0x18) + #define GPIO_LEVEL_MASK_MV78200_OFF(cpu) ((cpu) ? 0x34 : 0x1C) + +-/* The Armada XP has per-CPU registers for interrupt cause, interrupt ++/* ++ * The Armada XP has per-CPU registers for interrupt cause, interrupt + * mask and interrupt level mask. Those are relative to the +- * percpu_membase. */ ++ * percpu_membase. ++ */ + #define GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu) ((cpu) * 0x4) + #define GPIO_EDGE_MASK_ARMADAXP_OFF(cpu) (0x10 + (cpu) * 0x4) + #define GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu) (0x20 + (cpu) * 0x4) +@@ -75,6 +89,23 @@ + + #define MVEBU_MAX_GPIO_PER_BANK 32 + ++struct mvebu_pwm { ++ void __iomem *membase; ++ unsigned long clk_rate; ++ struct gpio_desc *gpiod; ++ bool used; ++ unsigned int pin; ++ struct pwm_chip chip; ++ int id; ++ spinlock_t lock; ++ struct mvebu_gpio_chip *mvchip; ++ ++ /* Used to preserve GPIO/PWM registers across suspend/resume */ ++ u32 blink_select; ++ u32 blink_on_duration; ++ u32 blink_off_duration; ++}; ++ + struct mvebu_gpio_chip { + struct gpio_chip chip; + spinlock_t lock; +@@ -84,6 +115,10 @@ struct mvebu_gpio_chip { + struct irq_domain *domain; + int soc_variant; + ++ /* Used for PWM support */ ++ struct clk *clk; ++ struct mvebu_pwm *mvpwm; ++ + /* Used to preserve GPIO registers across suspend/resume */ + u32 out_reg; + u32 io_conf_reg; +@@ -102,6 +137,11 @@ static inline void __iomem *mvebu_gpioreg_out(struct mvebu_gpio_chip *mvchip) + return mvchip->membase + GPIO_OUT_OFF; + } + ++static void __iomem *mvebu_gpioreg_blink_select(struct mvebu_gpio_chip *mvchip) ++{ ++ return mvchip->membase + GPIO_BLINK_CNT_SELECT_OFF; ++} ++ + static inline void __iomem *mvebu_gpioreg_blink(struct mvebu_gpio_chip *mvchip) + { + return mvchip->membase + GPIO_BLINK_EN_OFF; +@@ -182,6 +222,20 @@ static void __iomem *mvebu_gpioreg_level_mask(struct mvebu_gpio_chip *mvchip) + } + + /* ++ * Functions returning addresses of individual registers for a given ++ * PWM controller. ++ */ ++static void __iomem *mvebu_pwmreg_blink_on_duration(struct mvebu_pwm *mvpwm) ++{ ++ return mvpwm->membase + PWM_BLINK_ON_DURATION_OFF; ++} ++ ++static void __iomem *mvebu_pwmreg_blink_off_duration(struct mvebu_pwm *mvpwm) ++{ ++ return mvpwm->membase + PWM_BLINK_OFF_DURATION_OFF; ++} ++ ++/* + * Functions implementing the gpio_chip methods + */ + +@@ -489,6 +543,220 @@ static void mvebu_gpio_irq_handler(struct irq_desc *desc) + chained_irq_exit(chip, desc); + } + ++/* ++ * Functions implementing the pwm_chip methods ++ */ ++static struct mvebu_pwm *to_mvebu_pwm(struct pwm_chip *chip) ++{ ++ return container_of(chip, struct mvebu_pwm, chip); ++} ++ ++static int mvebu_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) ++{ ++ struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip); ++ struct mvebu_gpio_chip *mvchip = mvpwm->mvchip; ++ struct gpio_desc *desc; ++ unsigned long flags; ++ int ret = 0; ++ ++ spin_lock_irqsave(&mvpwm->lock, flags); ++ if (mvpwm->gpiod) { ++ ret = -EBUSY; ++ } else { ++ desc = gpio_to_desc(mvchip->chip.base + pwm->hwpwm); ++ if (!desc) { ++ ret = -ENODEV; ++ goto out; ++ } ++ ret = gpiod_request(desc, "mvebu-pwm"); ++ if (ret) ++ goto out; ++ ++ ret = gpiod_direction_output(desc, 0); ++ if (ret) { ++ gpiod_free(desc); ++ goto out; ++ } ++ ++ mvpwm->gpiod = desc; ++ mvpwm->pin = pwm->pwm - mvchip->chip.base; ++ mvpwm->used = true; ++ } ++ ++out: ++ spin_unlock_irqrestore(&mvpwm->lock, flags); ++ return ret; ++} ++ ++static void mvebu_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) ++{ ++ struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip); ++ unsigned long flags; ++ ++ spin_lock_irqsave(&mvpwm->lock, flags); ++ gpiod_free(mvpwm->gpiod); ++ mvpwm->used = false; ++ spin_unlock_irqrestore(&mvpwm->lock, flags); ++} ++ ++static int mvebu_pwm_config(struct pwm_chip *chip, struct pwm_device *pwmd, ++ int duty_ns, int period_ns) ++{ ++ struct mvebu_pwm *pwm = to_mvebu_pwm(chip); ++ struct mvebu_gpio_chip *mvchip = pwm->mvchip; ++ unsigned int on, off; ++ unsigned long long val; ++ u32 u; ++ ++ val = (unsigned long long) pwm->clk_rate * duty_ns; ++ do_div(val, NSEC_PER_SEC); ++ if (val > UINT_MAX) ++ return -EINVAL; ++ if (val) ++ on = val; ++ else ++ on = 1; ++ ++ val = (unsigned long long) pwm->clk_rate * (period_ns - duty_ns); ++ do_div(val, NSEC_PER_SEC); ++ if (val > UINT_MAX) ++ return -EINVAL; ++ if (val) ++ off = val; ++ else ++ off = 1; ++ ++ u = readl_relaxed(mvebu_gpioreg_blink_select(mvchip)); ++ u &= ~(1 << pwm->pin); ++ u |= (pwm->id << pwm->pin); ++ writel_relaxed(u, mvebu_gpioreg_blink_select(mvchip)); ++ ++ writel_relaxed(on, mvebu_pwmreg_blink_on_duration(pwm)); ++ writel_relaxed(off, mvebu_pwmreg_blink_off_duration(pwm)); ++ ++ return 0; ++} ++ ++static int mvebu_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) ++{ ++ struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip); ++ struct mvebu_gpio_chip *mvchip = mvpwm->mvchip; ++ ++ mvebu_gpio_blink(&mvchip->chip, mvpwm->pin, 1); ++ ++ return 0; ++} ++ ++static void mvebu_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) ++{ ++ struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip); ++ struct mvebu_gpio_chip *mvchip = mvpwm->mvchip; ++ ++ mvebu_gpio_blink(&mvchip->chip, mvpwm->pin, 0); ++} ++ ++static const struct pwm_ops mvebu_pwm_ops = { ++ .request = mvebu_pwm_request, ++ .free = mvebu_pwm_free, ++ .config = mvebu_pwm_config, ++ .enable = mvebu_pwm_enable, ++ .disable = mvebu_pwm_disable, ++ .owner = THIS_MODULE, ++}; ++ ++static void mvebu_pwm_suspend(struct mvebu_gpio_chip *mvchip) ++{ ++ struct mvebu_pwm *mvpwm = mvchip->mvpwm; ++ ++ mvpwm->blink_select = ++ readl_relaxed(mvebu_gpioreg_blink_select(mvchip)); ++ mvpwm->blink_on_duration = ++ readl_relaxed(mvebu_pwmreg_blink_on_duration(mvpwm)); ++ mvpwm->blink_off_duration = ++ readl_relaxed(mvebu_pwmreg_blink_off_duration(mvpwm)); ++} ++ ++static void mvebu_pwm_resume(struct mvebu_gpio_chip *mvchip) ++{ ++ struct mvebu_pwm *mvpwm = mvchip->mvpwm; ++ ++ writel_relaxed(mvpwm->blink_select, ++ mvebu_gpioreg_blink_select(mvchip)); ++ writel_relaxed(mvpwm->blink_on_duration, ++ mvebu_pwmreg_blink_on_duration(mvpwm)); ++ writel_relaxed(mvpwm->blink_off_duration, ++ mvebu_pwmreg_blink_off_duration(mvpwm)); ++} ++ ++/* ++ * Armada 370/XP has simple PWM support for gpio lines. Other SoCs ++ * don't have this hardware. So if we don't have the necessary ++ * resource, it is not an error. ++ */ ++static int mvebu_pwm_probe(struct platform_device *pdev, ++ struct mvebu_gpio_chip *mvchip, ++ int id) ++{ ++ struct device *dev = &pdev->dev; ++ struct mvebu_pwm *mvpwm; ++ struct resource *res; ++ u32 set; ++ ++ if (!of_device_is_compatible(mvchip->chip.of_node, ++ "marvell,armada-370-xp-gpio")) ++ return 0; ++ ++ if (IS_ERR(mvchip->clk)) ++ return PTR_ERR(mvchip->clk); ++ ++ /* ++ * There are only two sets of PWM configuration registers for ++ * all the GPIO lines on those SoCs which this driver reserves ++ * for the first two GPIO chips. So if the resource is missing ++ * we can't treat it as an error. ++ */ ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwm"); ++ if (!res) ++ return 0; ++ ++ /* ++ * Use set A for lines of GPIO chip with id 0, B for GPIO chip ++ * with id 1. Don't allow further GPIO chips to be used for PWM. ++ */ ++ if (id == 0) ++ set = 0; ++ else if (id == 1) ++ set = U32_MAX; ++ else ++ return -EINVAL; ++ writel_relaxed(set, mvebu_gpioreg_blink_select(mvchip)); ++ mvpwm->id = id; ++ ++ mvpwm = devm_kzalloc(dev, sizeof(struct mvebu_pwm), GFP_KERNEL); ++ if (!mvpwm) ++ return -ENOMEM; ++ mvchip->mvpwm = mvpwm; ++ mvpwm->mvchip = mvchip; ++ ++ mvpwm->membase = devm_ioremap_resource(dev, res); ++ if (IS_ERR(mvpwm->membase)) ++ return PTR_ERR(mvpwm->membase); ++ ++ mvpwm->clk_rate = clk_get_rate(mvchip->clk); ++ if (!mvpwm->clk_rate) { ++ dev_err(dev, "failed to get clock rate\n"); ++ return -EINVAL; ++ } ++ ++ mvpwm->chip.dev = dev; ++ mvpwm->chip.ops = &mvebu_pwm_ops; ++ mvpwm->chip.npwm = mvchip->chip.ngpio; ++ ++ spin_lock_init(&mvpwm->lock); ++ ++ return pwmchip_add(&mvpwm->chip); ++} ++ + #ifdef CONFIG_DEBUG_FS + #include + +@@ -561,6 +829,10 @@ static const struct of_device_id mvebu_gpio_of_match[] = { + .data = (void *) MVEBU_GPIO_SOC_VARIANT_ARMADAXP, + }, + { ++ .compatible = "marvell,armada-370-xp-gpio", ++ .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION, ++ }, ++ { + /* sentinel */ + }, + }; +@@ -607,6 +879,9 @@ static int mvebu_gpio_suspend(struct platform_device *pdev, pm_message_t state) + BUG(); + } + ++ if (IS_ENABLED(CONFIG_PWM)) ++ mvebu_pwm_suspend(mvchip); ++ + return 0; + } + +@@ -650,6 +925,9 @@ static int mvebu_gpio_resume(struct platform_device *pdev) + BUG(); + } + ++ if (IS_ENABLED(CONFIG_PWM)) ++ mvebu_pwm_resume(mvchip); ++ + return 0; + } + +@@ -661,7 +939,6 @@ static int mvebu_gpio_probe(struct platform_device *pdev) + struct resource *res; + struct irq_chip_generic *gc; + struct irq_chip_type *ct; +- struct clk *clk; + unsigned int ngpios; + unsigned int gpio_base = -1; + int soc_variant; +@@ -695,10 +972,10 @@ static int mvebu_gpio_probe(struct platform_device *pdev) + return id; + } + +- clk = devm_clk_get(&pdev->dev, NULL); ++ mvchip->clk = devm_clk_get(&pdev->dev, NULL); + /* Not all SoCs require a clock.*/ +- if (!IS_ERR(clk)) +- clk_prepare_enable(clk); ++ if (!IS_ERR(mvchip->clk)) ++ clk_prepare_enable(mvchip->clk); + + mvchip->soc_variant = soc_variant; + mvchip->chip.label = dev_name(&pdev->dev); +@@ -835,6 +1112,10 @@ static int mvebu_gpio_probe(struct platform_device *pdev) + goto err_generic_chip; + } + ++ /* Armada 370/XP has simple PWM support for GPIO lines */ ++ if (IS_ENABLED(CONFIG_PWM)) ++ return mvebu_pwm_probe(pdev, mvchip, id); ++ + return 0; + + err_generic_chip: +-- +2.7.4 + diff --git a/patch/kernel/mvebu-default/91-ARM-dts-mvebu-Add-PWM-properties-to-.dtsi-armada-38x.patch.disabled b/patch/kernel/mvebu-default/91-ARM-dts-mvebu-Add-PWM-properties-to-.dtsi-armada-38x.patch.disabled new file mode 100644 index 0000000000..e19aa068d1 --- /dev/null +++ b/patch/kernel/mvebu-default/91-ARM-dts-mvebu-Add-PWM-properties-to-.dtsi-armada-38x.patch.disabled @@ -0,0 +1,62 @@ +From e85a492b45f49e374f544bbffe8c975b1dabe87f Mon Sep 17 00:00:00 2001 +From: aprayoga +Date: Sun, 3 Sep 2017 16:08:59 +0800 +Subject: ARM: dts: mvebu: Add PWM properties to .dtsi (armada-38x) + +reference: +https://patchwork.kernel.org/patch/9681397/ +--- + arch/arm/boot/dts/armada-38x.dtsi | 16 ++++++++++++---- + 1 file changed, 12 insertions(+), 4 deletions(-) + +diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi +index a73cbe2..f87204f 100644 +--- a/arch/arm/boot/dts/armada-38x.dtsi ++++ b/arch/arm/boot/dts/armada-38x.dtsi +@@ -345,31 +345,39 @@ + }; + + gpio0: gpio@18100 { +- compatible = "marvell,orion-gpio"; +- reg = <0x18100 0x40>; ++ compatible = "marvell,armada-370-xp-gpio", ++ "marvell,orion-gpio"; ++ reg = <0x18100 0x40>, <0x181c0 0x08>; ++ reg-names = "gpio", "pwm"; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; ++ #pwm-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = , + , + , + ; ++ clocks = <&coreclk 0>; + }; + + gpio1: gpio@18140 { +- compatible = "marvell,orion-gpio"; +- reg = <0x18140 0x40>; ++ compatible = "marvell,armada-370-xp-gpio", ++ "marvell,orion-gpio"; ++ reg = <0x18140 0x40>, <0x181c8 0x08>; ++ reg-names = "gpio", "pwm"; + ngpios = <28>; + gpio-controller; + #gpio-cells = <2>; ++ #pwm-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = , + , + , + ; ++ clocks = <&coreclk 0>; + }; + + system-controller@18200 { +-- +2.7.4 + diff --git a/patch/kernel/mvebu-default/92-libata-add-ledtrig-support.patch b/patch/kernel/mvebu-default/92-libata-add-ledtrig-support.patch new file mode 100644 index 0000000000..272964ec11 --- /dev/null +++ b/patch/kernel/mvebu-default/92-libata-add-ledtrig-support.patch @@ -0,0 +1,179 @@ +From 5843af891d0dabf9bb80039cfe807d01e9495154 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Fri, 12 Dec 2014 13:38:33 +0100 +Subject: libata: add ledtrig support + +This adds a LED trigger for each ATA port indicating disk activity. + +As this is needed only on specific platforms (NAS SoCs and such), +these platforms should define ARCH_WANTS_LIBATA_LEDS if there +are boards with LED(s) intended to indicate ATA disk activity and +need the OS to take care of that. +In that way, if not selected, LED trigger support not will be +included in libata-core and both, codepaths and structures remain +untouched. + +Signed-off-by: Daniel Golle +--- + drivers/ata/Kconfig | 16 ++++++++++++++ + drivers/ata/libata-core.c | 56 +++++++++++++++++++++++++++++++++++++++++++++++ + include/linux/libata.h | 7 ++++++ + 3 files changed, 79 insertions(+) + +diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig +index 6aaa3f8..4e24b64 100644 +--- a/drivers/ata/Kconfig ++++ b/drivers/ata/Kconfig +@@ -46,6 +46,22 @@ config ATA_VERBOSE_ERROR + + If unsure, say Y. + ++config ARCH_WANT_LIBATA_LEDS ++ bool ++ ++config ATA_LEDS ++ bool "support ATA port LED triggers" ++ depends on ARCH_WANT_LIBATA_LEDS ++ select NEW_LEDS ++ select LEDS_CLASS ++ select LEDS_TRIGGERS ++ default y ++ help ++ This option adds a LED trigger for each registered ATA port. ++ It is used to drive disk activity leds connected via GPIO. ++ ++ If unsure, say N. ++ + config ATA_ACPI + bool "ATA ACPI Support" + depends on ACPI +diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c +index b0b77b6..1400f4d 100644 +--- a/drivers/ata/libata-core.c ++++ b/drivers/ata/libata-core.c +@@ -728,6 +728,7 @@ u64 ata_tf_read_block(struct ata_taskfile *tf, struct ata_device *dev) + return block; + } + ++ + /** + * ata_build_rw_tf - Build ATA taskfile for given read/write request + * @tf: Target ATA taskfile +@@ -4757,6 +4758,30 @@ void swap_buf_le16(u16 *buf, unsigned int buf_words) + } + + /** ++ * ata_led_act - Trigger port activity LED ++ * @ap: indicating port ++ * ++ * Blinks any LEDs registered to the trigger. ++ * Commonly used with leds-gpio on NAS systems with disk activity ++ * indicator LEDs. ++ * ++ * LOCKING: ++ * None. ++ */ ++static inline void ata_led_act(struct ata_port *ap) ++{ ++#if CONFIG_ATA_LEDS ++#define LIBATA_BLINK_DELAY 20 /* ms */ ++ unsigned long led_delay = LIBATA_BLINK_DELAY; ++ ++ if (unlikely(!ap->ledtrig)) ++ return; ++ ++ led_trigger_blink_oneshot(ap->ledtrig, &led_delay, &led_delay, 0); ++#endif /* CONFIG_ATA_LEDS */ ++} ++ ++/** + * ata_qc_new_init - Request an available ATA command, and initialize it + * @dev: Device from whom we request an available command structure + * @tag: tag +@@ -4780,6 +4805,9 @@ struct ata_queued_cmd *ata_qc_new_init(struct ata_device *dev, int tag) + if (tag < 0) + return NULL; + } ++#if CONFIG_ATA_LEDS ++ ata_led_act(ap); ++#endif + + qc = __ata_qc_from_tag(ap, tag); + qc->tag = tag; +@@ -5677,6 +5705,9 @@ struct ata_port *ata_port_alloc(struct ata_host *host) + ap->stats.unhandled_irq = 1; + ap->stats.idle_irq = 1; + #endif ++#if CONFIG_ATA_LEDS ++ ap->ledtrig = kzalloc(sizeof(struct led_trigger), GFP_KERNEL); ++#endif + ata_sff_port_init(ap); + + return ap; +@@ -5698,6 +5729,12 @@ static void ata_host_release(struct device *gendev, void *res) + + kfree(ap->pmp_link); + kfree(ap->slave_link); ++#if CONFIG_ATA_LEDS ++ if (ap->ledtrig) { ++ led_trigger_unregister(ap->ledtrig); ++ kfree(ap->ledtrig); ++ }; ++#endif + kfree(ap); + host->ports[i] = NULL; + } +@@ -6145,6 +6182,25 @@ int ata_host_register(struct ata_host *host, struct scsi_host_template *sht) + host->ports[i]->local_port_no = i + 1; + } + ++#if CONFIG_ATA_LEDS ++ /* register LED triggers for all ports */ ++ for (i = 0; i < host->n_ports; i++) { ++ if (unlikely(!host->ports[i]->ledtrig)) ++ continue; ++ ++ snprintf(host->ports[i]->ledtrig_name, ++ sizeof(host->ports[i]->ledtrig_name), "ata%u", ++ host->ports[i]->print_id); ++ ++ host->ports[i]->ledtrig->name = host->ports[i]->ledtrig_name; ++ ++ if (led_trigger_register(host->ports[i]->ledtrig)) { ++ kfree(host->ports[i]->ledtrig); ++ host->ports[i]->ledtrig = NULL; ++ } ++ } ++#endif ++ + /* Create associated sysfs transport objects */ + for (i = 0; i < host->n_ports; i++) { + rc = ata_tport_add(host->dev,host->ports[i]); +diff --git a/include/linux/libata.h b/include/linux/libata.h +index b20a275..50eeee3 100644 +--- a/include/linux/libata.h ++++ b/include/linux/libata.h +@@ -38,6 +38,7 @@ + #include + #include + #include ++#include + + /* + * Define if arch has non-standard setup. This is a _PCI_ standard +@@ -877,6 +878,12 @@ struct ata_port { + #ifdef CONFIG_ATA_ACPI + struct ata_acpi_gtm __acpi_init_gtm; /* use ata_acpi_init_gtm() */ + #endif ++ ++#ifdef CONFIG_ATA_LEDS ++ struct led_trigger *ledtrig; ++ char ledtrig_name[8]; ++#endif ++ + /* owned by EH */ + u8 sector_buf[ATA_SECT_SIZE] ____cacheline_aligned; + }; +-- +2.7.4 + diff --git a/patch/kernel/mvebu-default/93-Enable-ATA-port-LED-trigger.patch b/patch/kernel/mvebu-default/93-Enable-ATA-port-LED-trigger.patch new file mode 100644 index 0000000000..2b5952f120 --- /dev/null +++ b/patch/kernel/mvebu-default/93-Enable-ATA-port-LED-trigger.patch @@ -0,0 +1,37 @@ +From 9ee6345ef82f7af5f98e17a40e667f8ad6b2fa1b Mon Sep 17 00:00:00 2001 +From: aprayoga +Date: Sun, 3 Sep 2017 18:10:12 +0800 +Subject: Enable ATA port LED trigger + +--- + arch/arm/configs/mvebu_v7_defconfig | 1 + + arch/arm/mach-mvebu/Kconfig | 1 + + 2 files changed, 2 insertions(+) + +diff --git a/arch/arm/configs/mvebu_v7_defconfig b/arch/arm/configs/mvebu_v7_defconfig +index cf363ab..19449d3 100644 +--- a/arch/arm/configs/mvebu_v7_defconfig ++++ b/arch/arm/configs/mvebu_v7_defconfig +@@ -61,6 +61,7 @@ CONFIG_MTD_SPI_NOR=y + CONFIG_EEPROM_AT24=y + CONFIG_BLK_DEV_SD=y + CONFIG_ATA=y ++CONFIG_ATA_LEDS=y + CONFIG_SATA_AHCI=y + CONFIG_AHCI_MVEBU=y + CONFIG_SATA_MV=y +diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig +index 053ea9d..aa1f389 100644 +--- a/arch/arm/mach-mvebu/Kconfig ++++ b/arch/arm/mach-mvebu/Kconfig +@@ -52,6 +52,7 @@ config MACH_ARMADA_375 + + config MACH_ARMADA_38X + bool "Marvell Armada 380/385 boards" if ARCH_MULTI_V7 ++ select ARCH_WANT_LIBATA_LEDS + select ARM_ERRATA_720789 + select ARM_ERRATA_753970 + select ARM_GIC +-- +2.7.4 + diff --git a/patch/kernel/mvebu-default/95-helios4-device-tree.patch b/patch/kernel/mvebu-default/95-helios4-device-tree.patch new file mode 100644 index 0000000000..0a1ec90cc9 --- /dev/null +++ b/patch/kernel/mvebu-default/95-helios4-device-tree.patch @@ -0,0 +1,387 @@ +From 9fe4b82ed5e62ac82df8294e9e02b4ffab23bb47 Mon Sep 17 00:00:00 2001 +From: Aditya Prayoga +Date: Sun, 19 Mar 2017 17:27:01 +0800 +Subject: Initial device tree + +- Tested using clearfrog u-boot +- Increase SD Card clock to 50 MHz from default 25 MHz +- All 7 LED declared as led-gpio +- LED1 (system) default to hearbeat +- LED7 (USB) triggered by USB Host activity +- GPIO23 (MPP23) declared as GPIO button +- SPI NOR flash declared as MTD +- Enable IO expander interrupt +- Allocate GPIOs for fans +--- + arch/arm/boot/dts/armada-388-helios4.dts | 318 ++++++++++++++++++++++++++++++ + 1 file changed, 318 insertions(+) + create mode 100644 arch/arm/boot/dts/armada-388-helios4.dts + +diff --git a/arch/arm/boot/dts/armada-388-helios4.dts b/arch/arm/boot/dts/armada-388-helios4.dts +new file mode 100644 +index 0000000..b7a2122 +--- /dev/null ++++ b/arch/arm/boot/dts/armada-388-helios4.dts +@@ -0,0 +1,346 @@ ++/* ++ * Device Tree file for Helios4 ++ * based on SolidRun Clearfog revision A1 rev 2.0 (88F6828) ++ * ++ * Copyright (C) 2017 ++ * ++ */ ++ ++/dts-v1/; ++#include "armada-388.dtsi" ++#include "armada-38x-solidrun-microsom.dtsi" ++ ++/ { ++ model = "Helios4"; ++ compatible = "marvell,armada388", ++ "marvell,armada385", "marvell,armada380"; ++ ++ memory { ++ device_type = "memory"; ++ reg = <0x00000000 0x40000000>; /* 1 GB */ ++ }; ++ ++ aliases { ++ /* So that mvebu u-boot can update the MAC addresses */ ++ ethernet1 = ð0; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ reg_12v: regulator-12v { ++ compatible = "regulator-fixed"; ++ regulator-name = "power_brick_12V"; ++ regulator-min-microvolt = <12000000>; ++ regulator-max-microvolt = <12000000>; ++ regulator-always-on; ++ }; ++ ++ reg_3p3v: regulator-3p3v { ++ compatible = "regulator-fixed"; ++ regulator-name = "3P3V"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ vin-supply = <®_12v>; ++ }; ++ ++ reg_5p0v_hdd: regulator-5v-hdd { ++ compatible = "regulator-fixed"; ++ regulator-name = "5V_HDD"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ vin-supply = <®_12v>; ++ }; ++ ++ reg_5p0v_usb: regulator-5v-usb { ++ compatible = "regulator-fixed"; ++ regulator-name = "USB-PWR"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-boot-on; ++ regulator-always-on; ++ enable-active-high; ++ gpio = <&expander0 6 GPIO_ACTIVE_HIGH>; ++ vin-supply = <®_12v>; ++ }; ++ ++ gpio-keys { ++ compatible = "gpio-keys"; ++ pinctrl-0 = <&user_button_pins>; ++ pinctrl-names = "default"; ++ ++ button_0 { ++ label = "User Button"; ++ gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; ++ linux,can-disable; ++ linux,code = ; ++ }; ++ }; ++ ++ system-leds { ++ compatible = "gpio-leds"; ++ status-led { ++ label = "helios4:green:status"; ++ gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; ++ linux,default-trigger = "heartbeat"; ++ default-state = "on"; ++ }; ++ ++ fault-led { ++ label = "helios4:red:fault"; ++ gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; ++ default-state = "keep"; ++ }; ++ }; ++ ++ io-leds { ++ compatible = "gpio-leds"; ++ sata1-led { ++ label = "helios4:green:ata1"; ++ gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; ++ linux,default-trigger = "ata1"; ++ default-state = "off"; ++ }; ++ sata2-led { ++ label = "helios4:green:ata2"; ++ gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; ++ linux,default-trigger = "ata2"; ++ default-state = "off"; ++ }; ++ sata3-led { ++ label = "helios4:green:ata3"; ++ gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; ++ linux,default-trigger = "ata3"; ++ default-state = "off"; ++ }; ++ sata4-led { ++ label = "helios4:green:ata4"; ++ gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; ++ linux,default-trigger = "ata4"; ++ default-state = "off"; ++ }; ++ usb-led { ++ label = "helios4:green:usb"; ++ gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; ++ linux,default-trigger = "usb-host"; ++ default-state = "off"; ++ }; ++ }; ++ ++ fan1: j10-pwm { ++ compatible = "pwm-fan"; ++ pwms = <&gpio1 9 3000>; ++ }; ++ ++ fan2: j17-pwm { ++ compatible = "pwm-fan"; ++ pwms = <&gpio1 4 4500>; ++ }; ++ ++ usb2_phy: usb2-phy { ++ compatible = "usb-nop-xceiv"; ++ vbus-regulator = <®_5p0v_usb>; ++ }; ++ ++ usb3_phy: usb3-phy { ++ compatible = "usb-nop-xceiv"; ++ //vbus-regulator = <®_5p0v_usb>; ++ }; ++ ++ soc { ++ internal-regs { ++ i2c@11000 { ++ clock-frequency = <100000>; ++ pinctrl-0 = <&i2c0_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ /* ++ * PCA9655 GPIO expander, up to 1MHz clock. ++ * 0-Board Revision bit 0 # ++ * 1-Board Revision bit 1 # ++ * 5-USB3 overcurrent ++ * 6-USB3 power ++ */ ++ expander0: gpio-expander@20 { ++ /* ++ * This is how it should be: ++ * compatible = "onnn,pca9655", ++ * "nxp,pca9555"; ++ * but you can't do this because of ++ * the way I2C works. ++ */ ++ compatible = "nxp,pca9555"; ++ gpio-controller; ++ #gpio-cells = <2>; ++ reg = <0x20>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pca0_pins>; ++ interrupt-parent = <&gpio0>; ++ interrupts = <18 IRQ_TYPE_EDGE_FALLING>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ ++ board_rev_bit_0 { ++ gpio-hog; ++ gpios = <0 GPIO_ACTIVE_LOW>; ++ input; ++ line-name = "board-rev-0"; ++ }; ++ board_rev_bit_1 { ++ gpio-hog; ++ gpios = <1 GPIO_ACTIVE_LOW>; ++ input; ++ line-name = "board-rev-1"; ++ }; ++ usb3_ilimit { ++ gpio-hog; ++ gpios = <5 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "usb-overcurrent-status"; ++ }; ++ }; ++ ++ temp_sensor: temp@4c { ++ compatible = "ti,lm75"; ++ reg = <0x4c>; ++ vcc-supply = <®_3p3v>; ++ }; ++ ++ /* What device at 0x64 ? */ ++ }; ++ ++ i2c@11100 { ++ /* ++ * External I2C Bus for user peripheral ++ */ ++ clock-frequency = <400000>; ++ pinctrl-0 = <&helios_i2c1_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ }; ++ ++ sata@a8000 { ++ status = "okay"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ sata0: sata-port@0 { ++ reg = <0>; ++ }; ++ ++ sata1: sata-port@1 { ++ reg = <1>; ++ }; ++ }; ++ ++ sata@e0000 { ++ status = "okay"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ sata2: sata-port@0 { ++ reg = <0>; ++ }; ++ ++ sata3: sata-port@1 { ++ reg = <1>; ++ }; ++ }; ++ ++ spi@10680 { ++ pinctrl-0 = <&spi1_pins ++ µsom_spi1_cs_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ spi-flash@0 { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ compatible = "w25q32", "jedec,spi-nor"; ++ reg = <0>; /* Chip select 0 */ ++ spi-max-frequency = <104000000>; ++ spi-cpha; ++ status = "okay"; ++ }; ++ }; ++ ++ sdhci@d8000 { ++ bus-width = <4>; ++ cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; ++ no-1-8-v; ++ pinctrl-0 = <&helios_sdhci_pins ++ &helios_sdhci_cd_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ vmmc = <®_3p3v>; ++ wp-inverted; ++ max-frequency = <50000000>; ++ cap-sd-highspeed; ++ sd-uhs-sdr12; ++ sd-uhs-sdr25; ++ sd-uhs-sdr50; ++ keep-power-in-suspend; ++ wakeup-source; ++ }; ++ ++ usb@58000 { ++ //vcc-supply = <®_5p0v_usb>; ++ usb-phy = <&usb2_phy>; ++ status = "okay"; ++ }; ++ ++ usb3@f0000 { ++ status = "okay"; ++ }; ++ ++ usb3@f8000 { ++ status = "okay"; ++ }; ++ ++ pinctrl@18000 { ++ pca0_pins: pca0_pins { ++ marvell,pins = "mpp18"; ++ marvell,function = "gpio"; ++ }; ++ helios_i2c1_pins: i2c1-pins { ++ marvell,pins = "mpp26", "mpp27"; ++ marvell,function = "i2c1"; ++ }; ++ helios_sdhci_cd_pins: helios-sdhci-cd-pins { ++ marvell,pins = "mpp20"; ++ marvell,function = "gpio"; ++ }; ++ helios_sdhci_pins: helios-sdhci-pins { ++ marvell,pins = "mpp21", "mpp28", ++ "mpp37", "mpp38", ++ "mpp39", "mpp40"; ++ marvell,function = "sd0"; ++ }; ++ helios_led_pins: helios-led-pins { ++ marvell,pins = "mpp24", "mpp25", ++ "mpp49", "mpp50", ++ "mpp52", "mpp53", ++ "mpp54"; ++ marvell,function = "gpio"; ++ }; ++ helios_fan_pins: helios-fan-pins { ++ marvell,pins = "mpp41", "mpp43", ++ "mpp36", "mpp25"; ++ marvell,function = "gpio"; ++ }; ++ microsom_spi1_cs_pins: spi1-cs-pins { ++ marvell,pins = "mpp59"; ++ marvell,function = "spi1"; ++ }; ++ user_button_pins: user-button-pins { ++ marvell,pins = "mpp23"; ++ marvell,function = "gpio"; ++ }; ++ }; ++ }; ++ }; ++}; + +diff -u a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile +--- a/arch/arm/boot/dts/Makefile 2017-10-19 03:51:29.758061000 +0800 ++++ b/arch/arm/boot/dts/Makefile 2017-10-19 05:58:52.613043929 +0800 +@@ -751,6 +751,7 @@ + armada-385-linksys-cobra.dtb \ + armada-388-clearfog-base.dtb \ + armada-388-clearfog-pro.dtb \ ++ armada-388-helios4.dtb \ + armada-388-db.dtb \ + armada-388-gp.dtb \ + armada-388-rd.dtb + +-- +2.7.4 + diff --git a/patch/kernel/mvebu-default/add-dtb-file-for-backwards-compatibility.patch b/patch/kernel/mvebu-default/add-dtb-file-for-backwards-compatibility.patch index b3f11fb83b..4e636de3d5 100644 --- a/patch/kernel/mvebu-default/add-dtb-file-for-backwards-compatibility.patch +++ b/patch/kernel/mvebu-default/add-dtb-file-for-backwards-compatibility.patch @@ -7,9 +7,9 @@ index face816..9dc5e06 100644 armada-388-clearfog-base.dtb \ armada-388-clearfog-pro.dtb \ + armada-388-clearfog.dtb \ + armada-388-helios4.dtb \ armada-388-db.dtb \ armada-388-gp.dtb \ - armada-388-rd.dtb diff --git a/arch/arm/boot/dts/armada-388-clearfog.dts b/arch/arm/boot/dts/armada-388-clearfog.dts new file mode 100644 index 0000000..7d906da