From 6fec2a296434e0f5bad3908aff42b116276e1d98 Mon Sep 17 00:00:00 2001 From: zador-blood-stained Date: Sun, 10 Sep 2017 17:58:22 +0300 Subject: [PATCH] Add H3 GPU clock SET_RATE_PARENT patch --- .../33-pll-gpu-allow-set-rate-parent.patch | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 patch/kernel/sunxi-next/33-pll-gpu-allow-set-rate-parent.patch diff --git a/patch/kernel/sunxi-next/33-pll-gpu-allow-set-rate-parent.patch b/patch/kernel/sunxi-next/33-pll-gpu-allow-set-rate-parent.patch new file mode 100644 index 0000000000..b151faf082 --- /dev/null +++ b/patch/kernel/sunxi-next/33-pll-gpu-allow-set-rate-parent.patch @@ -0,0 +1,28 @@ +The GPU clock on H3 has only one parent, PLL-GPU, and the PLL is only +the parent of the GPU clock. The GPU clock can be tweaked by tweaking +the PLL-GPU clock. + +Add CLK_SET_RATE_PARENT flag to allow tweaking the GPU clock via +tweaking PLL-GPU. + +Fixes: 0577e4853bfb ("clk: sunxi-ng: Add H3 clocks") +Signed-off-by: Icenowy Zheng +--- + drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c +index 7a81c4885836..543c46d0e045 100644 +--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c ++++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c +@@ -484,7 +484,7 @@ static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents, + 0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL); + + static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu", +- 0x1a0, 0, 3, BIT(31), 0); ++ 0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT); + + static struct ccu_common *sun8i_h3_ccu_clks[] = { + &pll_cpux_clk.common, +-- +2.13.5