From 589a7d0b910c3100a5200e6898c0e709b7e512ee Mon Sep 17 00:00:00 2001 From: EvilOlaf Date: Sat, 31 Jan 2026 07:11:13 +0000 Subject: [PATCH] sun55i: rewrite recent uboot patches --- ...er-sun55i-a523-add-pcie-spi-combophy.patch | 21 ++------ ...rangepi-4a-enable-spi0-pcie-combophy.patch | 23 +++------ .../edit-orangepi-4a-defconfig.patch | 7 ++- ...-cubie-a5e-enable-spi0-pcie-combophy.patch | 28 +++-------- .../edit-radxa-cubie-a5e-defconfig.patch | 8 ++- ...nxi-add-sun55i-a523-pcie-usb3-clocks.patch | 16 ++---- ...sunxi-add-dw-pcie-support-for-sun55i.patch | 8 +-- .../phy-allwinner-add-pcie-usb3-driver.patch | 8 +-- ...pi-sunxi-add-sun55i-a523-spl-support.patch | 50 ++++--------------- .../spi-sunxi-add-sun55i-a523-support.patch | 36 +++---------- .../v2026.01/sunxi-add-nvme-boot-target.patch | 12 +---- 11 files changed, 50 insertions(+), 167 deletions(-) diff --git a/patch/u-boot/v2026.01/arm64-dts-allwinner-sun55i-a523-add-pcie-spi-combophy.patch b/patch/u-boot/v2026.01/arm64-dts-allwinner-sun55i-a523-add-pcie-spi-combophy.patch index 22d6b3bf92..36862d45f4 100644 --- a/patch/u-boot/v2026.01/arm64-dts-allwinner-sun55i-a523-add-pcie-spi-combophy.patch +++ b/patch/u-boot/v2026.01/arm64-dts-allwinner-sun55i-a523-add-pcie-spi-combophy.patch @@ -5,15 +5,14 @@ Subject: arm64: dts: allwinner: sun55i-a523: Add SPI0, PCIe and Combophy nodes Signed-off-by: Marvin Wewer --- - dts/upstream/src/arm64/allwinner/sun55i-a523.dtsi | 66 ++++++++++ - 1 file changed, 66 insertions(+) + dts/upstream/src/arm64/allwinner/sun55i-a523.dtsi | 65 ++++++++++ + 1 file changed, 65 insertions(+) diff --git a/dts/upstream/src/arm64/allwinner/sun55i-a523.dtsi b/dts/upstream/src/arm64/allwinner/sun55i-a523.dtsi index 111111111111..222222222222 100644 --- a/dts/upstream/src/arm64/allwinner/sun55i-a523.dtsi +++ b/dts/upstream/src/arm64/allwinner/sun55i-a523.dtsi -@@ -1,9 +1,10 @@ - // SPDX-License-Identifier: (GPL-2.0-only OR MIT) +@@ -2,6 +2,7 @@ // Copyright (C) 2023-2024 Arm Ltd. #include @@ -21,11 +20,7 @@ index 111111111111..222222222222 100644 #include #include #include - #include - #include -@@ -607,10 +608,38 @@ - clocks = <&r_ccu CLK_BUS_R_PPU1>; - resets = <&r_ccu RST_BUS_R_PPU1>; +@@ -609,6 +610,34 @@ #power-domain-cells = <1>; }; @@ -60,11 +55,7 @@ index 111111111111..222222222222 100644 r_ccu: clock-controller@7010000 { compatible = "allwinner,sun55i-a523-r-ccu"; reg = <0x7010000 0x250>; - clocks = <&osc24M>, - <&rtc CLK_OSC32K>, -@@ -624,10 +653,46 @@ - "pll-audio"; - #clock-cells = <1>; +@@ -626,6 +655,42 @@ #reset-cells = <1>; }; @@ -107,8 +98,6 @@ index 111111111111..222222222222 100644 nmi_intc: interrupt-controller@7010320 { compatible = "allwinner,sun55i-a523-nmi"; reg = <0x07010320 0xc>; - interrupt-controller; - #interrupt-cells = <2>; -- Armbian diff --git a/patch/u-boot/v2026.01/board_orangepi-4a/arm64-dts-sun55i-t527-orangepi-4a-enable-spi0-pcie-combophy.patch b/patch/u-boot/v2026.01/board_orangepi-4a/arm64-dts-sun55i-t527-orangepi-4a-enable-spi0-pcie-combophy.patch index ba337019d1..e24a0ce6a7 100644 --- a/patch/u-boot/v2026.01/board_orangepi-4a/arm64-dts-sun55i-t527-orangepi-4a-enable-spi0-pcie-combophy.patch +++ b/patch/u-boot/v2026.01/board_orangepi-4a/arm64-dts-sun55i-t527-orangepi-4a-enable-spi0-pcie-combophy.patch @@ -1,20 +1,19 @@ From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Marvin Wewer Date: Sun, 4 Jan 2026 21:16:16 +0000 -Subject: arm64: dts: allwinner: sun55i-t527-orangepi-4a: Enable SPI0 and PCIe with ComboPHY +Subject: arm64: dts: allwinner: sun55i-t527-orangepi-4a: Enable SPI0 and PCIe + with ComboPHY Signed-off-by: Marvin Wewer --- - dts/upstream/src/arm64/allwinner/sun55i-t527-orangepi-4a.dts | 38 ++++++++-- - 1 file changed, 38 insertions(+) + dts/upstream/src/arm64/allwinner/sun55i-t527-orangepi-4a.dts | 39 ++++++++++ + 1 file changed, 39 insertions(+) diff --git a/dts/upstream/src/arm64/allwinner/sun55i-t527-orangepi-4a.dts b/dts/upstream/src/arm64/allwinner/sun55i-t527-orangepi-4a.dts index 111111111111..222222222222 100644 --- a/dts/upstream/src/arm64/allwinner/sun55i-t527-orangepi-4a.dts +++ b/dts/upstream/src/arm64/allwinner/sun55i-t527-orangepi-4a.dts -@@ -152,10 +152,22 @@ - vcc-pg-supply = <®_bldo1>; - vcc-ph-supply = <®_cldo3>; /* via VCC-IO */ +@@ -154,6 +154,18 @@ vcc-pi-supply = <®_cldo3>; vcc-pj-supply = <®_cldo1>; vcc-pk-supply = <®_cldo1>; @@ -33,11 +32,7 @@ index 111111111111..222222222222 100644 }; &r_i2c0 { - status = "okay"; - -@@ -368,10 +390,36 @@ - host-wakeup-gpios = <&r_pio 1 4 GPIO_ACTIVE_HIGH>; /* PM4 */ - shutdown-gpios = <&r_pio 1 2 GPIO_ACTIVE_HIGH>; /* PM2 */ +@@ -370,6 +382,32 @@ }; }; @@ -70,11 +65,7 @@ index 111111111111..222222222222 100644 &usb_otg { /* * The OTG controller is connected to one of the type-A ports. - * There is a regulator, controlled by a GPIO, to provide VBUS power - * to the port, and a VBUSDET GPIO, to detect externally provided -@@ -386,5 +414,6 @@ - usb0_vbus-supply = <®_otg_vbus>; - usb0_vbus_det-gpios = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */ +@@ -388,3 +426,4 @@ usb1_vbus-supply = <®_usb_vbus>; status = "okay"; }; diff --git a/patch/u-boot/v2026.01/board_orangepi-4a/edit-orangepi-4a-defconfig.patch b/patch/u-boot/v2026.01/board_orangepi-4a/edit-orangepi-4a-defconfig.patch index dba510ce64..22ace19774 100644 --- a/patch/u-boot/v2026.01/board_orangepi-4a/edit-orangepi-4a-defconfig.patch +++ b/patch/u-boot/v2026.01/board_orangepi-4a/edit-orangepi-4a-defconfig.patch @@ -1,7 +1,8 @@ From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Marvin Wewer Date: Mon, 12 Jan 2026 13:45:24 +0000 -Subject: Enable PCIe, NVMe, SPI and additional commands in orangepi_4a_defconfig +Subject: Enable PCIe, NVMe, SPI and additional commands in + orangepi_4a_defconfig Signed-off-by: Marvin Wewer --- @@ -12,9 +13,7 @@ diff --git a/configs/orangepi_4a_defconfig b/configs/orangepi_4a_defconfig index 111111111111..222222222222 100644 --- a/configs/orangepi_4a_defconfig +++ b/configs/orangepi_4a_defconfig -@@ -28,5 +28,25 @@ CONFIG_AXP717_POWER=y - CONFIG_AXP_I2C_ADDRESS=0x35 - CONFIG_AXP_DCDC2_VOLT=920 +@@ -30,3 +30,23 @@ CONFIG_AXP_DCDC2_VOLT=920 CONFIG_AXP_DCDC3_VOLT=1160 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/patch/u-boot/v2026.01/board_radxa-cubie-a5e/arm64-dts-sun55i-a527-cubie-a5e-enable-spi0-pcie-combophy.patch b/patch/u-boot/v2026.01/board_radxa-cubie-a5e/arm64-dts-sun55i-a527-cubie-a5e-enable-spi0-pcie-combophy.patch index a193a6dd3f..eef7c0264f 100644 --- a/patch/u-boot/v2026.01/board_radxa-cubie-a5e/arm64-dts-sun55i-a527-cubie-a5e-enable-spi0-pcie-combophy.patch +++ b/patch/u-boot/v2026.01/board_radxa-cubie-a5e/arm64-dts-sun55i-a527-cubie-a5e-enable-spi0-pcie-combophy.patch @@ -1,20 +1,19 @@ From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Marvin Wewer Date: Sat, 25 Oct 2025 16:50:43 +0000 -Subject: arm64: dts: allwinner: sun55i-a527-cubie-a5e: Enable SPI0 and PCIe with ComboPHY +Subject: arm64: dts: allwinner: sun55i-a527-cubie-a5e: Enable SPI0 and PCIe + with ComboPHY Signed-off-by: Marvin Wewer --- - dts/upstream/src/arm64/allwinner/sun55i-a527-cubie-a5e.dts | 84 ++++++++++ - 1 file changed, 84 insertions(+) + dts/upstream/src/arm64/allwinner/sun55i-a527-cubie-a5e.dts | 83 ++++++++++ + 1 file changed, 83 insertions(+) diff --git a/dts/upstream/src/arm64/allwinner/sun55i-a527-cubie-a5e.dts b/dts/upstream/src/arm64/allwinner/sun55i-a527-cubie-a5e.dts index 111111111111..222222222222 100644 --- a/dts/upstream/src/arm64/allwinner/sun55i-a527-cubie-a5e.dts +++ b/dts/upstream/src/arm64/allwinner/sun55i-a527-cubie-a5e.dts -@@ -43,10 +43,34 @@ - regulator-max-microvolt = <5000000>; - vin-supply = <®_vcc5v>; +@@ -45,6 +45,30 @@ gpio = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */ enable-active-high; }; @@ -45,11 +44,7 @@ index 111111111111..222222222222 100644 }; &ehci0 { - status = "okay"; - }; -@@ -102,10 +126,34 @@ - vcc-pg-supply = <®_bldo1>; - vcc-ph-supply = <®_cldo3>; /* via VCC-IO */ +@@ -104,6 +128,30 @@ vcc-pi-supply = <®_cldo3>; vcc-pj-supply = <®_cldo4>; vcc-pk-supply = <®_cldo1>; @@ -80,11 +75,7 @@ index 111111111111..222222222222 100644 }; &r_i2c0 { - status = "okay"; - -@@ -280,18 +328,53 @@ - * Specifying the supply would create a circular dependency. - * +@@ -282,6 +330,14 @@ * vcc-pl-supply = <®_aldo3>; */ vcc-pm-supply = <®_aldo3>; @@ -99,8 +90,7 @@ index 111111111111..222222222222 100644 }; &uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; +@@ -290,6 +346,33 @@ status = "okay"; }; @@ -134,8 +124,6 @@ index 111111111111..222222222222 100644 &usb_otg { /* * The USB-C port is the primary power supply, so in this configuration - * relies on the other end of the USB cable to supply the VBUS power. - * So use this port in peripheral mode. -- Armbian diff --git a/patch/u-boot/v2026.01/board_radxa-cubie-a5e/edit-radxa-cubie-a5e-defconfig.patch b/patch/u-boot/v2026.01/board_radxa-cubie-a5e/edit-radxa-cubie-a5e-defconfig.patch index b655b8d4bd..89d7f59958 100644 --- a/patch/u-boot/v2026.01/board_radxa-cubie-a5e/edit-radxa-cubie-a5e-defconfig.patch +++ b/patch/u-boot/v2026.01/board_radxa-cubie-a5e/edit-radxa-cubie-a5e-defconfig.patch @@ -5,16 +5,14 @@ Subject: Enable PCIe, NVMe, SPI and GPIO support in radxa-cubie-a5e_defconfig Signed-off-by: Marvin Wewer --- - configs/radxa-cubie-a5e_defconfig | 55 ++++++++++ - 1 file changed, 55 insertions(+) + configs/radxa-cubie-a5e_defconfig | 20 ++++++++++ + 1 file changed, 20 insertions(+) diff --git a/configs/radxa-cubie-a5e_defconfig b/configs/radxa-cubie-a5e_defconfig index 111111111111..222222222222 100644 --- a/configs/radxa-cubie-a5e_defconfig +++ b/configs/radxa-cubie-a5e_defconfig -@@ -28,5 +28,25 @@ CONFIG_REGULATOR_AXP=y - CONFIG_AXP717_POWER=y - CONFIG_AXP_DCDC2_VOLT=920 +@@ -30,3 +30,23 @@ CONFIG_AXP_DCDC2_VOLT=920 CONFIG_AXP_DCDC3_VOLT=1100 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/patch/u-boot/v2026.01/clk-sunxi-add-sun55i-a523-pcie-usb3-clocks.patch b/patch/u-boot/v2026.01/clk-sunxi-add-sun55i-a523-pcie-usb3-clocks.patch index 68094041ec..a6ecfdd4dd 100644 --- a/patch/u-boot/v2026.01/clk-sunxi-add-sun55i-a523-pcie-usb3-clocks.patch +++ b/patch/u-boot/v2026.01/clk-sunxi-add-sun55i-a523-pcie-usb3-clocks.patch @@ -13,9 +13,7 @@ diff --git a/drivers/clk/sunxi/clk_a523.c b/drivers/clk/sunxi/clk_a523.c index 111111111111..222222222222 100644 --- a/drivers/clk/sunxi/clk_a523.c +++ b/drivers/clk/sunxi/clk_a523.c -@@ -44,10 +44,12 @@ static struct ccu_clk_gate a523_gates[] = { - [CLK_BUS_OHCI0] = GATE(0xa8c, BIT(0)), - [CLK_BUS_OHCI1] = GATE(0xa8c, BIT(1)), +@@ -46,6 +46,8 @@ static struct ccu_clk_gate a523_gates[] = { [CLK_BUS_EHCI0] = GATE(0xa8c, BIT(4)), [CLK_BUS_EHCI1] = GATE(0xa8c, BIT(5)), [CLK_BUS_OTG] = GATE(0xa8c, BIT(8)), @@ -24,11 +22,7 @@ index 111111111111..222222222222 100644 }; static struct ccu_reset a523_resets[] = { - [RST_BUS_MMC0] = RESET(0x84c, BIT(16)), - [RST_BUS_MMC1] = RESET(0x84c, BIT(17)), -@@ -73,10 +75,11 @@ static struct ccu_reset a523_resets[] = { - [RST_BUS_OHCI0] = RESET(0xa8c, BIT(16)), - [RST_BUS_OHCI1] = RESET(0xa8c, BIT(17)), +@@ -75,6 +77,7 @@ static struct ccu_reset a523_resets[] = { [RST_BUS_EHCI0] = RESET(0xa8c, BIT(20)), [RST_BUS_EHCI1] = RESET(0xa8c, BIT(21)), [RST_BUS_OTG] = RESET(0xa8c, BIT(24)), @@ -36,15 +30,11 @@ index 111111111111..222222222222 100644 }; const struct ccu_desc a523_ccu_desc = { - .gates = a523_gates, - .resets = a523_resets, diff --git a/dts/upstream/include/dt-bindings/clock/sun55i-a523-ccu.h b/dts/upstream/include/dt-bindings/clock/sun55i-a523-ccu.h index 111111111111..222222222222 100644 --- a/dts/upstream/include/dt-bindings/clock/sun55i-a523-ccu.h +++ b/dts/upstream/include/dt-bindings/clock/sun55i-a523-ccu.h -@@ -183,7 +183,8 @@ - #define CLK_FANOUT_27M 174 - #define CLK_FANOUT_PCLK 175 +@@ -185,5 +185,6 @@ #define CLK_FANOUT0 176 #define CLK_FANOUT1 177 #define CLK_FANOUT2 178 diff --git a/patch/u-boot/v2026.01/pcie-sunxi-add-dw-pcie-support-for-sun55i.patch b/patch/u-boot/v2026.01/pcie-sunxi-add-dw-pcie-support-for-sun55i.patch index 5555df08b9..734802d48d 100644 --- a/patch/u-boot/v2026.01/pcie-sunxi-add-dw-pcie-support-for-sun55i.patch +++ b/patch/u-boot/v2026.01/pcie-sunxi-add-dw-pcie-support-for-sun55i.patch @@ -16,9 +16,7 @@ diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 111111111111..222222222222 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig -@@ -462,6 +462,14 @@ config PCIE_DW_IMX - select SYSCON - help +@@ -464,4 +464,12 @@ config PCIE_DW_IMX Say Y here if you want to enable DW PCIe controller support on iMX SoCs. @@ -35,9 +33,7 @@ diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index 111111111111..222222222222 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile -@@ -55,5 +55,6 @@ obj-$(CONFIG_PCIE_DW_SIFIVE) += pcie_dw_sifive.o - obj-$(CONFIG_PCIE_UNIPHIER) += pcie_uniphier.o - obj-$(CONFIG_PCIE_XILINX_NWL) += pcie-xilinx-nwl.o +@@ -57,3 +57,4 @@ obj-$(CONFIG_PCIE_XILINX_NWL) += pcie-xilinx-nwl.o obj-$(CONFIG_PCIE_PLDA_COMMON) += pcie_plda_common.o obj-$(CONFIG_PCIE_STARFIVE_JH7110) += pcie_starfive_jh7110.o obj-$(CONFIG_PCIE_DW_IMX) += pcie_dw_imx.o diff --git a/patch/u-boot/v2026.01/phy-allwinner-add-pcie-usb3-driver.patch b/patch/u-boot/v2026.01/phy-allwinner-add-pcie-usb3-driver.patch index a4bb064ece..cc08ddce40 100644 --- a/patch/u-boot/v2026.01/phy-allwinner-add-pcie-usb3-driver.patch +++ b/patch/u-boot/v2026.01/phy-allwinner-add-pcie-usb3-driver.patch @@ -14,9 +14,7 @@ diff --git a/drivers/phy/allwinner/Kconfig b/drivers/phy/allwinner/Kconfig index 111111111111..222222222222 100644 --- a/drivers/phy/allwinner/Kconfig +++ b/drivers/phy/allwinner/Kconfig -@@ -31,5 +31,13 @@ config PHY_SUN50I_USB3 - depends on ARCH_SUNXI - select PHY +@@ -33,3 +33,11 @@ config PHY_SUN50I_USB3 help Enable this to support the USB3 transceiver that is part of Allwinner sun50i SoCs. @@ -32,9 +30,7 @@ diff --git a/drivers/phy/allwinner/Makefile b/drivers/phy/allwinner/Makefile index 111111111111..222222222222 100644 --- a/drivers/phy/allwinner/Makefile +++ b/drivers/phy/allwinner/Makefile -@@ -3,5 +3,6 @@ - # Copyright (C) 2016 Amarula Solutions - # +@@ -5,3 +5,4 @@ obj-$(CONFIG_PHY_SUN4I_USB) += phy-sun4i-usb.o obj-$(CONFIG_PHY_SUN50I_USB3) += phy-sun50i-usb3.o diff --git a/patch/u-boot/v2026.01/spi-sunxi-add-sun55i-a523-spl-support.patch b/patch/u-boot/v2026.01/spi-sunxi-add-sun55i-a523-spl-support.patch index e815bdc6e4..0791207572 100644 --- a/patch/u-boot/v2026.01/spi-sunxi-add-sun55i-a523-spl-support.patch +++ b/patch/u-boot/v2026.01/spi-sunxi-add-sun55i-a523-spl-support.patch @@ -12,9 +12,7 @@ diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c b/arch/arm/mach-sunxi/spl_spi_s index 111111111111..222222222222 100644 --- a/arch/arm/mach-sunxi/spl_spi_sunxi.c +++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c -@@ -99,35 +99,44 @@ - - #define SPI0_CLK_DIV_BY_2 0x1000 +@@ -101,6 +101,8 @@ #define SPI0_CLK_DIV_BY_4 0x1001 #define SPI0_CLK_DIV_BY_32 0x100f @@ -23,9 +21,7 @@ index 111111111111..222222222222 100644 /*****************************************************************************/ /* - * Allwinner A10/A20 SoCs were using pins PC0,PC1,PC2,PC23 for booting - * from SPI Flash, everything else is using pins PC0,PC1,PC2,PC3. - * The H6 uses PC0, PC2, PC3, PC5, the H616 PC0, PC2, PC3, PC4. +@@ -110,22 +112,29 @@ */ static void spi0_pinmux_setup(unsigned int pin_function) { @@ -58,11 +54,7 @@ index 111111111111..222222222222 100644 sunxi_gpio_set_cfgpin(SUNXI_GPC(4), pin_function); /* Older generations use PC23 for CS, newer ones use PC3. */ - if (IS_ENABLED(CONFIG_MACH_SUN4I) || IS_ENABLED(CONFIG_MACH_SUN7I) || - IS_ENABLED(CONFIG_MACH_SUN8I_R40)) -@@ -142,10 +151,15 @@ static bool is_sun6i_gen_spi(void) - IS_ENABLED(CONFIG_SUN50I_GEN_H6) || - IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2) || +@@ -144,6 +153,11 @@ static bool is_sun6i_gen_spi(void) IS_ENABLED(CONFIG_MACH_SUN8I_V3S); } @@ -74,11 +66,7 @@ index 111111111111..222222222222 100644 static uintptr_t spi0_base_address(void) { if (IS_ENABLED(CONFIG_MACH_SUN8I_R40)) - return 0x01C05000; - -@@ -225,11 +239,11 @@ static void spi0_enable_clock(void) - static void spi0_disable_clock(void) - { +@@ -227,7 +241,7 @@ static void spi0_disable_clock(void) uintptr_t base = spi0_base_address(); /* Disable the SPI0 controller */ @@ -87,11 +75,7 @@ index 111111111111..222222222222 100644 clrbits_le32(base + SUN6I_SPI0_GCR, SUN6I_CTL_MASTER | SUN6I_CTL_ENABLE); else - clrbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | - SUN4I_CTL_ENABLE); -@@ -255,11 +269,12 @@ static void spi0_disable_clock(void) - static void spi0_init(void) - { +@@ -257,7 +271,8 @@ static void spi0_init(void) unsigned int pin_function = SUNXI_GPC_SPI0; if (IS_ENABLED(CONFIG_MACH_SUN50I) || @@ -101,11 +85,7 @@ index 111111111111..222222222222 100644 pin_function = SUN50I_GPC_SPI0; else if (IS_ENABLED(CONFIG_MACH_SUNIV) || IS_ENABLED(CONFIG_MACH_SUN8I_R528)) - pin_function = SUNIV_GPC_SPI0; - -@@ -270,11 +285,12 @@ static void spi0_init(void) - static void spi0_deinit(void) - { +@@ -272,7 +287,8 @@ static void spi0_deinit(void) /* New SoCs can disable pins, older could only set them as input */ unsigned int pin_function = SUNXI_GPIO_INPUT; @@ -115,11 +95,7 @@ index 111111111111..222222222222 100644 pin_function = SUNXI_GPIO_DISABLE; spi0_disable_clock(); - spi0_pinmux_setup(pin_function); - } -@@ -282,46 +298,49 @@ static void spi0_deinit(void) - /*****************************************************************************/ - +@@ -284,42 +300,45 @@ static void spi0_deinit(void) #define SPI_READ_MAX_SIZE 60 /* FIFO size, minus 4 bytes of the header */ static void sunxi_spi0_read_data(u8 *buf, u32 addr, u32 bufsize, @@ -197,11 +173,7 @@ index 111111111111..222222222222 100644 } static void spi0_read_data(void *buf, u32 addr, u32 len) - { - u8 *buf8 = buf; -@@ -331,20 +350,30 @@ static void spi0_read_data(void *buf, u32 addr, u32 len) - while (len > 0) { - chunk_len = len; +@@ -333,7 +352,7 @@ static void spi0_read_data(void *buf, u32 addr, u32 len) if (chunk_len > SPI_READ_MAX_SIZE) chunk_len = SPI_READ_MAX_SIZE; @@ -210,9 +182,7 @@ index 111111111111..222222222222 100644 sunxi_spi0_read_data(buf8, addr, chunk_len, base + SUN6I_SPI0_TCR, SUN6I_TCR_XCH, - base + SUN6I_SPI0_FIFO_STA, - base + SUN6I_SPI0_TXD, - base + SUN6I_SPI0_RXD, +@@ -343,6 +362,16 @@ static void spi0_read_data(void *buf, u32 addr, u32 len) base + SUN6I_SPI0_MBC, base + SUN6I_SPI0_MTC, base + SUN6I_SPI0_BCC); @@ -229,8 +199,6 @@ index 111111111111..222222222222 100644 } else { sunxi_spi0_read_data(buf8, addr, chunk_len, base + SUN4I_SPI0_CTL, - SUN4I_CTL_XCH, - base + SUN4I_SPI0_FIFO_STA, -- Armbian diff --git a/patch/u-boot/v2026.01/spi-sunxi-add-sun55i-a523-support.patch b/patch/u-boot/v2026.01/spi-sunxi-add-sun55i-a523-support.patch index 265df25515..97473c9729 100644 --- a/patch/u-boot/v2026.01/spi-sunxi-add-sun55i-a523-support.patch +++ b/patch/u-boot/v2026.01/spi-sunxi-add-sun55i-a523-support.patch @@ -12,9 +12,7 @@ diff --git a/drivers/spi/spi-sunxi.c b/drivers/spi/spi-sunxi.c index 111111111111..222222222222 100644 --- a/drivers/spi/spi-sunxi.c +++ b/drivers/spi/spi-sunxi.c -@@ -82,10 +82,12 @@ DECLARE_GLOBAL_DATA_PTR; - #endif - #define SUN4I_SPI_MIN_RATE 3000 +@@ -84,6 +84,8 @@ DECLARE_GLOBAL_DATA_PTR; #define SUN4I_SPI_DEFAULT_RATE 1000000 #define SUN4I_SPI_TIMEOUT_MS 1000 @@ -23,11 +21,7 @@ index 111111111111..222222222222 100644 #define SPI_REG(priv, reg) ((priv)->base + \ (priv)->variant->regs[reg]) #define SPI_BIT(priv, bit) ((priv)->variant->bits[bit]) - #define SPI_CS(priv, cs) (((cs) << SPI_BIT(priv, SPI_TCR_CS_SEL)) & \ - SPI_BIT(priv, SPI_TCR_CS_MASK)) -@@ -128,10 +130,11 @@ struct sun4i_spi_variant { - const u32 *bits; - u32 fifo_depth; +@@ -130,6 +132,7 @@ struct sun4i_spi_variant { bool has_soft_reset; bool has_burst_ctl; bool has_clk_ctl; @@ -35,11 +29,7 @@ index 111111111111..222222222222 100644 }; struct sun4i_spi_plat { - struct sun4i_spi_variant *variant; - u32 base; -@@ -364,10 +367,25 @@ static int sun4i_spi_xfer(struct udevice *dev, unsigned int bitlen, - - /* Reset FIFOs */ +@@ -366,6 +369,21 @@ static int sun4i_spi_xfer(struct udevice *dev, unsigned int bitlen, setbits_le32(SPI_REG(priv, SPI_FCR), SPI_BIT(priv, SPI_FCR_RF_RST) | SPI_BIT(priv, SPI_FCR_TF_RST)); @@ -61,11 +51,7 @@ index 111111111111..222222222222 100644 while (len) { /* Setup the transfer now... */ nbytes = min(len, (priv->variant->fifo_depth - 1)); - - /* Setup the counters */ -@@ -517,10 +535,23 @@ static const unsigned long sun6i_spi_regs[] = { - [SPI_BCTL] = SUN6I_BURST_CTL_REG, - [SPI_TXD] = SUN6I_TXDATA_REG, +@@ -519,6 +537,19 @@ static const unsigned long sun6i_spi_regs[] = { [SPI_RXD] = SUN6I_RXDATA_REG, }; @@ -85,11 +71,7 @@ index 111111111111..222222222222 100644 static const u32 sun6i_spi_bits[] = { [SPI_GCR_TP] = BIT(7), [SPI_GCR_SRST] = BIT(31), - [SPI_TCR_CPHA] = BIT(0), - [SPI_TCR_CPOL] = BIT(1), -@@ -568,10 +599,19 @@ static const struct sun4i_spi_variant sun50i_r329_spi_variant = { - .fifo_depth = 64, - .has_soft_reset = true, +@@ -570,6 +601,15 @@ static const struct sun4i_spi_variant sun50i_r329_spi_variant = { .has_burst_ctl = true, }; @@ -105,11 +87,7 @@ index 111111111111..222222222222 100644 static const struct udevice_id sun4i_spi_ids[] = { { .compatible = "allwinner,sun4i-a10-spi", - .data = (ulong)&sun4i_a10_spi_variant, - }, -@@ -585,10 +625,14 @@ static const struct udevice_id sun4i_spi_ids[] = { - }, - { +@@ -587,6 +627,10 @@ static const struct udevice_id sun4i_spi_ids[] = { .compatible = "allwinner,sun50i-r329-spi", .data = (ulong)&sun50i_r329_spi_variant, }, @@ -120,8 +98,6 @@ index 111111111111..222222222222 100644 { /* sentinel */ } }; - U_BOOT_DRIVER(sun4i_spi) = { - .name = "sun4i_spi", -- Armbian diff --git a/patch/u-boot/v2026.01/sunxi-add-nvme-boot-target.patch b/patch/u-boot/v2026.01/sunxi-add-nvme-boot-target.patch index 6fd9793fe7..6ba2dfdabe 100644 --- a/patch/u-boot/v2026.01/sunxi-add-nvme-boot-target.patch +++ b/patch/u-boot/v2026.01/sunxi-add-nvme-boot-target.patch @@ -12,9 +12,7 @@ diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 111111111111..222222222222 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h -@@ -206,10 +206,16 @@ - #define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na) - #else +@@ -208,6 +208,12 @@ #define BOOT_TARGET_DEVICES_DHCP(func) #endif @@ -27,11 +25,7 @@ index 111111111111..222222222222 100644 /* FEL boot support, auto-execute boot.scr if a script address was provided */ #define BOOTENV_DEV_FEL(devtypeu, devtypel, instance) \ "bootcmd_fel=" \ - "if test -n ${fel_booted} && test -n ${fel_scriptaddr}; then " \ - "echo '(FEL boot)'; " \ -@@ -218,10 +224,11 @@ - #define BOOTENV_DEV_NAME_FEL(devtypeu, devtypel, instance) \ - "fel " +@@ -220,6 +226,7 @@ #define BOOT_TARGET_DEVICES(func) \ func(FEL, fel, na) \ @@ -39,8 +33,6 @@ index 111111111111..222222222222 100644 BOOT_TARGET_DEVICES_MMC(func) \ BOOT_TARGET_DEVICES_SCSI(func) \ BOOT_TARGET_DEVICES_USB(func) \ - BOOT_TARGET_DEVICES_PXE(func) \ - BOOT_TARGET_DEVICES_DHCP(func) -- Armbian