From 3084b25c5e07f0cdfae124f4f4bd3916108b2ecd Mon Sep 17 00:00:00 2001 From: may Date: Tue, 4 Jun 2019 09:45:25 +0800 Subject: [PATCH 1/2] [h6] set minimum voltage to 880mV according to datasheet suggest operation voltage rage is 0.873V~0.927V. --- .../0012-general-h6-new-opp-table.patch | 27 ++++++++++++------- 1 file changed, 17 insertions(+), 10 deletions(-) diff --git a/patch/kernel/sunxi-dev/0012-general-h6-new-opp-table.patch b/patch/kernel/sunxi-dev/0012-general-h6-new-opp-table.patch index c895dd5e8c..6f7a80bb18 100644 --- a/patch/kernel/sunxi-dev/0012-general-h6-new-opp-table.patch +++ b/patch/kernel/sunxi-dev/0012-general-h6-new-opp-table.patch @@ -1,41 +1,48 @@ diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi -index 141fd186b..5356ca6f6 100644 +index 141fd186b..4ab42048d 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi -@@ -73,55 +73,55 @@ +@@ -67,61 +67,62 @@ + }; + }; + ++ /* 0.6~1.1V, 10mV/Step, 51 steps */ + cpu_opp_table: opp_table { + compatible = "operating-points-v2"; + opp-shared; opp@480000000 { opp-hz = /bits/ 64 <480000000>; - opp-microvolt = <880000 880000 880000>; -+ opp-microvolt = <800000 800000 880000>; ++ opp-microvolt = <880000 870000 900000>; clock-latency-ns = <244144>; /* 8 32k periods */ }; opp@720000000 { opp-hz = /bits/ 64 <720000000>; - opp-microvolt = <880000 880000 880000>; -+ opp-microvolt = <800000 800000 880000>; ++ opp-microvolt = <880000 870000 900000>; clock-latency-ns = <244144>; /* 8 32k periods */ }; opp@816000000 { opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <880000 880000 880000>; -+ opp-microvolt = <800000 800000 880000>; ++ opp-microvolt = <880000 870000 900000>; clock-latency-ns = <244144>; /* 8 32k periods */ }; opp@888000000 { opp-hz = /bits/ 64 <888000000>; - opp-microvolt = <880000 880000 880000>; -+ opp-microvolt = <800000 800000 900000>; ++ opp-microvolt = <880000 870000 900000>; clock-latency-ns = <244144>; /* 8 32k periods */ }; opp@1080000000 { opp-hz = /bits/ 64 <1080000000>; - opp-microvolt = <940000 940000 940000>; -+ opp-microvolt = <840000 840000 900000>; ++ opp-microvolt = <880000 880000 900000>; clock-latency-ns = <244144>; /* 8 32k periods */ }; @@ -49,21 +56,21 @@ index 141fd186b..5356ca6f6 100644 opp@1488000000 { opp-hz = /bits/ 64 <1488000000>; - opp-microvolt = <1060000 1060000 1060000>; -+ opp-microvolt = <900000 900000 910000>; ++ opp-microvolt = <900000 900000 920000>; clock-latency-ns = <244144>; /* 8 32k periods */ }; opp@1640000000 { opp-hz = /bits/ 64 <1640000000>; - opp-microvolt = <1160000 1160000 1160000>; -+ opp-microvolt = <910000 910000 920000>; ++ opp-microvolt = <910000 910000 930000>; clock-latency-ns = <244144>; /* 8 32k periods */ }; opp@1800000000 { opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <1160000 1160000 1160000>; -+ opp-microvolt = <950000 930000 950000>; ++ opp-microvolt = <950000 930000 960000>; clock-latency-ns = <244144>; /* 8 32k periods */ }; }; From 77f72312266b94903ac6f66f6f4f644bd5d13105 Mon Sep 17 00:00:00 2001 From: may Date: Wed, 5 Jun 2019 03:27:12 +0800 Subject: [PATCH 2/2] [dev][h6] update opp, fix stability issue new values are based on stabilityTester results when using 930mV for 1.6GHz and 980mV for 1.8GHz, xhpl failed randomly. So 930/980mV are the critical operation voltage.Then increase 10mV and run 100 times test, result shows that xhpl (not always) failed 1~2 times. It seems +10mV is still not enough to ensure dc-dc output voltage always above operation voltage, that means the design of dc-dc converter is not good enough that results in large ripple. The testing script is "github.com/mzhboy/StabilityTester" The following configuration have been tested. 1.08-1.32-1.48-1.64-1.8 GHz 900-910-920-930-990 *ok, 930 failed 2/100 900-900-910-940-990 *ok, 990 failed 1/100 890-900-910-940-990 *ok, 990 failed 1/100 880-880-910-940-1000 *ok, 940 failed 2/100 880-880-910-950-1000 *ok, 1000 failed 1/100 880-880-910-950-1010 *ok --- .../sunxi-dev/0012-general-h6-new-opp-table.patch | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/patch/kernel/sunxi-dev/0012-general-h6-new-opp-table.patch b/patch/kernel/sunxi-dev/0012-general-h6-new-opp-table.patch index 6f7a80bb18..3fe76dd816 100644 --- a/patch/kernel/sunxi-dev/0012-general-h6-new-opp-table.patch +++ b/patch/kernel/sunxi-dev/0012-general-h6-new-opp-table.patch @@ -1,12 +1,12 @@ diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi -index 141fd186b..4ab42048d 100644 +index 141fd186b..4d4dcf8eb 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -67,61 +67,62 @@ }; }; -+ /* 0.6~1.1V, 10mV/Step, 51 steps */ ++ /* axp80,DCDC-A: 0.6~1.1V, 10mV/Step, 51 steps; 1.12~1.52V, 20mV/Step, 21 Steps */ cpu_opp_table: opp_table { compatible = "operating-points-v2"; opp-shared; @@ -42,35 +42,35 @@ index 141fd186b..4ab42048d 100644 opp@1080000000 { opp-hz = /bits/ 64 <1080000000>; - opp-microvolt = <940000 940000 940000>; -+ opp-microvolt = <880000 880000 900000>; ++ opp-microvolt = <880000 880000 940000>; clock-latency-ns = <244144>; /* 8 32k periods */ }; opp@1320000000 { opp-hz = /bits/ 64 <1320000000>; - opp-microvolt = <1000000 1000000 1000000>; -+ opp-microvolt = <880000 880000 900000>; ++ opp-microvolt = <880000 880000 960000>; clock-latency-ns = <244144>; /* 8 32k periods */ }; opp@1488000000 { opp-hz = /bits/ 64 <1488000000>; - opp-microvolt = <1060000 1060000 1060000>; -+ opp-microvolt = <900000 900000 920000>; ++ opp-microvolt = <910000 900000 980000>; clock-latency-ns = <244144>; /* 8 32k periods */ }; opp@1640000000 { opp-hz = /bits/ 64 <1640000000>; - opp-microvolt = <1160000 1160000 1160000>; -+ opp-microvolt = <910000 910000 930000>; ++ opp-microvolt = <950000 910000 1100000>; clock-latency-ns = <244144>; /* 8 32k periods */ }; opp@1800000000 { opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <1160000 1160000 1160000>; -+ opp-microvolt = <950000 930000 960000>; ++ opp-microvolt = <1010000 930000 1160000>; clock-latency-ns = <244144>; /* 8 32k periods */ }; };