From 4de4c42e6f641eb6fc8eb02066486a7c42a7f73e Mon Sep 17 00:00:00 2001 From: Heisath Date: Fri, 11 Feb 2022 11:00:57 +0100 Subject: [PATCH] Bump mvebu-current to 5.15 and mvebu-edge to 5.16 --- config/kernel/linux-mvebu-current.config | 545 +++++-- config/sources/families/mvebu.conf | 4 +- ...e-net-ipx.h-and-uapi-linux-ipx.h-hea.patch | 287 ++++ ...dicate-failure-to-enter-deeper-sleep.patch | 43 + .../mvebu-5.16/09-pci-link-retraining.patch | 219 +++ .../mvebu-5.16/10-pcie-bridge-emul.patch | 273 ++++ .../11-mvebu-clearfog-pcie-updates.patch | 244 +++ .../12-implement-slot-capabilities-SSPL.patch | 60 + .../mvebu-5.16/12-net-dsa-mv88e6xxx.patch | 1325 +++++++++++++++++ ...da388-clearfog-emmc-on-clearfog-base.patch | 87 ++ .../91-01-libata-add-ledtrig-support.patch | 149 ++ .../91-02-Enable-ATA-port-LED-trigger.patch | 30 + ...-mvebu-gpio-add_wake_on_gpio_support.patch | 88 ++ ...io-remove-hardcoded-timer-assignment.patch | 446 ++++++ ...-helios4-dts-add-wake-on-lan-support.patch | 21 + .../compile-dtb-with-symbol-support.patch | 12 + ...s-disable-spi-flash-on-a388-microsom.patch | 10 + ..._DMA_block_memory_allocation_to_2048.patch | 11 + ...lock_atheros_regulatory_restrictions.patch | 70 + .../use-1000BaseX-clearfog-switch.patch | 39 + patch/kernel/mvebu-current | 2 +- patch/kernel/mvebu-edge | 2 +- 22 files changed, 3805 insertions(+), 162 deletions(-) create mode 100644 patch/kernel/archive/mvebu-5.16/0001-Revert-net-Remove-net-ipx.h-and-uapi-linux-ipx.h-hea.patch create mode 100644 patch/kernel/archive/mvebu-5.16/0001-cpuidle-mvebu-indicate-failure-to-enter-deeper-sleep.patch create mode 100644 patch/kernel/archive/mvebu-5.16/09-pci-link-retraining.patch create mode 100644 patch/kernel/archive/mvebu-5.16/10-pcie-bridge-emul.patch create mode 100644 patch/kernel/archive/mvebu-5.16/11-mvebu-clearfog-pcie-updates.patch create mode 100644 patch/kernel/archive/mvebu-5.16/12-implement-slot-capabilities-SSPL.patch create mode 100644 patch/kernel/archive/mvebu-5.16/12-net-dsa-mv88e6xxx.patch create mode 100644 patch/kernel/archive/mvebu-5.16/412-ARM-dts-armada388-clearfog-emmc-on-clearfog-base.patch create mode 100644 patch/kernel/archive/mvebu-5.16/91-01-libata-add-ledtrig-support.patch create mode 100644 patch/kernel/archive/mvebu-5.16/91-02-Enable-ATA-port-LED-trigger.patch create mode 100644 patch/kernel/archive/mvebu-5.16/92-mvebu-gpio-add_wake_on_gpio_support.patch create mode 100644 patch/kernel/archive/mvebu-5.16/92-mvebu-gpio-remove-hardcoded-timer-assignment.patch create mode 100644 patch/kernel/archive/mvebu-5.16/94-helios4-dts-add-wake-on-lan-support.patch create mode 100644 patch/kernel/archive/mvebu-5.16/compile-dtb-with-symbol-support.patch create mode 100644 patch/kernel/archive/mvebu-5.16/dts-disable-spi-flash-on-a388-microsom.patch create mode 100644 patch/kernel/archive/mvebu-5.16/general-increasing_DMA_block_memory_allocation_to_2048.patch create mode 100644 patch/kernel/archive/mvebu-5.16/unlock_atheros_regulatory_restrictions.patch create mode 100644 patch/kernel/archive/mvebu-5.16/use-1000BaseX-clearfog-switch.patch diff --git a/config/kernel/linux-mvebu-current.config b/config/kernel/linux-mvebu-current.config index 246e190447..ec1dd1ed96 100644 --- a/config/kernel/linux-mvebu-current.config +++ b/config/kernel/linux-mvebu-current.config @@ -1,17 +1,21 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm 5.10.85 Kernel Configuration +# Linux/arm 5.15.1 Kernel Configuration # CONFIG_CC_VERSION_TEXT="arm-linux-gnueabihf-gcc (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36)) 8.3.0" CONFIG_CC_IS_GCC=y CONFIG_GCC_VERSION=80300 -CONFIG_LD_VERSION=232000000 CONFIG_CLANG_VERSION=0 +CONFIG_AS_IS_GNU=y +CONFIG_AS_VERSION=23200 +CONFIG_LD_IS_BFD=y +CONFIG_LD_VERSION=23200 CONFIG_LLD_VERSION=0 CONFIG_CC_CAN_LINK=y CONFIG_CC_CAN_LINK_STATIC=y CONFIG_CC_HAS_ASM_GOTO=y CONFIG_CC_HAS_ASM_INLINE=y +CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y CONFIG_IRQ_WORK=y CONFIG_BUILDTIME_TABLE_SORT=y @@ -20,6 +24,7 @@ CONFIG_BUILDTIME_TABLE_SORT=y # CONFIG_INIT_ENV_ARG_LIMIT=32 # CONFIG_COMPILE_TEST is not set +# CONFIG_WERROR is not set CONFIG_LOCALVERSION="" # CONFIG_LOCALVERSION_AUTO is not set CONFIG_BUILD_SALT="" @@ -84,6 +89,19 @@ CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y # end of Timers subsystem +CONFIG_BPF=y +CONFIG_HAVE_EBPF_JIT=y + +# +# BPF subsystem +# +CONFIG_BPF_SYSCALL=y +CONFIG_BPF_JIT=y +# CONFIG_BPF_JIT_ALWAYS_ON is not set +# CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set +# CONFIG_BPF_PRELOAD is not set +# end of BPF subsystem + CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set @@ -131,6 +149,7 @@ CONFIG_IKHEADERS=m CONFIG_LOG_BUF_SHIFT=16 CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13 +# CONFIG_PRINTK_INDEX is not set CONFIG_GENERIC_SCHED_CLOCK=y # @@ -159,6 +178,7 @@ CONFIG_CGROUP_DEVICE=y CONFIG_CGROUP_CPUACCT=y CONFIG_CGROUP_PERF=y CONFIG_CGROUP_BPF=y +# CONFIG_CGROUP_MISC is not set # CONFIG_CGROUP_DEBUG is not set CONFIG_SOCK_CGROUP_DATA=y CONFIG_NAMESPACES=y @@ -186,7 +206,6 @@ CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y CONFIG_LD_ORPHAN_WARN=y CONFIG_SYSCTL=y CONFIG_HAVE_UID16=y -CONFIG_BPF=y # CONFIG_EXPERT is not set CONFIG_UID16=y CONFIG_MULTIUSER=y @@ -194,7 +213,6 @@ CONFIG_SYSFS_SYSCALL=y CONFIG_FHANDLE=y CONFIG_POSIX_TIMERS=y CONFIG_PRINTK=y -CONFIG_PRINTK_NMI=y CONFIG_BUG=y CONFIG_ELF_CORE=y CONFIG_BASE_FULL=y @@ -213,9 +231,6 @@ CONFIG_MEMBARRIER=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_ALL is not set CONFIG_KALLSYMS_BASE_RELATIVE=y -CONFIG_BPF_SYSCALL=y -# CONFIG_BPF_JIT_ALWAYS_ON is not set -# CONFIG_BPF_PRELOAD is not set # CONFIG_USERFAULTFD is not set CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y CONFIG_RSEQ=y @@ -250,7 +265,6 @@ CONFIG_SYS_SUPPORTS_APM_EMULATION=y CONFIG_HAVE_PROC_CPU=y CONFIG_STACKTRACE_SUPPORT=y CONFIG_LOCKDEP_SUPPORT=y -CONFIG_TRACE_IRQFLAGS_SUPPORT=y CONFIG_FIX_EARLYCON_MEM=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y @@ -266,7 +280,6 @@ CONFIG_MMU=y CONFIG_ARCH_MMAP_RND_BITS_MIN=8 CONFIG_ARCH_MMAP_RND_BITS_MAX=16 CONFIG_ARCH_MULTIPLATFORM=y -# CONFIG_ARCH_EBSA110 is not set # CONFIG_ARCH_EP93XX is not set # CONFIG_ARCH_FOOTBRIDGE is not set # CONFIG_ARCH_IOP32X is not set @@ -331,7 +344,6 @@ CONFIG_MACH_DOVE=y # CONFIG_SOC_DRA7XX is not set # end of TI OMAP/AM/DM/DRA Family -# CONFIG_ARCH_SIRF is not set # CONFIG_ARCH_QCOM is not set # CONFIG_ARCH_RDA is not set # CONFIG_ARCH_REALTEK is not set @@ -339,18 +351,16 @@ CONFIG_MACH_DOVE=y # CONFIG_ARCH_ROCKCHIP is not set # CONFIG_ARCH_S5PV210 is not set # CONFIG_ARCH_RENESAS is not set -# CONFIG_ARCH_SOCFPGA is not set +# CONFIG_ARCH_INTEL_SOCFPGA is not set # CONFIG_PLAT_SPEAR is not set # CONFIG_ARCH_STI is not set # CONFIG_ARCH_STM32 is not set # CONFIG_ARCH_SUNXI is not set -# CONFIG_ARCH_TANGO is not set # CONFIG_ARCH_TEGRA is not set # CONFIG_ARCH_UNIPHIER is not set # CONFIG_ARCH_U8500 is not set # CONFIG_ARCH_VEXPRESS is not set # CONFIG_ARCH_WM8850 is not set -# CONFIG_ARCH_ZX is not set # CONFIG_ARCH_ZYNQ is not set CONFIG_PLAT_ORION=y @@ -471,7 +481,6 @@ CONFIG_AEABI=y CONFIG_ARCH_SELECT_MEMORY_MODEL=y CONFIG_ARCH_FLATMEM_ENABLE=y CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_HAVE_ARCH_PFN_VALID=y CONFIG_HIGHMEM=y CONFIG_HIGHPTE=y CONFIG_CPU_SW_DOMAIN_PAN=y @@ -484,6 +493,7 @@ CONFIG_ALIGNMENT_TRAP=y # CONFIG_PARAVIRT is not set # CONFIG_PARAVIRT_TIME_ACCOUNTING is not set # CONFIG_XEN is not set +# CONFIG_STACKPROTECTOR_PER_TASK is not set # end of Kernel Features # @@ -533,6 +543,7 @@ CONFIG_CPUFREQ_DT=m CONFIG_CPUFREQ_DT_PLATDEV=y CONFIG_ARM_ARMADA_37XX_CPUFREQ=m CONFIG_ARM_ARMADA_8K_CPUFREQ=m +CONFIG_ARM_SCMI_CPUFREQ=m # end of CPU Frequency scaling # @@ -592,20 +603,6 @@ CONFIG_ARM_CPU_SUSPEND=y CONFIG_ARCH_HIBERNATION_POSSIBLE=y # end of Power management options -# -# Firmware Drivers -# -# CONFIG_FW_CFG_SYSFS is not set -# CONFIG_TRUSTED_FOUNDATIONS is not set -# CONFIG_GOOGLE_FIRMWARE is not set -CONFIG_HAVE_ARM_SMCCC=y - -# -# Tegra firmware driver -# -# end of Tegra firmware driver -# end of Firmware Drivers - CONFIG_ARM_CRYPTO=y CONFIG_CRYPTO_SHA1_ARM=m CONFIG_CRYPTO_SHA1_ARM_NEON=m @@ -613,6 +610,8 @@ CONFIG_CRYPTO_SHA1_ARM_CE=m CONFIG_CRYPTO_SHA2_ARM_CE=m CONFIG_CRYPTO_SHA256_ARM=m CONFIG_CRYPTO_SHA512_ARM=m +CONFIG_CRYPTO_BLAKE2S_ARM=m +CONFIG_CRYPTO_BLAKE2B_NEON=m CONFIG_CRYPTO_AES_ARM=m CONFIG_CRYPTO_AES_ARM_BS=m CONFIG_CRYPTO_AES_ARM_CE=m @@ -628,8 +627,6 @@ CONFIG_AS_VFP_VMRS_FPINST=y # # General architecture-dependent options # -CONFIG_SET_FS=y -CONFIG_HAVE_OPROFILE=y # CONFIG_KPROBES is not set CONFIG_JUMP_LABEL=y # CONFIG_STATIC_KEYS_SELFTEST is not set @@ -638,6 +635,7 @@ CONFIG_ARCH_USE_BUILTIN_BSWAP=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_NMI=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y CONFIG_HAVE_ARCH_TRACEHOOK=y CONFIG_HAVE_DMA_CONTIGUOUS=y CONFIG_GENERIC_SMP_IDLE_THREAD=y @@ -653,14 +651,17 @@ CONFIG_HAVE_HW_BREAKPOINT=y CONFIG_HAVE_PERF_REGS=y CONFIG_HAVE_PERF_USER_STACK_DUMP=y CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y CONFIG_HAVE_ARCH_SECCOMP=y CONFIG_HAVE_ARCH_SECCOMP_FILTER=y CONFIG_SECCOMP=y CONFIG_SECCOMP_FILTER=y +# CONFIG_SECCOMP_CACHE_DEBUG is not set CONFIG_HAVE_STACKPROTECTOR=y CONFIG_STACKPROTECTOR=y CONFIG_STACKPROTECTOR_STRONG=y +CONFIG_LTO_NONE=y CONFIG_HAVE_CONTEXT_TRACKING=y CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y @@ -684,6 +685,7 @@ CONFIG_STRICT_MODULE_RWX=y CONFIG_ARCH_HAS_PHYS_TO_DMA=y # CONFIG_LOCK_EVENT_COUNTS is not set CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y +CONFIG_HAVE_ARCH_PFN_VALID=y # # GCOV-based kernel profiling @@ -693,7 +695,9 @@ CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y # end of GCOV-based kernel profiling CONFIG_HAVE_GCC_PLUGINS=y -# CONFIG_GCC_PLUGINS is not set +CONFIG_GCC_PLUGINS=y +# CONFIG_GCC_PLUGIN_LATENT_ENTROPY is not set +# CONFIG_GCC_PLUGIN_RANDSTRUCT is not set # end of General architecture-dependent options CONFIG_RT_MUTEXES=y @@ -714,26 +718,27 @@ CONFIG_MODULE_SIG_SHA1=y # CONFIG_MODULE_SIG_SHA384 is not set # CONFIG_MODULE_SIG_SHA512 is not set CONFIG_MODULE_SIG_HASH="sha1" -# CONFIG_MODULE_COMPRESS is not set +# CONFIG_MODULE_COMPRESS_NONE is not set +# CONFIG_MODULE_COMPRESS_GZIP is not set +CONFIG_MODULE_COMPRESS_XZ=y +# CONFIG_MODULE_COMPRESS_ZSTD is not set # CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set -# CONFIG_UNUSED_SYMBOLS is not set -# CONFIG_TRIM_UNUSED_KSYMS is not set +CONFIG_MODPROBE_PATH="/sbin/modprobe" CONFIG_MODULES_TREE_LOOKUP=y CONFIG_BLOCK=y -CONFIG_BLK_SCSI_REQUEST=y CONFIG_BLK_CGROUP_RWSTAT=y -CONFIG_BLK_DEV_BSG=y +CONFIG_BLK_DEV_BSG_COMMON=y CONFIG_BLK_DEV_BSGLIB=y CONFIG_BLK_DEV_INTEGRITY=y CONFIG_BLK_DEV_INTEGRITY_T10=y CONFIG_BLK_DEV_ZONED=y CONFIG_BLK_DEV_THROTTLING=y # CONFIG_BLK_DEV_THROTTLING_LOW is not set -# CONFIG_BLK_CMDLINE_PARSER is not set CONFIG_BLK_WBT=y +CONFIG_BLK_WBT_MQ=y # CONFIG_BLK_CGROUP_IOLATENCY is not set # CONFIG_BLK_CGROUP_IOCOST is not set -CONFIG_BLK_WBT_MQ=y +# CONFIG_BLK_CGROUP_IOPRIO is not set # CONFIG_BLK_DEBUG_FS is not set # CONFIG_BLK_SED_OPAL is not set # CONFIG_BLK_INLINE_ENCRYPTION is not set @@ -749,6 +754,7 @@ CONFIG_EFI_PARTITION=y CONFIG_BLK_MQ_PCI=y CONFIG_BLK_MQ_VIRTIO=y CONFIG_BLK_PM=y +CONFIG_BLOCK_HOLDER_DEPRECATED=y # # IO Schedulers @@ -799,7 +805,6 @@ CONFIG_SELECT_MEMORY_MODEL=y CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y CONFIG_ARCH_KEEP_MEMBLOCK=y CONFIG_MEMORY_ISOLATION=y CONFIG_SPLIT_PTLOCK_CPUS=4 @@ -817,6 +822,7 @@ CONFIG_FRONTSWAP=y CONFIG_CMA=y # CONFIG_CMA_DEBUG is not set # CONFIG_CMA_DEBUGFS is not set +# CONFIG_CMA_SYSFS is not set CONFIG_CMA_AREAS=7 CONFIG_ZSWAP=y # CONFIG_ZSWAP_COMPRESSOR_DEFAULT_DEFLATE is not set @@ -837,10 +843,17 @@ CONFIG_Z3FOLD=y CONFIG_ZSMALLOC=m # CONFIG_ZSMALLOC_STAT is not set CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_PAGE_IDLE_FLAG=y CONFIG_IDLE_PAGE_TRACKING=y -CONFIG_FRAME_VECTOR=y # CONFIG_PERCPU_STATS is not set -# CONFIG_GUP_BENCHMARK is not set +# CONFIG_GUP_TEST is not set +CONFIG_KMAP_LOCAL=y + +# +# Data Access Monitoring +# +# CONFIG_DAMON is not set +# end of Data Access Monitoring # end of Memory Management options CONFIG_NET=y @@ -856,6 +869,7 @@ CONFIG_PACKET=y CONFIG_PACKET_DIAG=m CONFIG_UNIX=y CONFIG_UNIX_SCM=y +CONFIG_AF_UNIX_OOB=y CONFIG_UNIX_DIAG=m CONFIG_TLS=m # CONFIG_TLS_DEVICE is not set @@ -964,6 +978,7 @@ CONFIG_IPV6_SEG6_LWTUNNEL=y CONFIG_IPV6_SEG6_HMAC=y CONFIG_IPV6_SEG6_BPF=y # CONFIG_IPV6_RPL_LWTUNNEL is not set +# CONFIG_IPV6_IOAM6_LWTUNNEL is not set CONFIG_NETLABEL=y # CONFIG_MPTCP is not set CONFIG_NETWORK_SECMARK=y @@ -980,13 +995,13 @@ CONFIG_NETFILTER_INGRESS=y CONFIG_NETFILTER_NETLINK=m CONFIG_NETFILTER_FAMILY_BRIDGE=y CONFIG_NETFILTER_FAMILY_ARP=y +CONFIG_NETFILTER_NETLINK_HOOK=m CONFIG_NETFILTER_NETLINK_ACCT=m CONFIG_NETFILTER_NETLINK_QUEUE=m CONFIG_NETFILTER_NETLINK_LOG=m CONFIG_NETFILTER_NETLINK_OSF=m CONFIG_NF_CONNTRACK=m -CONFIG_NF_LOG_COMMON=m -CONFIG_NF_LOG_NETDEV=m +CONFIG_NF_LOG_SYSLOG=m CONFIG_NETFILTER_CONNCOUNT=m CONFIG_NF_CONNTRACK_MARK=y CONFIG_NF_CONNTRACK_SECMARK=y @@ -1056,6 +1071,7 @@ CONFIG_NF_DUP_NETDEV=m CONFIG_NFT_DUP_NETDEV=m CONFIG_NFT_FWD_NETDEV=m CONFIG_NFT_FIB_NETDEV=m +CONFIG_NFT_REJECT_NETDEV=m CONFIG_NF_FLOW_TABLE_INET=m CONFIG_NF_FLOW_TABLE=m CONFIG_NETFILTER_XTABLES=m @@ -1198,6 +1214,7 @@ CONFIG_IP_VS_SH=m CONFIG_IP_VS_MH=m CONFIG_IP_VS_SED=m CONFIG_IP_VS_NQ=m +CONFIG_IP_VS_TWOS=m # # IPVS SH scheduler @@ -1298,7 +1315,6 @@ CONFIG_NF_DEFRAG_IPV6=m CONFIG_NF_TABLES_BRIDGE=m CONFIG_NFT_BRIDGE_META=m CONFIG_NFT_BRIDGE_REJECT=m -CONFIG_NF_LOG_BRIDGE=m CONFIG_NF_CONNTRACK_BRIDGE=m CONFIG_BRIDGE_NF_EBTABLES=m CONFIG_BRIDGE_EBT_BROUTE=m @@ -1374,24 +1390,28 @@ CONFIG_BRIDGE=m CONFIG_BRIDGE_IGMP_SNOOPING=y CONFIG_BRIDGE_VLAN_FILTERING=y # CONFIG_BRIDGE_MRP is not set -CONFIG_HAVE_NET_DSA=y +# CONFIG_BRIDGE_CFM is not set CONFIG_NET_DSA=m -CONFIG_NET_DSA_TAG_8021Q=m # CONFIG_NET_DSA_TAG_AR9331 is not set CONFIG_NET_DSA_TAG_BRCM_COMMON=m CONFIG_NET_DSA_TAG_BRCM=m +CONFIG_NET_DSA_TAG_BRCM_LEGACY=m CONFIG_NET_DSA_TAG_BRCM_PREPEND=m +CONFIG_NET_DSA_TAG_HELLCREEK=m CONFIG_NET_DSA_TAG_GSWIP=m +CONFIG_NET_DSA_TAG_DSA_COMMON=m CONFIG_NET_DSA_TAG_DSA=m CONFIG_NET_DSA_TAG_EDSA=m CONFIG_NET_DSA_TAG_MTK=m CONFIG_NET_DSA_TAG_KSZ=m CONFIG_NET_DSA_TAG_RTL4_A=m CONFIG_NET_DSA_TAG_OCELOT=m +CONFIG_NET_DSA_TAG_OCELOT_8021Q=m CONFIG_NET_DSA_TAG_QCA=m CONFIG_NET_DSA_TAG_LAN9303=m CONFIG_NET_DSA_TAG_SJA1105=m CONFIG_NET_DSA_TAG_TRAILER=m +CONFIG_NET_DSA_TAG_XRS700X=m CONFIG_VLAN_8021Q=m CONFIG_VLAN_8021Q_GVRP=y CONFIG_VLAN_8021Q_MVRP=y @@ -1534,9 +1554,7 @@ CONFIG_BATMAN_ADV_BLA=y CONFIG_BATMAN_ADV_DAT=y CONFIG_BATMAN_ADV_NC=y CONFIG_BATMAN_ADV_MCAST=y -# CONFIG_BATMAN_ADV_DEBUGFS is not set # CONFIG_BATMAN_ADV_DEBUG is not set -CONFIG_BATMAN_ADV_SYSFS=y CONFIG_OPENVSWITCH=m CONFIG_OPENVSWITCH_GRE=m CONFIG_OPENVSWITCH_VXLAN=m @@ -1560,16 +1578,18 @@ CONFIG_QRTR_TUN=m CONFIG_QRTR_MHI=m CONFIG_NET_NCSI=y CONFIG_NCSI_OEM_CMD_GET_MAC=y +# CONFIG_NCSI_OEM_CMD_KEEP_PHY is not set +CONFIG_PCPU_DEV_REFCNT=y CONFIG_RPS=y CONFIG_RFS_ACCEL=y +CONFIG_SOCK_RX_QUEUE_MAPPING=y CONFIG_XPS=y CONFIG_HWBM=y CONFIG_CGROUP_NET_PRIO=y CONFIG_CGROUP_NET_CLASSID=y CONFIG_NET_RX_BUSY_POLL=y CONFIG_BQL=y -CONFIG_BPF_JIT=y -CONFIG_BPF_STREAM_PARSER=y +# CONFIG_BPF_STREAM_PARSER is not set CONFIG_NET_FLOW_LIMIT=y # @@ -1629,6 +1649,7 @@ CONFIG_CAN_CC770_ISA=m CONFIG_CAN_CC770_PLATFORM=m # CONFIG_CAN_IFI_CANFD is not set CONFIG_CAN_M_CAN=m +CONFIG_CAN_M_CAN_PCI=m CONFIG_CAN_M_CAN_PLATFORM=m CONFIG_CAN_M_CAN_TCAN4X5X=m CONFIG_CAN_PEAK_PCIEFD=m @@ -1660,6 +1681,7 @@ CONFIG_CAN_MCP251XFD=m CONFIG_CAN_8DEV_USB=m CONFIG_CAN_EMS_USB=m CONFIG_CAN_ESD_USB2=m +CONFIG_CAN_ETAS_ES58X=m CONFIG_CAN_GS_USB=m CONFIG_CAN_KVASER_USB=m CONFIG_CAN_MCBA_USB=m @@ -1683,6 +1705,7 @@ CONFIG_BT_LE=y CONFIG_BT_6LOWPAN=m CONFIG_BT_LEDS=y # CONFIG_BT_MSFTEXT is not set +# CONFIG_BT_AOSPEXT is not set # CONFIG_BT_DEBUGFS is not set # CONFIG_BT_SELFTEST is not set @@ -1722,6 +1745,7 @@ CONFIG_BT_MRVL_SDIO=m CONFIG_BT_ATH3K=m CONFIG_BT_MTKSDIO=m CONFIG_BT_MTKUART=m +CONFIG_BT_VIRTIO=m # end of Bluetooth device drivers CONFIG_AF_RXRPC=m @@ -1731,6 +1755,7 @@ CONFIG_AF_RXRPC=m # CONFIG_RXKAD is not set CONFIG_AF_KCM=m CONFIG_STREAM_PARSER=y +CONFIG_MCTP=m CONFIG_FIB_RULES=y CONFIG_WIRELESS=y CONFIG_WIRELESS_EXT=y @@ -1764,8 +1789,6 @@ CONFIG_MAC80211_DEBUGFS=y # CONFIG_MAC80211_MESSAGE_TRACING is not set # CONFIG_MAC80211_DEBUG_MENU is not set CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 -CONFIG_WIMAX=m -CONFIG_WIMAX_DEBUG_LEVEL=8 CONFIG_RFKILL=m CONFIG_RFKILL_LEDS=y CONFIG_RFKILL_INPUT=y @@ -1791,6 +1814,7 @@ CONFIG_NFC_SHDLC=y CONFIG_NFC_TRF7970A=m CONFIG_NFC_SIM=m CONFIG_NFC_PORT100=m +CONFIG_NFC_VIRTUAL_NCI=m CONFIG_NFC_FDP=m CONFIG_NFC_FDP_I2C=m CONFIG_NFC_PN544=m @@ -1815,6 +1839,7 @@ CONFIG_NFC_NXP_NCI=m CONFIG_NFC_NXP_NCI_I2C=m CONFIG_NFC_S3FWRN5=m CONFIG_NFC_S3FWRN5_I2C=m +CONFIG_NFC_S3FWRN82_UART=m CONFIG_NFC_ST95HF=m # end of Near Field Communication (NFC) devices @@ -1824,12 +1849,12 @@ CONFIG_LWTUNNEL=y CONFIG_LWTUNNEL_BPF=y CONFIG_DST_CACHE=y CONFIG_GRO_CELLS=y +CONFIG_NET_SELFTESTS=y CONFIG_NET_SOCK_MSG=y CONFIG_NET_DEVLINK=y CONFIG_PAGE_POOL=y CONFIG_FAILOVER=m CONFIG_ETHTOOL_NETLINK=y -CONFIG_HAVE_EBPF_JIT=y # # Device Drivers @@ -1866,6 +1891,7 @@ CONFIG_PCI_MVEBU=y # CONFIG_PCIE_XILINX is not set # CONFIG_PCI_V3_SEMI is not set # CONFIG_PCIE_ALTERA is not set +# CONFIG_PCIE_MICROCHIP_HOST is not set # # DesignWare PCI Core Support @@ -1901,6 +1927,9 @@ CONFIG_PCI_MVEBU=y # CONFIG_PCI_SW_SWITCHTEC is not set # end of PCI switch controller drivers +CONFIG_CXL_BUS=m +CONFIG_CXL_MEM=m +# CONFIG_CXL_MEM_RAW_COMMANDS is not set # CONFIG_PCCARD is not set CONFIG_RAPIDIO=m CONFIG_RAPIDIO_DISC_TIMEOUT=30 @@ -1971,13 +2000,37 @@ CONFIG_ARM_CCI=y # CONFIG_BRCMSTB_GISB_ARB is not set # CONFIG_MOXTET is not set CONFIG_MVEBU_MBUS=y -CONFIG_SIMPLE_PM_BUS=y # CONFIG_VEXPRESS_CONFIG is not set CONFIG_MHI_BUS=m # CONFIG_MHI_BUS_DEBUG is not set +CONFIG_MHI_BUS_PCI_GENERIC=m # end of Bus devices # CONFIG_CONNECTOR is not set + +# +# Firmware Drivers +# + +# +# ARM System Control and Management Interface Protocol +# +CONFIG_ARM_SCMI_PROTOCOL=m +# CONFIG_ARM_SCMI_TRANSPORT_VIRTIO is not set +CONFIG_ARM_SCMI_POWER_DOMAIN=m +# end of ARM System Control and Management Interface Protocol + +# CONFIG_FW_CFG_SYSFS is not set +# CONFIG_TRUSTED_FOUNDATIONS is not set +# CONFIG_GOOGLE_FIRMWARE is not set +CONFIG_HAVE_ARM_SMCCC=y + +# +# Tegra firmware driver +# +# end of Tegra firmware driver +# end of Firmware Drivers + # CONFIG_GNSS is not set CONFIG_MTD=y # CONFIG_MTD_TESTS is not set @@ -1997,6 +2050,10 @@ CONFIG_MTD_OF_PARTS=y # CONFIG_MTD_BLKDEVS=y CONFIG_MTD_BLOCK=y + +# +# Note that in some cases UBI block is preferred. See MTD_UBI_BLOCK. +# # CONFIG_FTL is not set # CONFIG_NFTL is not set # CONFIG_INFTL is not set @@ -2043,6 +2100,7 @@ CONFIG_MTD_CFI_UTIL=m # CONFIG_MTD_PMC551 is not set # CONFIG_MTD_DATAFLASH is not set # CONFIG_MTD_MCHP23K256 is not set +CONFIG_MTD_MCHP48L640=m # CONFIG_MTD_SST25L is not set # CONFIG_MTD_SLRAM is not set # CONFIG_MTD_PHRAM is not set @@ -2058,12 +2116,9 @@ CONFIG_MTD_BLOCK2MTD=m # # NAND # -CONFIG_MTD_NAND_CORE=m +CONFIG_MTD_NAND_CORE=y # CONFIG_MTD_ONENAND is not set -CONFIG_MTD_NAND_ECC_SW_HAMMING=m -# CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC is not set CONFIG_MTD_RAW_NAND=m -# CONFIG_MTD_NAND_ECC_SW_BCH is not set # # Raw/parallel NAND flash controllers @@ -2080,6 +2135,7 @@ CONFIG_MTD_NAND_GPIO=m CONFIG_MTD_NAND_PLATFORM=m # CONFIG_MTD_NAND_CADENCE is not set # CONFIG_MTD_NAND_ARASAN is not set +CONFIG_MTD_NAND_INTEL_LGM=m # # Misc @@ -2097,6 +2153,9 @@ CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0 # ECC engine support # CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_ECC_SW_HAMMING=y +# CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC is not set +# CONFIG_MTD_NAND_ECC_SW_BCH is not set # end of ECC engine support # end of NAND @@ -2109,6 +2168,9 @@ CONFIG_MTD_NAND_ECC=y CONFIG_MTD_SPI_NOR=y CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y +# CONFIG_MTD_SPI_NOR_SWP_DISABLE is not set +CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE=y +# CONFIG_MTD_SPI_NOR_SWP_KEEP is not set # CONFIG_MTD_UBI is not set # CONFIG_MTD_HYPERBUS is not set CONFIG_DTC=y @@ -2134,9 +2196,15 @@ CONFIG_BLK_DEV=y CONFIG_BLK_DEV_NULL_BLK=m # CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set CONFIG_ZRAM=m +CONFIG_ZRAM_DEF_COMP_LZORLE=y +# CONFIG_ZRAM_DEF_COMP_ZSTD is not set +# CONFIG_ZRAM_DEF_COMP_LZ4 is not set +# CONFIG_ZRAM_DEF_COMP_LZO is not set +# CONFIG_ZRAM_DEF_COMP_LZ4HC is not set +# CONFIG_ZRAM_DEF_COMP_842 is not set +CONFIG_ZRAM_DEF_COMP="lzo-rle" CONFIG_ZRAM_WRITEBACK=y # CONFIG_ZRAM_MEMORY_TRACKING is not set -# CONFIG_BLK_DEV_UMEM is not set CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 CONFIG_BLK_DEV_CRYPTOLOOP=m @@ -2186,10 +2254,10 @@ CONFIG_NVME_TCP=m # CONFIG_LATTICE_ECP3_CONFIG is not set CONFIG_SRAM=y CONFIG_SRAM_EXEC=y +CONFIG_DW_XDATA_PCIE=m # CONFIG_PCI_ENDPOINT_TEST is not set # CONFIG_XILINX_SDFEC is not set CONFIG_MISC_RTSX=m -CONFIG_PVPANIC=m CONFIG_HISI_HIKEY_USB=m # CONFIG_C2PORT is not set @@ -2218,21 +2286,22 @@ CONFIG_EEPROM_EE1004=m # CONFIG_SENSORS_LIS3_I2C is not set # CONFIG_ALTERA_STAPL is not set # CONFIG_ECHO is not set +CONFIG_BCM_VK=m +# CONFIG_BCM_VK_TTY is not set CONFIG_MISC_ALCOR_PCI=m CONFIG_MISC_RTSX_PCI=m CONFIG_MISC_RTSX_USB=m CONFIG_HABANA_AI=m CONFIG_UACCE=m +# CONFIG_PVPANIC is not set # end of Misc devices -CONFIG_HAVE_IDE=y -# CONFIG_IDE is not set - # # SCSI device support # CONFIG_SCSI_MOD=y CONFIG_RAID_ATTRS=m +CONFIG_SCSI_COMMON=y CONFIG_SCSI=y CONFIG_SCSI_DMA=y CONFIG_SCSI_PROC_FS=y @@ -2244,6 +2313,7 @@ CONFIG_BLK_DEV_SD=y # CONFIG_CHR_DEV_ST is not set # CONFIG_BLK_DEV_SR is not set CONFIG_CHR_DEV_SG=y +CONFIG_BLK_DEV_BSG=y # CONFIG_CHR_DEV_SCH is not set # CONFIG_SCSI_CONSTANTS is not set # CONFIG_SCSI_LOGGING is not set @@ -2286,6 +2356,7 @@ CONFIG_ISCSI_BOOT_SYSFS=m # CONFIG_MEGARAID_SAS is not set # CONFIG_SCSI_MPT3SAS is not set # CONFIG_SCSI_MPT2SAS is not set +CONFIG_SCSI_MPI3MR=m # CONFIG_SCSI_SMARTPQI is not set # CONFIG_SCSI_UFSHCD is not set # CONFIG_SCSI_HPTIOP is not set @@ -2294,7 +2365,6 @@ CONFIG_SCSI_MYRS=m # CONFIG_SCSI_SNIC is not set # CONFIG_SCSI_DMX3191D is not set # CONFIG_SCSI_FDOMAIN_PCI is not set -CONFIG_SCSI_GDTH=m # CONFIG_SCSI_IPS is not set # CONFIG_SCSI_INITIO is not set # CONFIG_SCSI_INIA100 is not set @@ -2440,7 +2510,6 @@ CONFIG_DM_THIN_PROVISIONING=m CONFIG_DM_CACHE=m CONFIG_DM_CACHE_SMQ=m CONFIG_DM_WRITECACHE=m -# CONFIG_DM_EBS is not set # CONFIG_DM_ERA is not set CONFIG_DM_CLONE=m CONFIG_DM_MIRROR=m @@ -2451,6 +2520,7 @@ CONFIG_DM_MULTIPATH=m # CONFIG_DM_MULTIPATH_QL is not set # CONFIG_DM_MULTIPATH_ST is not set # CONFIG_DM_MULTIPATH_HST is not set +CONFIG_DM_MULTIPATH_IOA=m CONFIG_DM_DELAY=m CONFIG_DM_DUST=m # CONFIG_DM_UEVENT is not set @@ -2515,6 +2585,7 @@ CONFIG_VIRTIO_NET=m CONFIG_NLMON=m CONFIG_NET_VRF=m CONFIG_VSOCKMON=m +CONFIG_MHI_NET=m # CONFIG_ARCNET is not set CONFIG_ATM_DRIVERS=y CONFIG_ATM_DUMMY=m @@ -2534,18 +2605,21 @@ CONFIG_ATM_TCP=m # CONFIG_B53 is not set # CONFIG_NET_DSA_BCM_SF2 is not set # CONFIG_NET_DSA_LOOP is not set +CONFIG_NET_DSA_HIRSCHMANN_HELLCREEK=m CONFIG_NET_DSA_LANTIQ_GSWIP=m # CONFIG_NET_DSA_MT7530 is not set CONFIG_NET_DSA_MV88E6060=m # CONFIG_NET_DSA_MICROCHIP_KSZ9477 is not set # CONFIG_NET_DSA_MICROCHIP_KSZ8795 is not set CONFIG_NET_DSA_MV88E6XXX=m -CONFIG_NET_DSA_MV88E6XXX_GLOBAL2=y # CONFIG_NET_DSA_MV88E6XXX_PTP is not set CONFIG_NET_DSA_MSCC_SEVILLE=m # CONFIG_NET_DSA_AR9331 is not set CONFIG_NET_DSA_SJA1105=m # CONFIG_NET_DSA_SJA1105_PTP is not set +CONFIG_NET_DSA_XRS700X=m +CONFIG_NET_DSA_XRS700X_I2C=m +CONFIG_NET_DSA_XRS700X_MDIO=m # CONFIG_NET_DSA_QCA8K is not set CONFIG_NET_DSA_REALTEK_SMI=m # CONFIG_NET_DSA_SMSC_LAN9303_I2C is not set @@ -2567,7 +2641,6 @@ CONFIG_ETHERNET=y # CONFIG_NET_VENDOR_AQUANTIA is not set # CONFIG_NET_VENDOR_ARC is not set # CONFIG_NET_VENDOR_ATHEROS is not set -# CONFIG_NET_VENDOR_AURORA is not set # CONFIG_NET_VENDOR_BROADCOM is not set # CONFIG_NET_VENDOR_BROCADE is not set CONFIG_NET_VENDOR_CADENCE=y @@ -2586,11 +2659,13 @@ CONFIG_GEMINI_ETHERNET=m # CONFIG_NET_VENDOR_EZCHIP is not set # CONFIG_NET_VENDOR_FARADAY is not set CONFIG_NET_VENDOR_GOOGLE=y -# CONFIG_GVE is not set # CONFIG_NET_VENDOR_HISILICON is not set CONFIG_NET_VENDOR_HUAWEI=y # CONFIG_NET_VENDOR_INTEL is not set +CONFIG_NET_VENDOR_MICROSOFT=y # CONFIG_JME is not set +CONFIG_NET_VENDOR_LITEX=y +CONFIG_LITEX_LITEETH=m CONFIG_NET_VENDOR_MARVELL=y CONFIG_MV643XX_ETH=y CONFIG_MVMDIO=y @@ -2653,6 +2728,7 @@ CONFIG_NET_VENDOR_SYNOPSYS=y # CONFIG_NET_VENDOR_VIA is not set # CONFIG_NET_VENDOR_WIZNET is not set CONFIG_NET_VENDOR_XILINX=y +CONFIG_XILINX_EMACLITE=m # CONFIG_XILINX_AXI_EMAC is not set # CONFIG_XILINX_LL_TEMAC is not set # CONFIG_FDDI is not set @@ -2685,11 +2761,16 @@ CONFIG_AX88796B_PHY=m # CONFIG_LSI_ET1011C_PHY is not set CONFIG_MARVELL_PHY=y # CONFIG_MARVELL_10G_PHY is not set +CONFIG_MARVELL_88X2222_PHY=m +CONFIG_MAXLINEAR_GPHY=m +CONFIG_MEDIATEK_GE_PHY=m # CONFIG_MICREL_PHY is not set CONFIG_MICROCHIP_PHY=m # CONFIG_MICROCHIP_T1_PHY is not set # CONFIG_MICROSEMI_PHY is not set +CONFIG_MOTORCOMM_PHY=m CONFIG_NATIONAL_PHY=m +CONFIG_NXP_C45_TJA11XX_PHY=m # CONFIG_NXP_TJA11XX_PHY is not set # CONFIG_AT803X_PHY is not set CONFIG_QSEMI_PHY=m @@ -2707,8 +2788,13 @@ CONFIG_DP83848_PHY=m CONFIG_VITESSE_PHY=m # CONFIG_XILINX_GMII2RGMII is not set # CONFIG_MICREL_KS8995MA is not set + +# +# MCTP Device Drivers +# CONFIG_MDIO_DEVICE=y CONFIG_MDIO_BUS=y +CONFIG_FWNODE_MDIO=y CONFIG_OF_MDIO=y CONFIG_MDIO_DEVRES=y # CONFIG_MDIO_BITBANG is not set @@ -2796,6 +2882,7 @@ CONFIG_USB_SIERRA_NET=m # CONFIG_USB_VL600 is not set # CONFIG_USB_NET_CH9200 is not set CONFIG_USB_NET_AQC111=m +# CONFIG_USB_RTL8153_ECM is not set CONFIG_WLAN=y # CONFIG_WLAN_VENDOR_ADMTEK is not set CONFIG_ATH_COMMON=m @@ -2937,6 +3024,7 @@ CONFIG_MT76_LEDS=y CONFIG_MT76_USB=m CONFIG_MT76x02_LIB=m CONFIG_MT76x02_USB=m +CONFIG_MT76_CONNAC_LIB=m CONFIG_MT76x0_COMMON=m CONFIG_MT76x0U=m CONFIG_MT76x0E=m @@ -2948,6 +3036,7 @@ CONFIG_MT76x2U=m # CONFIG_MT7663U is not set # CONFIG_MT7663S is not set # CONFIG_MT7915E is not set +CONFIG_MT7921E=m CONFIG_WLAN_VENDOR_MICROCHIP=y # CONFIG_WILC1000_SDIO is not set # CONFIG_WILC1000_SPI is not set @@ -3025,7 +3114,7 @@ CONFIG_WLAN_VENDOR_TI=y # CONFIG_WL12XX is not set # CONFIG_WL18XX is not set # CONFIG_WLCORE is not set -CONFIG_RTL8822BS=m +# CONFIG_RTL8822BS is not set CONFIG_RTL8723DU=m CONFIG_RTL8723DS=m CONFIG_RTL8822CS=m @@ -3046,15 +3135,6 @@ CONFIG_QTNFMAC_PCIE=m # CONFIG_MAC80211_HWSIM is not set CONFIG_USB_NET_RNDIS_WLAN=m CONFIG_VIRT_WIFI=m - -# -# WiMAX Wireless Broadband devices -# -CONFIG_WIMAX_I2400M=m -CONFIG_WIMAX_I2400M_USB=m -CONFIG_WIMAX_I2400M_DEBUG_LEVEL=8 -# end of WiMAX Wireless Broadband devices - # CONFIG_WAN is not set CONFIG_IEEE802154_DRIVERS=m CONFIG_IEEE802154_FAKELB=m @@ -3068,12 +3148,20 @@ CONFIG_IEEE802154_CA8210=m # CONFIG_IEEE802154_CA8210_DEBUGFS is not set CONFIG_IEEE802154_MCR20A=m CONFIG_IEEE802154_HWSIM=m + +# +# Wireless WAN +# +CONFIG_WWAN=m +CONFIG_WWAN_HWSIM=m +CONFIG_MHI_WWAN_CTRL=m +CONFIG_MHI_WWAN_MBIM=m +# end of Wireless WAN + # CONFIG_VMXNET3 is not set # CONFIG_NETDEVSIM is not set CONFIG_NET_FAILOVER=m # CONFIG_ISDN is not set -CONFIG_NVM=y -# CONFIG_NVM_PBLK is not set # # Input device support @@ -3081,7 +3169,6 @@ CONFIG_NVM=y CONFIG_INPUT=y CONFIG_INPUT_LEDS=m CONFIG_INPUT_FF_MEMLESS=m -CONFIG_INPUT_POLLDEV=m # CONFIG_INPUT_SPARSEKMAP is not set CONFIG_INPUT_MATRIXKMAP=m @@ -3186,6 +3273,7 @@ CONFIG_JOYSTICK_XPAD_LEDS=y CONFIG_JOYSTICK_WALKERA0701=m # CONFIG_JOYSTICK_PSXPAD_SPI is not set # CONFIG_JOYSTICK_PXRC is not set +CONFIG_JOYSTICK_QWIIC=m # CONFIG_JOYSTICK_FSIA6B is not set # CONFIG_INPUT_TABLET is not set # CONFIG_INPUT_TOUCHSCREEN is not set @@ -3268,7 +3356,6 @@ CONFIG_SERIAL_SIFIVE=m # CONFIG_SERIAL_BCM63XX is not set # CONFIG_SERIAL_ALTERA_JTAGUART is not set # CONFIG_SERIAL_ALTERA_UART is not set -# CONFIG_SERIAL_IFX6X60 is not set # CONFIG_SERIAL_XILINX_PS_UART is not set # CONFIG_SERIAL_ARC is not set # CONFIG_SERIAL_RP2 is not set @@ -3279,22 +3366,19 @@ CONFIG_SERIAL_SIFIVE=m # CONFIG_SERIAL_SPRD is not set CONFIG_SERIAL_MVEBU_UART=y CONFIG_SERIAL_MVEBU_CONSOLE=y +CONFIG_SERIAL_LITEUART=m +CONFIG_SERIAL_LITEUART_MAX_PORTS=1 # end of Serial drivers CONFIG_SERIAL_MCTRL_GPIO=y CONFIG_SERIAL_NONSTANDARD=y -# CONFIG_ROCKETPORT is not set -# CONFIG_CYCLADES is not set # CONFIG_MOXA_INTELLIO is not set # CONFIG_MOXA_SMARTIO is not set -# CONFIG_SYNCLINKMP is not set # CONFIG_SYNCLINK_GT is not set -# CONFIG_ISI is not set # CONFIG_N_HDLC is not set # CONFIG_N_GSM is not set # CONFIG_NOZOMI is not set CONFIG_NULL_TTY=m -# CONFIG_TRACE_SINK is not set CONFIG_HVC_DRIVER=y # CONFIG_HVC_DCC is not set CONFIG_SERIAL_DEV_BUS=y @@ -3314,14 +3398,13 @@ CONFIG_HW_RANDOM_OPTEE=m CONFIG_HW_RANDOM_XIPHERA=m # CONFIG_APPLICOM is not set CONFIG_DEVMEM=y -CONFIG_DEVKMEM=y -# CONFIG_RAW_DRIVER is not set CONFIG_DEVPORT=y # CONFIG_TCG_TPM is not set +CONFIG_XILLYBUS_CLASS=m # CONFIG_XILLYBUS is not set -# end of Character devices - +CONFIG_XILLYUSB=m # CONFIG_RANDOM_TRUST_BOOTLOADER is not set +# end of Character devices # # I2C support @@ -3394,6 +3477,7 @@ CONFIG_I2C_MV64XXX=y # External I2C/SMBus adapter drivers # # CONFIG_I2C_DIOLAN_U2C is not set +CONFIG_I2C_CP2615=m CONFIG_I2C_PARPORT=m # CONFIG_I2C_ROBOTFUZZ_OSIF is not set # CONFIG_I2C_TAOS_EVM is not set @@ -3403,6 +3487,7 @@ CONFIG_I2C_PARPORT=m # Other I2C/SMBus bus drivers # CONFIG_I2C_FSI=m +CONFIG_I2C_VIRTIO=m # end of I2C Hardware Bus support # CONFIG_I2C_STUB is not set @@ -3415,6 +3500,8 @@ CONFIG_I2C_FSI=m CONFIG_I3C=m CONFIG_CDNS_I3C_MASTER=m CONFIG_DW_I3C_MASTER=m +CONFIG_SVC_I3C_MASTER=m +CONFIG_MIPI_I3C_HCI=m CONFIG_SPI=y # CONFIG_SPI_DEBUG is not set CONFIG_SPI_MASTER=y @@ -3485,10 +3572,12 @@ CONFIG_PPS_CLIENT_GPIO=m # PTP clock support # CONFIG_PTP_1588_CLOCK=m +CONFIG_PTP_1588_CLOCK_OPTIONAL=m CONFIG_DP83640_PHY=m # CONFIG_PTP_1588_CLOCK_INES is not set # CONFIG_PTP_1588_CLOCK_IDT82P33 is not set # CONFIG_PTP_1588_CLOCK_IDTCM is not set +CONFIG_PTP_1588_CLOCK_OCP=m # end of PTP clock support CONFIG_PINCTRL=y @@ -3501,6 +3590,7 @@ CONFIG_GENERIC_PINCONF=y # CONFIG_PINCTRL_SX150X is not set CONFIG_PINCTRL_STMFX=m # CONFIG_PINCTRL_OCELOT is not set +# CONFIG_PINCTRL_MICROCHIP_SGPIO is not set CONFIG_PINCTRL_MVEBU=y CONFIG_PINCTRL_DOVE=y CONFIG_PINCTRL_ARMADA_370=y @@ -3520,7 +3610,6 @@ CONFIG_GPIOLIB_FASTPATH_LIMIT=512 CONFIG_OF_GPIO=y CONFIG_GPIOLIB_IRQCHIP=y # CONFIG_DEBUG_GPIO is not set -CONFIG_GPIO_SYSFS=y CONFIG_GPIO_CDEV=y CONFIG_GPIO_CDEV_V1=y CONFIG_GPIO_GENERIC=y @@ -3597,8 +3686,14 @@ CONFIG_GPIO_XRA1403=m # # end of USB GPIO expanders +# +# Virtual GPIO drivers +# # CONFIG_GPIO_AGGREGATOR is not set # CONFIG_GPIO_MOCKUP is not set +CONFIG_GPIO_VIRTIO=m +# end of Virtual GPIO drivers + CONFIG_W1=m # @@ -3637,6 +3732,7 @@ CONFIG_W1_SLAVE_DS28E17=m # end of 1-wire Slaves CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_ATC260X=m # CONFIG_POWER_RESET_BRCMKONA is not set # CONFIG_POWER_RESET_BRCMSTB is not set # CONFIG_POWER_RESET_GPIO is not set @@ -3644,6 +3740,7 @@ CONFIG_POWER_RESET=y # CONFIG_POWER_RESET_LINKSTATION is not set # CONFIG_POWER_RESET_LTC2952 is not set # CONFIG_POWER_RESET_QNAP is not set +# CONFIG_POWER_RESET_REGULATOR is not set # CONFIG_POWER_RESET_RESTART is not set CONFIG_POWER_RESET_VERSATILE=y CONFIG_POWER_RESET_SYSCON=y @@ -3679,6 +3776,7 @@ CONFIG_CHARGER_LP8727=m CONFIG_CHARGER_GPIO=m CONFIG_CHARGER_MANAGER=y CONFIG_CHARGER_LT3651=m +CONFIG_CHARGER_LTC4162L=m CONFIG_CHARGER_DETECTOR_MAX14656=m CONFIG_CHARGER_MAX77650=m CONFIG_CHARGER_BQ2415X=m @@ -3688,8 +3786,10 @@ CONFIG_CHARGER_BQ24735=m # CONFIG_CHARGER_BQ2515X is not set CONFIG_CHARGER_BQ25890=m CONFIG_CHARGER_BQ25980=m +CONFIG_CHARGER_BQ256XX=m CONFIG_CHARGER_SMB347=m CONFIG_BATTERY_GAUGE_LTC2941=m +CONFIG_BATTERY_GOLDFISH=m CONFIG_BATTERY_RT5033=m CONFIG_CHARGER_RT9455=m CONFIG_CHARGER_UCS1002=m @@ -3718,12 +3818,16 @@ CONFIG_SENSORS_ADT7411=m CONFIG_SENSORS_ADT7462=m CONFIG_SENSORS_ADT7470=m CONFIG_SENSORS_ADT7475=m +CONFIG_SENSORS_AHT10=m +CONFIG_SENSORS_AQUACOMPUTER_D5NEXT=m CONFIG_SENSORS_AS370=m CONFIG_SENSORS_ASC7621=m # CONFIG_SENSORS_AXI_FAN_CONTROL is not set +CONFIG_SENSORS_ARM_SCMI=m CONFIG_SENSORS_ASPEED=m CONFIG_SENSORS_ATXP1=m # CONFIG_SENSORS_CORSAIR_CPRO is not set +CONFIG_SENSORS_CORSAIR_PSU=m # CONFIG_SENSORS_DRIVETEMP is not set CONFIG_SENSORS_DS620=m CONFIG_SENSORS_DS1621=m @@ -3747,6 +3851,7 @@ CONFIG_SENSORS_LTC2945=m # CONFIG_SENSORS_LTC2947_I2C is not set # CONFIG_SENSORS_LTC2947_SPI is not set CONFIG_SENSORS_LTC2990=m +CONFIG_SENSORS_LTC2992=m CONFIG_SENSORS_LTC4151=m CONFIG_SENSORS_LTC4215=m CONFIG_SENSORS_LTC4222=m @@ -3754,6 +3859,7 @@ CONFIG_SENSORS_LTC4245=m CONFIG_SENSORS_LTC4260=m CONFIG_SENSORS_LTC4261=m CONFIG_SENSORS_MAX1111=m +CONFIG_SENSORS_MAX127=m CONFIG_SENSORS_MAX16065=m CONFIG_SENSORS_MAX1619=m CONFIG_SENSORS_MAX1668=m @@ -3768,6 +3874,7 @@ CONFIG_SENSORS_MAX6697=m CONFIG_SENSORS_MAX31790=m CONFIG_SENSORS_MCP3021=m CONFIG_SENSORS_TC654=m +CONFIG_SENSORS_TPS23861=m CONFIG_SENSORS_MR75203=m CONFIG_SENSORS_ADCXX=m CONFIG_SENSORS_LM63=m @@ -3794,6 +3901,7 @@ CONFIG_SENSORS_NCT6775=m CONFIG_SENSORS_NCT7802=m CONFIG_SENSORS_NCT7904=m CONFIG_SENSORS_NPCM7XX=m +CONFIG_SENSORS_NZXT_KRAKEN2=m CONFIG_SENSORS_OCC_P8_I2C=m CONFIG_SENSORS_OCC=m CONFIG_SENSORS_PCF8591=m @@ -3802,15 +3910,20 @@ CONFIG_SENSORS_PMBUS=m CONFIG_SENSORS_ADM1266=m CONFIG_SENSORS_ADM1275=m # CONFIG_SENSORS_BEL_PFE is not set +CONFIG_SENSORS_BPA_RS600=m +CONFIG_SENSORS_FSP_3Y=m CONFIG_SENSORS_IBM_CFFPS=m +CONFIG_SENSORS_DPS920AB=m CONFIG_SENSORS_INSPUR_IPSPS=m CONFIG_SENSORS_IR35221=m +CONFIG_SENSORS_IR36021=m CONFIG_SENSORS_IR38064=m # CONFIG_SENSORS_IRPS5401 is not set CONFIG_SENSORS_ISL68137=m CONFIG_SENSORS_LM25066=m # CONFIG_SENSORS_LTC2978 is not set CONFIG_SENSORS_LTC3815=m +CONFIG_SENSORS_MAX15301=m CONFIG_SENSORS_MAX16064=m # CONFIG_SENSORS_MAX16601 is not set # CONFIG_SENSORS_MAX20730 is not set @@ -3818,8 +3931,13 @@ CONFIG_SENSORS_MAX20751=m CONFIG_SENSORS_MAX31785=m CONFIG_SENSORS_MAX34440=m CONFIG_SENSORS_MAX8688=m +CONFIG_SENSORS_MP2888=m CONFIG_SENSORS_MP2975=m +CONFIG_SENSORS_PIM4328=m +CONFIG_SENSORS_PM6764TR=m CONFIG_SENSORS_PXE1610=m +CONFIG_SENSORS_Q54SJ108A2=m +CONFIG_SENSORS_STPDDC60=m CONFIG_SENSORS_TPS40422=m CONFIG_SENSORS_TPS53679=m CONFIG_SENSORS_UCD9000=m @@ -3827,9 +3945,12 @@ CONFIG_SENSORS_UCD9200=m # CONFIG_SENSORS_XDPE122 is not set CONFIG_SENSORS_ZL6100=m CONFIG_SENSORS_PWM_FAN=m +CONFIG_SENSORS_SBTSI=m +CONFIG_SENSORS_SBRMI=m CONFIG_SENSORS_SHT15=m CONFIG_SENSORS_SHT21=m CONFIG_SENSORS_SHT3x=m +CONFIG_SENSORS_SHT4x=m CONFIG_SENSORS_SHTC1=m CONFIG_SENSORS_SIS5595=m CONFIG_SENSORS_DME1737=m @@ -3900,6 +4021,7 @@ CONFIG_WATCHDOG_CORE=y CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y CONFIG_WATCHDOG_OPEN_TIMEOUT=0 # CONFIG_WATCHDOG_SYSFS is not set +# CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT is not set # # Watchdog Pretimeout Governors @@ -3916,6 +4038,7 @@ CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_NOOP=y # CONFIG_SOFT_WATCHDOG=m # CONFIG_SOFT_WATCHDOG_PRETIMEOUT is not set +CONFIG_BD957XMUF_WATCHDOG=m # CONFIG_GPIO_WATCHDOG is not set # CONFIG_XILINX_WATCHDOG is not set # CONFIG_ZIIRAVE_WATCHDOG is not set @@ -3997,6 +4120,7 @@ CONFIG_MFD_CORE=m # CONFIG_HTC_I2CPLD is not set # CONFIG_LPC_ICH is not set # CONFIG_LPC_SCH is not set +CONFIG_MFD_INTEL_PMT=m # CONFIG_MFD_IQS62X is not set # CONFIG_MFD_JANZ_CMODIO is not set # CONFIG_MFD_KEMPLD is not set @@ -4019,10 +4143,12 @@ CONFIG_MFD_MAX77650=m # CONFIG_EZX_PCAP is not set # CONFIG_MFD_CPCAP is not set # CONFIG_MFD_VIPERBOARD is not set +CONFIG_MFD_NTXEC=m # CONFIG_MFD_RETU is not set # CONFIG_MFD_PCF50633 is not set # CONFIG_MFD_PM8XXX is not set # CONFIG_MFD_RDC321X is not set +CONFIG_MFD_RT4831=m # CONFIG_MFD_RT5033 is not set # CONFIG_MFD_RC5T583 is not set # CONFIG_MFD_RK808 is not set @@ -4031,7 +4157,6 @@ CONFIG_MFD_MAX77650=m # CONFIG_MFD_SI476X_CORE is not set # CONFIG_MFD_SM501 is not set # CONFIG_MFD_SKY81452 is not set -# CONFIG_ABX500_CORE is not set # CONFIG_MFD_STMPE is not set CONFIG_MFD_SYSCON=y # CONFIG_MFD_TI_AM335X_TSCADC is not set @@ -4074,10 +4199,16 @@ CONFIG_MFD_TQMX86=m CONFIG_MFD_ROHM_BD718XX=m # CONFIG_MFD_ROHM_BD70528 is not set # CONFIG_MFD_ROHM_BD71828 is not set +CONFIG_MFD_ROHM_BD957XMUF=m CONFIG_MFD_STPMIC1=m CONFIG_MFD_STMFX=m +CONFIG_MFD_ATC260X=m +CONFIG_MFD_ATC260X_I2C=m +CONFIG_MFD_QCOM_PM8008=m # CONFIG_RAVE_SP_CORE is not set CONFIG_MFD_INTEL_M10_BMC=m +CONFIG_MFD_RSMU_I2C=m +CONFIG_MFD_RSMU_SPI=m # end of Multifunction device drivers CONFIG_REGULATOR=y @@ -4088,7 +4219,11 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_88PG86X=m CONFIG_REGULATOR_ACT8865=m # CONFIG_REGULATOR_AD5398 is not set +CONFIG_REGULATOR_ARM_SCMI=m +CONFIG_REGULATOR_ATC260X=m CONFIG_REGULATOR_BD718XX=m +CONFIG_REGULATOR_BD957XMUF=m +CONFIG_REGULATOR_DA9121=m # CONFIG_REGULATOR_DA9210 is not set # CONFIG_REGULATOR_DA9211 is not set # CONFIG_REGULATOR_FAN53555 is not set @@ -4106,6 +4241,7 @@ CONFIG_REGULATOR_GPIO=m CONFIG_REGULATOR_MAX77650=m # CONFIG_REGULATOR_MAX8649 is not set # CONFIG_REGULATOR_MAX8660 is not set +CONFIG_REGULATOR_MAX8893=m # CONFIG_REGULATOR_MAX8952 is not set # CONFIG_REGULATOR_MAX8973 is not set # CONFIG_REGULATOR_MAX77826 is not set @@ -4116,6 +4252,7 @@ CONFIG_REGULATOR_MCP16502=m # CONFIG_REGULATOR_MPQ7920 is not set # CONFIG_REGULATOR_MT6311 is not set # CONFIG_REGULATOR_PCA9450 is not set +CONFIG_REGULATOR_PF8X00=m # CONFIG_REGULATOR_PFUZE100 is not set # CONFIG_REGULATOR_PV88060 is not set # CONFIG_REGULATOR_PV88080 is not set @@ -4124,7 +4261,12 @@ CONFIG_REGULATOR_MCP16502=m CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY=m CONFIG_REGULATOR_ROHM=m CONFIG_REGULATOR_RT4801=m +CONFIG_REGULATOR_RT4831=m +CONFIG_REGULATOR_RT6160=m +CONFIG_REGULATOR_RT6245=m +CONFIG_REGULATOR_RTQ2134=m CONFIG_REGULATOR_RTMV20=m +CONFIG_REGULATOR_RTQ6752=m # CONFIG_REGULATOR_SLG51000 is not set CONFIG_REGULATOR_STPMIC1=m # CONFIG_REGULATOR_SY8106A is not set @@ -4167,11 +4309,12 @@ CONFIG_DVB_CORE=m # CONFIG_VIDEO_V4L2=m CONFIG_VIDEO_V4L2_I2C=y -# CONFIG_VIDEO_V4L2_SUBDEV_API is not set +CONFIG_VIDEO_V4L2_SUBDEV_API=y # CONFIG_VIDEO_ADV_DEBUG is not set # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set CONFIG_VIDEO_TUNER=m CONFIG_V4L2_FWNODE=m +CONFIG_V4L2_ASYNC=m CONFIG_VIDEOBUF_GEN=m CONFIG_VIDEOBUF_VMALLOC=m # end of Video4Linux options @@ -4380,14 +4523,20 @@ CONFIG_VIDEO_CX25840=m # # Camera sensor devices # +CONFIG_VIDEO_CCS_PLL=m # CONFIG_VIDEO_HI556 is not set +CONFIG_VIDEO_IMX208=m # CONFIG_VIDEO_IMX214 is not set # CONFIG_VIDEO_IMX219 is not set # CONFIG_VIDEO_IMX258 is not set # CONFIG_VIDEO_IMX274 is not set # CONFIG_VIDEO_IMX290 is not set # CONFIG_VIDEO_IMX319 is not set +CONFIG_VIDEO_IMX334=m +CONFIG_VIDEO_IMX335=m # CONFIG_VIDEO_IMX355 is not set +CONFIG_VIDEO_IMX412=m +CONFIG_VIDEO_OV02A10=m CONFIG_VIDEO_OV2640=m # CONFIG_VIDEO_OV2659 is not set # CONFIG_VIDEO_OV2680 is not set @@ -4395,6 +4544,7 @@ CONFIG_VIDEO_OV2640=m # CONFIG_VIDEO_OV5640 is not set # CONFIG_VIDEO_OV5645 is not set # CONFIG_VIDEO_OV5647 is not set +CONFIG_VIDEO_OV5648=m # CONFIG_VIDEO_OV6650 is not set # CONFIG_VIDEO_OV5670 is not set # CONFIG_VIDEO_OV5675 is not set @@ -4405,6 +4555,8 @@ CONFIG_VIDEO_OV7640=m # CONFIG_VIDEO_OV7670 is not set # CONFIG_VIDEO_OV7740 is not set # CONFIG_VIDEO_OV8856 is not set +CONFIG_VIDEO_OV8865=m +CONFIG_VIDEO_OV9282=m # CONFIG_VIDEO_OV9640 is not set # CONFIG_VIDEO_OV9650 is not set # CONFIG_VIDEO_OV13858 is not set @@ -4421,13 +4573,15 @@ CONFIG_VIDEO_MT9V011=m # CONFIG_VIDEO_SR030PC30 is not set # CONFIG_VIDEO_NOON010PC30 is not set # CONFIG_VIDEO_M5MOLS is not set +CONFIG_VIDEO_MAX9271_LIB=m # CONFIG_VIDEO_RDACM20 is not set +CONFIG_VIDEO_RDACM21=m # CONFIG_VIDEO_RJ54N1 is not set # CONFIG_VIDEO_S5K6AA is not set # CONFIG_VIDEO_S5K6A3 is not set # CONFIG_VIDEO_S5K4ECGX is not set # CONFIG_VIDEO_S5K5BAF is not set -# CONFIG_VIDEO_SMIAPP is not set +CONFIG_VIDEO_CCS=m # CONFIG_VIDEO_ET8EK8 is not set # CONFIG_VIDEO_S5C73M3 is not set # end of Camera sensor devices @@ -4557,6 +4711,7 @@ CONFIG_DVB_AU8522=m CONFIG_DVB_AU8522_DTV=m CONFIG_DVB_AU8522_V4L=m CONFIG_DVB_S5H1411=m +CONFIG_DVB_MXL692=m # # ISDB-T (terrestrial) frontends @@ -4627,6 +4782,7 @@ CONFIG_BACKLIGHT_CLASS_DEVICE=m CONFIG_BACKLIGHT_KTD253=m CONFIG_BACKLIGHT_PWM=m # CONFIG_BACKLIGHT_QCOM_WLED is not set +CONFIG_BACKLIGHT_RT4831=m CONFIG_BACKLIGHT_ADP8860=m CONFIG_BACKLIGHT_ADP8870=m CONFIG_BACKLIGHT_LM3630A=m @@ -4653,6 +4809,8 @@ CONFIG_SND_PCM=m CONFIG_SND_HWDEP=m CONFIG_SND_SEQ_DEVICE=m CONFIG_SND_RAWMIDI=m +CONFIG_SND_JACK=y +CONFIG_SND_JACK_INPUT_DEV=y # CONFIG_SND_OSSEMUL is not set CONFIG_SND_PCM_TIMER=y # CONFIG_SND_HRTIMER is not set @@ -4699,6 +4857,7 @@ CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y # CONFIG_SND_USB_TONEPORT is not set # CONFIG_SND_USB_VARIAX is not set # CONFIG_SND_SOC is not set +CONFIG_SND_VIRTIO=m # # HID support @@ -4738,6 +4897,7 @@ CONFIG_HID_MACALLY=m # CONFIG_HID_ELECOM is not set # CONFIG_HID_ELO is not set # CONFIG_HID_EZKEY is not set +CONFIG_HID_FT260=m # CONFIG_HID_GEMBIRD is not set # CONFIG_HID_GFRM is not set # CONFIG_HID_GLORIOUS is not set @@ -4774,11 +4934,14 @@ CONFIG_HID_REDRAGON=y # CONFIG_HID_PETALYNX is not set # CONFIG_HID_PICOLCD is not set # CONFIG_HID_PLANTRONICS is not set +CONFIG_HID_PLAYSTATION=m +# CONFIG_PLAYSTATION_FF is not set # CONFIG_HID_PRIMAX is not set # CONFIG_HID_RETRODE is not set CONFIG_HID_ROCCAT=m CONFIG_HID_SAITEK=m CONFIG_HID_SAMSUNG=m +CONFIG_HID_SEMITEK=m CONFIG_HID_SONY=m CONFIG_SONY_FF=y CONFIG_HID_SPEEDLINK=m @@ -4815,8 +4978,11 @@ CONFIG_USB_HIDDEV=y # # I2C HID support # -CONFIG_I2C_HID=m +CONFIG_I2C_HID_OF=m +CONFIG_I2C_HID_OF_GOODIX=m # end of I2C HID support + +CONFIG_I2C_HID_CORE=m # end of HID support CONFIG_USB_OHCI_LITTLE_ENDIAN=y @@ -4917,6 +5083,7 @@ CONFIG_USBIP_CORE=m # CONFIG_USBIP_VHCI_HCD is not set # CONFIG_USBIP_HOST is not set # CONFIG_USBIP_DEBUG is not set +CONFIG_USB_CDNS_SUPPORT=m # CONFIG_USB_CDNS3 is not set # CONFIG_USB_MUSB_HDRC is not set # CONFIG_USB_DWC3 is not set @@ -4973,7 +5140,6 @@ CONFIG_USB_SERIAL_SIERRAWIRELESS=m CONFIG_USB_SERIAL_SYMBOL=m CONFIG_USB_SERIAL_TI=m CONFIG_USB_SERIAL_CYBERJACK=m -CONFIG_USB_SERIAL_XIRCOM=m CONFIG_USB_SERIAL_WWAN=m CONFIG_USB_SERIAL_OPTION=m CONFIG_USB_SERIAL_OMNINET=m @@ -4983,6 +5149,7 @@ CONFIG_USB_SERIAL_WISHBONE=m CONFIG_USB_SERIAL_SSU100=m CONFIG_USB_SERIAL_QT2=m CONFIG_USB_SERIAL_UPD78F0730=m +CONFIG_USB_SERIAL_XR=m CONFIG_USB_SERIAL_DEBUG=m # @@ -5131,6 +5298,10 @@ CONFIG_LEDS_SPI_BYTE=m CONFIG_LEDS_TI_LMU_COMMON=m CONFIG_LEDS_LM3697=m +# +# Flash and Torch LED drivers +# + # # LED Triggers # @@ -5155,6 +5326,7 @@ CONFIG_LEDS_TRIGGER_PANIC=y CONFIG_LEDS_TRIGGER_NETDEV=m CONFIG_LEDS_TRIGGER_PATTERN=m CONFIG_LEDS_TRIGGER_AUDIO=m +CONFIG_LEDS_TRIGGER_TTY=m # CONFIG_ACCESSIBILITY is not set # CONFIG_INFINIBAND is not set CONFIG_EDAC_ATOMIC_SCRUB=y @@ -5228,7 +5400,6 @@ CONFIG_RTC_DRV_DS1302=m # CONFIG_RTC_DRV_MAX6916 is not set # CONFIG_RTC_DRV_R9701 is not set # CONFIG_RTC_DRV_RX4581 is not set -CONFIG_RTC_DRV_RX6110=m # CONFIG_RTC_DRV_RS5C348 is not set # CONFIG_RTC_DRV_MAX6902 is not set # CONFIG_RTC_DRV_PCF2123 is not set @@ -5241,6 +5412,7 @@ CONFIG_RTC_I2C_AND_SPI=y # CONFIG_RTC_DRV_DS3232 is not set # CONFIG_RTC_DRV_PCF2127 is not set # CONFIG_RTC_DRV_RV3029C2 is not set +CONFIG_RTC_DRV_RX6110=m # # Platform RTC drivers @@ -5261,6 +5433,7 @@ CONFIG_RTC_I2C_AND_SPI=y # CONFIG_RTC_DRV_RP5C01 is not set # CONFIG_RTC_DRV_V3020 is not set # CONFIG_RTC_DRV_ZYNQMP is not set +CONFIG_RTC_DRV_NTXEC=m # # on-CPU RTC drivers @@ -5274,6 +5447,7 @@ CONFIG_RTC_DRV_FTRTC010=m # # HID Sensor RTC drivers # +CONFIG_RTC_DRV_GOLDFISH=m CONFIG_DMADEVICES=y # CONFIG_DMADEVICES_DEBUG is not set @@ -5314,13 +5488,18 @@ CONFIG_DMA_ENGINE_RAID=y # CONFIG_SYNC_FILE is not set # CONFIG_UDMABUF is not set # CONFIG_DMABUF_MOVE_NOTIFY is not set +# CONFIG_DMABUF_DEBUG is not set # CONFIG_DMABUF_SELFTESTS is not set # CONFIG_DMABUF_HEAPS is not set +# CONFIG_DMABUF_SYSFS_STATS is not set # end of DMABUF options CONFIG_AUXDISPLAY=y +CONFIG_CHARLCD=m +CONFIG_HD44780_COMMON=m CONFIG_HD44780=m CONFIG_IMG_ASCII_LCD=m +CONFIG_LCD2S=m CONFIG_PARPORT_PANEL=m CONFIG_PANEL_PARPORT=0 CONFIG_PANEL_PROFILE=5 @@ -5329,15 +5508,20 @@ CONFIG_PANEL_PROFILE=5 # CONFIG_CHARLCD_BL_ON is not set CONFIG_CHARLCD_BL_FLASH=y CONFIG_PANEL=m -CONFIG_CHARLCD=m # CONFIG_UIO is not set -CONFIG_VFIO_IOMMU_TYPE1=m CONFIG_VFIO=m +CONFIG_VFIO_IOMMU_TYPE1=m +CONFIG_VFIO_VIRQFD=m # CONFIG_VFIO_NOIOMMU is not set -# CONFIG_VFIO_PCI is not set -# CONFIG_VFIO_PLATFORM is not set +CONFIG_VFIO_PCI_CORE=m +CONFIG_VFIO_PCI_MMAP=y +CONFIG_VFIO_PCI_INTX=y +CONFIG_VFIO_PCI=m +CONFIG_VFIO_PLATFORM=m +CONFIG_VFIO_PLATFORM_CALXEDAXGMAC_RESET=m +CONFIG_VFIO_PLATFORM_AMDXGBE_RESET=m CONFIG_VFIO_MDEV=m -CONFIG_VFIO_MDEV_DEVICE=m +CONFIG_IRQ_BYPASS_MANAGER=m # CONFIG_VIRT_DRIVERS is not set CONFIG_VIRTIO=m CONFIG_VIRTIO_MENU=y @@ -5360,9 +5544,9 @@ CONFIG_VHOST_VSOCK=m # end of Microsoft Hyper-V guest support # CONFIG_GREYBUS is not set +# CONFIG_COMEDI is not set CONFIG_STAGING=y # CONFIG_PRISM2_USB is not set -# CONFIG_COMEDI is not set CONFIG_RTL8192U=m CONFIG_RTLLIB=m CONFIG_RTLLIB_CRYPTO_CCMP=m @@ -5404,7 +5588,6 @@ CONFIG_88EU_AP_MODE=y # # Capacitance to digital converters # -# CONFIG_AD7150 is not set # CONFIG_AD7746 is not set # end of Capacitance to digital converters @@ -5449,12 +5632,6 @@ CONFIG_COMMON_CLK_XLNX_CLKWZRD=m # CONFIG_MOST_COMPONENTS is not set # CONFIG_KS7010 is not set # CONFIG_PI433 is not set - -# -# Gasket devices -# -# end of Gasket devices - CONFIG_XIL_AXIS_FIFO=m CONFIG_FIELDBUS_DEV=m CONFIG_HMS_ANYBUSS_BUS=m @@ -5466,10 +5643,19 @@ CONFIG_HMS_PROFINET=m # CONFIG_CHROME_PLATFORMS is not set # CONFIG_MELLANOX_PLATFORM is not set CONFIG_HAVE_CLK=y -CONFIG_CLKDEV_LOOKUP=y CONFIG_HAVE_CLK_PREPARE=y CONFIG_COMMON_CLK=y + +# +# Clock driver for ARM Reference designs +# +# CONFIG_ICST is not set +# CONFIG_CLK_SP810 is not set +# end of Clock driver for ARM Reference designs + +CONFIG_LMK04832=m CONFIG_COMMON_CLK_MAX9485=m +CONFIG_COMMON_CLK_SCMI=m # CONFIG_COMMON_CLK_SI5341 is not set # CONFIG_COMMON_CLK_SI5351 is not set # CONFIG_COMMON_CLK_SI514 is not set @@ -5478,7 +5664,7 @@ CONFIG_COMMON_CLK_MAX9485=m # CONFIG_COMMON_CLK_CDCE706 is not set # CONFIG_COMMON_CLK_CDCE925 is not set # CONFIG_COMMON_CLK_CS2000_CP is not set -CONFIG_CLK_QORIQ=y +CONFIG_COMMON_CLK_AXI_CLKGEN=m # CONFIG_COMMON_CLK_PWM is not set # CONFIG_COMMON_CLK_VC5 is not set CONFIG_COMMON_CLK_BD718XX=m @@ -5494,6 +5680,7 @@ CONFIG_ARMADA_39X_CLK=y CONFIG_ARMADA_XP_CLK=y CONFIG_ARMADA_AP_CPU_CLK=y CONFIG_DOVE_CLK=y +# CONFIG_XILINX_VCU is not set # CONFIG_HWSPINLOCK is not set # @@ -5505,6 +5692,7 @@ CONFIG_CLKSRC_MMIO=y CONFIG_ARMADA_370_XP_TIMER=y CONFIG_ORION_TIMER=y CONFIG_ARM_GLOBAL_TIMER=y +CONFIG_ARM_GT_INITIAL_PRESCALER_VAL=1 CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK=y # CONFIG_MICROCHIP_PIT64B is not set # end of Clock Source drivers @@ -5536,11 +5724,6 @@ CONFIG_IOMMU_API=y # # end of Amlogic SoC drivers -# -# Aspeed SoC drivers -# -# end of Aspeed SoC drivers - # # Broadcom SoC drivers # @@ -5559,6 +5742,13 @@ CONFIG_SOC_BRCMSTB=y # # end of i.MX SoC drivers +# +# Enable LiteX SoC Builder specific drivers +# +CONFIG_LITEX=y +CONFIG_LITEX_SOC_CONTROLLER=m +# end of Enable LiteX SoC Builder specific drivers + # # Qualcomm SoC drivers # @@ -5570,7 +5760,6 @@ CONFIG_QCOM_QMI_HELPERS=m # # Xilinx SoC drivers # -# CONFIG_XILINX_VCU is not set # end of Xilinx SoC drivers # end of SOC (System On Chip) specific Drivers @@ -5588,6 +5777,7 @@ CONFIG_EXTCON_PTN5150=m # CONFIG_EXTCON_RT8973A is not set # CONFIG_EXTCON_SM5502 is not set CONFIG_EXTCON_USB_GPIO=m +CONFIG_EXTCON_USBC_TUSB320=m CONFIG_MEMORY=y CONFIG_MVEBU_DEVBUS=y CONFIG_IIO=m @@ -5622,11 +5812,16 @@ CONFIG_BMA220=m CONFIG_BMC150_ACCEL=m CONFIG_BMC150_ACCEL_I2C=m CONFIG_BMC150_ACCEL_SPI=m +CONFIG_BMI088_ACCEL=m +CONFIG_BMI088_ACCEL_SPI=m CONFIG_DA280=m CONFIG_DA311=m CONFIG_DMARD06=m CONFIG_DMARD09=m CONFIG_DMARD10=m +CONFIG_FXLS8962AF=m +CONFIG_FXLS8962AF_I2C=m +CONFIG_FXLS8962AF_SPI=m CONFIG_IIO_ST_ACCEL_3AXIS=m CONFIG_IIO_ST_ACCEL_I2C_3AXIS=m CONFIG_IIO_ST_ACCEL_SPI_3AXIS=m @@ -5646,6 +5841,7 @@ CONFIG_MMA9553=m CONFIG_MXC4005=m CONFIG_MXC6255=m CONFIG_SCA3000=m +CONFIG_SCA3300=m CONFIG_STK8312=m CONFIG_STK8BA50=m # end of Accelerometers @@ -5707,7 +5903,9 @@ CONFIG_TI_ADS7950=m CONFIG_TI_ADS8344=m CONFIG_TI_ADS8688=m CONFIG_TI_ADS124S08=m +CONFIG_TI_ADS131E08=m CONFIG_TI_TLC4541=m +CONFIG_TI_TSC2046=m # CONFIG_VF610_ADC is not set CONFIG_XILINX_XADC=m # end of Analog to digital converters @@ -5725,6 +5923,12 @@ CONFIG_XILINX_XADC=m # CONFIG_HMC425 is not set # end of Amplifiers +# +# Capacitance to digital converters +# +# CONFIG_AD7150 is not set +# end of Capacitance to digital converters + # # Chemical Sensors # @@ -5738,7 +5942,10 @@ CONFIG_BME680_SPI=m CONFIG_PMS7003=m # CONFIG_SCD30_CORE is not set CONFIG_SENSIRION_SGP30=m +CONFIG_SENSIRION_SGP40=m CONFIG_SPS30=m +CONFIG_SPS30_I2C=m +CONFIG_SPS30_SERIAL=m # CONFIG_VZ89X is not set # end of Chemical Sensors @@ -5749,6 +5956,12 @@ CONFIG_SPS30=m CONFIG_IIO_MS_SENSORS_I2C=m +# +# IIO SCMI Sensors +# +CONFIG_IIO_SCMI=m +# end of IIO SCMI Sensors + # # SSP Sensor Common # @@ -5779,6 +5992,7 @@ CONFIG_AD5696_I2C=m CONFIG_AD5758=m # CONFIG_AD5761 is not set # CONFIG_AD5764 is not set +CONFIG_AD5766=m # CONFIG_AD5770R is not set # CONFIG_AD5791 is not set # CONFIG_AD7303 is not set @@ -5884,6 +6098,9 @@ CONFIG_SI7020=m # CONFIG_INV_MPU6050_I2C is not set # CONFIG_INV_MPU6050_SPI is not set # CONFIG_IIO_ST_LSM6DSX is not set +CONFIG_IIO_ST_LSM9DS0=m +CONFIG_IIO_ST_LSM9DS0_I2C=m +CONFIG_IIO_ST_LSM9DS0_SPI=m # end of Inertial measurement units CONFIG_IIO_ADIS_LIB=m @@ -5930,6 +6147,7 @@ CONFIG_TCS3414=m CONFIG_TCS3472=m CONFIG_SENSORS_TSL2563=m CONFIG_TSL2583=m +CONFIG_TSL2591=m CONFIG_TSL2772=m CONFIG_TSL4531=m CONFIG_US5182D=m @@ -5961,6 +6179,7 @@ CONFIG_SENSORS_HMC5843_SPI=m CONFIG_SENSORS_RM3100=m CONFIG_SENSORS_RM3100_I2C=m CONFIG_SENSORS_RM3100_SPI=m +CONFIG_YAMAHA_YAS530=m # end of Magnetometer sensors # @@ -5989,6 +6208,7 @@ CONFIG_IIO_SYSFS_TRIGGER=m # # Digital potentiometers # +CONFIG_AD5110=m # CONFIG_AD5272 is not set # CONFIG_DS1803 is not set CONFIG_MAX5432=m @@ -6067,6 +6287,7 @@ CONFIG_MLX90614=m CONFIG_MLX90632=m CONFIG_TMP006=m CONFIG_TMP007=m +CONFIG_TMP117=m # CONFIG_TSYS01 is not set # CONFIG_TSYS02D is not set # CONFIG_MAX31856 is not set @@ -6077,7 +6298,10 @@ CONFIG_TMP007=m CONFIG_PWM=y CONFIG_PWM_SYSFS=y # CONFIG_PWM_DEBUG is not set +CONFIG_PWM_ATMEL_TCB=m +CONFIG_PWM_DWC=m # CONFIG_PWM_FSL_FTM is not set +CONFIG_PWM_NTXEC=m # CONFIG_PWM_PCA9685 is not set # @@ -6099,6 +6323,7 @@ CONFIG_ORION_IRQCHIP=y # CONFIG_GENERIC_PHY=y CONFIG_GENERIC_PHY_MIPI_DPHY=y +CONFIG_PHY_CAN_TRANSCEIVER=m # CONFIG_BCM_KONA_USB2_PHY is not set # CONFIG_PHY_CADENCE_TORRENT is not set # CONFIG_PHY_CADENCE_DPHY is not set @@ -6110,6 +6335,7 @@ CONFIG_PHY_MVEBU_A3700_COMPHY=m CONFIG_PHY_MVEBU_A3700_UTMI=m CONFIG_PHY_MVEBU_A38X_COMPHY=y CONFIG_PHY_MVEBU_CP110_COMPHY=m +CONFIG_PHY_MVEBU_CP110_UTMI=m CONFIG_PHY_MVEBU_SATA=y CONFIG_PHY_PXA_28NM_HSIC=m CONFIG_PHY_PXA_28NM_USB2=m @@ -6143,6 +6369,7 @@ CONFIG_RAS=y CONFIG_DAX=m CONFIG_NVMEM=y CONFIG_NVMEM_SYSFS=y +CONFIG_NVMEM_RMEM=m # # HW tracing support @@ -6189,11 +6416,14 @@ CONFIG_PM_OPP=y # CONFIG_SLIMBUS is not set # CONFIG_INTERCONNECT is not set CONFIG_COUNTER=m +CONFIG_INTERRUPT_CNT=m CONFIG_FTM_QUADDEC=m # CONFIG_MICROCHIP_TCB_CAPTURE is not set +CONFIG_INTEL_QEP=m CONFIG_MOST=m # CONFIG_MOST_USB_HDM is not set CONFIG_MOST_CDEV=m +CONFIG_MOST_SND=m # end of Device Drivers # @@ -6259,12 +6489,12 @@ CONFIG_F2FS_FS_SECURITY=y CONFIG_F2FS_CHECK_FS=y # CONFIG_F2FS_FAULT_INJECTION is not set # CONFIG_F2FS_FS_COMPRESSION is not set +CONFIG_F2FS_IOSTAT=y # CONFIG_ZONEFS_FS is not set CONFIG_FS_POSIX_ACL=y CONFIG_EXPORTFS=y CONFIG_EXPORTFS_BLOCK_OPS=y CONFIG_FILE_LOCKING=y -CONFIG_MANDATORY_FILE_LOCKING=y CONFIG_FS_ENCRYPTION=y CONFIG_FS_ENCRYPTION_ALGS=y CONFIG_FS_VERITY=y @@ -6297,14 +6527,13 @@ CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y # # Caches # +CONFIG_NETFS_SUPPORT=m +CONFIG_NETFS_STATS=y CONFIG_FSCACHE=m CONFIG_FSCACHE_STATS=y -# CONFIG_FSCACHE_HISTOGRAM is not set # CONFIG_FSCACHE_DEBUG is not set -# CONFIG_FSCACHE_OBJECT_LIST is not set CONFIG_CACHEFILES=m # CONFIG_CACHEFILES_DEBUG is not set -# CONFIG_CACHEFILES_HISTOGRAM is not set # end of Caches # @@ -6327,9 +6556,10 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" CONFIG_FAT_DEFAULT_UTF8=y CONFIG_EXFAT_FS=m CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8" -CONFIG_NTFS_FS=m -# CONFIG_NTFS_DEBUG is not set -CONFIG_NTFS_RW=y +# CONFIG_NTFS_FS is not set +CONFIG_NTFS3_FS=m +CONFIG_NTFS3_LZX_XPRESS=y +CONFIG_NTFS3_FS_POSIX_ACL=y # end of DOS/FAT/EXFAT/NT Filesystems # @@ -6409,6 +6639,7 @@ CONFIG_ROMFS_BACKED_BY_BLOCK=y # CONFIG_ROMFS_BACKED_BY_BOTH is not set CONFIG_ROMFS_ON_BLOCK=y CONFIG_PSTORE=y +CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240 CONFIG_PSTORE_DEFLATE_COMPRESS=y CONFIG_PSTORE_LZO_COMPRESS=m CONFIG_PSTORE_LZ4_COMPRESS=m @@ -6435,24 +6666,6 @@ CONFIG_EROFS_FS_XATTR=y CONFIG_EROFS_FS_POSIX_ACL=y CONFIG_EROFS_FS_SECURITY=y # CONFIG_EROFS_FS_ZIP is not set -CONFIG_AUFS_FS=m -CONFIG_AUFS_BRANCH_MAX_127=y -# CONFIG_AUFS_BRANCH_MAX_511 is not set -# CONFIG_AUFS_BRANCH_MAX_1023 is not set -# CONFIG_AUFS_BRANCH_MAX_32767 is not set -CONFIG_AUFS_SBILIST=y -# CONFIG_AUFS_HNOTIFY is not set -# CONFIG_AUFS_EXPORT is not set -# CONFIG_AUFS_XATTR is not set -# CONFIG_AUFS_FHSM is not set -# CONFIG_AUFS_RDU is not set -# CONFIG_AUFS_DIRREN is not set -# CONFIG_AUFS_SHWH is not set -# CONFIG_AUFS_BR_RAMFS is not set -# CONFIG_AUFS_BR_FUSE is not set -CONFIG_AUFS_BR_HFSPLUS=y -CONFIG_AUFS_BDEV_LOOP=y -# CONFIG_AUFS_DEBUG is not set CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=m CONFIG_NFS_V2=m @@ -6490,6 +6703,7 @@ CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_NFS_ACL_SUPPORT=y CONFIG_NFS_COMMON=y +CONFIG_NFS_V4_2_SSC_HELPER=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y CONFIG_SUNRPC_BACKCHANNEL=y @@ -6504,7 +6718,6 @@ CONFIG_CEPH_FS_SECURITY_LABEL=y CONFIG_CIFS=m CONFIG_CIFS_STATS2=y CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y -CONFIG_CIFS_WEAK_PW_HASH=y CONFIG_CIFS_UPCALL=y CONFIG_CIFS_XATTR=y CONFIG_CIFS_POSIX=y @@ -6512,7 +6725,13 @@ CONFIG_CIFS_DEBUG=y # CONFIG_CIFS_DEBUG2 is not set # CONFIG_CIFS_DEBUG_DUMP_KEYS is not set CONFIG_CIFS_DFS_UPCALL=y +# CONFIG_CIFS_SWN_UPCALL is not set CONFIG_CIFS_FSCACHE=y +CONFIG_SMB_SERVER=m +CONFIG_SMB_SERVER_SMBDIRECT=y +CONFIG_SMB_SERVER_CHECK_CAP_NET_ADMIN=y +CONFIG_SMB_SERVER_KERBEROS5=y +CONFIG_SMBFS_COMMON=m CONFIG_CODA_FS=m CONFIG_AFS_FS=m # CONFIG_AFS_DEBUG is not set @@ -6631,6 +6850,7 @@ CONFIG_SECURITY_LOCKDOWN_LSM_EARLY=y CONFIG_LOCK_DOWN_KERNEL_FORCE_NONE=y # CONFIG_LOCK_DOWN_KERNEL_FORCE_INTEGRITY is not set # CONFIG_LOCK_DOWN_KERNEL_FORCE_CONFIDENTIALITY is not set +# CONFIG_SECURITY_LANDLOCK is not set CONFIG_INTEGRITY=y CONFIG_INTEGRITY_SIGNATURE=y CONFIG_INTEGRITY_ASYMMETRIC_KEYS=y @@ -6655,6 +6875,9 @@ CONFIG_LSM="lockdown,yama,integrity,apparmor" # Memory initialization # CONFIG_INIT_STACK_NONE=y +# CONFIG_GCC_PLUGIN_STRUCTLEAK_USER is not set +# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF is not set +# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF_ALL is not set CONFIG_INIT_ON_ALLOC_DEFAULT_ON=y # CONFIG_INIT_ON_FREE_DEFAULT_ON is not set # end of Memory initialization @@ -6709,6 +6932,7 @@ CONFIG_CRYPTO_RSA=y CONFIG_CRYPTO_DH=y CONFIG_CRYPTO_ECC=m CONFIG_CRYPTO_ECDH=m +CONFIG_CRYPTO_ECDSA=m CONFIG_CRYPTO_ECRDSA=m CONFIG_CRYPTO_SM2=m # CONFIG_CRYPTO_CURVE25519 is not set @@ -6763,17 +6987,13 @@ CONFIG_CRYPTO_POLY1305=m CONFIG_CRYPTO_MD4=m CONFIG_CRYPTO_MD5=y CONFIG_CRYPTO_MICHAEL_MIC=m -CONFIG_CRYPTO_RMD128=m CONFIG_CRYPTO_RMD160=m -CONFIG_CRYPTO_RMD256=m -CONFIG_CRYPTO_RMD320=m CONFIG_CRYPTO_SHA1=y CONFIG_CRYPTO_SHA256=y CONFIG_CRYPTO_SHA512=y CONFIG_CRYPTO_SHA3=m CONFIG_CRYPTO_SM3=m CONFIG_CRYPTO_STREEBOG=m -CONFIG_CRYPTO_TGR192=m CONFIG_CRYPTO_WP512=m # @@ -6792,7 +7012,6 @@ CONFIG_CRYPTO_CAST6=m CONFIG_CRYPTO_DES=m CONFIG_CRYPTO_FCRYPT=m CONFIG_CRYPTO_KHAZAD=m -CONFIG_CRYPTO_SALSA20=m CONFIG_CRYPTO_CHACHA20=m CONFIG_CRYPTO_SEED=m CONFIG_CRYPTO_SERPENT=m @@ -6836,7 +7055,7 @@ CONFIG_CRYPTO_HASH_INFO=y # CONFIG_CRYPTO_LIB_AES=y CONFIG_CRYPTO_LIB_ARC4=m -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=m +CONFIG_CRYPTO_ARCH_HAVE_LIB_BLAKE2S=m CONFIG_CRYPTO_LIB_BLAKE2S=m CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=m CONFIG_CRYPTO_LIB_CHACHA_GENERIC=m @@ -6851,6 +7070,7 @@ CONFIG_CRYPTO_LIB_POLY1305_GENERIC=m CONFIG_CRYPTO_LIB_POLY1305=m CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m CONFIG_CRYPTO_LIB_SHA256=y +CONFIG_CRYPTO_LIB_SM4=m CONFIG_CRYPTO_HW=y CONFIG_CRYPTO_DEV_HIFN_795X=m # CONFIG_CRYPTO_DEV_HIFN_795X_RNG is not set @@ -6875,6 +7095,8 @@ CONFIG_SIGNED_PE_FILE_VERIFICATION=y # Certificates for signature checking # CONFIG_MODULE_SIG_KEY="certs/signing_key.pem" +CONFIG_MODULE_SIG_KEY_TYPE_RSA=y +# CONFIG_MODULE_SIG_KEY_TYPE_ECDSA is not set CONFIG_SYSTEM_TRUSTED_KEYRING=y CONFIG_SYSTEM_TRUSTED_KEYS="" CONFIG_SYSTEM_EXTRA_CERTIFICATE=y @@ -6885,6 +7107,8 @@ CONFIG_SYSTEM_BLACKLIST_HASH_LIST="" # CONFIG_SYSTEM_REVOCATION_LIST is not set # end of Certificates for signature checking +CONFIG_BINARY_PRINTF=y + # # Library routines # @@ -6981,6 +7205,7 @@ CONFIG_CMA_SIZE_SEL_MBYTES=y # CONFIG_CMA_SIZE_SEL_MAX is not set CONFIG_CMA_ALIGNMENT=8 # CONFIG_DMA_API_DEBUG is not set +# CONFIG_DMA_MAP_BENCHMARK is not set CONFIG_SGL_ALLOC=y CONFIG_CPU_RMAP=y CONFIG_DQL=y @@ -6995,9 +7220,10 @@ CONFIG_LIBFDT=y CONFIG_OID_REGISTRY=y CONFIG_SG_POOL=y CONFIG_SBITMAP=y -# CONFIG_STRING_SELFTEST is not set # end of Library routines +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y + # # Kernel hacking # @@ -7007,6 +7233,7 @@ CONFIG_SBITMAP=y # CONFIG_PRINTK_TIME=y # CONFIG_PRINTK_CALLER is not set +# CONFIG_STACKTRACE_BUILD_ID is not set CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 CONFIG_CONSOLE_LOGLEVEL_QUIET=4 CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 @@ -7021,7 +7248,6 @@ CONFIG_DEBUG_BUGVERBOSE=y # Compile-time checks and compiler options # # CONFIG_DEBUG_INFO is not set -CONFIG_ENABLE_MUST_CHECK=y CONFIG_FRAME_WARN=1024 # CONFIG_STRIP_ASM_SYMS is not set # CONFIG_READABLE_ASM is not set @@ -7071,9 +7297,12 @@ CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y # CONFIG_DEBUG_VIRTUAL is not set CONFIG_DEBUG_MEMORY_INIT=y # CONFIG_DEBUG_PER_CPU_MAPS is not set +# CONFIG_DEBUG_KMAP_LOCAL is not set # CONFIG_DEBUG_HIGHMEM is not set +CONFIG_HAVE_ARCH_KASAN=y CONFIG_CC_HAS_KASAN_GENERIC=y CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y +# CONFIG_KASAN is not set # end of Memory Debugging # CONFIG_DEBUG_SHIRQ is not set @@ -7122,6 +7351,7 @@ CONFIG_LOCK_DEBUGGING_SUPPORT=y CONFIG_SCF_TORTURE_TEST=m # end of Lock Debugging (spinlocks, mutexes, etc...) +# CONFIG_DEBUG_IRQFLAGS is not set # CONFIG_STACKTRACE is not set # CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set # CONFIG_DEBUG_KOBJECT is not set @@ -7148,11 +7378,9 @@ CONFIG_RCU_SCALE_TEST=m CONFIG_RCU_CPU_STALL_TIMEOUT=21 CONFIG_RCU_TRACE=y # CONFIG_RCU_EQS_DEBUG is not set -# CONFIG_RCU_STRICT_GRACE_PERIOD is not set # end of RCU Debugging # CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set -# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set # CONFIG_LATENCYTOP is not set CONFIG_HAVE_FUNCTION_TRACER=y @@ -7165,7 +7393,6 @@ CONFIG_TRACE_CLOCK=y CONFIG_TRACING_SUPPORT=y # CONFIG_FTRACE is not set # CONFIG_SAMPLES is not set -CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y # CONFIG_STRICT_DEVMEM is not set # @@ -7209,9 +7436,8 @@ CONFIG_CC_HAS_SANCOV_TRACE_PC=y # CONFIG_KCOV is not set CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_LKDTM is not set -# CONFIG_TEST_LIST_SORT is not set # CONFIG_TEST_MIN_HEAP is not set -# CONFIG_TEST_SORT is not set +CONFIG_TEST_DIV64=m # CONFIG_BACKTRACE_SELF_TEST is not set # CONFIG_RBTREE_TEST is not set CONFIG_REED_SOLOMON_TEST=m @@ -7220,10 +7446,12 @@ CONFIG_REED_SOLOMON_TEST=m # CONFIG_ATOMIC64_SELFTEST is not set # CONFIG_ASYNC_RAID6_TEST is not set CONFIG_TEST_HEXDUMP=m +# CONFIG_STRING_SELFTEST is not set # CONFIG_TEST_STRING_HELPERS is not set CONFIG_TEST_STRSCPY=m # CONFIG_TEST_KSTRTOX is not set # CONFIG_TEST_PRINTF is not set +CONFIG_TEST_SCANF=m # CONFIG_TEST_BITMAP is not set # CONFIG_TEST_UUID is not set CONFIG_TEST_XARRAY=m @@ -7247,6 +7475,7 @@ CONFIG_TEST_MEMCAT_P=m CONFIG_TEST_STACKINIT=m # CONFIG_TEST_MEMINIT is not set # CONFIG_TEST_FREE_PAGES is not set +CONFIG_ARCH_USE_MEMTEST=y # CONFIG_MEMTEST is not set # end of Kernel Testing and Coverage # end of Kernel hacking diff --git a/config/sources/families/mvebu.conf b/config/sources/families/mvebu.conf index 48f3be10e9..e1af71ab50 100644 --- a/config/sources/families/mvebu.conf +++ b/config/sources/families/mvebu.conf @@ -17,13 +17,13 @@ case $BRANCH in current) - KERNELBRANCH='branch:linux-5.10.y' + KERNELBRANCH='branch:linux-5.15.y' ;; edge) - KERNELBRANCH='branch:linux-5.15.y' + KERNELBRANCH='branch:linux-5.16.y' LINUXCONFIG='linux-mvebu-edge' KERNELPATCHDIR="mvebu-edge" diff --git a/patch/kernel/archive/mvebu-5.16/0001-Revert-net-Remove-net-ipx.h-and-uapi-linux-ipx.h-hea.patch b/patch/kernel/archive/mvebu-5.16/0001-Revert-net-Remove-net-ipx.h-and-uapi-linux-ipx.h-hea.patch new file mode 100644 index 0000000000..8fe8cd6434 --- /dev/null +++ b/patch/kernel/archive/mvebu-5.16/0001-Revert-net-Remove-net-ipx.h-and-uapi-linux-ipx.h-hea.patch @@ -0,0 +1,287 @@ +From 3ec70749ae3cb072f19d886981a217121f776415 Mon Sep 17 00:00:00 2001 +From: Igor Pecovnik +Date: Sat, 6 Nov 2021 19:15:23 +0100 +Subject: [PATCH] Revert "net: Remove net/ipx.h and uapi/linux/ipx.h header + files" + +This reverts commit 6c9b40844751ea30c72f7a2f92f4d704bc6b2927. +--- + include/net/ipx.h | 171 +++++++++++++++++++++++++++++++++++++++ + include/uapi/linux/ipx.h | 87 ++++++++++++++++++++ + 2 files changed, 258 insertions(+) + create mode 100644 include/net/ipx.h + create mode 100644 include/uapi/linux/ipx.h + +diff --git a/include/net/ipx.h b/include/net/ipx.h +new file mode 100644 +index 000000000000..9d1342807b59 +--- /dev/null ++++ b/include/net/ipx.h +@@ -0,0 +1,171 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++#ifndef _NET_INET_IPX_H_ ++#define _NET_INET_IPX_H_ ++/* ++ * The following information is in its entirety obtained from: ++ * ++ * Novell 'IPX Router Specification' Version 1.10 ++ * Part No. 107-000029-001 ++ * ++ * Which is available from ftp.novell.com ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++struct ipx_address { ++ __be32 net; ++ __u8 node[IPX_NODE_LEN]; ++ __be16 sock; ++}; ++ ++#define ipx_broadcast_node "\377\377\377\377\377\377" ++#define ipx_this_node "\0\0\0\0\0\0" ++ ++#define IPX_MAX_PPROP_HOPS 8 ++ ++struct ipxhdr { ++ __be16 ipx_checksum __packed; ++#define IPX_NO_CHECKSUM cpu_to_be16(0xFFFF) ++ __be16 ipx_pktsize __packed; ++ __u8 ipx_tctrl; ++ __u8 ipx_type; ++#define IPX_TYPE_UNKNOWN 0x00 ++#define IPX_TYPE_RIP 0x01 /* may also be 0 */ ++#define IPX_TYPE_SAP 0x04 /* may also be 0 */ ++#define IPX_TYPE_SPX 0x05 /* SPX protocol */ ++#define IPX_TYPE_NCP 0x11 /* $lots for docs on this (SPIT) */ ++#define IPX_TYPE_PPROP 0x14 /* complicated flood fill brdcast */ ++ struct ipx_address ipx_dest __packed; ++ struct ipx_address ipx_source __packed; ++}; ++ ++/* From af_ipx.c */ ++extern int sysctl_ipx_pprop_broadcasting; ++ ++struct ipx_interface { ++ /* IPX address */ ++ __be32 if_netnum; ++ unsigned char if_node[IPX_NODE_LEN]; ++ refcount_t refcnt; ++ ++ /* physical device info */ ++ struct net_device *if_dev; ++ struct datalink_proto *if_dlink; ++ __be16 if_dlink_type; ++ ++ /* socket support */ ++ unsigned short if_sknum; ++ struct hlist_head if_sklist; ++ spinlock_t if_sklist_lock; ++ ++ /* administrative overhead */ ++ int if_ipx_offset; ++ unsigned char if_internal; ++ unsigned char if_primary; ++ ++ struct list_head node; /* node in ipx_interfaces list */ ++}; ++ ++struct ipx_route { ++ __be32 ir_net; ++ struct ipx_interface *ir_intrfc; ++ unsigned char ir_routed; ++ unsigned char ir_router_node[IPX_NODE_LEN]; ++ struct list_head node; /* node in ipx_routes list */ ++ refcount_t refcnt; ++}; ++ ++struct ipx_cb { ++ u8 ipx_tctrl; ++ __be32 ipx_dest_net; ++ __be32 ipx_source_net; ++ struct { ++ __be32 netnum; ++ int index; ++ } last_hop; ++}; ++ ++#include ++ ++struct ipx_sock { ++ /* struct sock has to be the first member of ipx_sock */ ++ struct sock sk; ++ struct ipx_address dest_addr; ++ struct ipx_interface *intrfc; ++ __be16 port; ++#ifdef CONFIG_IPX_INTERN ++ unsigned char node[IPX_NODE_LEN]; ++#endif ++ unsigned short type; ++ /* ++ * To handle special ncp connection-handling sockets for mars_nwe, ++ * the connection number must be stored in the socket. ++ */ ++ unsigned short ipx_ncp_conn; ++}; ++ ++static inline struct ipx_sock *ipx_sk(struct sock *sk) ++{ ++ return (struct ipx_sock *)sk; ++} ++ ++#define IPX_SKB_CB(__skb) ((struct ipx_cb *)&((__skb)->cb[0])) ++ ++#define IPX_MIN_EPHEMERAL_SOCKET 0x4000 ++#define IPX_MAX_EPHEMERAL_SOCKET 0x7fff ++ ++extern struct list_head ipx_routes; ++extern rwlock_t ipx_routes_lock; ++ ++extern struct list_head ipx_interfaces; ++struct ipx_interface *ipx_interfaces_head(void); ++extern spinlock_t ipx_interfaces_lock; ++ ++extern struct ipx_interface *ipx_primary_net; ++ ++int ipx_proc_init(void); ++void ipx_proc_exit(void); ++ ++const char *ipx_frame_name(__be16); ++const char *ipx_device_name(struct ipx_interface *intrfc); ++ ++static __inline__ void ipxitf_hold(struct ipx_interface *intrfc) ++{ ++ refcount_inc(&intrfc->refcnt); ++} ++ ++void ipxitf_down(struct ipx_interface *intrfc); ++struct ipx_interface *ipxitf_find_using_net(__be32 net); ++int ipxitf_send(struct ipx_interface *intrfc, struct sk_buff *skb, char *node); ++__be16 ipx_cksum(struct ipxhdr *packet, int length); ++int ipxrtr_add_route(__be32 network, struct ipx_interface *intrfc, ++ unsigned char *node); ++void ipxrtr_del_routes(struct ipx_interface *intrfc); ++int ipxrtr_route_packet(struct sock *sk, struct sockaddr_ipx *usipx, ++ struct msghdr *msg, size_t len, int noblock); ++int ipxrtr_route_skb(struct sk_buff *skb); ++struct ipx_route *ipxrtr_lookup(__be32 net); ++int ipxrtr_ioctl(unsigned int cmd, void __user *arg); ++ ++static __inline__ void ipxitf_put(struct ipx_interface *intrfc) ++{ ++ if (refcount_dec_and_test(&intrfc->refcnt)) ++ ipxitf_down(intrfc); ++} ++ ++static __inline__ void ipxrtr_hold(struct ipx_route *rt) ++{ ++ refcount_inc(&rt->refcnt); ++} ++ ++static __inline__ void ipxrtr_put(struct ipx_route *rt) ++{ ++ if (refcount_dec_and_test(&rt->refcnt)) ++ kfree(rt); ++} ++#endif /* _NET_INET_IPX_H_ */ +diff --git a/include/uapi/linux/ipx.h b/include/uapi/linux/ipx.h +new file mode 100644 +index 000000000000..3168137adae8 +--- /dev/null ++++ b/include/uapi/linux/ipx.h +@@ -0,0 +1,87 @@ ++/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ ++#ifndef _IPX_H_ ++#define _IPX_H_ ++#include /* for compatibility with glibc netipx/ipx.h */ ++#include ++#include ++#include ++#define IPX_NODE_LEN 6 ++#define IPX_MTU 576 ++ ++#if __UAPI_DEF_SOCKADDR_IPX ++struct sockaddr_ipx { ++ __kernel_sa_family_t sipx_family; ++ __be16 sipx_port; ++ __be32 sipx_network; ++ unsigned char sipx_node[IPX_NODE_LEN]; ++ __u8 sipx_type; ++ unsigned char sipx_zero; /* 16 byte fill */ ++}; ++#endif /* __UAPI_DEF_SOCKADDR_IPX */ ++ ++/* ++ * So we can fit the extra info for SIOCSIFADDR into the address nicely ++ */ ++#define sipx_special sipx_port ++#define sipx_action sipx_zero ++#define IPX_DLTITF 0 ++#define IPX_CRTITF 1 ++ ++#if __UAPI_DEF_IPX_ROUTE_DEFINITION ++struct ipx_route_definition { ++ __be32 ipx_network; ++ __be32 ipx_router_network; ++ unsigned char ipx_router_node[IPX_NODE_LEN]; ++}; ++#endif /* __UAPI_DEF_IPX_ROUTE_DEFINITION */ ++ ++#if __UAPI_DEF_IPX_INTERFACE_DEFINITION ++struct ipx_interface_definition { ++ __be32 ipx_network; ++ unsigned char ipx_device[16]; ++ unsigned char ipx_dlink_type; ++#define IPX_FRAME_NONE 0 ++#define IPX_FRAME_SNAP 1 ++#define IPX_FRAME_8022 2 ++#define IPX_FRAME_ETHERII 3 ++#define IPX_FRAME_8023 4 ++#define IPX_FRAME_TR_8022 5 /* obsolete */ ++ unsigned char ipx_special; ++#define IPX_SPECIAL_NONE 0 ++#define IPX_PRIMARY 1 ++#define IPX_INTERNAL 2 ++ unsigned char ipx_node[IPX_NODE_LEN]; ++}; ++#endif /* __UAPI_DEF_IPX_INTERFACE_DEFINITION */ ++ ++#if __UAPI_DEF_IPX_CONFIG_DATA ++struct ipx_config_data { ++ unsigned char ipxcfg_auto_select_primary; ++ unsigned char ipxcfg_auto_create_interfaces; ++}; ++#endif /* __UAPI_DEF_IPX_CONFIG_DATA */ ++ ++/* ++ * OLD Route Definition for backward compatibility. ++ */ ++ ++#if __UAPI_DEF_IPX_ROUTE_DEF ++struct ipx_route_def { ++ __be32 ipx_network; ++ __be32 ipx_router_network; ++#define IPX_ROUTE_NO_ROUTER 0 ++ unsigned char ipx_router_node[IPX_NODE_LEN]; ++ unsigned char ipx_device[16]; ++ unsigned short ipx_flags; ++#define IPX_RT_SNAP 8 ++#define IPX_RT_8022 4 ++#define IPX_RT_BLUEBOOK 2 ++#define IPX_RT_ROUTED 1 ++}; ++#endif /* __UAPI_DEF_IPX_ROUTE_DEF */ ++ ++#define SIOCAIPXITFCRT (SIOCPROTOPRIVATE) ++#define SIOCAIPXPRISLT (SIOCPROTOPRIVATE + 1) ++#define SIOCIPXCFGDATA (SIOCPROTOPRIVATE + 2) ++#define SIOCIPXNCPCONN (SIOCPROTOPRIVATE + 3) ++#endif /* _IPX_H_ */ +-- +2.25.1 + diff --git a/patch/kernel/archive/mvebu-5.16/0001-cpuidle-mvebu-indicate-failure-to-enter-deeper-sleep.patch b/patch/kernel/archive/mvebu-5.16/0001-cpuidle-mvebu-indicate-failure-to-enter-deeper-sleep.patch new file mode 100644 index 0000000000..da5c35ff04 --- /dev/null +++ b/patch/kernel/archive/mvebu-5.16/0001-cpuidle-mvebu-indicate-failure-to-enter-deeper-sleep.patch @@ -0,0 +1,43 @@ +From: Russell King +Subject: [PATCH 01/30] cpuidle: mvebu: indicate failure to enter deeper sleep + states +MIME-Version: 1.0 +Content-Disposition: inline +Content-Transfer-Encoding: 8bit +Content-Type: text/plain; charset="utf-8" + +The cpuidle ->enter method expects the return value to be the sleep +state we entered. Returning negative numbers or other codes is not +permissible since coupled CPU idle was merged. + +At least some of the mvebu_v7_cpu_suspend() implementations return the +value from cpu_suspend(), which returns zero if the CPU vectors back +into the kernel via cpu_resume() (the success case), or the non-zero +return value of the suspend actor, or one (failure cases). + +We do not want to be returning the failure case value back to CPU idle +as that indicates that we successfully entered one of the deeper idle +states. Always return zero instead, indicating that we slept for the +shortest amount of time. + +Signed-off-by: Russell King +--- + drivers/cpuidle/cpuidle-mvebu-v7.c | 6 +++++- + 1 file changed, 5 insertions(+), 1 deletion(-) + +--- a/drivers/cpuidle/cpuidle-mvebu-v7.c ++++ b/drivers/cpuidle/cpuidle-mvebu-v7.c +@@ -39,8 +39,12 @@ static int mvebu_v7_enter_idle(struct cp + ret = mvebu_v7_cpu_suspend(deepidle); + cpu_pm_exit(); + ++ /* ++ * If we failed to enter the desired state, indicate that we ++ * slept lightly. ++ */ + if (ret) +- return ret; ++ return 0; + + return index; + } diff --git a/patch/kernel/archive/mvebu-5.16/09-pci-link-retraining.patch b/patch/kernel/archive/mvebu-5.16/09-pci-link-retraining.patch new file mode 100644 index 0000000000..d3cf9df1cd --- /dev/null +++ b/patch/kernel/archive/mvebu-5.16/09-pci-link-retraining.patch @@ -0,0 +1,219 @@ +Subject: [PATCH v3] PCI: Disallow retraining link for Atheros chips on non-Gen1 PCIe bridges +Atheros AR9xxx and QCA9xxx chips have behaviour issues not only after a +bus reset, but also after doing retrain link, if PCIe bridge is not in +GEN1 mode (at 2.5 GT/s speed): + +- QCA9880 and QCA9890 chips throw a Link Down event and completely + disappear from the bus and their config space is not accessible + afterwards. + +- QCA9377 chip throws a Link Down event followed by Link Up event, the + config space is accessible and PCI device ID is correct. But trying to + access chip's I/O space causes Uncorrected (Non-Fatal) AER error, + followed by Synchronous external abort 96000210 and Segmentation fault + of insmod while loading ath10k_pci.ko module. + +- AR9390 chip throws a Link Down event followed by Link Up event, config + space is accessible, but contains nonsense values. PCI device ID is + 0xABCD which indicates HW bug that chip itself was not able to read + values from internal EEPROM/OTP. + +- AR9287 chip throws also Link Down and Link Up events, also has + accessible config space containing correct values. But ath9k driver + fails to initialize card from this state as it is unable to access HW + registers. This also indicates that the chip iself is not able to read + values from internal EEPROM/OTP. + +These issues related to PCI device ID 0xABCD and to reading internal +EEPROM/OTP were previously discussed at ath9k-devel mailing list in +following thread: + + https://www.mail-archive.com/ath9k-devel@lists.ath9k.org/msg07529.html + +After experiments we've come up with a solution: it seems that Retrain +link can be called only when using GEN1 PCIe bridge or when PCIe bridge +link speed is forced to 2.5 GT/s. Applying this workaround fixes all +mentioned cards. + +This issue was reproduced with more cards: +- Compex WLE900VX (QCA9880 based / device ID 0x003c) +- QCNFA435 (QCA9377 based / device ID 0x0042) +- Compex WLE200NX (AR9287 based / device ID 0x002e) +- "noname" card (QCA9890 based / device ID 0x003c) +- Wistron NKR-DNXAH1 (AR9390 based / device ID 0x0030) +on Armada 385 with pci-mvebu.c driver and also on Armada 3720 with +pci-aardvark.c driver. + +To workaround this issue, this change introduces a new PCI quirk called +PCI_DEV_FLAGS_NO_RETRAIN_LINK_WHEN_NOT_GEN1, which is enabled for all +Atheros chips with PCI_DEV_FLAGS_NO_BUS_RESET quirk, and also for Atheros +chip AR9287. + +When this quirk is set, kernel disallows triggering PCI_EXP_LNKCTL_RL +bit in config space of PCIe Bridge in the case when PCIe Bridge is +capable of higher speed than 2.5 GT/s and this higher speed is already +allowed. When PCIe Bridge has accessible LNKCTL2 register, we try to +force target link speed to 2.5 GT/s. After this change it is possible +to trigger PCI_EXP_LNKCTL_RL bit without issues. + +Currently only PCIe ASPM kernel code triggers this PCI_EXP_LNKCTL_RL bit, +so quirk check is added only into pcie/aspm.c file. + +Signed-off-by: Pali Rohár +Reported-by: Toke Høiland-Jørgensen +Tested-by: Toke Høiland-Jørgensen +Tested-by: Marek Behún +BugLink: https://lore.kernel.org/linux-pci/87h7l8axqp.fsf@toke.dk/ +BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=84821 +BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=192441 +BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=209833 +Cc: stable@vger.kernel.org # c80851f6ce63a ("PCI: Add PCI_EXP_LNKCTL2_TLS* macros") + +--- +Changes since v1: +* Move whole quirk code into pcie_downgrade_link_to_gen1() function +* Reformat to 80 chars per line where possible +* Add quirk also for cards with AR9287 chip (PCI ID 0x002e) +* Extend commit message description and add information about 0xABCD + +Changes since v2: +* Add quirk also for Atheros QCA9377 chip +--- + drivers/pci/pcie/aspm.c | 44 +++++++++++++++++++++++++++++++++++++++++ + drivers/pci/quirks.c | 39 ++++++++++++++++++++++++++++-------- + include/linux/pci.h | 2 ++ + 3 files changed, 77 insertions(+), 8 deletions(-) + +diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c +index ac0557a305af..729b0389562b 100644 +--- a/drivers/pci/pcie/aspm.c ++++ b/drivers/pci/pcie/aspm.c +@@ -192,12 +192,56 @@ static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist) + link->clkpm_disable = blacklist ? 1 : 0; + } + ++static int pcie_downgrade_link_to_gen1(struct pci_dev *parent) ++{ ++ u16 reg16; ++ u32 reg32; ++ int ret; ++ ++ /* Check if link is capable of higher speed than 2.5 GT/s */ ++ pcie_capability_read_dword(parent, PCI_EXP_LNKCAP, ®32); ++ if ((reg32 & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB) ++ return 0; ++ ++ /* Check if link speed can be downgraded to 2.5 GT/s */ ++ pcie_capability_read_dword(parent, PCI_EXP_LNKCAP2, ®32); ++ if (!(reg32 & PCI_EXP_LNKCAP2_SLS_2_5GB)) { ++ pci_err(parent, "ASPM: Bridge does not support changing Link Speed to 2.5 GT/s\n"); ++ return -EOPNOTSUPP; ++ } ++ ++ /* Force link speed to 2.5 GT/s */ ++ ret = pcie_capability_clear_and_set_word(parent, PCI_EXP_LNKCTL2, ++ PCI_EXP_LNKCTL2_TLS, ++ PCI_EXP_LNKCTL2_TLS_2_5GT); ++ if (!ret) { ++ /* Verify that new value was really set */ ++ pcie_capability_read_word(parent, PCI_EXP_LNKCTL2, ®16); ++ if ((reg16 & PCI_EXP_LNKCTL2_TLS) != PCI_EXP_LNKCTL2_TLS_2_5GT) ++ ret = -EINVAL; ++ } ++ ++ if (ret) { ++ pci_err(parent, "ASPM: Changing Target Link Speed to 2.5 GT/s failed: %d\n", ret); ++ return ret; ++ } ++ ++ pci_info(parent, "ASPM: Target Link Speed changed to 2.5 GT/s due to quirk\n"); ++ return 0; ++} ++ + static bool pcie_retrain_link(struct pcie_link_state *link) + { + struct pci_dev *parent = link->pdev; + unsigned long end_jiffies; + u16 reg16; + ++ if ((link->downstream->dev_flags & PCI_DEV_FLAGS_NO_RETRAIN_LINK_WHEN_NOT_GEN1) && ++ pcie_downgrade_link_to_gen1(parent)) { ++ pci_err(parent, "ASPM: Retrain Link at higher speed is disallowed by quirk\n"); ++ return false; ++ } ++ + pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16); + reg16 |= PCI_EXP_LNKCTL_RL; + pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16); +diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c +index 5d2acebc3..91d675e0d 100644 +--- a/drivers/pci/quirks.c ++++ b/drivers/pci/quirks.c +@@ -3572,19 +3572,46 @@ static void quirk_nvidia_no_bus_reset(struct pci_dev *dev) + DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, + quirk_nvidia_no_bus_reset); + ++ ++static void quirk_no_bus_reset_and_no_retrain_link(struct pci_dev *dev) ++{ ++ dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET | ++ PCI_DEV_FLAGS_NO_RETRAIN_LINK_WHEN_NOT_GEN1; ++} ++ + /* + * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset. ++ * Atheros AR9xxx and QCA9xxx chips do not behave after a bus reset and also ++ * after retrain link when PCIe bridge is not in GEN1 mode at 2.5 GT/s speed. + * The device will throw a Link Down error on AER-capable systems and + * regardless of AER, config space of the device is never accessible again + * and typically causes the system to hang or reset when access is attempted. ++ * Or if config space is accessible again then it contains only dummy values ++ * like fixed PCI device ID 0xABCD or values not initialized at all. ++ * Retrain link can be called only when using GEN1 PCIe bridge or when ++ * PCIe bridge has forced link speed to 2.5 GT/s via PCI_EXP_LNKCTL2 register. ++ * To reset these cards it is required to do PCIe Warm Reset via PERST# pin. + * https://lore.kernel.org/r/20140923210318.498dacbd@dualc.maya.org/ ++ * https://lore.kernel.org/r/87h7l8axqp.fsf@toke.dk/ ++ * https://www.mail-archive.com/ath9k-devel@lists.ath9k.org/msg07529.html + */ +-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset); +-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset); +-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset); +-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset); +-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034, quirk_no_bus_reset); +-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003e, quirk_no_bus_reset); ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x002e, ++ quirk_no_bus_reset_and_no_retrain_link); ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, ++ quirk_no_bus_reset_and_no_retrain_link); ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, ++ quirk_no_bus_reset_and_no_retrain_link); ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, ++ quirk_no_bus_reset_and_no_retrain_link); ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034, ++ quirk_no_bus_reset_and_no_retrain_link); ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003e, ++ quirk_no_bus_reset_and_no_retrain_link); ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, ++ quirk_no_bus_reset_and_no_retrain_link); ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0042, ++ quirk_no_bus_reset_and_no_retrain_link); ++ + + /* + * Root port on some Cavium CN8xxx chips do not successfully complete a bus +diff --git a/include/linux/pci.h b/include/linux/pci.h +index 86c799c97b77..fdbf7254e4ab 100644 +--- a/include/linux/pci.h ++++ b/include/linux/pci.h +@@ -227,6 +227,8 @@ enum pci_dev_flags { + PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11), + /* Device does honor MSI masking despite saying otherwise */ + PCI_DEV_FLAGS_HAS_MSI_MASKING = (__force pci_dev_flags_t) (1 << 12), ++ /* Don't Retrain Link for device when bridge is not in GEN1 mode */ ++ PCI_DEV_FLAGS_NO_RETRAIN_LINK_WHEN_NOT_GEN1 = (__force pci_dev_flags_t) (1 << 12), + }; + + enum pci_irq_reroute_variant { +-- +2.20.1 diff --git a/patch/kernel/archive/mvebu-5.16/10-pcie-bridge-emul.patch b/patch/kernel/archive/mvebu-5.16/10-pcie-bridge-emul.patch new file mode 100644 index 0000000000..b8d2f17f04 --- /dev/null +++ b/patch/kernel/archive/mvebu-5.16/10-pcie-bridge-emul.patch @@ -0,0 +1,273 @@ +From 4549e5c52af22611dcd847a6b5f9df1ccac57b12 Mon Sep 17 00:00:00 2001 +From: Russell King +Date: Tue, 2 Feb 2021 13:45:28 +0000 +Subject: PCI: pci-bridge-emul: re-arrange register tests + +Re-arrange the tests for which sets of registers are being accessed +so that it is easier to add further regions later. No functional +change. + +Signed-off-by: Russell King +--- + drivers/pci/pci-bridge-emul.c | 53 ++++++++++++++++++++++--------------------- + 1 file changed, 27 insertions(+), 26 deletions(-) + +diff --git a/drivers/pci/pci-bridge-emul.c b/drivers/pci/pci-bridge-emul.c +index db97cddfc85e..49160193840b 100644 +--- a/drivers/pci/pci-bridge-emul.c ++++ b/drivers/pci/pci-bridge-emul.c +@@ -328,25 +328,25 @@ int pci_bridge_emul_conf_read(struct pci_bridge_emul *bridge, int where, + __le32 *cfgspace; + const struct pci_bridge_reg_behavior *behavior; + +- if (bridge->has_pcie && reg >= PCI_CAP_PCIE_END) { +- *value = 0; +- return PCIBIOS_SUCCESSFUL; +- } +- +- if (!bridge->has_pcie && reg >= PCI_BRIDGE_CONF_END) { ++ if (reg < PCI_BRIDGE_CONF_END) { ++ /* Emulated PCI space */ ++ read_op = bridge->ops->read_base; ++ cfgspace = (__le32 *) &bridge->conf; ++ behavior = bridge->pci_regs_behavior; ++ } else if (!bridge->has_pcie) { ++ /* PCIe space is not implemented, and no PCI capabilities */ + *value = 0; + return PCIBIOS_SUCCESSFUL; +- } +- +- if (bridge->has_pcie && reg >= PCI_CAP_PCIE_START) { ++ } else if (reg < PCI_CAP_PCIE_END) { ++ /* Our emulated PCIe capability */ + reg -= PCI_CAP_PCIE_START; + read_op = bridge->ops->read_pcie; + cfgspace = (__le32 *) &bridge->pcie_conf; + behavior = bridge->pcie_cap_regs_behavior; + } else { +- read_op = bridge->ops->read_base; +- cfgspace = (__le32 *) &bridge->conf; +- behavior = bridge->pci_regs_behavior; ++ /* Beyond our PCIe space */ ++ *value = 0; ++ return PCIBIOS_SUCCESSFUL; + } + + if (read_op) +@@ -390,11 +390,23 @@ int pci_bridge_emul_conf_write(struct pci_bridge_emul *bridge, int where, + __le32 *cfgspace; + const struct pci_bridge_reg_behavior *behavior; + +- if (bridge->has_pcie && reg >= PCI_CAP_PCIE_END) ++ if (reg < PCI_BRIDGE_CONF_END) { ++ /* Emulated PCI space */ ++ write_op = bridge->ops->write_base; ++ cfgspace = (__le32 *) &bridge->conf; ++ behavior = bridge->pci_regs_behavior; ++ } else if (!bridge->has_pcie) { ++ /* PCIe space is not implemented, and no PCI capabilities */ + return PCIBIOS_SUCCESSFUL; +- +- if (!bridge->has_pcie && reg >= PCI_BRIDGE_CONF_END) ++ } else if (reg < PCI_CAP_PCIE_END) { ++ /* Our emulated PCIe capability */ ++ reg -= PCI_CAP_PCIE_START; ++ write_op = bridge->ops->write_pcie; ++ cfgspace = (__le32 *) &bridge->pcie_conf; ++ behavior = bridge->pcie_cap_regs_behavior; ++ } else { + return PCIBIOS_SUCCESSFUL; ++ } + + shift = (where & 0x3) * 8; + +@@ -411,17 +423,6 @@ int pci_bridge_emul_conf_write(struct pci_bridge_emul *bridge, int where, + if (ret != PCIBIOS_SUCCESSFUL) + return ret; + +- if (bridge->has_pcie && reg >= PCI_CAP_PCIE_START) { +- reg -= PCI_CAP_PCIE_START; +- write_op = bridge->ops->write_pcie; +- cfgspace = (__le32 *) &bridge->pcie_conf; +- behavior = bridge->pcie_cap_regs_behavior; +- } else { +- write_op = bridge->ops->write_base; +- cfgspace = (__le32 *) &bridge->conf; +- behavior = bridge->pci_regs_behavior; +- } +- + /* Keep all bits, except the RW bits */ + new = old & (~mask | ~behavior[reg / 4].rw); + +-- +cgit v1.2.3 +From 908f7290240209dedf88f91ced8254380ab0c5e5 Mon Sep 17 00:00:00 2001 +From: Russell King +Date: Tue, 2 Feb 2021 13:57:04 +0000 +Subject: PCI: pci-bridge-emul: add support for PCIe extended capabilities + +Add support for PCIe extended capabilities, which we just redirect to +the emulating driver. + +Signed-off-by: Russell King +--- + drivers/pci/pci-bridge-emul.c | 74 +++++++++++++++++++++++++++++-------------- + drivers/pci/pci-bridge-emul.h | 15 +++++++++ + 2 files changed, 65 insertions(+), 24 deletions(-) + +diff --git a/drivers/pci/pci-bridge-emul.c b/drivers/pci/pci-bridge-emul.c +index 49160193840b..c5e21f1f210b 100644 +--- a/drivers/pci/pci-bridge-emul.c ++++ b/drivers/pci/pci-bridge-emul.c +@@ -343,10 +343,16 @@ int pci_bridge_emul_conf_read(struct pci_bridge_emul *bridge, int where, + read_op = bridge->ops->read_pcie; + cfgspace = (__le32 *) &bridge->pcie_conf; + behavior = bridge->pcie_cap_regs_behavior; +- } else { +- /* Beyond our PCIe space */ ++ } else if (reg < PCI_CFG_SPACE_SIZE) { ++ /* Rest of PCI space not implemented */ + *value = 0; + return PCIBIOS_SUCCESSFUL; ++ } else { ++ /* PCIe extended capability space */ ++ reg -= PCI_CFG_SPACE_SIZE; ++ read_op = bridge->ops->read_ext; ++ cfgspace = NULL; ++ behavior = NULL; + } + + if (read_op) +@@ -354,15 +360,20 @@ int pci_bridge_emul_conf_read(struct pci_bridge_emul *bridge, int where, + else + ret = PCI_BRIDGE_EMUL_NOT_HANDLED; + +- if (ret == PCI_BRIDGE_EMUL_NOT_HANDLED) +- *value = le32_to_cpu(cfgspace[reg / 4]); ++ if (ret == PCI_BRIDGE_EMUL_NOT_HANDLED) { ++ if (cfgspace) ++ *value = le32_to_cpu(cfgspace[reg / 4]); ++ else ++ *value = 0; ++ } + + /* + * Make sure we never return any reserved bit with a value + * different from 0. + */ +- *value &= behavior[reg / 4].ro | behavior[reg / 4].rw | +- behavior[reg / 4].w1c; ++ if (behavior) ++ *value &= behavior[reg / 4].ro | behavior[reg / 4].rw | ++ behavior[reg / 4].w1c; + + if (size == 1) + *value = (*value >> (8 * (where & 3))) & 0xff; +@@ -404,8 +415,15 @@ int pci_bridge_emul_conf_write(struct pci_bridge_emul *bridge, int where, + write_op = bridge->ops->write_pcie; + cfgspace = (__le32 *) &bridge->pcie_conf; + behavior = bridge->pcie_cap_regs_behavior; +- } else { ++ } else if (reg < PCI_CFG_SPACE_SIZE) { ++ /* Rest of PCI space not implemented */ + return PCIBIOS_SUCCESSFUL; ++ } else { ++ /* PCIe extended capability space */ ++ reg -= PCI_CFG_SPACE_SIZE; ++ write_op = bridge->ops->write_ext; ++ cfgspace = NULL; ++ behavior = NULL; + } + + shift = (where & 0x3) * 8; +@@ -423,29 +441,37 @@ int pci_bridge_emul_conf_write(struct pci_bridge_emul *bridge, int where, + if (ret != PCIBIOS_SUCCESSFUL) + return ret; + +- /* Keep all bits, except the RW bits */ +- new = old & (~mask | ~behavior[reg / 4].rw); ++ if (behavior) { ++ /* Keep all bits, except the RW bits */ ++ new = old & (~mask | ~behavior[reg / 4].rw); + +- /* Update the value of the RW bits */ +- new |= (value << shift) & (behavior[reg / 4].rw & mask); ++ /* Update the value of the RW bits */ ++ new |= (value << shift) & (behavior[reg / 4].rw & mask); + +- /* Clear the W1C bits */ +- new &= ~((value << shift) & (behavior[reg / 4].w1c & mask)); ++ /* Clear the W1C bits */ ++ new &= ~((value << shift) & (behavior[reg / 4].w1c & mask)); ++ } else { ++ new = old & ~mask; ++ new |= (value << shift) & mask; ++ } + + /* Save the new value with the cleared W1C bits into the cfgspace */ +- cfgspace[reg / 4] = cpu_to_le32(new); ++ if (cfgspace) ++ cfgspace[reg / 4] = cpu_to_le32(new); + +- /* +- * Clear the W1C bits not specified by the write mask, so that the +- * write_op() does not clear them. +- */ +- new &= ~(behavior[reg / 4].w1c & ~mask); ++ if (behavior) { ++ /* ++ * Clear the W1C bits not specified by the write mask, so that ++ * the write_op() does not clear them. ++ */ ++ new &= ~(behavior[reg / 4].w1c & ~mask); + +- /* +- * Set the W1C bits specified by the write mask, so that write_op() +- * knows about that they are to be cleared. +- */ +- new |= (value << shift) & (behavior[reg / 4].w1c & mask); ++ /* ++ * Set the W1C bits specified by the write mask, so that ++ * write_op() knows about that they are to be cleared. ++ */ ++ new |= (value << shift) & (behavior[reg / 4].w1c & mask); ++ } + + if (write_op) + write_op(bridge, reg, old, new, mask); +diff --git a/drivers/pci/pci-bridge-emul.h b/drivers/pci/pci-bridge-emul.h +index 49bbd37ee318..2552ab660b08 100644 +--- a/drivers/pci/pci-bridge-emul.h ++++ b/drivers/pci/pci-bridge-emul.h +@@ -90,6 +90,14 @@ struct pci_bridge_emul_ops { + */ + pci_bridge_emul_read_status_t (*read_pcie)(struct pci_bridge_emul *bridge, + int reg, u32 *value); ++ ++ /* ++ * Same as ->read_base(), except it is for reading from the ++ * PCIe extended capability configuration space. ++ */ ++ pci_bridge_emul_read_status_t (*read_ext)(struct pci_bridge_emul *bridge, ++ int reg, u32 *value); ++ + /* + * Called when writing to the regular PCI bridge configuration + * space. old is the current value, new is the new value being +@@ -105,6 +113,13 @@ struct pci_bridge_emul_ops { + */ + void (*write_pcie)(struct pci_bridge_emul *bridge, int reg, + u32 old, u32 new, u32 mask); ++ ++ /* ++ * Same as ->write_base(), except it is for writing from the ++ * PCIe extended capability configuration space. ++ */ ++ void (*write_ext)(struct pci_bridge_emul *bridge, int reg, ++ u32 old, u32 new, u32 mask); + }; + + struct pci_bridge_reg_behavior; +-- +cgit v1.2.3 + diff --git a/patch/kernel/archive/mvebu-5.16/11-mvebu-clearfog-pcie-updates.patch b/patch/kernel/archive/mvebu-5.16/11-mvebu-clearfog-pcie-updates.patch new file mode 100644 index 0000000000..306c983daa --- /dev/null +++ b/patch/kernel/archive/mvebu-5.16/11-mvebu-clearfog-pcie-updates.patch @@ -0,0 +1,244 @@ +From 9d274182feb7642db60ac4b713ac6572b5dbd04b Mon Sep 17 00:00:00 2001 +From: Russell King +Date: Tue, 29 Nov 2016 10:13:46 +0000 +Subject: mvebu/clearfog pcie updates + +Signed-off-by: Russell King +--- + drivers/pci/controller/pci-mvebu.c | 112 ++++++++++++++++++++++++++++++++++++- + drivers/pci/pci-bridge-emul.c | 2 + + drivers/pci/pcie/aspm.c | 6 ++ + drivers/pci/pcie/portdrv_core.c | 2 + + 4 files changed, 121 insertions(+), 1 deletion(-) + +diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c +index ed13e81cd691..2dc9f457bc76 100644 +--- a/drivers/pci/controller/pci-mvebu.c ++++ b/drivers/pci/controller/pci-mvebu.c +@@ -52,7 +52,14 @@ + PCIE_CONF_ADDR_EN) + #define PCIE_CONF_DATA_OFF 0x18fc + #define PCIE_MASK_OFF 0x1910 ++#define PCIE_MASK_PM_PME BIT(28) + #define PCIE_MASK_ENABLE_INTS 0x0f000000 ++#define PCIE_MASK_ERR_COR BIT(18) ++#define PCIE_MASK_ERR_NONFATAL BIT(17) ++#define PCIE_MASK_ERR_FATAL BIT(16) ++#define PCIE_MASK_FERR_DET BIT(10) ++#define PCIE_MASK_NFERR_DET BIT(9) ++#define PCIE_MASK_CORERR_DET BIT(8) + #define PCIE_CTRL_OFF 0x1a00 + #define PCIE_CTRL_X1_MODE 0x0001 + #define PCIE_STAT_OFF 0x1a04 +@@ -430,6 +437,54 @@ static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port) + &port->memwin); + } + ++static void mvebu_pcie_handle_irq_change(struct mvebu_pcie_port *port) ++{ ++ u32 reg, old; ++ u16 devctl, rtctl; ++ ++ /* ++ * Errors from downstream devices: ++ * bridge control register SERR: enables reception of errors ++ * Errors from this device, or received errors: ++ * command SERR: enables ERR_NONFATAL and ERR_FATAL messages ++ * => when enabled, these conditions also flag SERR in status register ++ * devctl CERE: enables ERR_CORR messages ++ * devctl NFERE: enables ERR_NONFATAL messages ++ * devctl FERE: enables ERR_FATAL messages ++ * Enabled messages then have three paths: ++ * 1. rtctl: enables system error indication ++ * 2. root error status register updated ++ * 3. root error command register: forwarding via MSI ++ */ ++ old = mvebu_readl(port, PCIE_MASK_OFF); ++ reg = old & ~(PCIE_MASK_PM_PME | PCIE_MASK_FERR_DET | ++ PCIE_MASK_NFERR_DET | PCIE_MASK_CORERR_DET | ++ PCIE_MASK_ERR_COR | PCIE_MASK_ERR_NONFATAL | ++ PCIE_MASK_ERR_FATAL); ++ ++ devctl = port->bridge.pcie_conf.devctl; ++ if (devctl & PCI_EXP_DEVCTL_FERE) ++ reg |= PCIE_MASK_FERR_DET | PCIE_MASK_ERR_FATAL; ++ if (devctl & PCI_EXP_DEVCTL_NFERE) ++ reg |= PCIE_MASK_NFERR_DET | PCIE_MASK_ERR_NONFATAL; ++ if (devctl & PCI_EXP_DEVCTL_CERE) ++ reg |= PCIE_MASK_CORERR_DET | PCIE_MASK_ERR_COR; ++ if (port->bridge.conf.command & PCI_COMMAND_SERR) ++ reg |= PCIE_MASK_FERR_DET | PCIE_MASK_NFERR_DET | ++ PCIE_MASK_ERR_FATAL | PCIE_MASK_ERR_NONFATAL; ++ ++ if (!(port->bridge.conf.bridgectrl & PCI_BRIDGE_CTL_SERR)) ++ reg &= ~(PCIE_MASK_ERR_COR | PCIE_MASK_ERR_NONFATAL | ++ PCIE_MASK_ERR_FATAL); ++ ++ rtctl = port->bridge.pcie_conf.rootctl; ++ if (rtctl & PCI_EXP_RTCTL_PMEIE) ++ reg |= PCIE_MASK_PM_PME; ++ ++ if (old != reg) ++ mvebu_writel(port, reg, PCIE_MASK_OFF); ++} ++ + static pci_bridge_emul_read_status_t + mvebu_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge, + int reg, u32 *value) +@@ -475,6 +530,30 @@ mvebu_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge, + return PCI_BRIDGE_EMUL_HANDLED; + } + ++static pci_bridge_emul_read_status_t ++mvebu_pci_bridge_emul_pcie_ext_read(struct pci_bridge_emul *bridge, ++ int reg, u32 *value) ++{ ++ struct mvebu_pcie_port *port = bridge->data; ++ ++ switch (reg) { ++ case 0x00 ... 0x28: ++ *value = mvebu_readl(port, 0x100 + (reg & ~3)); ++ break; ++ ++ case PCI_ERR_ROOT_COMMAND: ++ case PCI_ERR_ROOT_STATUS: ++ case PCI_ERR_ROOT_ERR_SRC: ++ *value = 0; ++ break; ++ ++ default: ++ return PCI_BRIDGE_EMUL_NOT_HANDLED; ++ } ++ ++ return PCI_BRIDGE_EMUL_HANDLED; ++} ++ + static void + mvebu_pci_bridge_emul_base_conf_write(struct pci_bridge_emul *bridge, + int reg, u32 old, u32 new, u32 mask) + +@@ -656,6 +656,8 @@ mvebu_pci_bridge_emul_base_conf_write(struct pci_bridge_emul *bridge, + + case PCI_IO_BASE: + mvebu_pcie_handle_iobase_change(port); ++ if ((old ^ new) & PCI_COMMAND_SERR) ++ mvebu_pcie_handle_irq_change(port); + break; + + case PCI_MEMORY_BASE: +@@ -672,6 +674,9 @@ mvebu_pci_bridge_emul_base_conf_write(struct pci_bridge_emul *bridge, + break; + + case PCI_INTERRUPT_LINE: ++ if (((old ^ new) >> 16) & PCI_BRIDGE_CTL_SERR) ++ mvebu_pcie_handle_irq_change(port); ++ + if (mask & (PCI_BRIDGE_CTL_BUS_RESET << 16)) { + u32 ctrl = mvebu_readl(port, PCIE_CTRL_OFF); + if (new & (PCI_BRIDGE_CTL_BUS_RESET << 16)) +@@ -532,6 +617,10 @@ mvebu_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge, + + switch (reg) { + case PCI_EXP_DEVCTL: ++ if ((new ^ old) & (PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_NFERE | ++ PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_URRE)) ++ mvebu_pcie_handle_irq_change(port); ++ + mvebu_writel(port, new, PCIE_CAP_PCIEXP + PCI_EXP_DEVCTL); + break; + +@@ -557,6 +646,25 @@ mvebu_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge, + case PCI_EXP_RTSTA: + mvebu_writel(port, new, PCIE_RC_RTSTA); + break; ++ ++ case PCI_EXP_RTCTL: ++ if ((new ^ old) & (PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE | ++ PCI_EXP_RTCTL_SEFEE | PCI_EXP_RTCTL_PMEIE)) ++ mvebu_pcie_handle_irq_change(port); ++ break; ++ } ++} ++ ++static void ++mvebu_pci_bridge_emul_pcie_ext_write(struct pci_bridge_emul *bridge, ++ int reg, u32 old, u32 new, u32 mask) ++{ ++ struct mvebu_pcie_port *port = bridge->data; ++ ++ switch (reg) { ++ case 0x00 ... 0x28: ++ mvebu_writel(port, new, 0x100 + (reg & ~3)); ++ break; + } + } + +@@ -564,6 +672,8 @@ static struct pci_bridge_emul_ops mvebu_pci_bridge_emul_ops = { + .write_base = mvebu_pci_bridge_emul_base_conf_write, + .read_pcie = mvebu_pci_bridge_emul_pcie_conf_read, + .write_pcie = mvebu_pci_bridge_emul_pcie_conf_write, ++ .read_ext = mvebu_pci_bridge_emul_pcie_ext_read, ++ .write_ext = mvebu_pci_bridge_emul_pcie_ext_write, + }; + + /* +diff --git a/drivers/pci/pci-bridge-emul.c b/drivers/pci/pci-bridge-emul.c +index c5e21f1f210b..b2a32af1e073 100644 +--- a/drivers/pci/pci-bridge-emul.c ++++ b/drivers/pci/pci-bridge-emul.c +@@ -153,6 +153,7 @@ struct pci_bridge_reg_behavior pci_regs_behavior[PCI_STD_HEADER_SIZEOF / 4] = { + .rw = (GENMASK(7, 0) | + ((PCI_BRIDGE_CTL_PARITY | + PCI_BRIDGE_CTL_SERR | ++ /* NOTE: PCIe does not allow ISA, VGA, MASTER_ABORT */ + PCI_BRIDGE_CTL_ISA | + PCI_BRIDGE_CTL_VGA | + PCI_BRIDGE_CTL_MASTER_ABORT | +@@ -269,6 +270,7 @@ int pci_bridge_emul_init(struct pci_bridge_emul *bridge, + bridge->conf.header_type = PCI_HEADER_TYPE_BRIDGE; + bridge->conf.cache_line_size = 0x10; + bridge->conf.status = cpu_to_le16(PCI_STATUS_CAP_LIST); ++ bridge->conf.bridgectrl = cpu_to_le16(PCI_BRIDGE_CTL_SERR); + bridge->pci_regs_behavior = kmemdup(pci_regs_behavior, + sizeof(pci_regs_behavior), + GFP_KERNEL); +diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c +index 52c74682601a..84c1448e1543 100644 +--- a/drivers/pci/pcie/aspm.c ++++ b/drivers/pci/pcie/aspm.c +@@ -578,6 +578,12 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) + pcie_capability_read_dword(child, PCI_EXP_LNKCAP, &child_lnkcap); + pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &parent_lnkctl); + pcie_capability_read_word(child, PCI_EXP_LNKCTL, &child_lnkctl); ++dev_info(&parent->dev, "up support %x enabled %x\n", ++ (parent_lnkcap & PCI_EXP_LNKCAP_ASPMS) >> 10, ++ !!(parent_lnkctl & PCI_EXP_LNKCTL_ASPMC)); ++dev_info(&parent->dev, "dn support %x enabled %x\n", ++ (child_lnkcap & PCI_EXP_LNKCAP_ASPMS) >> 10, ++ !!(child_lnkctl & PCI_EXP_LNKCTL_ASPMC)); + + /* + * Setup L0s state +diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c +index bda630889f95..a9be5002a56c 100644 +--- a/drivers/pci/pcie/portdrv_core.c ++++ b/drivers/pci/pcie/portdrv_core.c +@@ -326,6 +326,7 @@ int pcie_port_device_register(struct pci_dev *dev) + + /* Get and check PCI Express port services */ + capabilities = get_port_device_capability(dev); ++dev_info(&dev->dev, "PCIe capabilities: 0x%x\n", capabilities); + if (!capabilities) + return 0; + +@@ -351,6 +352,7 @@ int pcie_port_device_register(struct pci_dev *dev) + * Allow them to determine if that is to be used. + */ + status = pcie_init_service_irqs(dev, irqs, irq_services); ++dev_info(&dev->dev, "init_service_irqs: %d\n", status); + if (status) { + irq_services &= PCIE_PORT_SERVICE_HP; + if (!irq_services) +-- +cgit v1.2.3 + diff --git a/patch/kernel/archive/mvebu-5.16/12-implement-slot-capabilities-SSPL.patch b/patch/kernel/archive/mvebu-5.16/12-implement-slot-capabilities-SSPL.patch new file mode 100644 index 0000000000..1c5ab06fd4 --- /dev/null +++ b/patch/kernel/archive/mvebu-5.16/12-implement-slot-capabilities-SSPL.patch @@ -0,0 +1,60 @@ +From 76e9a0db445a3fdaa7685fe133a55673c94e9b5e Mon Sep 17 00:00:00 2001 +From: Russell King +Date: Tue, 29 Nov 2016 10:13:48 +0000 +Subject: implement slot capabilities (SSPL) + +--- + drivers/pci/controller/pci-mvebu.c | 23 +++++++++++++++++++++++ + 1 file changed, 23 insertions(+) + +diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c +index 2dc9f457bc76..f3d2745f62b0 100644 +--- a/drivers/pci/controller/pci-mvebu.c ++++ b/drivers/pci/controller/pci-mvebu.c +@@ -66,6 +66,12 @@ + #define PCIE_STAT_BUS 0xff00 + #define PCIE_STAT_DEV 0x1f0000 + #define PCIE_STAT_LINK_DOWN BIT(0) ++#define PCIE_SSPL 0x1a0c ++#define PCIE_SSPL_MSGEN BIT(14) ++#define PCIE_SSPL_SPLS(x) (((x) & 3) << 8) ++#define PCIE_SSPL_SPLS_VAL(x) (((x) >> 8) & 3) ++#define PCIE_SSPL_SPLV(x) ((x) & 0xff) ++#define PCIE_SSPL_SPLV_VAL(x) ((x) & 0xff) + #define PCIE_RC_RTSTA 0x1a14 + #define PCIE_DEBUG_CTRL 0x1a60 + #define PCIE_DEBUG_SOFT_RESET BIT(20) +@@ -515,6 +521,14 @@ mvebu_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge, + *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL); + break; + ++ case PCI_EXP_SLTCAP: ++ { ++ u32 tmp = mvebu_readl(port, PCIE_SSPL); ++ *value = PCIE_SSPL_SPLS_VAL(tmp) << 15 | ++ PCIE_SSPL_SPLV_VAL(tmp) << 7; ++ break; ++ } ++ + case PCI_EXP_SLTCTL: + *value = PCI_EXP_SLTSTA_PDS << 16; + break; +@@ -643,6 +657,15 @@ mvebu_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge, + mvebu_writel(port, new, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL); + break; + ++ case PCI_EXP_SLTCAP: ++ { ++ u32 sspl = PCIE_SSPL_SPLV((new & PCI_EXP_SLTCAP_SPLV) >> 7) | ++ PCIE_SSPL_SPLS((new & PCI_EXP_SLTCAP_SPLS) >> 15) | ++ PCIE_SSPL_MSGEN; ++ mvebu_writel(port, sspl, PCIE_SSPL); ++ break; ++ } ++ + case PCI_EXP_RTSTA: + mvebu_writel(port, new, PCIE_RC_RTSTA); + break; +-- +cgit v1.2.3 + diff --git a/patch/kernel/archive/mvebu-5.16/12-net-dsa-mv88e6xxx.patch b/patch/kernel/archive/mvebu-5.16/12-net-dsa-mv88e6xxx.patch new file mode 100644 index 0000000000..6a87fa64df --- /dev/null +++ b/patch/kernel/archive/mvebu-5.16/12-net-dsa-mv88e6xxx.patch @@ -0,0 +1,1325 @@ +From 3724260d6f3b5e821ce7ead6410416bf02c3fff6 Mon Sep 17 00:00:00 2001 +From: Vivien Didelot +Date: Thu, 22 Oct 2015 14:31:23 -0400 +Subject: net: dsa: mv88e6xxx: add debugfs interface + +Add a debugfs directory named mv88e6xxx.X where X is the DSA switch +index. Mount the debugfs file system with: + + # mount -t debugfs none /sys/kernel/debug + +Signed-off-by: Vivien Didelot +[Modified by rmk for current kernels.] +Signed-off-by: Russell King +--- + drivers/net/dsa/mv88e6xxx/chip.c | 7 + + drivers/net/dsa/mv88e6xxx/chip.h | 2 + + drivers/net/dsa/mv88e6xxx/mv88e6xxx_debugfs.c | 1099 +++++++++++++++++++++++++ + 3 files changed, 1108 insertions(+) + create mode 100644 drivers/net/dsa/mv88e6xxx/mv88e6xxx_debugfs.c + +diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c +index 272b0535d946..34b7f057a80d 100644 +--- a/drivers/net/dsa/mv88e6xxx/chip.c ++++ b/drivers/net/dsa/mv88e6xxx/chip.c +@@ -3008,8 +3008,13 @@ static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip) + return mv88e6xxx_software_reset(chip); + } + ++#include "mv88e6xxx_debugfs.c" ++ + static void mv88e6xxx_teardown(struct dsa_switch *ds) + { ++ struct mv88e6xxx_chip *chip = ds->priv; ++ ++ mv88e6xxx_remove_debugfs(chip); + mv88e6xxx_teardown_devlink_params(ds); + dsa_devlink_resources_unregister(ds); + mv88e6xxx_teardown_devlink_regions(ds); +@@ -3128,6 +3133,8 @@ static int mv88e6xxx_setup(struct dsa_switch *ds) + if (err) + goto unlock; + ++ mv88e6xxx_init_debugfs(chip); ++ + unlock: + mv88e6xxx_reg_unlock(chip); + +diff --git a/drivers/net/dsa/mv88e6xxx/chip.h b/drivers/net/dsa/mv88e6xxx/chip.h +index 675b1f3e43b7..850706ed2dad 100644 +--- a/drivers/net/dsa/mv88e6xxx/chip.h ++++ b/drivers/net/dsa/mv88e6xxx/chip.h +@@ -377,6 +377,8 @@ struct mv88e6xxx_chip { + + /* devlink regions */ + struct devlink_region *regions[_MV88E6XXX_REGION_MAX]; ++ ++ struct dentry *dbgfs; + }; + + struct mv88e6xxx_bus_ops { +diff --git a/drivers/net/dsa/mv88e6xxx/mv88e6xxx_debugfs.c b/drivers/net/dsa/mv88e6xxx/mv88e6xxx_debugfs.c +new file mode 100644 +index 000000000000..931e769fe9ce +--- /dev/null ++++ b/drivers/net/dsa/mv88e6xxx/mv88e6xxx_debugfs.c +@@ -0,0 +1,1099 @@ ++#include ++#include ++ ++#define GLOBAL2_PVT_ADDR 0x0b ++#define GLOBAL2_PVT_ADDR_BUSY BIT(15) ++#define GLOBAL2_PVT_ADDR_OP_INIT_ONES ((0x01 << 12) | GLOBAL2_PVT_ADDR_BUSY) ++#define GLOBAL2_PVT_ADDR_OP_WRITE_PVLAN ((0x03 << 12) | GLOBAL2_PVT_ADDR_BUSY) ++#define GLOBAL2_PVT_ADDR_OP_READ ((0x04 << 12) | GLOBAL2_PVT_ADDR_BUSY) ++#define GLOBAL2_PVT_DATA 0x0c ++ ++#define ADDR_GLOBAL2 0x1c ++ ++static int mv88e6xxx_serdes_read(struct mv88e6xxx_chip *chip, int reg, u16 *val) ++{ ++ return mv88e6xxx_phy_page_read(chip, MV88E6352_ADDR_SERDES, ++ MV88E6352_SERDES_PAGE_FIBER, ++ reg, val); ++} ++ ++static int mv88e6xxx_serdes_write(struct mv88e6xxx_chip *chip, int reg, u16 val) ++{ ++ return mv88e6xxx_phy_page_write(chip, MV88E6352_ADDR_SERDES, ++ MV88E6352_SERDES_PAGE_FIBER, ++ reg, val); ++} ++ ++static int _mv88e6xxx_pvt_wait(struct mv88e6xxx_chip *chip) ++{ ++ return mv88e6xxx_wait_mask(chip, ADDR_GLOBAL2, GLOBAL2_PVT_ADDR, ++ GLOBAL2_PVT_ADDR_BUSY, 0); ++} ++ ++static int _mv88e6xxx_pvt_cmd(struct mv88e6xxx_chip *chip, int src_dev, ++ int src_port, u16 op) ++{ ++ u16 reg = op; ++ int err; ++ ++ /* 9-bit Cross-chip PVT pointer: with GLOBAL2_MISC_5_BIT_PORT cleared, ++ * source device is 5-bit, source port is 4-bit. ++ */ ++ reg |= (src_dev & 0x1f) << 4; ++ reg |= (src_port & 0xf); ++ ++ err = mv88e6xxx_g2_write(chip, GLOBAL2_PVT_ADDR, reg); ++ if (err) ++ return err; ++ ++ return _mv88e6xxx_pvt_wait(chip); ++} ++ ++static int _mv88e6xxx_pvt_read(struct mv88e6xxx_chip *chip, int src_dev, ++ int src_port, u16 *data) ++{ ++ int ret; ++ ++ ret = _mv88e6xxx_pvt_wait(chip); ++ if (ret < 0) ++ return ret; ++ ++ ret = _mv88e6xxx_pvt_cmd(chip, src_dev, src_port, ++ GLOBAL2_PVT_ADDR_OP_READ); ++ if (ret < 0) ++ return ret; ++ ++ return mv88e6xxx_g2_read(chip, GLOBAL2_PVT_DATA, data); ++} ++ ++static int _mv88e6xxx_pvt_write(struct mv88e6xxx_chip *chip, int src_dev, ++ int src_port, u16 data) ++{ ++ int err; ++ ++ err = _mv88e6xxx_pvt_wait(chip); ++ if (err) ++ return err; ++ ++ err = mv88e6xxx_g2_write(chip, GLOBAL2_PVT_DATA, data); ++ if (err) ++ return err; ++ ++ return _mv88e6xxx_pvt_cmd(chip, src_dev, src_port, ++ GLOBAL2_PVT_ADDR_OP_WRITE_PVLAN); ++} ++ ++static int mv88e6xxx_regs_show(struct seq_file *s, void *p) ++{ ++ struct mv88e6xxx_chip *chip = s->private; ++ int port, reg, ret; ++ u16 data; ++ ++ seq_puts(s, " GLOBAL GLOBAL2 SERDES "); ++ for (port = 0; port < mv88e6xxx_num_ports(chip); port++) ++ seq_printf(s, " %2d ", port); ++ seq_puts(s, "\n"); ++ ++ mutex_lock(&chip->reg_lock); ++ ++ for (reg = 0; reg < 32; reg++) { ++ seq_printf(s, "%2x:", reg); ++ ++ ret = mv88e6xxx_g1_read(chip, reg, &data); ++ if (ret < 0) ++ goto unlock; ++ seq_printf(s, " %4x ", data); ++ ++ ret = mv88e6xxx_g2_read(chip, reg, &data); ++ if (ret < 0) ++ goto unlock; ++ seq_printf(s, " %4x ", data); ++ ++ if (reg != MV88E6XXX_PHY_PAGE) { ++ ret = mv88e6xxx_serdes_read(chip, reg, &data); ++ if (ret < 0) ++ goto unlock; ++ } else { ++ data = 0; ++ } ++ seq_printf(s, " %4x ", data); ++ ++ /* Port regs 0x1a-0x1f are reserved in 6185 family */ ++ if (chip->info->family == MV88E6XXX_FAMILY_6185 && reg > 25) { ++ for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) ++ seq_printf(s, "%4c ", '-'); ++ seq_puts(s, "\n"); ++ continue; ++ } ++ ++ for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) { ++ ret = mv88e6xxx_port_read(chip, port, reg, &data); ++ if (ret < 0) ++ goto unlock; ++ ++ seq_printf(s, "%4x ", data); ++ } ++ ++ seq_puts(s, "\n"); ++ } ++ ++ ret = 0; ++unlock: ++ mutex_unlock(&chip->reg_lock); ++ ++ return ret; ++} ++ ++static ssize_t mv88e6xxx_regs_write(struct file *file, const char __user *buf, ++ size_t count, loff_t *ppos) ++{ ++ struct seq_file *s = file->private_data; ++ struct mv88e6xxx_chip *chip = s->private; ++ char cmd[32], name[32] = { 0 }; ++ unsigned int port, reg, val; ++ int ret; ++ ++ if (count > sizeof(name) - 1) ++ return -EINVAL; ++ ++ if (copy_from_user(cmd, buf, sizeof(cmd))) ++ return -EFAULT; ++ ++ ret = sscanf(cmd, "%s %x %x", name, ®, &val); ++ if (ret != 3) ++ return -EINVAL; ++ ++ if (reg > 0x1f || val > 0xffff) ++ return -ERANGE; ++ ++ mutex_lock(&chip->reg_lock); ++ ++ if (strcasecmp(name, "GLOBAL") == 0) ++ ret = mv88e6xxx_g1_write(chip, reg, val); ++ else if (strcasecmp(name, "GLOBAL2") == 0) ++ ret = mv88e6xxx_g2_write(chip, reg, val); ++ else if (strcasecmp(name, "SERDES") == 0) ++ ret = mv88e6xxx_serdes_write(chip, reg, val); ++ else if (kstrtouint(name, 10, &port) == 0 && port < mv88e6xxx_num_ports(chip)) ++ ret = mv88e6xxx_port_write(chip, port, reg, val); ++ else ++ ret = -EINVAL; ++ ++ mutex_unlock(&chip->reg_lock); ++ ++ return ret < 0 ? ret : count; ++} ++ ++static int mv88e6xxx_regs_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, mv88e6xxx_regs_show, inode->i_private); ++} ++ ++static const struct file_operations mv88e6xxx_regs_fops = { ++ .open = mv88e6xxx_regs_open, ++ .read = seq_read, ++ .write = mv88e6xxx_regs_write, ++ .llseek = no_llseek, ++ .release = single_release, ++ .owner = THIS_MODULE, ++}; ++ ++static int mv88e6xxx_name_show(struct seq_file *s, void *p) ++{ ++ struct mv88e6xxx_chip *chip = s->private; ++ struct dsa_switch *ds = chip->ds; ++ struct dsa_switch_tree *dst = ds->dst; ++ struct dsa_port *dp; ++ int i; ++ ++ if (!ds->cd) ++ return 0; ++ ++ seq_puts(s, " Port Name\n"); ++ ++ list_for_each_entry(dp, &dst->ports, list) { ++ if (dp->ds != ds) ++ continue; ++ ++ i = dp->index; ++ if (!ds->cd->port_names[i]) ++ continue; ++ ++ seq_printf(s, "%4d %s", i, ds->cd->port_names[i]); ++ ++ if (dp->slave) ++ seq_printf(s, " (%s)", netdev_name(dp->slave)); ++ ++ seq_puts(s, "\n"); ++ } ++ ++ return 0; ++} ++ ++static int mv88e6xxx_name_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, mv88e6xxx_name_show, inode->i_private); ++} ++ ++static const struct file_operations mv88e6xxx_name_fops = { ++ .open = mv88e6xxx_name_open, ++ .read = seq_read, ++ .llseek = no_llseek, ++ .release = single_release, ++ .owner = THIS_MODULE, ++}; ++ ++static int mv88e6xxx_atu_show(struct seq_file *s, void *p) ++{ ++ struct mv88e6xxx_chip *chip = s->private; ++ struct mv88e6xxx_atu_entry addr; ++ const char *state; ++ int fid, i, err; ++ ++ seq_puts(s, " FID MAC Addr State Trunk? DPV/Trunk ID\n"); ++ ++ for (fid = 0; fid < mv88e6xxx_num_databases(chip); ++fid) { ++ addr.state = 0; ++ eth_broadcast_addr(addr.mac); ++ ++ do { ++ mutex_lock(&chip->reg_lock); ++ err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); ++ mutex_unlock(&chip->reg_lock); ++ if (err) ++ return err; ++ ++ if (addr.state == 0) ++ break; ++ ++ /* print ATU entry */ ++ seq_printf(s, "%4d %pM", fid, addr.mac); ++ ++ if (is_multicast_ether_addr(addr.mac)) { ++ switch (addr.state) { ++ case MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_PO: ++ state = "MC_STATIC_PO"; ++ break; ++ case MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_DA_MGMT_PO: ++ state = "MC_STATIC_MGMT_PO"; ++ break; ++ case MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_AVB_NRL_PO: ++ state = "MC_STATIC_NRL_PO"; ++ break; ++ case MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY_PO: ++ state = "MC_STATIC_POLICY_PO"; ++ break; ++ case MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC: ++ state = "MC_STATIC"; ++ break; ++ case MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_DA_MGMT: ++ state = "MC_STATIC_MGMT"; ++ break; ++ case MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_AVB_NRL: ++ state = "MC_STATIC_NRL"; ++ break; ++ case MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY: ++ state = "MC_STATIC_POLICY"; ++ break; ++ case 0xb: case 0xa: case 0x9: case 0x8: ++ /* Reserved for future use */ ++ case 0x3: case 0x2: case 0x1: ++ /* Reserved for future use */ ++ case MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED: ++ default: ++ state = "???"; ++ break; ++ } ++ } else { ++ switch (addr.state) { ++ case MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_PO: ++ state = "UC_STATIC_PO"; ++ break; ++ case MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC: ++ state = "UC_STATIC"; ++ break; ++ case MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_DA_MGMT_PO: ++ state = "UC_STATIC_MGMT_PO"; ++ break; ++ case MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_DA_MGMT: ++ state = "UC_STATIC_MGMT"; ++ break; ++ case MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_AVB_NRL_PO: ++ state = "UC_STATIC_NRL_PO"; ++ break; ++ case MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_AVB_NRL: ++ state = "UC_STATIC_NRL"; ++ break; ++ case MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY_PO: ++ state = "UC_STATIC_POLICY_PO"; ++ break; ++ case MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY: ++ state = "UC_STATIC_POLICY"; ++ break; ++ case MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_7_NEWEST: ++ state = "Age 7 (newest)"; ++ break; ++ case MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_6: ++ state = "Age 6"; ++ break; ++ case MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_5: ++ state = "Age 5"; ++ break; ++ case MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_4: ++ state = "Age 4"; ++ break; ++ case MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_3: ++ state = "Age 3"; ++ break; ++ case MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_2: ++ state = "Age 2"; ++ break; ++ case MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_1_OLDEST: ++ state = "Age 1 (oldest)"; ++ break; ++ case MV88E6XXX_G1_ATU_DATA_STATE_UC_UNUSED: ++ default: ++ state = "???"; ++ break; ++ } ++ } ++ ++ seq_printf(s, " %19s", state); ++ ++ if (addr.trunk) { ++ seq_printf(s, " y %d", ++ addr.portvec); ++ } else { ++ seq_puts(s, " n "); ++ for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) ++ seq_printf(s, " %c", ++ addr.portvec & BIT(i) ? ++ 48 + i : '-'); ++ } ++ ++ seq_puts(s, "\n"); ++ } while (!is_broadcast_ether_addr(addr.mac)); ++ } ++ ++ return 0; ++} ++ ++static ssize_t mv88e6xxx_atu_write(struct file *file, const char __user *buf, ++ size_t count, loff_t *ppos) ++{ ++ struct seq_file *s = file->private_data; ++ struct mv88e6xxx_chip *chip = s->private; ++ char cmd[64]; ++ unsigned int fid; ++ int ret; ++ ++ if (copy_from_user(cmd, buf, sizeof(cmd))) ++ return -EFAULT; ++ ++ ret = sscanf(cmd, "%u", &fid); ++ if (ret != 1) ++ return -EINVAL; ++ ++ if (fid >= mv88e6xxx_num_databases(chip)) ++ return -ERANGE; ++ ++ mutex_lock(&chip->reg_lock); ++ ret = mv88e6xxx_g1_atu_flush(chip, fid, true); ++ mutex_unlock(&chip->reg_lock); ++ ++ return ret < 0 ? ret : count; ++} ++ ++static int mv88e6xxx_atu_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, mv88e6xxx_atu_show, inode->i_private); ++} ++ ++static const struct file_operations mv88e6xxx_atu_fops = { ++ .open = mv88e6xxx_atu_open, ++ .read = seq_read, ++ .write = mv88e6xxx_atu_write, ++ .llseek = no_llseek, ++ .release = single_release, ++ .owner = THIS_MODULE, ++}; ++ ++static int mv88e6xxx_default_vid_show(struct seq_file *s, void *p) ++{ ++ struct mv88e6xxx_chip *chip = s->private; ++ u16 pvid; ++ int i, err; ++ ++ seq_puts(s, " Port DefaultVID\n"); ++ ++ mutex_lock(&chip->reg_lock); ++ ++ for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { ++ err = mv88e6xxx_port_get_pvid(chip, i, &pvid); ++ if (err) ++ break; ++ ++ seq_printf(s, "%4d %d\n", i, pvid); ++ } ++ ++ mutex_unlock(&chip->reg_lock); ++ ++ return err; ++} ++ ++static ssize_t mv88e6xxx_default_vid_write(struct file *file, ++ const char __user *buf, size_t count, ++ loff_t *ppos) ++{ ++ struct seq_file *s = file->private_data; ++ struct mv88e6xxx_chip *chip = s->private; ++ char cmd[32]; ++ unsigned int port, pvid; ++ int ret; ++ ++ if (copy_from_user(cmd, buf, sizeof(cmd))) ++ return -EFAULT; ++ ++ ret = sscanf(cmd, "%u %u", &port, &pvid); ++ if (ret != 2) ++ return -EINVAL; ++ ++ if (port >= mv88e6xxx_num_ports(chip) || pvid > 0xfff) ++ return -ERANGE; ++ ++ mutex_lock(&chip->reg_lock); ++ ret = mv88e6xxx_port_set_pvid(chip, port, pvid); ++ mutex_unlock(&chip->reg_lock); ++ ++ return ret < 0 ? ret : count; ++} ++ ++static int mv88e6xxx_default_vid_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, mv88e6xxx_default_vid_show, inode->i_private); ++} ++ ++static const struct file_operations mv88e6xxx_default_vid_fops = { ++ .open = mv88e6xxx_default_vid_open, ++ .read = seq_read, ++ .write = mv88e6xxx_default_vid_write, ++ .llseek = no_llseek, ++ .release = single_release, ++ .owner = THIS_MODULE, ++}; ++ ++static int mv88e6xxx_fid_show(struct seq_file *s, void *p) ++{ ++ struct mv88e6xxx_chip *chip = s->private; ++ u16 fid; ++ int i, err; ++ ++ seq_puts(s, " Port FID\n"); ++ ++ mutex_lock(&chip->reg_lock); ++ ++ for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { ++ err = mv88e6xxx_port_get_fid(chip, i, &fid); ++ if (err) ++ break; ++ ++ seq_printf(s, "%4d %d\n", i, fid); ++ } ++ ++ mutex_unlock(&chip->reg_lock); ++ ++ return err; ++} ++ ++static int mv88e6xxx_fid_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, mv88e6xxx_fid_show, inode->i_private); ++} ++ ++static const struct file_operations mv88e6xxx_fid_fops = { ++ .open = mv88e6xxx_fid_open, ++ .read = seq_read, ++ .llseek = no_llseek, ++ .release = single_release, ++ .owner = THIS_MODULE, ++}; ++ ++static const char * const mv88e6xxx_port_state_names[] = { ++ [MV88E6XXX_PORT_CTL0_STATE_DISABLED] = "Disabled", ++ [MV88E6XXX_PORT_CTL0_STATE_BLOCKING] = "Blocking/Listening", ++ [MV88E6XXX_PORT_CTL0_STATE_LEARNING] = "Learning", ++ [MV88E6XXX_PORT_CTL0_STATE_FORWARDING] = "Forwarding", ++}; ++ ++static int mv88e6xxx_state_show(struct seq_file *s, void *p) ++{ ++ struct mv88e6xxx_chip *chip = s->private; ++ int i, ret; ++ u16 data; ++ ++ /* header */ ++ seq_puts(s, " Port Mode\n"); ++ ++ mutex_lock(&chip->reg_lock); ++ ++ /* One line per input port */ ++ for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { ++ seq_printf(s, "%4d ", i); ++ ++ ret = mv88e6xxx_port_read(chip, i, MV88E6XXX_PORT_CTL0, &data); ++ if (ret < 0) ++ goto unlock; ++ ++ data &= MV88E6XXX_PORT_CTL0_STATE_MASK; ++ seq_printf(s, " %s\n", mv88e6xxx_port_state_names[data]); ++ ret = 0; ++ } ++ ++unlock: ++ mutex_unlock(&chip->reg_lock); ++ ++ return ret; ++} ++ ++static int mv88e6xxx_state_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, mv88e6xxx_state_show, inode->i_private); ++} ++ ++static const struct file_operations mv88e6xxx_state_fops = { ++ .open = mv88e6xxx_state_open, ++ .read = seq_read, ++ .llseek = no_llseek, ++ .release = single_release, ++ .owner = THIS_MODULE, ++}; ++ ++static const char * const mv88e6xxx_port_8021q_mode_names[] = { ++ [MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED] = "Disabled", ++ [MV88E6XXX_PORT_CTL2_8021Q_MODE_FALLBACK] = "Fallback", ++ [MV88E6XXX_PORT_CTL2_8021Q_MODE_CHECK] = "Check", ++ [MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE] = "Secure", ++}; ++ ++static int mv88e6xxx_8021q_mode_show(struct seq_file *s, void *p) ++{ ++ struct mv88e6xxx_chip *chip = s->private; ++ int i, ret; ++ u16 data; ++ ++ /* header */ ++ seq_puts(s, " Port Mode\n"); ++ ++ mutex_lock(&chip->reg_lock); ++ ++ /* One line per input port */ ++ for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { ++ seq_printf(s, "%4d ", i); ++ ++ ret = mv88e6xxx_port_read(chip, i, MV88E6XXX_PORT_CTL2, &data); ++ if (ret < 0) ++ goto unlock; ++ ++ data &= MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK; ++ seq_printf(s, " %s\n", mv88e6xxx_port_8021q_mode_names[data]); ++ ret = 0; ++ } ++ ++unlock: ++ mutex_unlock(&chip->reg_lock); ++ ++ return ret; ++} ++ ++static int mv88e6xxx_8021q_mode_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, mv88e6xxx_8021q_mode_show, inode->i_private); ++} ++ ++static const struct file_operations mv88e6xxx_8021q_mode_fops = { ++ .open = mv88e6xxx_8021q_mode_open, ++ .read = seq_read, ++ .llseek = no_llseek, ++ .release = single_release, ++ .owner = THIS_MODULE, ++}; ++ ++static int mv88e6xxx_vlan_table_show(struct seq_file *s, void *p) ++{ ++ struct mv88e6xxx_chip *chip = s->private; ++ int i, j, ret; ++ u16 data; ++ ++ /* header */ ++ seq_puts(s, " Port"); ++ for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) ++ seq_printf(s, " %2d", i); ++ seq_puts(s, "\n"); ++ ++ mutex_lock(&chip->reg_lock); ++ ++ /* One line per input port */ ++ for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { ++ seq_printf(s, "%4d ", i); ++ ++ ret = mv88e6xxx_port_read(chip, i, MV88E6XXX_PORT_BASE_VLAN, &data); ++ if (ret < 0) ++ goto unlock; ++ ++ /* One column per output port */ ++ for (j = 0; j < mv88e6xxx_num_ports(chip); ++j) ++ seq_printf(s, " %c", data & BIT(j) ? '*' : '-'); ++ seq_puts(s, "\n"); ++ } ++ ++ ret = 0; ++unlock: ++ mutex_unlock(&chip->reg_lock); ++ ++ return ret; ++} ++ ++static int mv88e6xxx_vlan_table_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, mv88e6xxx_vlan_table_show, inode->i_private); ++} ++ ++static const struct file_operations mv88e6xxx_vlan_table_fops = { ++ .open = mv88e6xxx_vlan_table_open, ++ .read = seq_read, ++ .llseek = no_llseek, ++ .release = single_release, ++ .owner = THIS_MODULE, ++}; ++ ++static int mv88e6xxx_pvt_show(struct seq_file *s, void *p) ++{ ++ struct mv88e6xxx_chip *chip = s->private; ++ struct dsa_switch_tree *dst = chip->ds->dst; ++ int port, src_dev, src_port; ++ u16 pvlan; ++ int err = 0; ++ ++ if (chip->info->family == MV88E6XXX_FAMILY_6185) ++ return -ENODEV; ++ ++ /* header */ ++ seq_puts(s, " Dev Port PVLAN"); ++ for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) ++ seq_printf(s, " %2d", port); ++ seq_puts(s, "\n"); ++ ++ mutex_lock(&chip->reg_lock); ++ ++ /* One line per external port */ ++ for (src_dev = 0; src_dev < DSA_MAX_SWITCHES; ++src_dev) { ++ if (!dst->ds[src_dev]) ++ break; ++ ++ if (src_dev == chip->ds->index) ++ continue; ++ ++ seq_puts(s, "\n"); ++ for (src_port = 0; src_port < 16; ++src_port) { ++ if (src_port >= DSA_MAX_PORTS) ++ break; ++ ++ err = _mv88e6xxx_pvt_read(chip, src_dev, src_port, ++ &pvlan); ++ if (err) ++ goto unlock; ++ ++ seq_printf(s, " %d %2d %03hhx ", src_dev, src_port, ++ pvlan); ++ ++ /* One column per internal output port */ ++ for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) ++ seq_printf(s, " %c", ++ pvlan & BIT(port) ? '*' : '-'); ++ seq_puts(s, "\n"); ++ } ++ } ++ ++unlock: ++ mutex_unlock(&chip->reg_lock); ++ ++ return err; ++} ++ ++static ssize_t mv88e6xxx_pvt_write(struct file *file, const char __user *buf, ++ size_t count, loff_t *ppos) ++{ ++ struct seq_file *s = file->private_data; ++ struct mv88e6xxx_chip *chip = s->private; ++ const u16 mask = (1 << mv88e6xxx_num_ports(chip)) - 1; ++ char cmd[32]; ++ unsigned int src_dev, src_port, pvlan; ++ int ret; ++ ++ if (copy_from_user(cmd, buf, sizeof(cmd))) ++ return -EFAULT; ++ ++ if (sscanf(cmd, "%d %d %x", &src_dev, &src_port, &pvlan) != 3) ++ return -EINVAL; ++ ++ if (src_dev >= 32 || src_port >= 16 || pvlan & ~mask) ++ return -ERANGE; ++ ++ mutex_lock(&chip->reg_lock); ++ ret = _mv88e6xxx_pvt_write(chip, src_dev, src_port, pvlan); ++ mutex_unlock(&chip->reg_lock); ++ ++ return ret < 0 ? ret : count; ++} ++ ++static int mv88e6xxx_pvt_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, mv88e6xxx_pvt_show, inode->i_private); ++} ++ ++static const struct file_operations mv88e6xxx_pvt_fops = { ++ .open = mv88e6xxx_pvt_open, ++ .read = seq_read, ++ .write = mv88e6xxx_pvt_write, ++ .llseek = no_llseek, ++ .release = single_release, ++ .owner = THIS_MODULE, ++}; ++ ++static int mv88e6xxx_vtu_show(struct seq_file *s, void *p) ++{ ++ struct mv88e6xxx_chip *chip = s->private; ++ struct mv88e6xxx_vtu_entry next = { 0 }; ++ int port, ret = 0; ++ ++ seq_puts(s, " VID FID SID"); ++ for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) ++ seq_printf(s, " %2d", port); ++ seq_puts(s, "\n"); ++ ++ if (!chip->info->ops->vtu_getnext) ++ return 0; ++ ++ next.vid = chip->info->max_vid; /* first or lowest VID */ ++ ++ do { ++ mutex_lock(&chip->reg_lock); ++ ret = chip->info->ops->vtu_getnext(chip, &next); ++ mutex_unlock(&chip->reg_lock); ++ if (ret < 0) ++ break; ++ ++ if (!next.valid) ++ break; ++ ++ seq_printf(s, "%4d %4d %2d", next.vid, next.fid, next.sid); ++ for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) { ++ switch (next.member[port]) { ++ case MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED: ++ seq_puts(s, " ="); ++ break; ++ case MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED: ++ seq_puts(s, " u"); ++ break; ++ case MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED: ++ seq_puts(s, " t"); ++ break; ++ case MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER: ++ seq_puts(s, " x"); ++ break; ++ default: ++ seq_puts(s, " ??"); ++ break; ++ } ++ } ++ seq_puts(s, "\n"); ++ } while (next.vid < chip->info->max_vid); ++ ++ return ret; ++} ++ ++static ssize_t mv88e6xxx_vtu_write(struct file *file, const char __user *buf, ++ size_t count, loff_t *ppos) ++{ ++ struct seq_file *s = file->private_data; ++ struct mv88e6xxx_chip *chip = s->private; ++ struct mv88e6xxx_vtu_entry entry = { 0 }; ++ bool valid = true; ++ char cmd[64], tags[12]; /* DSA_MAX_PORTS */ ++ int vid, fid, sid, port, ret; ++ ++ if (!chip->info->ops->vtu_loadpurge) ++ return -EOPNOTSUPP; ++ ++ if (copy_from_user(cmd, buf, sizeof(cmd))) ++ return -EFAULT; ++ ++ /* scan 12 chars instead of num_ports to avoid dynamic scanning... */ ++ ret = sscanf(cmd, "%d %d %d %c %c %c %c %c %c %c %c %c %c %c %c", &vid, ++ &fid, &sid, &tags[0], &tags[1], &tags[2], &tags[3], ++ &tags[4], &tags[5], &tags[6], &tags[7], &tags[8], &tags[9], ++ &tags[10], &tags[11]); ++ if (ret == 1) ++ valid = false; ++ else if (ret != 3 + mv88e6xxx_num_ports(chip)) ++ return -EINVAL; ++ ++ entry.vid = vid; ++ entry.valid = valid; ++ ++ if (valid) { ++ entry.fid = fid; ++ entry.sid = sid; ++ /* Note: The VTU entry pointed by VID will be loaded but not ++ * considered valid until the STU entry pointed by SID is valid. ++ */ ++ ++ for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) { ++ u8 tag; ++ ++ switch (tags[port]) { ++ case 'u': ++ tag = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; ++ break; ++ case 't': ++ tag = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; ++ break; ++ case 'x': ++ tag = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; ++ break; ++ case '=': ++ tag = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ entry.member[port] = tag; ++ } ++ } ++ ++ mutex_lock(&chip->reg_lock); ++ ret = chip->info->ops->vtu_loadpurge(chip, &entry); ++ mutex_unlock(&chip->reg_lock); ++ ++ return ret < 0 ? ret : count; ++} ++ ++static int mv88e6xxx_vtu_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, mv88e6xxx_vtu_show, inode->i_private); ++} ++ ++static const struct file_operations mv88e6xxx_vtu_fops = { ++ .open = mv88e6xxx_vtu_open, ++ .read = seq_read, ++ .write = mv88e6xxx_vtu_write, ++ .llseek = no_llseek, ++ .release = single_release, ++ .owner = THIS_MODULE, ++}; ++#if 0 ++static int mv88e6xxx_stats_show(struct seq_file *s, void *p) ++{ ++ struct mv88e6xxx_chip *chip = s->private; ++ char *strs; ++ u64 *stats; ++ int stat, port, num_stats, num_ports; ++ int err = 0; ++ ++ num_stats = mv88e6xxx_get_sset_count(chip->ds); ++ if (num_stats == 0) ++ return 0; ++ ++ num_ports = mv88e6xxx_num_ports(chip); ++ ++ strs = kcalloc(num_stats, ETH_GSTRING_LEN, GFP_KERNEL); ++ stats = kcalloc(num_stats, num_ports * sizeof(*stats), GFP_KERNEL); ++ if (!strs || !strs) { ++ kfree(strs); ++ kfree(stats); ++ return -ENOMEM; ++ } ++ ++ mv88e6xxx_get_strings(chip->ds, 0, strs); ++ ++ for (port = 0; port < num_ports; port++) ++ mv88e6xxx_get_ethtool_stats(chip->ds, port, stats + (port * num_stats)); ++ ++ seq_puts(s, " Statistic "); ++ for (port = 0; port < mv88e6xxx_num_ports(chip); port++) ++ seq_printf(s, " Port %2d ", port); ++ seq_puts(s, "\n"); ++ ++ for (stat = 0; stat < num_stats; stat++) { ++ seq_printf(s, "%19s: ", strs + stat * ETH_GSTRING_LEN); ++ for (port = 0 ; port < num_ports; port++) { ++ u64 value = stats[stat + port * num_stats]; ++ ++ seq_printf(s, "%8llu ", value); ++ } ++ seq_puts(s, "\n"); ++ } ++ ++ kfree(stats); ++ kfree(strs); ++ ++ return err; ++} ++ ++static int mv88e6xxx_stats_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, mv88e6xxx_stats_show, inode->i_private); ++} ++ ++static const struct file_operations mv88e6xxx_stats_fops = { ++ .open = mv88e6xxx_stats_open, ++ .read = seq_read, ++ .llseek = no_llseek, ++ .release = single_release, ++ .owner = THIS_MODULE, ++}; ++#endif ++static int mv88e6xxx_device_map_show(struct seq_file *s, void *p) ++{ ++ struct mv88e6xxx_chip *chip = s->private; ++ int target, ret; ++ u16 data, port_mask; ++ ++ seq_puts(s, "Target Port\n"); ++ ++ /* FIXME */ ++ port_mask = MV88E6390_G2_DEVICE_MAPPING_PORT_MASK; ++ ++ mutex_lock(&chip->reg_lock); ++ for (target = 0; target < 32; target++) { ++ ret = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_DEVICE_MAPPING, ++ target << 8 /* MV88E6XXX_G2_DEVICE_MAPPING_DEV_MASK */); ++ if (ret < 0) ++ goto out; ++ ret = mv88e6xxx_g2_read(chip, MV88E6XXX_G2_DEVICE_MAPPING, &data); ++ if (ret < 0) ++ goto out; ++ seq_printf(s, " %2d %2d\n", target, data & port_mask); ++ } ++out: ++ mutex_unlock(&chip->reg_lock); ++ ++ return 0; ++} ++ ++static int mv88e6xxx_device_map_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, mv88e6xxx_device_map_show, inode->i_private); ++} ++ ++static const struct file_operations mv88e6xxx_device_map_fops = { ++ .open = mv88e6xxx_device_map_open, ++ .read = seq_read, ++ .llseek = no_llseek, ++ .release = single_release, ++ .owner = THIS_MODULE, ++}; ++ ++/* Must be called with SMI lock held */ ++static int _mv88e6xxx_scratch_wait(struct mv88e6xxx_chip *chip) ++{ ++ return mv88e6xxx_wait_mask(chip, ADDR_GLOBAL2, ++ MV88E6XXX_G2_SCRATCH_MISC_MISC, ++ MV88E6XXX_G2_SCRATCH_MISC_UPDATE, 0); ++} ++ ++static int mv88e6xxx_scratch_show(struct seq_file *s, void *p) ++{ ++ struct mv88e6xxx_chip *chip = s->private; ++ int reg, ret; ++ u16 data; ++ ++ seq_puts(s, "Register Value\n"); ++ ++ mutex_lock(&chip->reg_lock); ++ for (reg = 0; reg < 0x80; reg++) { ++ ret = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_SCRATCH_MISC_MISC, ++ reg << 8 /* MV88E6XXX_G2_SCRATCH_MISC_PTR_MASK */); ++ if (ret < 0) ++ goto out; ++ ++ ret = _mv88e6xxx_scratch_wait(chip); ++ if (ret < 0) ++ goto out; ++ ++ ret = mv88e6xxx_g2_read(chip, MV88E6XXX_G2_SCRATCH_MISC_MISC, &data); ++ seq_printf(s, " %2x %2x\n", reg, ++ data & MV88E6XXX_G2_SCRATCH_MISC_DATA_MASK); ++ } ++out: ++ mutex_unlock(&chip->reg_lock); ++ ++ return 0; ++} ++ ++static int mv88e6xxx_scratch_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, mv88e6xxx_scratch_show, inode->i_private); ++} ++ ++static const struct file_operations mv88e6xxx_scratch_fops = { ++ .open = mv88e6xxx_scratch_open, ++ .read = seq_read, ++ .llseek = no_llseek, ++ .release = single_release, ++ .owner = THIS_MODULE, ++}; ++ ++static void mv88e6xxx_init_debugfs(struct mv88e6xxx_chip *chip) ++{ ++ char *name; ++ ++ name = kasprintf(GFP_KERNEL, "mv88e6xxx.%d", chip->ds->index); ++ chip->dbgfs = debugfs_create_dir(name, NULL); ++ ++ kfree(name); ++ ++ debugfs_create_file("regs", S_IRUGO | S_IWUSR, chip->dbgfs, chip, ++ &mv88e6xxx_regs_fops); ++ ++ debugfs_create_file("name", S_IRUGO, chip->dbgfs, chip, ++ &mv88e6xxx_name_fops); ++ ++ debugfs_create_file("atu", S_IRUGO | S_IWUSR, chip->dbgfs, chip, ++ &mv88e6xxx_atu_fops); ++ ++ debugfs_create_file("default_vid", S_IRUGO | S_IWUSR, chip->dbgfs, chip, ++ &mv88e6xxx_default_vid_fops); ++ ++ debugfs_create_file("fid", S_IRUGO, chip->dbgfs, chip, &mv88e6xxx_fid_fops); ++ ++ debugfs_create_file("state", S_IRUGO, chip->dbgfs, chip, ++ &mv88e6xxx_state_fops); ++ ++ debugfs_create_file("8021q_mode", S_IRUGO, chip->dbgfs, chip, ++ &mv88e6xxx_8021q_mode_fops); ++ ++ debugfs_create_file("vlan_table", S_IRUGO, chip->dbgfs, chip, ++ &mv88e6xxx_vlan_table_fops); ++ ++ debugfs_create_file("pvt", S_IRUGO | S_IWUSR, chip->dbgfs, chip, ++ &mv88e6xxx_pvt_fops); ++ ++ debugfs_create_file("vtu", S_IRUGO | S_IWUSR, chip->dbgfs, chip, ++ &mv88e6xxx_vtu_fops); ++#if 0 ++ debugfs_create_file("stats", S_IRUGO, chip->dbgfs, chip, ++ &mv88e6xxx_stats_fops); ++#endif ++ debugfs_create_file("device_map", S_IRUGO, chip->dbgfs, chip, ++ &mv88e6xxx_device_map_fops); ++ ++ debugfs_create_file("scratch", S_IRUGO, chip->dbgfs, chip, ++ &mv88e6xxx_scratch_fops); ++} ++ ++static void mv88e6xxx_remove_debugfs(struct mv88e6xxx_chip *chip) ++{ ++ debugfs_remove_recursive(chip->dbgfs); ++} +-- +cgit v1.2.3 +From ee71c167800c79ed367a6cb8d0efb4e2cfffabf7 Mon Sep 17 00:00:00 2001 +From: Russell King +Date: Mon, 27 Jan 2020 14:00:12 +0000 +Subject: net: dsa: mv88e6xxx: debugfs hacks to fix the compile + +This is the problem with out-of-tree maintained patches; they break, +sometimes requiring substantial rework. It's all very well promising +to publish new versions as that happens, but it causes pain when they +aren't published in a timely manner. Hence this hack. + +Signed-off-by: Russell King +--- + drivers/net/dsa/mv88e6xxx/mv88e6xxx_debugfs.c | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +diff --git a/drivers/net/dsa/mv88e6xxx/mv88e6xxx_debugfs.c b/drivers/net/dsa/mv88e6xxx/mv88e6xxx_debugfs.c +index 931e769fe9ce..4005a4760884 100644 +--- a/drivers/net/dsa/mv88e6xxx/mv88e6xxx_debugfs.c ++++ b/drivers/net/dsa/mv88e6xxx/mv88e6xxx_debugfs.c +@@ -668,6 +668,7 @@ static const struct file_operations mv88e6xxx_vlan_table_fops = { + + static int mv88e6xxx_pvt_show(struct seq_file *s, void *p) + { ++#if 0 + struct mv88e6xxx_chip *chip = s->private; + struct dsa_switch_tree *dst = chip->ds->dst; + int port, src_dev, src_port; +@@ -716,8 +717,10 @@ static int mv88e6xxx_pvt_show(struct seq_file *s, void *p) + + unlock: + mutex_unlock(&chip->reg_lock); +- + return err; ++#else ++ return 0; ++#endif + } + + static ssize_t mv88e6xxx_pvt_write(struct file *file, const char __user *buf, +-- +cgit v1.2.3 +From 04bcd6e51433052a79feb37fe6d02c9c06980d62 Mon Sep 17 00:00:00 2001 +From: Russell King +Date: Thu, 28 Sep 2017 12:09:56 +0100 +Subject: Revert "net: dsa: mv88e6xxx: remove LED control register" + +This reverts commit c56a71a92114e3198e249593841cb744abaadcb7. +--- + drivers/net/dsa/mv88e6xxx/port.h | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/drivers/net/dsa/mv88e6xxx/port.h b/drivers/net/dsa/mv88e6xxx/port.h +index b10e5aebacf6..bfc37d152f4d 100644 +--- a/drivers/net/dsa/mv88e6xxx/port.h ++++ b/drivers/net/dsa/mv88e6xxx/port.h +@@ -282,6 +282,9 @@ + /* Offset 0x13: OutFiltered Counter */ + #define MV88E6XXX_PORT_OUT_FILTERED 0x13 + ++/* Offset 0x16: LED Control */ ++#define MV88E6XXX_PORT_LED_CONTROL 0x16 ++ + /* Offset 0x18: IEEE Priority Mapping Table */ + #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE 0x18 + #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_UPDATE 0x8000 +-- +cgit v1.2.3 +From e43ea2d687d58c0df5ca0334fe99385664b38431 Mon Sep 17 00:00:00 2001 +From: Russell King +Date: Sat, 7 Jan 2017 20:47:36 +0000 +Subject: net: dsa: program 6176 LED registers + +Signed-off-by: Russell King +--- + drivers/net/dsa/mv88e6xxx/chip.c | 20 ++++++++++++++++++++ + 1 file changed, 20 insertions(+) + +diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c +index 34b7f057a80d..ff4d9cf2fbd1 100644 +--- a/drivers/net/dsa/mv88e6xxx/chip.c ++++ b/drivers/net/dsa/mv88e6xxx/chip.c +@@ -2720,6 +2720,20 @@ static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) + return 0; + } + ++static int mv88e6xxx_setup_led(struct mv88e6xxx_chip *chip, int port) ++{ ++ int err; ++ ++ /* LED0 = link/activity, LED1 = 10/100 */ ++ err = mv88e6xxx_wait_bit(chip, chip->info->port_base_addr + port, ++ MV88E6XXX_PORT_LED_CONTROL, 15, 0); ++ if (err) ++ return err; ++ ++ return mv88e6xxx_write(chip, chip->info->port_base_addr + port, ++ MV88E6XXX_PORT_LED_CONTROL, 0x80b3); ++} ++ + static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) + { + struct dsa_switch *ds = chip->ds; +@@ -2775,6 +2789,12 @@ static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) + if (err) + return err; + ++ if (chip->info->num_gpio) { ++ err = mv88e6xxx_setup_led(chip, port); ++ if (err) ++ return err; ++ } ++ + /* Port Control 2: don't force a good FCS, set the MTU size to + * 10222 bytes, disable 802.1q tags checking, don't discard tagged or + * untagged frames on this port, do a destination address lookup on all +-- +cgit v1.2.3 +From 0732f844ba9e295c78a911016fec9f00b14a8f59 Mon Sep 17 00:00:00 2001 +From: Russell King +Date: Wed, 8 Jul 2020 12:31:01 +0100 +Subject: net: dsa/mv88e6xxx: add support for rate-matching PHYs + +Add basic support for rate-matching 10G PHYs for mv88e6xxx - if we are +in RXAUI, XAUI or 10GBASE-R mode, the link speed is 10G, even if the +media is running at a slower speed. + +Signed-off-by: Russell King +--- + drivers/net/dsa/mv88e6xxx/chip.c | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c +index ff4d9cf2fbd1..5925d5402306 100644 +--- a/drivers/net/dsa/mv88e6xxx/chip.c ++++ b/drivers/net/dsa/mv88e6xxx/chip.c +@@ -784,6 +784,18 @@ static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port, + if (err) + goto error; + ++ /* The link parameters passed in are the media side parameters. ++ * If in RXAUI, XAUI or 10GBASE-R with a rate matching PHY, we ++ * need to operate our link at 10G. Only full duplex is ++ * supported at this speed. ++ */ ++ if (interface == PHY_INTERFACE_MODE_RXAUI || ++ interface == PHY_INTERFACE_MODE_XAUI || ++ interface == PHY_INTERFACE_MODE_10GBASER) { ++ speed = SPEED_10000; ++ duplex = DUPLEX_FULL; ++ } ++ + if (ops->port_set_speed_duplex) { + err = ops->port_set_speed_duplex(chip, port, + speed, duplex); +-- +cgit v1.2.3 + + diff --git a/patch/kernel/archive/mvebu-5.16/412-ARM-dts-armada388-clearfog-emmc-on-clearfog-base.patch b/patch/kernel/archive/mvebu-5.16/412-ARM-dts-armada388-clearfog-emmc-on-clearfog-base.patch new file mode 100644 index 0000000000..dd2bef7f63 --- /dev/null +++ b/patch/kernel/archive/mvebu-5.16/412-ARM-dts-armada388-clearfog-emmc-on-clearfog-base.patch @@ -0,0 +1,87 @@ +From 8137da20701c776ad3481115305a5e8e410871ba Mon Sep 17 00:00:00 2001 +From: Russell King +Date: Tue, 29 Nov 2016 10:15:45 +0000 +Subject: ARM: dts: armada388-clearfog: emmc on clearfog base + +Signed-off-by: Russell King +--- + arch/arm/boot/dts/armada-388-clearfog-base.dts | 1 + + .../dts/armada-38x-solidrun-microsom-emmc.dtsi | 62 ++++++++++++++++++++++ + 2 files changed, 63 insertions(+) + create mode 100644 arch/arm/boot/dts/armada-38x-solidrun-microsom-emmc.dtsi + +--- a/arch/arm/boot/dts/armada-388-clearfog-base.dts ++++ b/arch/arm/boot/dts/armada-388-clearfog-base.dts +@@ -7,6 +7,7 @@ + + /dts-v1/; + #include "armada-388-clearfog.dtsi" ++#include "armada-38x-solidrun-microsom-emmc.dtsi" + + / { + model = "SolidRun Clearfog Base A1"; +--- /dev/null ++++ b/arch/arm/boot/dts/armada-38x-solidrun-microsom-emmc.dtsi +@@ -0,0 +1,62 @@ ++/* ++ * Device Tree file for SolidRun Armada 38x Microsom add-on for eMMC ++ * ++ * Copyright (C) 2015 Russell King ++ * ++ * This board is in development; the contents of this file work with ++ * the A1 rev 2.0 of the board, which does not represent final ++ * production board. Things will change, don't expect this file to ++ * remain compatible info the future. ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This file is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * version 2 as published by the Free Software Foundation. ++ * ++ * This file is distributed in the hope that it will be useful ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++/ { ++ soc { ++ internal-regs { ++ sdhci@d8000 { ++ bus-width = <4>; ++ no-1-8-v; ++ non-removable; ++ pinctrl-0 = <µsom_sdhci_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ wp-inverted; ++ }; ++ }; ++ }; ++}; diff --git a/patch/kernel/archive/mvebu-5.16/91-01-libata-add-ledtrig-support.patch b/patch/kernel/archive/mvebu-5.16/91-01-libata-add-ledtrig-support.patch new file mode 100644 index 0000000000..a52e712d8c --- /dev/null +++ b/patch/kernel/archive/mvebu-5.16/91-01-libata-add-ledtrig-support.patch @@ -0,0 +1,149 @@ +From: Daniel Golle +Subject: libata: add ledtrig support + +This adds a LED trigger for each ATA port indicating disk activity. + +As this is needed only on specific platforms (NAS SoCs and such), +these platforms should define ARCH_WANTS_LIBATA_LEDS if there +are boards with LED(s) intended to indicate ATA disk activity and +need the OS to take care of that. +In that way, if not selected, LED trigger support not will be +included in libata-core and both, codepaths and structures remain +untouched. + +Signed-off-by: Daniel Golle +--- + drivers/ata/Kconfig | 16 ++++++++++++++++ + drivers/ata/libata-core.c | 41 +++++++++++++++++++++++++++++++++++++++++ + include/linux/libata.h | 9 +++++++++ + 3 files changed, 66 insertions(+) + +--- a/drivers/ata/Kconfig ++++ b/drivers/ata/Kconfig +@@ -67,6 +67,22 @@ config ATA_FORCE + + If unsure, say Y. + ++config ARCH_WANT_LIBATA_LEDS ++ bool ++ ++config ATA_LEDS ++ bool "support ATA port LED triggers" ++ depends on ARCH_WANT_LIBATA_LEDS ++ select NEW_LEDS ++ select LEDS_CLASS ++ select LEDS_TRIGGERS ++ default y ++ help ++ This option adds a LED trigger for each registered ATA port. ++ It is used to drive disk activity leds connected via GPIO. ++ ++ If unsure, say N. ++ + config ATA_ACPI + bool "ATA ACPI Support" + depends on ACPI +--- a/drivers/ata/libata-core.c ++++ b/drivers/ata/libata-core.c +@@ -650,6 +650,19 @@ u64 ata_tf_read_block(const struct ata_t + return block; + } + ++#ifdef CONFIG_ATA_LEDS ++#define LIBATA_BLINK_DELAY 20 /* ms */ ++static inline void ata_led_act(struct ata_port *ap) ++{ ++ unsigned long led_delay = LIBATA_BLINK_DELAY; ++ ++ if (unlikely(!ap->ledtrig)) ++ return; ++ ++ led_trigger_blink_oneshot(ap->ledtrig, &led_delay, &led_delay, 0); ++} ++#endif ++ + /** + * ata_build_rw_tf - Build ATA taskfile for given read/write request + * @tf: Target ATA taskfile +@@ -4513,6 +4526,9 @@ struct ata_queued_cmd *ata_qc_new_init(s + if (tag < 0) + return NULL; + } ++#ifdef CONFIG_ATA_LEDS ++ ata_led_act(ap); ++#endif + + qc = __ata_qc_from_tag(ap, tag); + qc->tag = qc->hw_tag = tag; +@@ -5291,6 +5307,9 @@ struct ata_port *ata_port_alloc(struct a + ap->stats.unhandled_irq = 1; + ap->stats.idle_irq = 1; + #endif ++#ifdef CONFIG_ATA_LEDS ++ ap->ledtrig = kzalloc(sizeof(struct led_trigger), GFP_KERNEL); ++#endif + ata_sff_port_init(ap); + + return ap; +@@ -5326,6 +5345,12 @@ static void ata_host_release(struct kref + + kfree(ap->pmp_link); + kfree(ap->slave_link); ++#ifdef CONFIG_ATA_LEDS ++ if (ap->ledtrig) { ++ led_trigger_unregister(ap->ledtrig); ++ kfree(ap->ledtrig); ++ }; ++#endif + kfree(ap); + host->ports[i] = NULL; + } +@@ -5732,7 +5757,23 @@ int ata_host_register(struct ata_host *h + host->ports[i]->print_id = atomic_inc_return(&ata_print_id); + host->ports[i]->local_port_no = i + 1; + } ++#ifdef CONFIG_ATA_LEDS ++ for (i = 0; i < host->n_ports; i++) { ++ if (unlikely(!host->ports[i]->ledtrig)) ++ continue; + ++ snprintf(host->ports[i]->ledtrig_name, ++ sizeof(host->ports[i]->ledtrig_name), "ata%u", ++ host->ports[i]->print_id); ++ ++ host->ports[i]->ledtrig->name = host->ports[i]->ledtrig_name; ++ ++ if (led_trigger_register(host->ports[i]->ledtrig)) { ++ kfree(host->ports[i]->ledtrig); ++ host->ports[i]->ledtrig = NULL; ++ } ++ } ++#endif + /* Create associated sysfs transport objects */ + for (i = 0; i < host->n_ports; i++) { + rc = ata_tport_add(host->dev,host->ports[i]); +--- a/include/linux/libata.h ++++ b/include/linux/libata.h +@@ -23,6 +23,9 @@ + #include + #include + #include ++#ifdef CONFIG_ATA_LEDS ++#include ++#endif + + /* + * Define if arch has non-standard setup. This is a _PCI_ standard +@@ -882,6 +885,12 @@ struct ata_port { + #ifdef CONFIG_ATA_ACPI + struct ata_acpi_gtm __acpi_init_gtm; /* use ata_acpi_init_gtm() */ + #endif ++ ++#ifdef CONFIG_ATA_LEDS ++ struct led_trigger *ledtrig; ++ char ledtrig_name[8]; ++#endif ++ + /* owned by EH */ + u8 sector_buf[ATA_SECT_SIZE] ____cacheline_aligned; + }; diff --git a/patch/kernel/archive/mvebu-5.16/91-02-Enable-ATA-port-LED-trigger.patch b/patch/kernel/archive/mvebu-5.16/91-02-Enable-ATA-port-LED-trigger.patch new file mode 100644 index 0000000000..10680f98cb --- /dev/null +++ b/patch/kernel/archive/mvebu-5.16/91-02-Enable-ATA-port-LED-trigger.patch @@ -0,0 +1,30 @@ +From 9ee6345ef82f7af5f98e17a40e667f8ad6b2fa1b Mon Sep 17 00:00:00 2001 +From: aprayoga +Date: Sun, 3 Sep 2017 18:10:12 +0800 +Subject: Enable ATA port LED trigger + +--- + arch/arm/configs/mvebu_v7_defconfig | 1 + + arch/arm/mach-mvebu/Kconfig | 1 + + 2 files changed, 2 insertions(+) + +--- a/arch/arm/configs/mvebu_v7_defconfig ++++ b/arch/arm/configs/mvebu_v7_defconfig +@@ -58,6 +58,7 @@ CONFIG_MTD_UBI=y + CONFIG_EEPROM_AT24=y + CONFIG_BLK_DEV_SD=y + CONFIG_ATA=y ++CONFIG_ATA_LEDS=y + CONFIG_SATA_AHCI=y + CONFIG_AHCI_MVEBU=y + CONFIG_SATA_MV=y +--- a/arch/arm/mach-mvebu/Kconfig ++++ b/arch/arm/mach-mvebu/Kconfig +@@ -56,6 +56,7 @@ config MACH_ARMADA_375 + config MACH_ARMADA_38X + bool "Marvell Armada 380/385 boards" + depends on ARCH_MULTI_V7 ++ select ARCH_WANT_LIBATA_LEDS + select ARM_ERRATA_720789 + select PL310_ERRATA_753970 + select ARM_GIC diff --git a/patch/kernel/archive/mvebu-5.16/92-mvebu-gpio-add_wake_on_gpio_support.patch b/patch/kernel/archive/mvebu-5.16/92-mvebu-gpio-add_wake_on_gpio_support.patch new file mode 100644 index 0000000000..9274f2b1a1 --- /dev/null +++ b/patch/kernel/archive/mvebu-5.16/92-mvebu-gpio-add_wake_on_gpio_support.patch @@ -0,0 +1,88 @@ +--- a/drivers/gpio/gpio-mvebu.c ++++ b/drivers/gpio/gpio-mvebu.c +@@ -40,6 +40,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -111,7 +112,7 @@ struct mvebu_gpio_chip { + struct regmap *regs; + u32 offset; + struct regmap *percpu_regs; +- int irqbase; ++ int bank_irq[4]; + struct irq_domain *domain; + int soc_variant; + +@@ -601,6 +602,33 @@ static void mvebu_gpio_irq_handler(struc + } + + /* ++ * Set interrupt number "irq" in the GPIO as a wake-up source. ++ * While system is running, all registered GPIO interrupts need to have ++ * wake-up enabled. When system is suspended, only selected GPIO interrupts ++ * need to have wake-up enabled. ++ * @param irq interrupt source number ++ * @param enable enable as wake-up if equal to non-zero ++ * @return This function returns 0 on success. ++ */ ++static int mvebu_gpio_set_wake_irq(struct irq_data *d, unsigned int enable) ++{ ++ struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); ++ struct mvebu_gpio_chip *mvchip = gc->private; ++ int irq; ++ int bank; ++ ++ bank = d->hwirq % 8; ++ irq = mvchip->bank_irq[bank]; ++ ++ if (enable) ++ enable_irq_wake(irq); ++ else ++ disable_irq_wake(irq); ++ ++ return 0; ++} ++ ++/* + * Functions implementing the pwm_chip methods + */ + static struct mvebu_pwm *to_mvebu_pwm(struct pwm_chip *chip) +@@ -1219,7 +1247,7 @@ static int mvebu_gpio_probe(struct platf + + err = irq_alloc_domain_generic_chips( + mvchip->domain, ngpios, 2, np->name, handle_level_irq, +- IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_LEVEL, 0, 0); ++ IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_LEVEL, 0, IRQ_GC_INIT_NESTED_LOCK); + if (err) { + dev_err(&pdev->dev, "couldn't allocate irq chips %s (DT).\n", + mvchip->chip.label); +@@ -1237,6 +1265,8 @@ static int mvebu_gpio_probe(struct platf + ct->chip.irq_mask = mvebu_gpio_level_irq_mask; + ct->chip.irq_unmask = mvebu_gpio_level_irq_unmask; + ct->chip.irq_set_type = mvebu_gpio_irq_set_type; ++ ct->chip.irq_set_wake = mvebu_gpio_set_wake_irq; ++ ct->chip.flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_MASK_ON_SUSPEND; + ct->chip.name = mvchip->chip.label; + + ct = &gc->chip_types[1]; +@@ -1245,6 +1275,8 @@ static int mvebu_gpio_probe(struct platf + ct->chip.irq_mask = mvebu_gpio_edge_irq_mask; + ct->chip.irq_unmask = mvebu_gpio_edge_irq_unmask; + ct->chip.irq_set_type = mvebu_gpio_irq_set_type; ++ ct->chip.irq_set_wake = mvebu_gpio_set_wake_irq; ++ ct->chip.flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_MASK_ON_SUSPEND; + ct->handler = handle_edge_irq; + ct->chip.name = mvchip->chip.label; + +@@ -1260,6 +1292,7 @@ static int mvebu_gpio_probe(struct platf + continue; + irq_set_chained_handler_and_data(irq, mvebu_gpio_irq_handler, + mvchip); ++ mvchip->bank_irq[i] = irq; + } + + return 0; diff --git a/patch/kernel/archive/mvebu-5.16/92-mvebu-gpio-remove-hardcoded-timer-assignment.patch b/patch/kernel/archive/mvebu-5.16/92-mvebu-gpio-remove-hardcoded-timer-assignment.patch new file mode 100644 index 0000000000..9216622d36 --- /dev/null +++ b/patch/kernel/archive/mvebu-5.16/92-mvebu-gpio-remove-hardcoded-timer-assignment.patch @@ -0,0 +1,446 @@ +From e4728fcf779c37d1bcbd4b6505c9b40d4bb9ff48 Mon Sep 17 00:00:00 2001 +From: Heisath +Date: Thu, 03 Jun 2021 10:56:53 +0200 +Subject: [PATCH] Removes the hardcoded timer assignment of timers to pwm controllers +This allows to use more than one pwm per gpio bank. + +Original patch by helios4 team, updated to work on LK5.11+ + +Signed-off-by: Heisath +--- + +diff --git a/drivers/gpio/gpio-mvebu.c b/drivers/gpio/gpio-mvebu.c +index bad399e3f..d3fdaf177 100644 +--- a/drivers/gpio/gpio-mvebu.c ++++ b/drivers/gpio/gpio-mvebu.c +@@ -97,21 +97,42 @@ + + #define MVEBU_MAX_GPIO_PER_BANK 32 + +-struct mvebu_pwm { ++enum mvebu_pwm_ctrl { ++ MVEBU_PWM_CTRL_SET_A = 0, ++ MVEBU_PWM_CTRL_SET_B, ++ MVEBU_PWM_CTRL_MAX ++}; ++ ++struct mvebu_pwmchip { + struct regmap *regs; + u32 offset; + unsigned long clk_rate; +- struct gpio_desc *gpiod; +- struct pwm_chip chip; + spinlock_t lock; +- struct mvebu_gpio_chip *mvchip; ++ bool in_use; + + /* Used to preserve GPIO/PWM registers across suspend/resume */ +- u32 blink_select; + u32 blink_on_duration; + u32 blink_off_duration; + }; + ++struct mvebu_pwm_chip_drv { ++ enum mvebu_pwm_ctrl ctrl; ++ struct gpio_desc *gpiod; ++ bool master; ++}; ++ ++struct mvebu_pwm { ++ struct pwm_chip chip; ++ struct mvebu_gpio_chip *mvchip; ++ struct mvebu_pwmchip controller; ++ enum mvebu_pwm_ctrl default_counter; ++ ++ /* Used to preserve GPIO/PWM registers across suspend/resume */ ++ u32 blink_select; ++}; ++ ++static struct mvebu_pwmchip *mvebu_pwm_list[MVEBU_PWM_CTRL_MAX]; ++ + struct mvebu_gpio_chip { + struct gpio_chip chip; + struct regmap *regs; +@@ -288,12 +309,12 @@ mvebu_gpio_write_level_mask(struct mvebu_gpio_chip *mvchip, u32 val) + * Functions returning offsets of individual registers for a given + * PWM controller. + */ +-static unsigned int mvebu_pwmreg_blink_on_duration(struct mvebu_pwm *mvpwm) ++static unsigned int mvebu_pwmreg_blink_on_duration(struct mvebu_pwmchip *mvpwm) + { + return mvpwm->offset + PWM_BLINK_ON_DURATION_OFF; + } + +-static unsigned int mvebu_pwmreg_blink_off_duration(struct mvebu_pwm *mvpwm) ++static unsigned int mvebu_pwmreg_blink_off_duration(struct mvebu_pwmchip *mvpwm) + { + return mvpwm->offset + PWM_BLINK_OFF_DURATION_OFF; + } +@@ -653,39 +674,84 @@ static int mvebu_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) + struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip); + struct mvebu_gpio_chip *mvchip = mvpwm->mvchip; + struct gpio_desc *desc; ++ enum mvebu_pwm_ctrl id; + unsigned long flags; + int ret = 0; ++ struct mvebu_pwm_chip_drv *chip_data; + +- spin_lock_irqsave(&mvpwm->lock, flags); ++ spin_lock_irqsave(&mvpwm->controller.lock, flags); + +- if (mvpwm->gpiod) { ++ if (pwm->chip_data || (mvchip->blink_en_reg & BIT(pwm->hwpwm))) { + ret = -EBUSY; +- } else { +- desc = gpiochip_request_own_desc(&mvchip->chip, +- pwm->hwpwm, "mvebu-pwm", +- GPIO_ACTIVE_HIGH, +- GPIOD_OUT_LOW); +- if (IS_ERR(desc)) { +- ret = PTR_ERR(desc); +- goto out; +- } ++ goto out; ++ } ++ ++ ++ ++ desc = gpiochip_request_own_desc(&mvchip->chip, ++ pwm->hwpwm, "mvebu-pwm", ++ GPIO_ACTIVE_HIGH, ++ GPIOD_OUT_LOW); ++ ++ if (IS_ERR(desc)) { ++ ret = PTR_ERR(desc); ++ goto out; ++ } ++ ++ ret = gpiod_direction_output(desc, 0); ++ if (ret) { ++ gpiochip_free_own_desc(desc); ++ goto out; ++ } + +- mvpwm->gpiod = desc; ++ chip_data = kzalloc(sizeof(struct mvebu_pwm_chip_drv), GFP_KERNEL); ++ if (!chip_data) { ++ gpiochip_free_own_desc(desc); ++ ret = -ENOMEM; ++ goto out; ++ } ++ ++ for (id = MVEBU_PWM_CTRL_SET_A; id < MVEBU_PWM_CTRL_MAX; id++) { ++ if (!mvebu_pwm_list[id]->in_use) { ++ chip_data->ctrl = id; ++ chip_data->master = true; ++ mvebu_pwm_list[id]->in_use = true; ++ break; ++ } + } ++ ++ if (!chip_data->master) ++ chip_data->ctrl = mvpwm->default_counter; ++ ++ regmap_update_bits(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, ++ BIT(pwm->hwpwm), chip_data->ctrl ? BIT(pwm->hwpwm) : 0); ++ ++ chip_data->gpiod = desc; ++ pwm->chip_data = chip_data; ++ ++ regmap_read(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, ++ &mvpwm->blink_select); ++ + out: +- spin_unlock_irqrestore(&mvpwm->lock, flags); ++ spin_unlock_irqrestore(&mvpwm->controller.lock, flags); + return ret; + } + + static void mvebu_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) + { + struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip); ++ struct mvebu_pwm_chip_drv *chip_data = (struct mvebu_pwm_chip_drv*) pwm->chip_data; + unsigned long flags; + +- spin_lock_irqsave(&mvpwm->lock, flags); +- gpiochip_free_own_desc(mvpwm->gpiod); +- mvpwm->gpiod = NULL; +- spin_unlock_irqrestore(&mvpwm->lock, flags); ++ spin_lock_irqsave(&mvpwm->controller.lock, flags); ++ if (chip_data->master) ++ mvebu_pwm_list[chip_data->ctrl]->in_use = false; ++ ++ ++ gpiochip_free_own_desc(chip_data->gpiod); ++ kfree(chip_data); ++ pwm->chip_data = NULL; ++ spin_unlock_irqrestore(&mvpwm->controller.lock, flags); + } + + static void mvebu_pwm_get_state(struct pwm_chip *chip, +@@ -693,29 +759,36 @@ static void mvebu_pwm_get_state(struct pwm_chip *chip, + struct pwm_state *state) { + + struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip); ++ struct mvebu_pwm_chip_drv *chip_data = (struct mvebu_pwm_chip_drv*) pwm->chip_data; ++ struct mvebu_pwmchip *controller; + struct mvebu_gpio_chip *mvchip = mvpwm->mvchip; + unsigned long long val; + unsigned long flags; + u32 u; + +- spin_lock_irqsave(&mvpwm->lock, flags); ++ if (chip_data) ++ controller = mvebu_pwm_list[chip_data->ctrl]; ++ else ++ controller = &mvpwm->controller; ++ ++ spin_lock_irqsave(&controller->lock, flags); + +- regmap_read(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm), &u); ++ regmap_read(controller->regs, mvebu_pwmreg_blink_on_duration(controller), &u); + /* Hardware treats zero as 2^32. See mvebu_pwm_apply(). */ + if (u > 0) + val = u; + else + val = UINT_MAX + 1ULL; + state->duty_cycle = DIV_ROUND_UP_ULL(val * NSEC_PER_SEC, +- mvpwm->clk_rate); ++ controller->clk_rate); + +- regmap_read(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm), &u); ++ regmap_read(controller->regs, mvebu_pwmreg_blink_off_duration(controller), &u); + /* period = on + off duration */ + if (u > 0) + val += u; + else + val += UINT_MAX + 1ULL; +- state->period = DIV_ROUND_UP_ULL(val * NSEC_PER_SEC, mvpwm->clk_rate); ++ state->period = DIV_ROUND_UP_ULL(val * NSEC_PER_SEC, controller->clk_rate); + + regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &u); + if (u) +@@ -723,19 +796,26 @@ static void mvebu_pwm_get_state(struct pwm_chip *chip, + else + state->enabled = false; + +- spin_unlock_irqrestore(&mvpwm->lock, flags); ++ spin_unlock_irqrestore(&controller->lock, flags); + } + + static int mvebu_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, + const struct pwm_state *state) + { + struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip); ++ struct mvebu_pwm_chip_drv *chip_data = (struct mvebu_pwm_chip_drv*) pwm->chip_data; ++ struct mvebu_pwmchip *controller; + struct mvebu_gpio_chip *mvchip = mvpwm->mvchip; + unsigned long long val; + unsigned long flags; + unsigned int on, off; + +- val = (unsigned long long) mvpwm->clk_rate * state->duty_cycle; ++ if (chip_data) ++ controller = mvebu_pwm_list[chip_data->ctrl]; ++ else ++ controller = &mvpwm->controller; ++ ++ val = (unsigned long long) controller->clk_rate * state->duty_cycle; + do_div(val, NSEC_PER_SEC); + if (val > UINT_MAX + 1ULL) + return -EINVAL; +@@ -750,7 +830,7 @@ static int mvebu_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, + else + on = 1; + +- val = (unsigned long long) mvpwm->clk_rate * state->period; ++ val = (unsigned long long) controller->clk_rate * state->period; + do_div(val, NSEC_PER_SEC); + val -= on; + if (val > UINT_MAX + 1ULL) +@@ -762,16 +842,16 @@ static int mvebu_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, + else + off = 1; + +- spin_lock_irqsave(&mvpwm->lock, flags); ++ spin_lock_irqsave(&controller->lock, flags); + +- regmap_write(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm), on); +- regmap_write(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm), off); ++ regmap_write(controller->regs, mvebu_pwmreg_blink_on_duration(controller), on); ++ regmap_write(controller->regs, mvebu_pwmreg_blink_off_duration(controller), off); + if (state->enabled) + mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 1); + else + mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 0); + +- spin_unlock_irqrestore(&mvpwm->lock, flags); ++ spin_unlock_irqrestore(&controller->lock, flags); + + return 0; + } +@@ -787,25 +867,27 @@ static const struct pwm_ops mvebu_pwm_ops = { + static void __maybe_unused mvebu_pwm_suspend(struct mvebu_gpio_chip *mvchip) + { + struct mvebu_pwm *mvpwm = mvchip->mvpwm; ++ struct mvebu_pwmchip *controller = &mvpwm->controller; + + regmap_read(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, + &mvpwm->blink_select); +- regmap_read(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm), +- &mvpwm->blink_on_duration); +- regmap_read(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm), +- &mvpwm->blink_off_duration); ++ regmap_read(controller->regs, mvebu_pwmreg_blink_on_duration(controller), ++ &controller->blink_on_duration); ++ regmap_read(controller->regs, mvebu_pwmreg_blink_off_duration(controller), ++ &controller->blink_off_duration); + } + + static void __maybe_unused mvebu_pwm_resume(struct mvebu_gpio_chip *mvchip) + { + struct mvebu_pwm *mvpwm = mvchip->mvpwm; ++ struct mvebu_pwmchip *controller = &mvpwm->controller; + + regmap_write(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, + mvpwm->blink_select); +- regmap_write(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm), +- mvpwm->blink_on_duration); +- regmap_write(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm), +- mvpwm->blink_off_duration); ++ regmap_write(controller->regs, mvebu_pwmreg_blink_on_duration(controller), ++ controller->blink_on_duration); ++ regmap_write(controller->regs, mvebu_pwmreg_blink_off_duration(controller), ++ controller->blink_off_duration); + } + + static int mvebu_pwm_probe(struct platform_device *pdev, +@@ -817,26 +899,20 @@ static int mvebu_pwm_probe(struct platform_device *pdev, + void __iomem *base; + u32 offset; + u32 set; ++ enum mvebu_pwm_ctrl ctrl_set; + +- if (of_device_is_compatible(mvchip->chip.of_node, +- "marvell,armada-370-gpio")) { +- /* +- * There are only two sets of PWM configuration registers for +- * all the GPIO lines on those SoCs which this driver reserves +- * for the first two GPIO chips. So if the resource is missing +- * we can't treat it as an error. +- */ +- if (!platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwm")) +- return 0; +- offset = 0; +- } else if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K) { +- int ret = of_property_read_u32(dev->of_node, +- "marvell,pwm-offset", &offset); +- if (ret < 0) +- return 0; +- } else { ++ if (!of_device_is_compatible(mvchip->chip.of_node, ++ "marvell,armada-370-gpio")) ++ return 0; ++ ++ /* ++ * There are only two sets of PWM configuration registers for ++ * all the GPIO lines on those SoCs which this driver reserves ++ * for the first two GPIO chips. So if the resource is missing ++ * we can't treat it as an error. ++ */ ++ if (!platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwm")) + return 0; +- } + + if (IS_ERR(mvchip->clk)) + return PTR_ERR(mvchip->clk); +@@ -844,54 +920,39 @@ static int mvebu_pwm_probe(struct platform_device *pdev, + mvpwm = devm_kzalloc(dev, sizeof(struct mvebu_pwm), GFP_KERNEL); + if (!mvpwm) + return -ENOMEM; ++ + mvchip->mvpwm = mvpwm; + mvpwm->mvchip = mvchip; +- mvpwm->offset = offset; ++ ++ ++ base = devm_platform_ioremap_resource_byname(pdev, "pwm"); ++ if (IS_ERR(base)) ++ return PTR_ERR(base); + +- if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K) { +- mvpwm->regs = mvchip->regs; ++ mvpwm->controller.regs = devm_regmap_init_mmio(&pdev->dev, base, ++ &mvebu_gpio_regmap_config); ++ if (IS_ERR(mvpwm->controller.regs)) ++ return PTR_ERR(mvpwm->controller.regs); + +- switch (mvchip->offset) { +- case AP80X_GPIO0_OFF_A8K: +- case CP11X_GPIO0_OFF_A8K: +- /* Blink counter A */ +- set = 0; +- break; +- case CP11X_GPIO1_OFF_A8K: +- /* Blink counter B */ +- set = U32_MAX; +- mvpwm->offset += PWM_BLINK_COUNTER_B_OFF; +- break; +- default: +- return -EINVAL; +- } ++ /* ++ * Use set A for lines of GPIO chip with id 0, B for GPIO chip ++ * with id 1. Don't allow further GPIO chips to be used for PWM. ++ */ ++ if (id == 0) { ++ set = 0; ++ ctrl_set = MVEBU_PWM_CTRL_SET_A; ++ } else if (id == 1) { ++ set = U32_MAX; ++ ctrl_set = MVEBU_PWM_CTRL_SET_B; + } else { +- base = devm_platform_ioremap_resource_byname(pdev, "pwm"); +- if (IS_ERR(base)) +- return PTR_ERR(base); +- +- mvpwm->regs = devm_regmap_init_mmio(&pdev->dev, base, +- &mvebu_gpio_regmap_config); +- if (IS_ERR(mvpwm->regs)) +- return PTR_ERR(mvpwm->regs); +- +- /* +- * Use set A for lines of GPIO chip with id 0, B for GPIO chip +- * with id 1. Don't allow further GPIO chips to be used for PWM. +- */ +- if (id == 0) +- set = 0; +- else if (id == 1) +- set = U32_MAX; +- else +- return -EINVAL; ++ return -EINVAL; + } + + regmap_write(mvchip->regs, + GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, set); + +- mvpwm->clk_rate = clk_get_rate(mvchip->clk); +- if (!mvpwm->clk_rate) { ++ mvpwm->controller.clk_rate = clk_get_rate(mvchip->clk); ++ if (!mvpwm->controller.clk_rate) { + dev_err(dev, "failed to get clock rate\n"); + return -EINVAL; + } +@@ -907,7 +968,10 @@ static int mvebu_pwm_probe(struct platform_device *pdev, + */ + mvpwm->chip.base = -1; + +- spin_lock_init(&mvpwm->lock); ++ spin_lock_init(&mvpwm->controller.lock); ++ ++ mvpwm->default_counter = ctrl_set; ++ mvebu_pwm_list[ctrl_set] = &mvpwm->controller; + + return pwmchip_add(&mvpwm->chip); + } diff --git a/patch/kernel/archive/mvebu-5.16/94-helios4-dts-add-wake-on-lan-support.patch b/patch/kernel/archive/mvebu-5.16/94-helios4-dts-add-wake-on-lan-support.patch new file mode 100644 index 0000000000..b3daf09f9a --- /dev/null +++ b/patch/kernel/archive/mvebu-5.16/94-helios4-dts-add-wake-on-lan-support.patch @@ -0,0 +1,21 @@ +--- a/arch/arm/boot/dts/armada-388-helios4.dts ++++ b/arch/arm/boot/dts/armada-388-helios4.dts +@@ -84,6 +84,18 @@ + }; + }; + ++ gpio-keys { ++ compatible = "gpio-keys"; ++ pinctrl-0 = <µsom_phy0_int_pins>; ++ ++ wol { ++ label = "Wake-On-LAN"; ++ linux,code = ; ++ gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; ++ wakeup-source; ++ }; ++ }; ++ + io-leds { + compatible = "gpio-leds"; + sata1-led { diff --git a/patch/kernel/archive/mvebu-5.16/compile-dtb-with-symbol-support.patch b/patch/kernel/archive/mvebu-5.16/compile-dtb-with-symbol-support.patch new file mode 100644 index 0000000000..a2bd279ae4 --- /dev/null +++ b/patch/kernel/archive/mvebu-5.16/compile-dtb-with-symbol-support.patch @@ -0,0 +1,12 @@ +--- a/scripts/Makefile.lib ++++ b/scripts/Makefile.lib +@@ -277,6 +277,9 @@ quiet_cmd_gzip = GZIP $@ + DTC ?= $(objtree)/scripts/dtc/dtc + DTC_FLAGS += -Wno-interrupt_provider + ++# Enable overlay support ++DTC_FLAGS += -@ ++ + # Disable noisy checks by default + ifeq ($(findstring 1,$(KBUILD_EXTRA_WARN)),) + DTC_FLAGS += -Wno-unit_address_vs_reg \ diff --git a/patch/kernel/archive/mvebu-5.16/dts-disable-spi-flash-on-a388-microsom.patch b/patch/kernel/archive/mvebu-5.16/dts-disable-spi-flash-on-a388-microsom.patch new file mode 100644 index 0000000000..b6597a72ff --- /dev/null +++ b/patch/kernel/archive/mvebu-5.16/dts-disable-spi-flash-on-a388-microsom.patch @@ -0,0 +1,10 @@ +--- a/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi ++++ b/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi +@@ -107,6 +107,7 @@ + compatible = "w25q32", "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <3000000>; ++ status = "disabled"; + }; + }; + diff --git a/patch/kernel/archive/mvebu-5.16/general-increasing_DMA_block_memory_allocation_to_2048.patch b/patch/kernel/archive/mvebu-5.16/general-increasing_DMA_block_memory_allocation_to_2048.patch new file mode 100644 index 0000000000..eef7296e75 --- /dev/null +++ b/patch/kernel/archive/mvebu-5.16/general-increasing_DMA_block_memory_allocation_to_2048.patch @@ -0,0 +1,11 @@ +--- a/arch/arm/mm/dma-mapping.c ++++ b/arch/arm/mm/dma-mapping.c +@@ -315,7 +315,7 @@ static void *__alloc_remap_buffer(struct + pgprot_t prot, struct page **ret_page, + const void *caller, bool want_vaddr); + +-#define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_256K ++#define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_2M + static struct gen_pool *atomic_pool __ro_after_init; + + static size_t atomic_pool_size __initdata = DEFAULT_DMA_COHERENT_POOL_SIZE; diff --git a/patch/kernel/archive/mvebu-5.16/unlock_atheros_regulatory_restrictions.patch b/patch/kernel/archive/mvebu-5.16/unlock_atheros_regulatory_restrictions.patch new file mode 100644 index 0000000000..7e57c379ad --- /dev/null +++ b/patch/kernel/archive/mvebu-5.16/unlock_atheros_regulatory_restrictions.patch @@ -0,0 +1,70 @@ +--- a/drivers/net/wireless/ath/regd.c ++++ b/drivers/net/wireless/ath/regd.c +@@ -50,12 +50,9 @@ static int __ath_regd_init(struct ath_re + #define ATH_5GHZ_5725_5850 REG_RULE(5725-10, 5850+10, 80, 0, 30,\ + NL80211_RRF_NO_IR) + +-#define ATH_2GHZ_ALL ATH_2GHZ_CH01_11, \ +- ATH_2GHZ_CH12_13, \ +- ATH_2GHZ_CH14 ++#define ATH_2GHZ_ALL REG_RULE(2400, 2483, 40, 0, 30, 0) + +-#define ATH_5GHZ_ALL ATH_5GHZ_5150_5350, \ +- ATH_5GHZ_5470_5850 ++#define ATH_5GHZ_ALL REG_RULE(5140, 5860, 40, 0, 30, 0) + + /* This one skips what we call "mid band" */ + #define ATH_5GHZ_NO_MIDBAND ATH_5GHZ_5150_5350, \ +@@ -77,9 +74,8 @@ static const struct ieee80211_regdomain + .n_reg_rules = 4, + .alpha2 = "99", + .reg_rules = { +- ATH_2GHZ_CH01_11, +- ATH_2GHZ_CH12_13, +- ATH_5GHZ_NO_MIDBAND, ++ ATH_2GHZ_ALL, ++ ATH_5GHZ_ALL, + } + }; + +@@ -88,8 +84,8 @@ static const struct ieee80211_regdomain + .n_reg_rules = 3, + .alpha2 = "99", + .reg_rules = { +- ATH_2GHZ_CH01_11, +- ATH_5GHZ_NO_MIDBAND, ++ ATH_2GHZ_ALL, ++ ATH_5GHZ_ALL, + } + }; + +@@ -98,7 +94,7 @@ static const struct ieee80211_regdomain + .n_reg_rules = 3, + .alpha2 = "99", + .reg_rules = { +- ATH_2GHZ_CH01_11, ++ ATH_2GHZ_ALL, + ATH_5GHZ_ALL, + } + }; +@@ -108,8 +104,7 @@ static const struct ieee80211_regdomain + .n_reg_rules = 4, + .alpha2 = "99", + .reg_rules = { +- ATH_2GHZ_CH01_11, +- ATH_2GHZ_CH12_13, ++ ATH_2GHZ_ALL, + ATH_5GHZ_ALL, + } + }; +@@ -258,9 +253,7 @@ static bool ath_is_radar_freq(u16 center + struct ath_regulatory *reg) + + { +- if (reg->country_code == CTRY_INDIA) +- return (center_freq >= 5500 && center_freq <= 5700); +- return (center_freq >= 5260 && center_freq <= 5700); ++ return false; + } + + static void ath_force_clear_no_ir_chan(struct wiphy *wiphy, diff --git a/patch/kernel/archive/mvebu-5.16/use-1000BaseX-clearfog-switch.patch b/patch/kernel/archive/mvebu-5.16/use-1000BaseX-clearfog-switch.patch new file mode 100644 index 0000000000..900d0f1142 --- /dev/null +++ b/patch/kernel/archive/mvebu-5.16/use-1000BaseX-clearfog-switch.patch @@ -0,0 +1,39 @@ +From 219f80b5cc03dab87fd05210b95c0b1a5afa8d33 Mon Sep 17 00:00:00 2001 +From: Russell King +Date: Thu, 14 Jul 2016 15:31:42 +0100 +Subject: ARM: dts: armada388-clearfog: use 1000BaseX mode for 88e6176 switch + +Use 1000BaseX mode for the 88e6176 switch, which allows mvneta to +negotiate correctly without needing to be forced. + +Signed-off-by: Russell King +--- + arch/arm/boot/dts/armada-388-clearfog.dts | 10 ++-------- + 1 file changed, 2 insertions(+), 8 deletions(-) + +--- a/arch/arm/boot/dts/armada-388-clearfog.dts ++++ b/arch/arm/boot/dts/armada-388-clearfog.dts +@@ -47,10 +47,8 @@ + + ð1 { + /* ethernet@30000 */ +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; ++ phy-mode = "1000base-x"; ++ managed = "in-band-status"; + }; + + &expander0 { +@@ -131,10 +129,6 @@ + reg = <5>; + label = "cpu"; + ethernet = <ð1>; +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; + }; + + port@6 { diff --git a/patch/kernel/mvebu-current b/patch/kernel/mvebu-current index 01e95c2987..d5f21b1198 120000 --- a/patch/kernel/mvebu-current +++ b/patch/kernel/mvebu-current @@ -1 +1 @@ -archive/mvebu-5.10 \ No newline at end of file +archive/mvebu-5.15 \ No newline at end of file diff --git a/patch/kernel/mvebu-edge b/patch/kernel/mvebu-edge index d5f21b1198..adf2c3c23d 120000 --- a/patch/kernel/mvebu-edge +++ b/patch/kernel/mvebu-edge @@ -1 +1 @@ -archive/mvebu-5.15 \ No newline at end of file +archive/mvebu-5.16 \ No newline at end of file