diff --git a/patch/kernel/sun50iw2-dev/add_sun50i_a64_spi.patch b/patch/kernel/sun50iw2-dev/add_sun50i_a64_spi.patch
new file mode 100644
index 0000000000..1b5537207c
--- /dev/null
+++ b/patch/kernel/sun50iw2-dev/add_sun50i_a64_spi.patch
@@ -0,0 +1,109 @@
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+index 02c0385..c0773d8 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+@@ -43,8 +43,10 @@
+  */
+ 
+ #include <dt-bindings/clock/sun50i-a64-ccu.h>
++#include <dt-bindings/clock/sun8i-r-ccu.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/reset/sun50i-a64-ccu.h>
++#include <dt-bindings/reset/sun8i-r-ccu.h>
+ 
+ / {
+ 	interrupt-parent = <&gic>;
+@@ -98,6 +100,13 @@
+ 		clock-output-names = "osc32k";
+ 	};
+ 
++	osc32000: osc32000_clk {
++		#clock-cells = <0>;
++		compatible = "fixed-clock";
++		clock-frequency = <32000>;
++		clock-output-names = "osc32000";
++	};
++
+ 	psci {
+ 		compatible = "arm,psci-0.2";
+ 		method = "smc";
+@@ -276,6 +301,16 @@
+ 				bias-pull-up;
+ 			};
+ 
++			spi0_pins: spi0 {
++				pins = "PC0", "PC1", "PC2", "PC3";
++				function = "spi0";
++			};
++
++			spi1_pins: spi1 {
++				pins = "PA15", "PA16", "PA14", "PA13";
++				function = "spi1";
++			};
++
+ 			uart0_pins_a: uart0@0 {
+ 				pins = "PB8", "PB9";
+ 				function = "uart0";
+@@ -306,6 +315,27 @@
+ 			};
+ 		};
+ 
++		r_ccu: clock@1f01400 {
++			compatible = "allwinner,sun50i-a64-r-ccu";
++			reg = <0x01f01400 0x100>;
++			clocks = <&osc24M>, <&osc32k>, <&osc32000>;
++			clock-names = "hosc", "losc", "iosc";
++			#clock-cells = <1>;
++			#reset-cells = <1>;
++		};
++
++		r_pio: pinctrl@1f02c00 {
++			compatible = "allwinner,sun50i-a64-r-pinctrl";
++			reg = <0x01f02c00 0x400>;
++			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
++			clock-names = "apb", "hosc", "losc";
++			gpio-controller;
++			#gpio-cells = <3>;
++			interrupt-controller;
++			#interrupt-cells = <3>;
++		};
++
+ 		uart0: serial@1c28000 {
+ 			compatible = "snps,dw-apb-uart";
+ 			reg = <0x01c28000 0x400>;
+@@ -431,5 +487,34 @@
+ 			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+ 				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ 		};
++
++		spi0: spi@01c68000 {
++			compatible = "allwinner,sun8i-h3-spi";
++			reg = <0x01c68000 0x1000>;
++			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
++			clock-names = "ahb", "mod";
++			pinctrl-names = "default";
++			pinctrl-0 = <&spi0_pins>;
++			resets = <&ccu RST_BUS_SPI0>;
++			status = "disabled";
++			#address-cells = <1>;
++			#size-cells = <0>;
++		};
++
++		spi1: spi@01c69000 {
++			compatible = "allwinner,sun8i-h3-spi";
++			reg = <0x01c69000 0x1000>;
++			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
++			clock-names = "ahb", "mod";
++			pinctrl-names = "default";
++			pinctrl-0 = <&spi1_pins>;
++			resets = <&ccu RST_BUS_SPI1>;
++			status = "disabled";
++			#address-cells = <1>;
++			#size-cells = <0>;
++		};
++
+ 	};
+ };