From 417c8b2efb41cfd089db317aa78c18832898faa9 Mon Sep 17 00:00:00 2001 From: Martin Ayotte Date: Fri, 22 Sep 2017 18:19:17 -0400 Subject: [PATCH] patch for missing SPI on A64 --- .../sunxi-next/add-missing-spi-a64.patch | 56 +++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 patch/kernel/sunxi-next/add-missing-spi-a64.patch diff --git a/patch/kernel/sunxi-next/add-missing-spi-a64.patch b/patch/kernel/sunxi-next/add-missing-spi-a64.patch new file mode 100644 index 0000000000..16edd725a4 --- /dev/null +++ b/patch/kernel/sunxi-next/add-missing-spi-a64.patch @@ -0,0 +1,56 @@ +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +index 68aadc9..912bb06 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +@@ -325,6 +325,16 @@ + drive-strength = <40>; + }; + ++ spi0_pins: spi0 { ++ pins = "PC0", "PC1", "PC2", "PC3"; ++ function = "spi0"; ++ }; ++ ++ spi1_pins: spi1 { ++ pins = "PA15", "PA16", "PA14", "PA13"; ++ function = "spi1"; ++ }; ++ + uart0_pins_a: uart0@0 { + pins = "PB8", "PB9"; + function = "uart0"; +@@ -361,6 +371,34 @@ + }; + }; + ++ spi0: spi@01c68000 { ++ compatible = "allwinner,sun8i-h3-spi"; ++ reg = <0x01c68000 0x1000>; ++ interrupts = ; ++ clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; ++ clock-names = "ahb", "mod"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi0_pins>; ++ resets = <&ccu RST_BUS_SPI0>; ++ status = "disabled"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ ++ spi1: spi@01c69000 { ++ compatible = "allwinner,sun8i-h3-spi"; ++ reg = <0x01c69000 0x1000>; ++ interrupts = ; ++ clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; ++ clock-names = "ahb", "mod"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi1_pins>; ++ resets = <&ccu RST_BUS_SPI1>; ++ status = "disabled"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ + uart0: serial@1c28000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28000 0x400>;