From 4cb57c62b3ade97596c802d1a05cff510c4e6540 Mon Sep 17 00:00:00 2001 From: tonymac32 Date: Wed, 16 Dec 2020 02:05:47 -0500 Subject: [PATCH 1/2] [ rockchip64 ] add RK3399 2GHz opp as overlay RK3399 maximum clockspeed according to Rockchip is 1.8 GHz for all but a couple variants. Almost all SBC's use 1.8 GHz silicon. Remove automatic application of extra 2 GHz opp, allow user to select an overlay at their own risk. --- .../rk3399-add-overclock-overlay.patch | 74 +++++++++++++++++++ ...k3399-enable_1.5_2.0_ghz_cpufreq_opp.patch | 26 ------- 2 files changed, 74 insertions(+), 26 deletions(-) create mode 100644 patch/kernel/rockchip64-current/rk3399-add-overclock-overlay.patch delete mode 100644 patch/kernel/rockchip64-current/rk3399-enable_1.5_2.0_ghz_cpufreq_opp.patch diff --git a/patch/kernel/rockchip64-current/rk3399-add-overclock-overlay.patch b/patch/kernel/rockchip64-current/rk3399-add-overclock-overlay.patch new file mode 100644 index 0000000000..04d50620c5 --- /dev/null +++ b/patch/kernel/rockchip64-current/rk3399-add-overclock-overlay.patch @@ -0,0 +1,74 @@ +From a9a60c0bccd0c2b9d35594934eae5e25b4a00b53 Mon Sep 17 00:00:00 2001 +From: tonymac32 +Date: Wed, 16 Dec 2020 01:32:03 -0500 +Subject: [PATCH] rk3399-add-2ghz-opp-overlay + +Signed-off-by: tonymac32 +--- + arch/arm64/boot/dts/rockchip/overlay/Makefile | 1 + + .../rockchip/overlay/README.rockchip-overlays | 5 ++++ + .../overlay/rockchip-rk3399-opp-2ghz.dts | 24 +++++++++++++++++++ + 3 files changed, 30 insertions(+) + create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3399-opp-2ghz.dts + +diff --git a/arch/arm64/boot/dts/rockchip/overlay/Makefile b/arch/arm64/boot/dts/rockchip/overlay/Makefile +index 0fce5206d..9bc4942bd 100644 +--- a/arch/arm64/boot/dts/rockchip/overlay/Makefile ++++ b/arch/arm64/boot/dts/rockchip/overlay/Makefile +@@ -3,6 +3,7 @@ dtbo-$(CONFIG_ARCH_ROCKCHIP) += \ + rockchip-i2c7.dtbo \ + rockchip-i2c8.dtbo \ + rockchip-pcie-gen2.dtbo \ ++ rockchip-rk3399-opp-2ghz.dtbo \ + rockchip-spi-jedec-nor.dtbo \ + rockchip-spi-spidev.dtbo \ + rockchip-uart4.dtbo \ +diff --git a/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays b/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays +index 48ca48fc3..ce0b84e00 100644 +--- a/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays ++++ b/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays +@@ -29,6 +29,11 @@ I2C8 pins (SCL, SDA): GPIO1-C5, GPIO1-C4 + Enables PCIe Gen2 link speed on RK3399. + WARNING! Not officially supported by Rockchip!!! + ++### rk3399-opp-2ghz ++ ++Adds the 2GHz big and 1.5 GHz LITTLE opps for overclocking ++WARNING! Not officially supported by Rockchip!!! ++ + ### spi-jedec-nor + + Activates MTD support for JEDEC compatible SPI NOR flash chips on SPI bus +diff --git a/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3399-opp-2ghz.dts b/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3399-opp-2ghz.dts +new file mode 100644 +index 000000000..1d7584b60 +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3399-opp-2ghz.dts +@@ -0,0 +1,24 @@ ++/dts-v1/; ++ ++/ { ++ compatible = "rockchip,rk3399"; ++ fragment@0 { ++ target-path = "/opp-table0"; ++ __overlay__ { ++ opp06 { ++ opp-hz = /bits/ 64 <1512000000>; ++ opp-microvolt = <1200000>; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target-path = "/opp-table1"; ++ __overlay__ { ++ opp08 { ++ opp-hz = /bits/ 64 <2016000000>; ++ opp-microvolt = <1300000>; ++ }; ++ }; ++ }; ++}; +-- +Created with Armbian build tools https://github.com/armbian/build + diff --git a/patch/kernel/rockchip64-current/rk3399-enable_1.5_2.0_ghz_cpufreq_opp.patch b/patch/kernel/rockchip64-current/rk3399-enable_1.5_2.0_ghz_cpufreq_opp.patch deleted file mode 100644 index ee91e34373..0000000000 --- a/patch/kernel/rockchip64-current/rk3399-enable_1.5_2.0_ghz_cpufreq_opp.patch +++ /dev/null @@ -1,26 +0,0 @@ -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi -index d6f1095..30f353c 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi -@@ -33,6 +33,10 @@ - opp-hz = /bits/ 64 <1416000000>; - opp-microvolt = <1125000>; - }; -+ opp06 { -+ opp-hz = /bits/ 64 <1512000000>; -+ opp-microvolt = <1200000>; -+ }; - }; - - cluster1_opp: opp-table1 { -@@ -72,6 +76,10 @@ - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <1200000>; - }; -+ opp08 { -+ opp-hz = /bits/ 64 <2016000000>; -+ opp-microvolt = <1300000>; -+ }; - }; - - gpu_opp_table: opp-table2 { From 129d8dbeb525044ca9070c737fa196ee72300d47 Mon Sep 17 00:00:00 2001 From: tonymac32 Date: Thu, 17 Dec 2020 01:54:05 -0500 Subject: [PATCH 2/2] [ rockchip64 ] add oc opps for rk3328 remove default 1.5 GHz operation, enable as overlay at user risk --- ...ch => overlays-00-add-oc-opp-rk3399.patch} | 0 .../overlays-01-add-oc-opp-rk3328.patch | 94 +++++++++++++++++++ .../rk3328-enable-1512mhz-opp.patch | 16 ---- 3 files changed, 94 insertions(+), 16 deletions(-) rename patch/kernel/rockchip64-current/{rk3399-add-overclock-overlay.patch => overlays-00-add-oc-opp-rk3399.patch} (100%) create mode 100644 patch/kernel/rockchip64-current/overlays-01-add-oc-opp-rk3328.patch delete mode 100644 patch/kernel/rockchip64-current/rk3328-enable-1512mhz-opp.patch diff --git a/patch/kernel/rockchip64-current/rk3399-add-overclock-overlay.patch b/patch/kernel/rockchip64-current/overlays-00-add-oc-opp-rk3399.patch similarity index 100% rename from patch/kernel/rockchip64-current/rk3399-add-overclock-overlay.patch rename to patch/kernel/rockchip64-current/overlays-00-add-oc-opp-rk3399.patch diff --git a/patch/kernel/rockchip64-current/overlays-01-add-oc-opp-rk3328.patch b/patch/kernel/rockchip64-current/overlays-01-add-oc-opp-rk3328.patch new file mode 100644 index 0000000000..61db1abb29 --- /dev/null +++ b/patch/kernel/rockchip64-current/overlays-01-add-oc-opp-rk3328.patch @@ -0,0 +1,94 @@ +From a053b706be60b3dd13803ece30ff6eb143339bc2 Mon Sep 17 00:00:00 2001 +From: tonymac32 +Date: Thu, 17 Dec 2020 01:33:33 -0500 +Subject: [PATCH] rk3328-oc-opps + +Signed-off-by: tonymac32 +--- + arch/arm64/boot/dts/rockchip/overlay/Makefile | 2 ++ + .../dts/rockchip/overlay/README.rockchip-overlays | 10 ++++++++++ + .../overlay/rockchip-rk3328-opp-1.4ghz.dts | 15 +++++++++++++++ + .../overlay/rockchip-rk3328-opp-1.5ghz.dts | 15 +++++++++++++++ + 4 files changed, 42 insertions(+) + create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3328-opp-1.4ghz.dts + create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3328-opp-1.5ghz.dts + +diff --git a/arch/arm64/boot/dts/rockchip/overlay/Makefile b/arch/arm64/boot/dts/rockchip/overlay/Makefile +index 9bc4942bd..9c07d64a1 100644 +--- a/arch/arm64/boot/dts/rockchip/overlay/Makefile ++++ b/arch/arm64/boot/dts/rockchip/overlay/Makefile +@@ -3,6 +3,8 @@ dtbo-$(CONFIG_ARCH_ROCKCHIP) += \ + rockchip-i2c7.dtbo \ + rockchip-i2c8.dtbo \ + rockchip-pcie-gen2.dtbo \ ++ rockchip-rk3328-opp-1.4ghz.dtbo \ ++ rockchip-rk3328-opp-1.5ghz.dtbo \ + rockchip-rk3399-opp-2ghz.dtbo \ + rockchip-spi-jedec-nor.dtbo \ + rockchip-spi-spidev.dtbo \ +diff --git a/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays b/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays +index ce0b84e00..d6979437a 100644 +--- a/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays ++++ b/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays +@@ -29,6 +29,16 @@ I2C8 pins (SCL, SDA): GPIO1-C5, GPIO1-C4 + Enables PCIe Gen2 link speed on RK3399. + WARNING! Not officially supported by Rockchip!!! + ++### rk3328-opp-1.4ghz ++ ++Adds the 1.4GHz opp for overclocking ++WARNING! Not officially supported by Rockchip!!! ++ ++### rk3328-opp-1.5ghz ++ ++Adds the 1.5GHz opp for overclocking ++WARNING! Not officially supported by Rockchip!!! ++ + ### rk3399-opp-2ghz + + Adds the 2GHz big and 1.5 GHz LITTLE opps for overclocking +diff --git a/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3328-opp-1.4ghz.dts b/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3328-opp-1.4ghz.dts +new file mode 100644 +index 000000000..a7ad9d572 +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3328-opp-1.4ghz.dts +@@ -0,0 +1,15 @@ ++/dts-v1/; ++ ++/ { ++ compatible = "rockchip,rk3328"; ++ fragment@0 { ++ target-path = "/opp_table0"; ++ __overlay__ { ++ opp-1392000000 { ++ opp-hz = /bits/ 64 <1392000000>; ++ opp-microvolt = <1400000>; ++ clock-latency-ns = <40000>; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3328-opp-1.5ghz.dts b/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3328-opp-1.5ghz.dts +new file mode 100644 +index 000000000..3dfd008ab +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3328-opp-1.5ghz.dts +@@ -0,0 +1,15 @@ ++/dts-v1/; ++ ++/ { ++ compatible = "rockchip,rk3328"; ++ fragment@0 { ++ target-path = "/opp_table0"; ++ __overlay__ { ++ opp-1512000000 { ++ opp-hz = /bits/ 64 <1512000000>; ++ opp-microvolt = <1450000>; ++ clock-latency-ns = <40000>; ++ }; ++ }; ++ }; ++}; +-- +Created with Armbian build tools https://github.com/armbian/build + diff --git a/patch/kernel/rockchip64-current/rk3328-enable-1512mhz-opp.patch b/patch/kernel/rockchip64-current/rk3328-enable-1512mhz-opp.patch deleted file mode 100644 index 7d67233d62..0000000000 --- a/patch/kernel/rockchip64-current/rk3328-enable-1512mhz-opp.patch +++ /dev/null @@ -1,16 +0,0 @@ -diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -index 8dabc6e29..d58c893a6 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -@@ -125,6 +125,11 @@ - opp-microvolt = <1300000>; - clock-latency-ns = <40000>; - }; -+ opp-1512000000 { -+ opp-hz = /bits/ 64 <1512000000>; -+ opp-microvolt = <1450000>; -+ clock-latency-ns = <40000>; -+ }; - }; - - amba {