diff --git a/patch/kernel/rockchip-rk3588-edge/0021-RK3588-Add-USB3-DRD-Support.patch b/patch/kernel/rockchip-rk3588-edge/0021-RK3588-Add-USB3-DRD-Support.patch index 3f3e31c737..6b3c70519b 100644 --- a/patch/kernel/rockchip-rk3588-edge/0021-RK3588-Add-USB3-DRD-Support.patch +++ b/patch/kernel/rockchip-rk3588-edge/0021-RK3588-Add-USB3-DRD-Support.patch @@ -1,24 +1,26 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From 28c3330b4225bf99d4793560bdabc2fc91230586 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel -Date: Tue, 25 Apr 2023 17:38:57 +0200 -Subject: dt-bindings: phy: add rockchip usbdp combo phy document +Date: Fri, 16 Feb 2024 18:01:16 +0100 +Subject: [PATCH 01/10] dt-bindings: phy: add rockchip usbdp combo phy document Add device tree binding document for Rockchip USBDP Combo PHY with Samsung IP block. Co-developed-by: Frank Wang Signed-off-by: Frank Wang +Reviewed-by: Conor Dooley Signed-off-by: Sebastian Reichel --- - Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml | 166 ++++++++++ - 1 file changed, 166 insertions(+) + .../bindings/phy/phy-rockchip-usbdp.yaml | 148 ++++++++++++++++++ + 1 file changed, 148 insertions(+) + create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml b/Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml new file mode 100644 -index 000000000000..dcca84d57e99 +index 000000000000..1f1f8863b80d --- /dev/null +++ b/Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml -@@ -0,0 +1,166 @@ +@@ -0,0 +1,148 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- @@ -39,6 +41,13 @@ index 000000000000..dcca84d57e99 + reg: + maxItems: 1 + ++ "#phy-cells": ++ description: | ++ Cell allows setting the type of the PHY. Possible values are: ++ - PHY_TYPE_USB3 ++ - PHY_TYPE_DP ++ const: 1 ++ + clocks: + maxItems: 4 + @@ -64,15 +73,18 @@ index 000000000000..dcca84d57e99 + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 2 + maxItems: 4 ++ items: ++ maximum: 3 + description: -+ An array of physical Tyep-C lanes indexes. Position of an entry determines -+ the dp lane index, while the value of an entry indicater physical Type-C lane. -+ The support dp lanes number are 2 or 4. e.g. for 2 lanes dp lanes map, we could -+ have "rockchip,dp-lane-mux = <2, 3>;", assuming dp lane0 on Type-C phy lane2, -+ dp lane1 on Type-C phy lane3. For 4 lanes dp lanes map, we could have -+ "rockchip,dp-lane-mux = <0, 1, 2, 3>;", assuming dp lane0 on Type-C phy lane0, -+ dp lane1 on Type-C phy lane1, dp lane2 on Type-C phy lane2, dp lane3 on Type-C -+ phy lane3. If dp lane map by DisplayPort Alt mode, this property is not need. ++ An array of physical Type-C lanes indexes. Position of an entry ++ determines the DisplayPort (DP) lane index, while the value of an entry ++ indicates physical Type-C lane. The supported DP lanes number are 2 or 4. ++ e.g. for 2 lanes DP lanes map, we could have "rockchip,dp-lane-mux = <2, ++ 3>;", assuming DP lane0 on Type-C phy lane2, DP lane1 on Type-C phy ++ lane3. For 4 lanes DP lanes map, we could have "rockchip,dp-lane-mux = ++ <0, 1, 2, 3>;", assuming DP lane0 on Type-C phy lane0, DP lane1 on Type-C ++ phy lane1, DP lane2 on Type-C phy lane2, DP lane3 on Type-C phy lane3. If ++ DP lanes are mapped by DisplayPort Alt mode, this property is not needed. + + rockchip,u2phy-grf: + $ref: /schemas/types.yaml#/definitions/phandle @@ -93,48 +105,28 @@ index 000000000000..dcca84d57e99 + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the syscon managing the 'video output general register files'. -+ When select the dp lane mapping will request its phandle. ++ When select the DP lane mapping will request its phandle. + + sbu1-dc-gpios: + description: + GPIO connected to the SBU1 line of the USB-C connector via a big resistor + (~100K) to apply a DC offset for signalling the connector orientation. ++ maxItems: 1 + + sbu2-dc-gpios: + description: + GPIO connected to the SBU2 line of the USB-C connector via a big resistor + (~100K) to apply a DC offset for signalling the connector orientation. ++ maxItems: 1 + + orientation-switch: + description: Flag the port as possible handler of orientation switching + type: boolean + + mode-switch: -+ description: Flag the port as possible handle of altmode switching ++ description: Flag the port as possible handler of altmode switching + type: boolean + -+ dp-port: -+ type: object -+ additionalProperties: false -+ -+ properties: -+ "#phy-cells": -+ const: 0 -+ -+ required: -+ - "#phy-cells" -+ -+ usb3-port: -+ type: object -+ additionalProperties: false -+ -+ properties: -+ "#phy-cells": -+ const: 0 -+ -+ required: -+ - "#phy-cells" -+ + port: + $ref: /schemas/graph.yaml#/properties/port + description: @@ -148,121 +140,59 @@ index 000000000000..dcca84d57e99 + - clock-names + - resets + - reset-names -+ - dp-port -+ - usb3-port ++ - "#phy-cells" + +additionalProperties: false + +examples: + - | -+ #include ++ #include ++ #include + + usbdp_phy0: phy@fed80000 { + compatible = "rockchip,rk3588-usbdp-phy"; -+ reg = <0x0 0xfed80000 0x0 0x10000>; -+ rockchip,u2phy-grf = <&usb2phy0_grf>; -+ rockchip,usb-grf = <&usb_grf>; -+ rockchip,usbdpphy-grf = <&usbdpphy0_grf>; -+ rockchip,vo-grf = <&vo0_grf>; ++ reg = <0xfed80000 0x10000>; ++ #phy-cells = <1>; + clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, + <&cru CLK_USBDP_PHY0_IMMORTAL>, -+ <&cru PCLK_USBDPPHY0>; -+ clock-names = "refclk", "immortal", "pclk"; ++ <&cru PCLK_USBDPPHY0>, ++ <&u2phy0>; ++ clock-names = "refclk", "immortal", "pclk", "utmi"; + resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>, + <&cru SRST_USBDP_COMBO_PHY0_CMN>, + <&cru SRST_USBDP_COMBO_PHY0_LANE>, + <&cru SRST_USBDP_COMBO_PHY0_PCS>, + <&cru SRST_P_USBDPPHY0>; + reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; -+ status = "disabled"; -+ -+ usbdp_phy0_dp: dp-port { -+ #phy-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ usbdp_phy0_u3: usb3-port { -+ #phy-cells = <0>; -+ status = "disabled"; ++ rockchip,u2phy-grf = <&usb2phy0_grf>; ++ rockchip,usb-grf = <&usb_grf>; ++ rockchip,usbdpphy-grf = <&usbdpphy0_grf>; ++ rockchip,vo-grf = <&vo0_grf>; + }; -- -Armbian +2.43.1 -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 + +From c20a93c09c33691a86bbdebc845594ddd72631f1 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel -Date: Tue, 30 May 2023 18:49:48 +0200 -Subject: dt-bindings: soc: rockchip: add rk3588 USB3 syscon - -RK3588 USB3 support requires the GRF for USB, USBDP PHY and VO. - -Signed-off-by: Sebastian Reichel ---- - Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 22 ++++++++++ - 1 file changed, 22 insertions(+) - -diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml -index 1309bf5ae0cd..f8fc5285e4c1 100644 ---- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml -+++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml -@@ -28,6 +28,8 @@ properties: - - rockchip,rk3588-sys-grf - - rockchip,rk3588-pcie3-phy-grf - - rockchip,rk3588-pcie3-pipe-grf -+ - rockchip,rk3588-usb-grf -+ - rockchip,rk3588-usbdpphy-grf - - rockchip,rk3588-vo-grf - - rockchip,rk3588-vop-grf - - rockchip,rv1108-usbgrf -@@ -64,6 +67,9 @@ properties: - reg: - maxItems: 1 - -+ clocks: -+ maxItems: 1 -+ - "#address-cells": - const: 1 - -@@ -246,6 +252,22 @@ allOf: - - unevaluatedProperties: false - -+ - if: -+ properties: -+ compatible: -+ contains: -+ enum: -+ - rockchip,rk3588-vo-grf -+ -+ then: -+ required: -+ - clocks -+ -+ else: -+ properties: -+ clocks: false -+ -+ - examples: - - | - #include --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Frank Wang -Date: Tue, 25 Apr 2023 15:55:54 +0200 -Subject: phy: rockchip: add usbdp combo phy driver +Date: Fri, 16 Feb 2024 18:01:17 +0100 +Subject: [PATCH 02/10] phy: rockchip: add usbdp combo phy driver This adds a new USBDP combo PHY with Samsung IP block driver. The driver get lane mux and mapping info in 2 ways, supporting DisplayPort alternate mode or parsing from DT. When parsing from DT, -the property "rockchip,dp-lane-mux" provide the DP mux and mapping info. +the property "rockchip,dp-lane-mux" provide the DP mux and mapping +info. This is needed when the PHY is not used with TypeC Alt-Mode. +For example if the USB3 interface of the PHY is connected to a USB +Type A connector and the DP interface is connected to a DisplayPort +connector. -When do DP link training, need to set lane number, link rate, swing, and -pre-emphasis via PHY configure interface. +When do DP link training, need to set lane number, link rate, swing, +and pre-emphasis via PHY configure interface. +Co-developed-by: Heiko Stuebner +Signed-off-by: Heiko Stuebner Co-developed-by: Zhang Yubing Signed-off-by: Zhang Yubing Co-developed-by: Frank Wang @@ -271,8 +201,9 @@ Signed-off-by: Sebastian Reichel --- drivers/phy/rockchip/Kconfig | 12 + drivers/phy/rockchip/Makefile | 1 + - drivers/phy/rockchip/phy-rockchip-usbdp.c | 1749 ++++++++++ - 3 files changed, 1762 insertions(+) + drivers/phy/rockchip/phy-rockchip-usbdp.c | 1612 +++++++++++++++++++++ + 3 files changed, 1625 insertions(+) + create mode 100644 drivers/phy/rockchip/phy-rockchip-usbdp.c diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig index 94360fc96a6f..d21b458c1d18 100644 @@ -305,10 +236,10 @@ index 7eab129230d1..25d2e1355db7 100644 +obj-$(CONFIG_PHY_ROCKCHIP_USBDP) += phy-rockchip-usbdp.o diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockchip/phy-rockchip-usbdp.c new file mode 100644 -index 000000000000..bb0beafb8578 +index 000000000000..1f3b7955c9f3 --- /dev/null +++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c -@@ -0,0 +1,1749 @@ +@@ -0,0 +1,1612 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Rockchip USBDP Combo PHY with Samsung IP block driver @@ -316,45 +247,37 @@ index 000000000000..bb0beafb8578 + * Copyright (C) 2021 Rockchip Electronics Co., Ltd + */ + ++#include +#include +#include +#include +#include +#include +#include -+#include -+#include -+#include +#include +#include +#include +#include -+#include -+#include +#include +#include ++#include +#include +#include +#include +#include +#include + -+/* RK3588 USBDP PHY Register Definitions */ -+ ++/* USBDP PHY Register Definitions */ +#define UDPHY_PCS 0x4000 +#define UDPHY_PMA 0x8000 + +/* VO0 GRF Registers */ -+#define RK3588_GRF_VO0_CON0 0x0000 -+#define RK3588_GRF_VO0_CON2 0x0008 +#define DP_SINK_HPD_CFG BIT(11) +#define DP_SINK_HPD_SEL BIT(10) +#define DP_AUX_DIN_SEL BIT(9) +#define DP_AUX_DOUT_SEL BIT(8) +#define DP_LANE_SEL_N(n) GENMASK(2 * (n) + 1, 2 * (n)) +#define DP_LANE_SEL_ALL GENMASK(7, 0) -+#define PHY_AUX_DP_DATA_POL_NORMAL 0 -+#define PHY_AUX_DP_DATA_POL_INVERT 1 + +/* PMA CMN Registers */ +#define CMN_LANE_MUX_AND_EN_OFFSET 0x0288 /* cmn_reg00A2 */ @@ -362,10 +285,8 @@ index 000000000000..bb0beafb8578 +#define CMN_DP_LANE_EN_N(n) BIT(n) +#define CMN_DP_LANE_MUX_ALL GENMASK(7, 4) +#define CMN_DP_LANE_EN_ALL GENMASK(3, 0) -+#define PHY_LANE_MUX_USB 0 -+#define PHY_LANE_MUX_DP 1 + -+#define CMN_DP_LINK_OFFSET 0x28c /*cmn_reg00A3 */ ++#define CMN_DP_LINK_OFFSET 0x28c /* cmn_reg00A3 */ +#define CMN_DP_TX_LINK_BW GENMASK(6, 5) +#define CMN_DP_TX_LANE_SWAP_EN BIT(2) + @@ -396,8 +317,11 @@ index 000000000000..bb0beafb8578 +#define TRSV_LN2_MON_RX_CDR_DONE_OFFSET 0x1b84 /* trsv_reg06E1 */ +#define TRSV_LN2_MON_RX_CDR_LOCK_DONE BIT(0) + -+ -+#define BIT_WRITEABLE_SHIFT 16 ++#define BIT_WRITEABLE_SHIFT 16 ++#define PHY_AUX_DP_DATA_POL_NORMAL 0 ++#define PHY_AUX_DP_DATA_POL_INVERT 1 ++#define PHY_LANE_MUX_USB 0 ++#define PHY_LANE_MUX_DP 1 + +enum { + DP_BW_RBR, @@ -413,62 +337,63 @@ index 000000000000..bb0beafb8578 + UDPHY_MODE_DP_USB = BIT(1) | BIT(0), +}; + -+struct udphy_grf_reg { ++struct rk_udphy_grf_reg { + unsigned int offset; -+ unsigned int bitend; -+ unsigned int bitstart; + unsigned int disable; + unsigned int enable; +}; + -+struct udphy_grf_cfg { ++#define _RK_UDPHY_GEN_GRF_REG(offset, mask, disable, enable) \ ++{\ ++ offset, \ ++ FIELD_PREP_CONST(mask, disable) | (mask << BIT_WRITEABLE_SHIFT), \ ++ FIELD_PREP_CONST(mask, enable) | (mask << BIT_WRITEABLE_SHIFT), \ ++} ++ ++#define RK_UDPHY_GEN_GRF_REG(offset, bitend, bitstart, disable, enable) \ ++ _RK_UDPHY_GEN_GRF_REG(offset, GENMASK(bitend, bitstart), disable, enable) ++ ++struct rk_udphy_grf_cfg { + /* u2phy-grf */ -+ struct udphy_grf_reg bvalid_phy_con; -+ struct udphy_grf_reg bvalid_grf_con; ++ struct rk_udphy_grf_reg bvalid_phy_con; ++ struct rk_udphy_grf_reg bvalid_grf_con; + + /* usb-grf */ -+ struct udphy_grf_reg usb3otg0_cfg; -+ struct udphy_grf_reg usb3otg1_cfg; ++ struct rk_udphy_grf_reg usb3otg0_cfg; ++ struct rk_udphy_grf_reg usb3otg1_cfg; + + /* usbdpphy-grf */ -+ struct udphy_grf_reg low_pwrn; -+ struct udphy_grf_reg rx_lfps; ++ struct rk_udphy_grf_reg low_pwrn; ++ struct rk_udphy_grf_reg rx_lfps; +}; + -+struct udphy_vogrf_cfg { ++struct rk_udphy_vogrf_cfg { + /* vo-grf */ -+ struct udphy_grf_reg hpd_trigger; ++ struct rk_udphy_grf_reg hpd_trigger; ++ u32 dp_lane_reg; +}; + -+struct dp_tx_drv_ctrl { ++struct rk_udphy_dp_tx_drv_ctrl { + u32 trsv_reg0204; + u32 trsv_reg0205; + u32 trsv_reg0206; + u32 trsv_reg0207; +}; + -+struct rockchip_udphy; -+ -+struct rockchip_udphy_cfg { ++struct rk_udphy_cfg { ++ unsigned int num_phys; ++ unsigned int phy_ids[2]; + /* resets to be requested */ + const char * const *rst_list; + int num_rsts; + -+ struct udphy_grf_cfg grfcfg; -+ struct udphy_vogrf_cfg vogrfcfg[2]; -+ const struct dp_tx_drv_ctrl (*dp_tx_ctrl_cfg[4])[4]; -+ const struct dp_tx_drv_ctrl (*dp_tx_ctrl_cfg_typec[4])[4]; -+ int (*combophy_init)(struct rockchip_udphy *udphy); -+ int (*dp_phy_set_rate)(struct rockchip_udphy *udphy, -+ struct phy_configure_opts_dp *dp); -+ int (*dp_phy_set_voltages)(struct rockchip_udphy *udphy, -+ struct phy_configure_opts_dp *dp); -+ int (*hpd_event_trigger)(struct rockchip_udphy *udphy, bool hpd); -+ int (*dplane_enable)(struct rockchip_udphy *udphy, int dp_lanes); -+ int (*dplane_select)(struct rockchip_udphy *udphy); ++ struct rk_udphy_grf_cfg grfcfg; ++ struct rk_udphy_vogrf_cfg vogrfcfg[2]; ++ const struct rk_udphy_dp_tx_drv_ctrl (*dp_tx_ctrl_cfg[4])[4]; ++ const struct rk_udphy_dp_tx_drv_ctrl (*dp_tx_ctrl_cfg_typec[4])[4]; +}; + -+struct rockchip_udphy { ++struct rk_udphy { + struct device *dev; + struct regmap *pma_regmap; + struct regmap *u2phygrf; @@ -483,7 +408,8 @@ index 000000000000..bb0beafb8578 + int num_clks; + struct clk_bulk_data *clks; + struct clk *refclk; -+ struct reset_control **rsts; ++ int num_rsts; ++ struct reset_control_bulk_data *rsts; + + /* PHY status management */ + bool flip; @@ -506,11 +432,17 @@ index 000000000000..bb0beafb8578 + u8 bw; + int id; + ++ bool dp_in_use; ++ + /* PHY const config */ -+ const struct rockchip_udphy_cfg *cfgs; ++ const struct rk_udphy_cfg *cfgs; ++ ++ /* PHY devices */ ++ struct phy *phy_dp; ++ struct phy *phy_u3; +}; + -+static const struct dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_rbr_hbr[4][4] = { ++static const struct rk_udphy_dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_rbr_hbr[4][4] = { + /* voltage swing 0, pre-emphasis 0->3 */ + { + { 0x20, 0x10, 0x42, 0xe5 }, @@ -538,7 +470,7 @@ index 000000000000..bb0beafb8578 + }, +}; + -+static const struct dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_rbr_hbr_typec[4][4] = { ++static const struct rk_udphy_dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_rbr_hbr_typec[4][4] = { + /* voltage swing 0, pre-emphasis 0->3 */ + { + { 0x20, 0x10, 0x42, 0xe5 }, @@ -566,7 +498,7 @@ index 000000000000..bb0beafb8578 + }, +}; + -+static const struct dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_hbr2[4][4] = { ++static const struct rk_udphy_dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_hbr2[4][4] = { + /* voltage swing 0, pre-emphasis 0->3 */ + { + { 0x21, 0x10, 0x42, 0xe5 }, @@ -594,7 +526,7 @@ index 000000000000..bb0beafb8578 + }, +}; + -+static const struct dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_hbr3[4][4] = { ++static const struct rk_udphy_dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_hbr3[4][4] = { + /* voltage swing 0, pre-emphasis 0->3 */ + { + { 0x21, 0x10, 0x42, 0xe5 }, @@ -622,7 +554,7 @@ index 000000000000..bb0beafb8578 + }, +}; + -+static const struct reg_sequence rk3588_udphy_24m_refclk_cfg[] = { ++static const struct reg_sequence rk_udphy_24m_refclk_cfg[] = { + {0x0090, 0x68}, {0x0094, 0x68}, + {0x0128, 0x24}, {0x012c, 0x44}, + {0x0130, 0x3f}, {0x0134, 0x44}, @@ -661,82 +593,76 @@ index 000000000000..bb0beafb8578 + {0x1a5c, 0xe0}, {0x1a64, 0xa8} +}; + -+static const struct reg_sequence rk3588_udphy_26m_refclk_cfg[] = { ++static const struct reg_sequence rk_udphy_26m_refclk_cfg[] = { + {0x0830, 0x07}, {0x085c, 0x80}, + {0x1030, 0x07}, {0x105c, 0x80}, + {0x1830, 0x07}, {0x185c, 0x80}, + {0x2030, 0x07}, {0x205c, 0x80}, + {0x0228, 0x38}, {0x0104, 0x44}, -+ {0x0248, 0x44}, {0x038C, 0x02}, ++ {0x0248, 0x44}, {0x038c, 0x02}, + {0x0878, 0x04}, {0x1878, 0x04}, + {0x0898, 0x77}, {0x1898, 0x77}, + {0x0054, 0x01}, {0x00e0, 0x38}, + {0x0060, 0x24}, {0x0064, 0x77}, -+ {0x0070, 0x76}, {0x0234, 0xE8}, -+ {0x0AF4, 0x15}, {0x1AF4, 0x15}, -+ {0x081C, 0xE5}, {0x181C, 0xE5}, -+ {0x099C, 0x48}, {0x199C, 0x48}, -+ {0x09A4, 0x07}, {0x09A8, 0x22}, -+ {0x19A4, 0x07}, {0x19A8, 0x22}, -+ {0x09B8, 0x3E}, {0x19B8, 0x3E}, -+ {0x09E4, 0x02}, {0x19E4, 0x02}, -+ {0x0A34, 0x1E}, {0x1A34, 0x1E}, -+ {0x0A98, 0x2F}, {0x1A98, 0x2F}, -+ {0x0c30, 0x0E}, {0x0C48, 0x06}, -+ {0x1C30, 0x0E}, {0x1C48, 0x06}, -+ {0x028C, 0x18}, {0x0AF0, 0x00}, -+ {0x1AF0, 0x00} ++ {0x0070, 0x76}, {0x0234, 0xe8}, ++ {0x0af4, 0x15}, {0x1af4, 0x15}, ++ {0x081c, 0xe5}, {0x181c, 0xe5}, ++ {0x099c, 0x48}, {0x199c, 0x48}, ++ {0x09a4, 0x07}, {0x09a8, 0x22}, ++ {0x19a4, 0x07}, {0x19a8, 0x22}, ++ {0x09b8, 0x3e}, {0x19b8, 0x3e}, ++ {0x09e4, 0x02}, {0x19e4, 0x02}, ++ {0x0a34, 0x1e}, {0x1a34, 0x1e}, ++ {0x0a98, 0x2f}, {0x1a98, 0x2f}, ++ {0x0c30, 0x0e}, {0x0c48, 0x06}, ++ {0x1c30, 0x0e}, {0x1c48, 0x06}, ++ {0x028c, 0x18}, {0x0af0, 0x00}, ++ {0x1af0, 0x00} +}; + -+static const struct reg_sequence rk3588_udphy_init_sequence[] = { -+ {0x0104, 0x44}, {0x0234, 0xE8}, -+ {0x0248, 0x44}, {0x028C, 0x18}, -+ {0x081C, 0xE5}, {0x0878, 0x00}, -+ {0x0994, 0x1C}, {0x0AF0, 0x00}, -+ {0x181C, 0xE5}, {0x1878, 0x00}, -+ {0x1994, 0x1C}, {0x1AF0, 0x00}, -+ {0x0428, 0x60}, {0x0D58, 0x33}, -+ {0x1D58, 0x33}, {0x0990, 0x74}, -+ {0x0D64, 0x17}, {0x08C8, 0x13}, -+ {0x1990, 0x74}, {0x1D64, 0x17}, -+ {0x18C8, 0x13}, {0x0D90, 0x40}, -+ {0x0DA8, 0x40}, {0x0DC0, 0x40}, -+ {0x0DD8, 0x40}, {0x1D90, 0x40}, -+ {0x1DA8, 0x40}, {0x1DC0, 0x40}, -+ {0x1DD8, 0x40}, {0x03C0, 0x30}, -+ {0x03C4, 0x06}, {0x0E10, 0x00}, -+ {0x1E10, 0x00}, {0x043C, 0x0F}, -+ {0x0D2C, 0xFF}, {0x1D2C, 0xFF}, -+ {0x0D34, 0x0F}, {0x1D34, 0x0F}, -+ {0x08FC, 0x2A}, {0x0914, 0x28}, -+ {0x0A30, 0x03}, {0x0E38, 0x05}, -+ {0x0ECC, 0x27}, {0x0ED0, 0x22}, -+ {0x0ED4, 0x26}, {0x18FC, 0x2A}, -+ {0x1914, 0x28}, {0x1A30, 0x03}, -+ {0x1E38, 0x05}, {0x1ECC, 0x27}, -+ {0x1ED0, 0x22}, {0x1ED4, 0x26}, -+ {0x0048, 0x0F}, {0x0060, 0x3C}, -+ {0x0064, 0xF7}, {0x006C, 0x20}, -+ {0x0070, 0x7D}, {0x0074, 0x68}, -+ {0x0AF4, 0x1A}, {0x1AF4, 0x1A}, -+ {0x0440, 0x3F}, {0x10D4, 0x08}, -+ {0x20D4, 0x08}, {0x00D4, 0x30}, ++static const struct reg_sequence rk_udphy_init_sequence[] = { ++ {0x0104, 0x44}, {0x0234, 0xe8}, ++ {0x0248, 0x44}, {0x028c, 0x18}, ++ {0x081c, 0xe5}, {0x0878, 0x00}, ++ {0x0994, 0x1c}, {0x0af0, 0x00}, ++ {0x181c, 0xe5}, {0x1878, 0x00}, ++ {0x1994, 0x1c}, {0x1af0, 0x00}, ++ {0x0428, 0x60}, {0x0d58, 0x33}, ++ {0x1d58, 0x33}, {0x0990, 0x74}, ++ {0x0d64, 0x17}, {0x08c8, 0x13}, ++ {0x1990, 0x74}, {0x1d64, 0x17}, ++ {0x18c8, 0x13}, {0x0d90, 0x40}, ++ {0x0da8, 0x40}, {0x0dc0, 0x40}, ++ {0x0dd8, 0x40}, {0x1d90, 0x40}, ++ {0x1da8, 0x40}, {0x1dc0, 0x40}, ++ {0x1dd8, 0x40}, {0x03c0, 0x30}, ++ {0x03c4, 0x06}, {0x0e10, 0x00}, ++ {0x1e10, 0x00}, {0x043c, 0x0f}, ++ {0x0d2c, 0xff}, {0x1d2c, 0xff}, ++ {0x0d34, 0x0f}, {0x1d34, 0x0f}, ++ {0x08fc, 0x2a}, {0x0914, 0x28}, ++ {0x0a30, 0x03}, {0x0e38, 0x03}, ++ {0x0ecc, 0x27}, {0x0ed0, 0x22}, ++ {0x0ed4, 0x26}, {0x18fc, 0x2a}, ++ {0x1914, 0x28}, {0x1a30, 0x03}, ++ {0x1e38, 0x03}, {0x1ecc, 0x27}, ++ {0x1ed0, 0x22}, {0x1ed4, 0x26}, ++ {0x0048, 0x0f}, {0x0060, 0x3c}, ++ {0x0064, 0xf7}, {0x006c, 0x20}, ++ {0x0070, 0x7d}, {0x0074, 0x68}, ++ {0x0af4, 0x1a}, {0x1af4, 0x1a}, ++ {0x0440, 0x3f}, {0x10d4, 0x08}, ++ {0x20d4, 0x08}, {0x00d4, 0x30}, + {0x0024, 0x6e}, +}; + -+static inline int grfreg_write(struct regmap *base, -+ const struct udphy_grf_reg *reg, bool en) ++static inline int rk_udphy_grfreg_write(struct regmap *base, ++ const struct rk_udphy_grf_reg *reg, bool en) +{ -+ u32 val, mask, tmp; -+ -+ tmp = en ? reg->enable : reg->disable; -+ mask = GENMASK(reg->bitend, reg->bitstart); -+ val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); -+ -+ return regmap_write(base, reg->offset, val); ++ return regmap_write(base, reg->offset, en ? reg->enable : reg->disable); +} + -+static int udphy_clk_init(struct rockchip_udphy *udphy, struct device *dev) ++static int rk_udphy_clk_init(struct rk_udphy *udphy, struct device *dev) +{ + int i; + @@ -753,117 +679,67 @@ index 000000000000..bb0beafb8578 + } + + if (!udphy->refclk) -+ dev_warn(udphy->dev, "no refclk found\n"); ++ return dev_err_probe(udphy->dev, -EINVAL, "no refclk found\n"); + + return 0; +} + -+static int udphy_reset_init(struct rockchip_udphy *udphy, struct device *dev) ++static int rk_udphy_reset_assert_all(struct rk_udphy *udphy) +{ -+ const struct rockchip_udphy_cfg *cfg = udphy->cfgs; ++ return reset_control_bulk_assert(udphy->num_rsts, udphy->rsts); ++} ++ ++static int rk_udphy_reset_deassert_all(struct rk_udphy *udphy) ++{ ++ return reset_control_bulk_deassert(udphy->num_rsts, udphy->rsts); ++} ++ ++static int rk_udphy_reset_deassert(struct rk_udphy *udphy, char *name) ++{ ++ struct reset_control_bulk_data *list = udphy->rsts; + int idx; + -+ udphy->rsts = devm_kcalloc(dev, cfg->num_rsts, -+ sizeof(*udphy->rsts), GFP_KERNEL); -+ if (!udphy->rsts) -+ return -ENOMEM; -+ -+ for (idx = 0; idx < cfg->num_rsts; idx++) { -+ struct reset_control *rst; -+ const char *name = cfg->rst_list[idx]; -+ -+ rst = devm_reset_control_get(dev, name); -+ if (IS_ERR(rst)) { -+ dev_err(dev, "failed to get %s reset\n", name); -+ devm_kfree(dev, (void *)udphy->rsts); -+ return PTR_ERR(rst); -+ } -+ -+ udphy->rsts[idx] = rst; -+ } -+ -+ return 0; -+} -+ -+static int udphy_reset_assert_all(struct rockchip_udphy *udphy) -+{ -+ const struct rockchip_udphy_cfg *cfg = udphy->cfgs; -+ int idx, ret; -+ -+ for (idx = 0; idx < cfg->num_rsts; idx++) { -+ ret = reset_control_assert(udphy->rsts[idx]); -+ if (ret < 0) -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static int udphy_reset_deassert_all(struct rockchip_udphy *udphy) -+{ -+ const struct rockchip_udphy_cfg *cfg = udphy->cfgs; -+ int idx, ret; -+ -+ for (idx = 0; idx < cfg->num_rsts; idx++) { -+ ret = reset_control_deassert(udphy->rsts[idx]); -+ if (ret < 0) -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static int udphy_get_rst_idx(const char * const *list, int num, char *name) -+{ -+ int idx; -+ -+ for (idx = 0; idx < num; idx++) { -+ if (!strcmp(list[idx], name)) -+ return idx; ++ for (idx = 0; idx < udphy->num_rsts; idx++) { ++ if (!strcmp(list[idx].id, name)) ++ return reset_control_deassert(list[idx].rstc); + } + + return -EINVAL; +} + -+static int udphy_reset_assert(struct rockchip_udphy *udphy, char *name) ++static int rk_udphy_reset_init(struct rk_udphy *udphy, struct device *dev) +{ -+ const struct rockchip_udphy_cfg *cfg = udphy->cfgs; ++ const struct rk_udphy_cfg *cfg = udphy->cfgs; + int idx; + -+ idx = udphy_get_rst_idx(cfg->rst_list, cfg->num_rsts, name); -+ if (idx < 0) -+ return idx; ++ udphy->num_rsts = cfg->num_rsts; ++ udphy->rsts = devm_kcalloc(dev, udphy->num_rsts, ++ sizeof(*udphy->rsts), GFP_KERNEL); ++ if (!udphy->rsts) ++ return -ENOMEM; + -+ return reset_control_assert(udphy->rsts[idx]); ++ for (idx = 0; idx < cfg->num_rsts; idx++) ++ udphy->rsts[idx].id = cfg->rst_list[idx]; ++ ++ return devm_reset_control_bulk_get_exclusive(dev, cfg->num_rsts, ++ udphy->rsts); +} + -+static int udphy_reset_deassert(struct rockchip_udphy *udphy, char *name) ++static void rk_udphy_u3_port_disable(struct rk_udphy *udphy, u8 disable) +{ -+ const struct rockchip_udphy_cfg *cfg = udphy->cfgs; -+ int idx; -+ -+ idx = udphy_get_rst_idx(cfg->rst_list, cfg->num_rsts, name); -+ if (idx < 0) -+ return idx; -+ -+ return reset_control_deassert(udphy->rsts[idx]); -+} -+ -+static void udphy_u3_port_disable(struct rockchip_udphy *udphy, u8 disable) -+{ -+ const struct rockchip_udphy_cfg *cfg = udphy->cfgs; -+ const struct udphy_grf_reg *preg; ++ const struct rk_udphy_cfg *cfg = udphy->cfgs; ++ const struct rk_udphy_grf_reg *preg; + + preg = udphy->id ? &cfg->grfcfg.usb3otg1_cfg : &cfg->grfcfg.usb3otg0_cfg; -+ grfreg_write(udphy->usbgrf, preg, disable); ++ rk_udphy_grfreg_write(udphy->usbgrf, preg, disable); +} + -+static void udphy_usb_bvalid_enable(struct rockchip_udphy *udphy, u8 enable) ++static void rk_udphy_usb_bvalid_enable(struct rk_udphy *udphy, u8 enable) +{ -+ const struct rockchip_udphy_cfg *cfg = udphy->cfgs; ++ const struct rk_udphy_cfg *cfg = udphy->cfgs; + -+ grfreg_write(udphy->u2phygrf, &cfg->grfcfg.bvalid_phy_con, enable); -+ grfreg_write(udphy->u2phygrf, &cfg->grfcfg.bvalid_grf_con, enable); ++ rk_udphy_grfreg_write(udphy->u2phygrf, &cfg->grfcfg.bvalid_phy_con, enable); ++ rk_udphy_grfreg_write(udphy->u2phygrf, &cfg->grfcfg.bvalid_grf_con, enable); +} + +/* @@ -902,17 +778,36 @@ index 000000000000..bb0beafb8578 + * --------------------------------------------------------------------------- + */ + -+static int udphy_dplane_select(struct rockchip_udphy *udphy) ++static void rk_udphy_dplane_select(struct rk_udphy *udphy) +{ -+ const struct rockchip_udphy_cfg *cfg = udphy->cfgs; ++ const struct rk_udphy_cfg *cfg = udphy->cfgs; ++ u32 value = 0; + -+ if (cfg->dplane_select) -+ return cfg->dplane_select(udphy); ++ switch (udphy->mode) { ++ case UDPHY_MODE_DP: ++ value |= 2 << udphy->dp_lane_sel[2] * 2; ++ value |= 3 << udphy->dp_lane_sel[3] * 2; ++ fallthrough; + -+ return 0; ++ case UDPHY_MODE_DP_USB: ++ value |= 0 << udphy->dp_lane_sel[0] * 2; ++ value |= 1 << udphy->dp_lane_sel[1] * 2; ++ break; ++ ++ case UDPHY_MODE_USB: ++ break; ++ ++ default: ++ break; ++ } ++ ++ regmap_write(udphy->vogrf, cfg->vogrfcfg[udphy->id].dp_lane_reg, ++ ((DP_AUX_DIN_SEL | DP_AUX_DOUT_SEL | DP_LANE_SEL_ALL) << 16) | ++ FIELD_PREP(DP_AUX_DIN_SEL, udphy->dp_aux_din_sel) | ++ FIELD_PREP(DP_AUX_DOUT_SEL, udphy->dp_aux_dout_sel) | value); +} + -+static int udphy_dplane_get(struct rockchip_udphy *udphy) ++static int rk_udphy_dplane_get(struct rk_udphy *udphy) +{ + int dp_lanes; + @@ -920,11 +815,12 @@ index 000000000000..bb0beafb8578 + case UDPHY_MODE_DP: + dp_lanes = 4; + break; ++ + case UDPHY_MODE_DP_USB: + dp_lanes = 2; + break; ++ + case UDPHY_MODE_USB: -+ fallthrough; + default: + dp_lanes = 0; + break; @@ -933,18 +829,36 @@ index 000000000000..bb0beafb8578 + return dp_lanes; +} + -+static int udphy_dplane_enable(struct rockchip_udphy *udphy, int dp_lanes) ++static void rk_udphy_dplane_enable(struct rk_udphy *udphy, int dp_lanes) +{ -+ const struct rockchip_udphy_cfg *cfg = udphy->cfgs; -+ int ret = 0; ++ u32 val = 0; ++ int i; + -+ if (cfg->dplane_enable) -+ ret = cfg->dplane_enable(udphy, dp_lanes); ++ for (i = 0; i < dp_lanes; i++) ++ val |= BIT(udphy->dp_lane_sel[i]); + -+ return ret; ++ regmap_update_bits(udphy->pma_regmap, CMN_LANE_MUX_AND_EN_OFFSET, CMN_DP_LANE_EN_ALL, ++ FIELD_PREP(CMN_DP_LANE_EN_ALL, val)); ++ ++ if (!dp_lanes) ++ regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET, ++ CMN_DP_CMN_RSTN, FIELD_PREP(CMN_DP_CMN_RSTN, 0x0)); +} + -+static int upphy_set_typec_default_mapping(struct rockchip_udphy *udphy) ++static void rk_udphy_dp_hpd_event_trigger(struct rk_udphy *udphy, bool hpd) ++{ ++ const struct rk_udphy_cfg *cfg = udphy->cfgs; ++ ++ udphy->dp_sink_hpd_sel = true; ++ udphy->dp_sink_hpd_cfg = hpd; ++ ++ if (!udphy->dp_in_use) ++ return; ++ ++ rk_udphy_grfreg_write(udphy->vogrf, &cfg->vogrfcfg[udphy->id].hpd_trigger, hpd); ++} ++ ++static void rk_udphy_set_typec_default_mapping(struct rk_udphy *udphy) +{ + if (udphy->flip) { + udphy->dp_lane_sel[0] = 0; @@ -975,14 +889,12 @@ index 000000000000..bb0beafb8578 + } + + udphy->mode = UDPHY_MODE_DP_USB; -+ -+ return 0; +} + -+static int udphy_orien_sw_set(struct typec_switch_dev *sw, -+ enum typec_orientation orien) ++static int rk_udphy_orien_sw_set(struct typec_switch_dev *sw, ++ enum typec_orientation orien) +{ -+ struct rockchip_udphy *udphy = typec_switch_get_drvdata(sw); ++ struct rk_udphy *udphy = typec_switch_get_drvdata(sw); + + mutex_lock(&udphy->mutex); + @@ -990,26 +902,33 @@ index 000000000000..bb0beafb8578 + gpiod_set_value_cansleep(udphy->sbu1_dc_gpio, 0); + gpiod_set_value_cansleep(udphy->sbu2_dc_gpio, 0); + /* unattached */ -+ udphy_usb_bvalid_enable(udphy, false); ++ rk_udphy_usb_bvalid_enable(udphy, false); + goto unlock_ret; + } + + udphy->flip = (orien == TYPEC_ORIENTATION_REVERSE) ? true : false; -+ upphy_set_typec_default_mapping(udphy); -+ udphy_usb_bvalid_enable(udphy, true); ++ rk_udphy_set_typec_default_mapping(udphy); ++ rk_udphy_usb_bvalid_enable(udphy, true); + +unlock_ret: + mutex_unlock(&udphy->mutex); + return 0; +} + -+static int udphy_setup_orien_switch(struct rockchip_udphy *udphy) ++static void rk_udphy_orien_switch_unregister(void *data) ++{ ++ struct rk_udphy *udphy = data; ++ ++ typec_switch_unregister(udphy->sw); ++} ++ ++static int rk_udphy_setup_orien_switch(struct rk_udphy *udphy) +{ + struct typec_switch_desc sw_desc = { }; + + sw_desc.drvdata = udphy; + sw_desc.fwnode = dev_fwnode(udphy->dev); -+ sw_desc.set = udphy_orien_sw_set; ++ sw_desc.set = rk_udphy_orien_sw_set; + + udphy->sw = typec_switch_register(udphy->dev, &sw_desc); + if (IS_ERR(udphy->sw)) { @@ -1018,19 +937,161 @@ index 000000000000..bb0beafb8578 + return PTR_ERR(udphy->sw); + } + ++ return devm_add_action_or_reset(udphy->dev, ++ rk_udphy_orien_switch_unregister, udphy); ++} ++ ++static int rk_udphy_refclk_set(struct rk_udphy *udphy) ++{ ++ unsigned long rate; ++ int ret; ++ ++ /* configure phy reference clock */ ++ rate = clk_get_rate(udphy->refclk); ++ dev_dbg(udphy->dev, "refclk freq %ld\n", rate); ++ ++ switch (rate) { ++ case 24000000: ++ ret = regmap_multi_reg_write(udphy->pma_regmap, rk_udphy_24m_refclk_cfg, ++ ARRAY_SIZE(rk_udphy_24m_refclk_cfg)); ++ if (ret) ++ return ret; ++ break; ++ ++ case 26000000: ++ /* register default is 26MHz */ ++ ret = regmap_multi_reg_write(udphy->pma_regmap, rk_udphy_26m_refclk_cfg, ++ ARRAY_SIZE(rk_udphy_26m_refclk_cfg)); ++ if (ret) ++ return ret; ++ break; ++ ++ default: ++ dev_err(udphy->dev, "unsupported refclk freq %ld\n", rate); ++ return -EINVAL; ++ } ++ + return 0; +} + -+static void udphy_orien_switch_unregister(void *data) ++static int rk_udphy_status_check(struct rk_udphy *udphy) +{ -+ struct rockchip_udphy *udphy = data; ++ unsigned int val; ++ int ret; + -+ typec_switch_unregister(udphy->sw); ++ /* LCPLL check */ ++ if (udphy->mode & UDPHY_MODE_USB) { ++ ret = regmap_read_poll_timeout(udphy->pma_regmap, CMN_ANA_LCPLL_DONE_OFFSET, ++ val, (val & CMN_ANA_LCPLL_AFC_DONE) && ++ (val & CMN_ANA_LCPLL_LOCK_DONE), 200, 100000); ++ if (ret) { ++ dev_err(udphy->dev, "cmn ana lcpll lock timeout\n"); ++ /* ++ * If earlier software (U-Boot) enabled USB once already ++ * the PLL may have problems locking on the first try. ++ * It will be successful on the second try, so for the ++ * time being a -EPROBE_DEFER will solve the issue. ++ * ++ * This requires further investigation to understand the ++ * root cause, especially considering that the driver is ++ * asserting all reset lines at probe time. ++ */ ++ return -EPROBE_DEFER; ++ } ++ ++ if (!udphy->flip) { ++ ret = regmap_read_poll_timeout(udphy->pma_regmap, ++ TRSV_LN0_MON_RX_CDR_DONE_OFFSET, val, ++ val & TRSV_LN0_MON_RX_CDR_LOCK_DONE, ++ 200, 100000); ++ if (ret) ++ dev_err(udphy->dev, "trsv ln0 mon rx cdr lock timeout\n"); ++ } else { ++ ret = regmap_read_poll_timeout(udphy->pma_regmap, ++ TRSV_LN2_MON_RX_CDR_DONE_OFFSET, val, ++ val & TRSV_LN2_MON_RX_CDR_LOCK_DONE, ++ 200, 100000); ++ if (ret) ++ dev_err(udphy->dev, "trsv ln2 mon rx cdr lock timeout\n"); ++ } ++ } ++ ++ return 0; +} + -+static int udphy_setup(struct rockchip_udphy *udphy) ++static int rk_udphy_init(struct rk_udphy *udphy) ++{ ++ const struct rk_udphy_cfg *cfg = udphy->cfgs; ++ int ret; ++ ++ rk_udphy_reset_assert_all(udphy); ++ usleep_range(10000, 11000); ++ ++ /* enable rx lfps for usb */ ++ if (udphy->mode & UDPHY_MODE_USB) ++ rk_udphy_grfreg_write(udphy->udphygrf, &cfg->grfcfg.rx_lfps, true); ++ ++ /* Step 1: power on pma and deassert apb rstn */ ++ rk_udphy_grfreg_write(udphy->udphygrf, &cfg->grfcfg.low_pwrn, true); ++ ++ rk_udphy_reset_deassert(udphy, "pma_apb"); ++ rk_udphy_reset_deassert(udphy, "pcs_apb"); ++ ++ /* Step 2: set init sequence and phy refclk */ ++ ret = regmap_multi_reg_write(udphy->pma_regmap, rk_udphy_init_sequence, ++ ARRAY_SIZE(rk_udphy_init_sequence)); ++ if (ret) { ++ dev_err(udphy->dev, "init sequence set error %d\n", ret); ++ goto assert_resets; ++ } ++ ++ ret = rk_udphy_refclk_set(udphy); ++ if (ret) { ++ dev_err(udphy->dev, "refclk set error %d\n", ret); ++ goto assert_resets; ++ } ++ ++ /* Step 3: configure lane mux */ ++ regmap_update_bits(udphy->pma_regmap, CMN_LANE_MUX_AND_EN_OFFSET, ++ CMN_DP_LANE_MUX_ALL | CMN_DP_LANE_EN_ALL, ++ FIELD_PREP(CMN_DP_LANE_MUX_N(3), udphy->lane_mux_sel[3]) | ++ FIELD_PREP(CMN_DP_LANE_MUX_N(2), udphy->lane_mux_sel[2]) | ++ FIELD_PREP(CMN_DP_LANE_MUX_N(1), udphy->lane_mux_sel[1]) | ++ FIELD_PREP(CMN_DP_LANE_MUX_N(0), udphy->lane_mux_sel[0]) | ++ FIELD_PREP(CMN_DP_LANE_EN_ALL, 0)); ++ ++ /* Step 4: deassert init rstn and wait for 200ns from datasheet */ ++ if (udphy->mode & UDPHY_MODE_USB) ++ rk_udphy_reset_deassert(udphy, "init"); ++ ++ if (udphy->mode & UDPHY_MODE_DP) { ++ regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET, ++ CMN_DP_INIT_RSTN, ++ FIELD_PREP(CMN_DP_INIT_RSTN, 0x1)); ++ } ++ ++ udelay(1); ++ ++ /* Step 5: deassert cmn/lane rstn */ ++ if (udphy->mode & UDPHY_MODE_USB) { ++ rk_udphy_reset_deassert(udphy, "cmn"); ++ rk_udphy_reset_deassert(udphy, "lane"); ++ } ++ ++ /* Step 6: wait for lock done of pll */ ++ ret = rk_udphy_status_check(udphy); ++ if (ret) ++ goto assert_resets; ++ ++ return 0; ++ ++assert_resets: ++ rk_udphy_reset_assert_all(udphy); ++ return ret; ++} ++ ++static int rk_udphy_setup(struct rk_udphy *udphy) +{ -+ const struct rockchip_udphy_cfg *cfg = udphy->cfgs; + int ret = 0; + + ret = clk_bulk_prepare_enable(udphy->num_clks, udphy->clks); @@ -1039,66 +1100,55 @@ index 000000000000..bb0beafb8578 + return ret; + } + -+ if (cfg->combophy_init) { -+ ret = cfg->combophy_init(udphy); -+ if (ret) { -+ dev_err(udphy->dev, "failed to init combophy\n"); -+ clk_bulk_disable_unprepare(udphy->num_clks, udphy->clks); -+ return ret; -+ } ++ ret = rk_udphy_init(udphy); ++ if (ret) { ++ dev_err(udphy->dev, "failed to init combophy\n"); ++ clk_bulk_disable_unprepare(udphy->num_clks, udphy->clks); ++ return ret; + } + + return 0; +} + -+static int udphy_disable(struct rockchip_udphy *udphy) ++static void rk_udphy_disable(struct rk_udphy *udphy) +{ + clk_bulk_disable_unprepare(udphy->num_clks, udphy->clks); -+ udphy_reset_assert_all(udphy); -+ -+ return 0; ++ rk_udphy_reset_assert_all(udphy); +} + -+static int udphy_parse_lane_mux_data(struct rockchip_udphy *udphy, struct device_node *np) ++static int rk_udphy_parse_lane_mux_data(struct rk_udphy *udphy) +{ -+ struct property *prop; -+ int ret, i, len, num_lanes; ++ int ret, i, num_lanes; + -+ prop = of_find_property(np, "rockchip,dp-lane-mux", &len); -+ if (!prop) { -+ dev_dbg(udphy->dev, "failed to find dp lane mux, following dp alt mode\n"); ++ num_lanes = device_property_count_u32(udphy->dev, "rockchip,dp-lane-mux"); ++ if (num_lanes < 0) { ++ dev_dbg(udphy->dev, "no dp-lane-mux, following dp alt mode\n"); + udphy->mode = UDPHY_MODE_USB; + return 0; + } + -+ num_lanes = len / sizeof(u32); ++ if (num_lanes != 2 && num_lanes != 4) ++ return dev_err_probe(udphy->dev, -EINVAL, ++ "invalid number of lane mux\n"); + -+ if (num_lanes != 2 && num_lanes != 4) { -+ dev_err(udphy->dev, "invalid number of lane mux\n"); -+ return -EINVAL; -+ } -+ -+ ret = of_property_read_u32_array(np, "rockchip,dp-lane-mux", udphy->dp_lane_sel, num_lanes); -+ if (ret) { -+ dev_err(udphy->dev, "get dp lane mux failed\n"); -+ return -EINVAL; -+ } ++ ret = device_property_read_u32_array(udphy->dev, "rockchip,dp-lane-mux", ++ udphy->dp_lane_sel, num_lanes); ++ if (ret) ++ return dev_err_probe(udphy->dev, ret, "get dp lane mux failed\n"); + + for (i = 0; i < num_lanes; i++) { + int j; + -+ if (udphy->dp_lane_sel[i] > 3) { -+ dev_err(udphy->dev, "lane mux between 0 and 3, exceeding the range\n"); -+ return -EINVAL; -+ } ++ if (udphy->dp_lane_sel[i] > 3) ++ return dev_err_probe(udphy->dev, -EINVAL, ++ "lane mux between 0 and 3, exceeding the range\n"); + + udphy->lane_mux_sel[udphy->dp_lane_sel[i]] = PHY_LANE_MUX_DP; + + for (j = i + 1; j < num_lanes; j++) { -+ if (udphy->dp_lane_sel[i] == udphy->dp_lane_sel[j]) { -+ dev_err(udphy->dev, "set repeat lane mux value\n"); -+ return -EINVAL; -+ } ++ if (udphy->dp_lane_sel[i] == udphy->dp_lane_sel[j]) ++ return dev_err_probe(udphy->dev, -EINVAL, ++ "set repeat lane mux value\n"); + } + } + @@ -1111,7 +1161,7 @@ index 000000000000..bb0beafb8578 + return 0; +} + -+static int udphy_get_initial_status(struct rockchip_udphy *udphy) ++static int rk_udphy_get_initial_status(struct rk_udphy *udphy) +{ + int ret; + u32 value; @@ -1122,64 +1172,41 @@ index 000000000000..bb0beafb8578 + return ret; + } + -+ udphy_reset_deassert_all(udphy); ++ rk_udphy_reset_deassert_all(udphy); + + regmap_read(udphy->pma_regmap, CMN_LANE_MUX_AND_EN_OFFSET, &value); + if (FIELD_GET(CMN_DP_LANE_MUX_ALL, value) && FIELD_GET(CMN_DP_LANE_EN_ALL, value)) + udphy->status = UDPHY_MODE_DP; + else -+ udphy_disable(udphy); ++ rk_udphy_disable(udphy); + + return 0; +} + -+static int udphy_parse_dt(struct rockchip_udphy *udphy, struct device *dev) ++static int rk_udphy_parse_dt(struct rk_udphy *udphy) +{ -+ struct device_node *np = dev->of_node; ++ struct device *dev = udphy->dev; ++ struct device_node *np = dev_of_node(dev); + enum usb_device_speed maximum_speed; + int ret; + + udphy->u2phygrf = syscon_regmap_lookup_by_phandle(np, "rockchip,u2phy-grf"); -+ if (IS_ERR(udphy->u2phygrf)) { -+ if (PTR_ERR(udphy->u2phygrf) == -ENODEV) { -+ dev_warn(dev, "missing u2phy-grf dt node\n"); -+ udphy->u2phygrf = NULL; -+ } else { -+ return PTR_ERR(udphy->u2phygrf); -+ } -+ } ++ if (IS_ERR(udphy->u2phygrf)) ++ return dev_err_probe(dev, PTR_ERR(udphy->u2phygrf), "failed to get u2phy-grf\n"); + + udphy->udphygrf = syscon_regmap_lookup_by_phandle(np, "rockchip,usbdpphy-grf"); -+ if (IS_ERR(udphy->udphygrf)) { -+ if (PTR_ERR(udphy->udphygrf) == -ENODEV) { -+ dev_warn(dev, "missing usbdpphy-grf dt node\n"); -+ udphy->udphygrf = NULL; -+ } else { -+ return PTR_ERR(udphy->udphygrf); -+ } -+ } ++ if (IS_ERR(udphy->udphygrf)) ++ return dev_err_probe(dev, PTR_ERR(udphy->udphygrf), "failed to get usbdpphy-grf\n"); + + udphy->usbgrf = syscon_regmap_lookup_by_phandle(np, "rockchip,usb-grf"); -+ if (IS_ERR(udphy->usbgrf)) { -+ if (PTR_ERR(udphy->usbgrf) == -ENODEV) { -+ dev_warn(dev, "missing usb-grf dt node\n"); -+ udphy->usbgrf = NULL; -+ } else { -+ return PTR_ERR(udphy->usbgrf); -+ } -+ } ++ if (IS_ERR(udphy->usbgrf)) ++ return dev_err_probe(dev, PTR_ERR(udphy->usbgrf), "failed to get usb-grf\n"); + + udphy->vogrf = syscon_regmap_lookup_by_phandle(np, "rockchip,vo-grf"); -+ if (IS_ERR(udphy->vogrf)) { -+ if (PTR_ERR(udphy->vogrf) == -ENODEV) { -+ dev_warn(dev, "missing vo-grf dt node\n"); -+ udphy->vogrf = NULL; -+ } else { -+ return PTR_ERR(udphy->vogrf); -+ } -+ } ++ if (IS_ERR(udphy->vogrf)) ++ return dev_err_probe(dev, PTR_ERR(udphy->vogrf), "failed to get vo-grf\n"); + -+ ret = udphy_parse_lane_mux_data(udphy, np); ++ ret = rk_udphy_parse_lane_mux_data(udphy); + if (ret) + return ret; + @@ -1196,18 +1223,18 @@ index 000000000000..bb0beafb8578 + udphy->hs = maximum_speed <= USB_SPEED_HIGH ? true : false; + } + -+ ret = udphy_clk_init(udphy, dev); ++ ret = rk_udphy_clk_init(udphy, dev); + if (ret) + return ret; + -+ ret = udphy_reset_init(udphy, dev); ++ ret = rk_udphy_reset_init(udphy, dev); + if (ret) + return ret; + + return 0; +} + -+static int udphy_power_on(struct rockchip_udphy *udphy, u8 mode) ++static int rk_udphy_power_on(struct rk_udphy *udphy, u8 mode) +{ + int ret; + @@ -1218,22 +1245,20 @@ index 000000000000..bb0beafb8578 + + if (udphy->status == UDPHY_MODE_NONE) { + udphy->mode_change = false; -+ ret = udphy_setup(udphy); ++ ret = rk_udphy_setup(udphy); + if (ret) + return ret; + + if (udphy->mode & UDPHY_MODE_USB) -+ udphy_u3_port_disable(udphy, false); ++ rk_udphy_u3_port_disable(udphy, false); + } else if (udphy->mode_change) { + udphy->mode_change = false; + udphy->status = UDPHY_MODE_NONE; + if (udphy->mode == UDPHY_MODE_DP) -+ udphy_u3_port_disable(udphy, true); ++ rk_udphy_u3_port_disable(udphy, true); + -+ ret = udphy_disable(udphy); -+ if (ret) -+ return ret; -+ ret = udphy_setup(udphy); ++ rk_udphy_disable(udphy); ++ ret = rk_udphy_setup(udphy); + if (ret) + return ret; + } @@ -1243,48 +1268,63 @@ index 000000000000..bb0beafb8578 + return 0; +} + -+static int udphy_power_off(struct rockchip_udphy *udphy, u8 mode) ++static void rk_udphy_power_off(struct rk_udphy *udphy, u8 mode) +{ -+ int ret; -+ + if (!(udphy->mode & mode)) { + dev_info(udphy->dev, "mode 0x%02x is not support\n", mode); -+ return 0; ++ return; + } + + if (!udphy->status) -+ return 0; ++ return; + + udphy->status &= ~mode; + -+ if (udphy->status == UDPHY_MODE_NONE) { -+ ret = udphy_disable(udphy); -+ if (ret) -+ return ret; -+ } ++ if (udphy->status == UDPHY_MODE_NONE) ++ rk_udphy_disable(udphy); ++} ++ ++static int rk_udphy_dp_phy_init(struct phy *phy) ++{ ++ struct rk_udphy *udphy = phy_get_drvdata(phy); ++ ++ mutex_lock(&udphy->mutex); ++ ++ udphy->dp_in_use = true; ++ rk_udphy_dp_hpd_event_trigger(udphy, udphy->dp_sink_hpd_cfg); ++ ++ mutex_unlock(&udphy->mutex); + + return 0; +} + -+static int rockchip_dp_phy_power_on(struct phy *phy) ++static int rk_udphy_dp_phy_exit(struct phy *phy) +{ -+ struct rockchip_udphy *udphy = phy_get_drvdata(phy); ++ struct rk_udphy *udphy = phy_get_drvdata(phy); ++ ++ mutex_lock(&udphy->mutex); ++ udphy->dp_in_use = false; ++ mutex_unlock(&udphy->mutex); ++ return 0; ++} ++ ++static int rk_udphy_dp_phy_power_on(struct phy *phy) ++{ ++ struct rk_udphy *udphy = phy_get_drvdata(phy); + int ret, dp_lanes; + + mutex_lock(&udphy->mutex); + -+ dp_lanes = udphy_dplane_get(udphy); ++ dp_lanes = rk_udphy_dplane_get(udphy); + phy_set_bus_width(phy, dp_lanes); + -+ ret = udphy_power_on(udphy, UDPHY_MODE_DP); ++ ret = rk_udphy_power_on(udphy, UDPHY_MODE_DP); + if (ret) + goto unlock; + -+ ret = udphy_dplane_enable(udphy, dp_lanes); -+ if (ret) -+ goto unlock; ++ rk_udphy_dplane_enable(udphy, dp_lanes); + -+ ret = udphy_dplane_select(udphy); ++ rk_udphy_dplane_select(udphy); + +unlock: + mutex_unlock(&udphy->mutex); @@ -1297,24 +1337,19 @@ index 000000000000..bb0beafb8578 + return ret; +} + -+static int rockchip_dp_phy_power_off(struct phy *phy) ++static int rk_udphy_dp_phy_power_off(struct phy *phy) +{ -+ struct rockchip_udphy *udphy = phy_get_drvdata(phy); -+ int ret; ++ struct rk_udphy *udphy = phy_get_drvdata(phy); + + mutex_lock(&udphy->mutex); -+ ret = udphy_dplane_enable(udphy, 0); -+ if (ret) -+ goto unlock; -+ -+ ret = udphy_power_off(udphy, UDPHY_MODE_DP); -+ -+unlock: ++ rk_udphy_dplane_enable(udphy, 0); ++ rk_udphy_power_off(udphy, UDPHY_MODE_DP); + mutex_unlock(&udphy->mutex); -+ return ret; ++ ++ return 0; +} + -+static int rockchip_dp_phy_verify_link_rate(unsigned int link_rate) ++static int rk_udphy_dp_phy_verify_link_rate(unsigned int link_rate) +{ + switch (link_rate) { + case 1620: @@ -1322,6 +1357,7 @@ index 000000000000..bb0beafb8578 + case 5400: + case 8100: + break; ++ + default: + return -EINVAL; + } @@ -1329,13 +1365,13 @@ index 000000000000..bb0beafb8578 + return 0; +} + -+static int rockchip_dp_phy_verify_config(struct rockchip_udphy *udphy, ++static int rk_udphy_dp_phy_verify_config(struct rk_udphy *udphy, + struct phy_configure_opts_dp *dp) +{ + int i, ret; + + /* If changing link rate was required, verify it's supported. */ -+ ret = rockchip_dp_phy_verify_link_rate(dp->link_rate); ++ ret = rk_udphy_dp_phy_verify_link_rate(dp->link_rate); + if (ret) + return ret; + @@ -1346,6 +1382,7 @@ index 000000000000..bb0beafb8578 + case 4: + /* valid lane count. */ + break; ++ + default: + return -EINVAL; + } @@ -1372,99 +1409,176 @@ index 000000000000..bb0beafb8578 + return 0; +} + -+static int rockchip_dp_phy_configure(struct phy *phy, ++static void rk_udphy_dp_set_voltage(struct rk_udphy *udphy, u8 bw, ++ u32 voltage, u32 pre, u32 lane) ++{ ++ const struct rk_udphy_cfg *cfg = udphy->cfgs; ++ const struct rk_udphy_dp_tx_drv_ctrl (*dp_ctrl)[4]; ++ u32 offset = 0x800 * lane; ++ u32 val; ++ ++ if (udphy->mux) ++ dp_ctrl = cfg->dp_tx_ctrl_cfg_typec[bw]; ++ else ++ dp_ctrl = cfg->dp_tx_ctrl_cfg[bw]; ++ ++ val = dp_ctrl[voltage][pre].trsv_reg0204; ++ regmap_write(udphy->pma_regmap, 0x0810 + offset, val); ++ ++ val = dp_ctrl[voltage][pre].trsv_reg0205; ++ regmap_write(udphy->pma_regmap, 0x0814 + offset, val); ++ ++ val = dp_ctrl[voltage][pre].trsv_reg0206; ++ regmap_write(udphy->pma_regmap, 0x0818 + offset, val); ++ ++ val = dp_ctrl[voltage][pre].trsv_reg0207; ++ regmap_write(udphy->pma_regmap, 0x081c + offset, val); ++} ++ ++static int rk_udphy_dp_phy_configure(struct phy *phy, + union phy_configure_opts *opts) +{ -+ struct rockchip_udphy *udphy = phy_get_drvdata(phy); -+ const struct rockchip_udphy_cfg *cfg = udphy->cfgs; ++ struct rk_udphy *udphy = phy_get_drvdata(phy); ++ struct phy_configure_opts_dp *dp = &opts->dp; ++ u32 i, val, lane; + int ret; + -+ ret = rockchip_dp_phy_verify_config(udphy, &opts->dp); ++ ret = rk_udphy_dp_phy_verify_config(udphy, dp); + if (ret) + return ret; + -+ if (opts->dp.set_rate && cfg->dp_phy_set_rate) { -+ ret = cfg->dp_phy_set_rate(udphy, &opts->dp); ++ if (dp->set_rate) { ++ regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET, ++ CMN_DP_CMN_RSTN, FIELD_PREP(CMN_DP_CMN_RSTN, 0x0)); ++ ++ switch (dp->link_rate) { ++ case 1620: ++ udphy->bw = DP_BW_RBR; ++ break; ++ ++ case 2700: ++ udphy->bw = DP_BW_HBR; ++ break; ++ ++ case 5400: ++ udphy->bw = DP_BW_HBR2; ++ break; ++ ++ case 8100: ++ udphy->bw = DP_BW_HBR3; ++ break; ++ ++ default: ++ return -EINVAL; ++ } ++ ++ regmap_update_bits(udphy->pma_regmap, CMN_DP_LINK_OFFSET, CMN_DP_TX_LINK_BW, ++ FIELD_PREP(CMN_DP_TX_LINK_BW, udphy->bw)); ++ regmap_update_bits(udphy->pma_regmap, CMN_SSC_EN_OFFSET, CMN_ROPLL_SSC_EN, ++ FIELD_PREP(CMN_ROPLL_SSC_EN, dp->ssc)); ++ regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET, CMN_DP_CMN_RSTN, ++ FIELD_PREP(CMN_DP_CMN_RSTN, 0x1)); ++ ++ ret = regmap_read_poll_timeout(udphy->pma_regmap, CMN_ANA_ROPLL_DONE_OFFSET, val, ++ FIELD_GET(CMN_ANA_ROPLL_LOCK_DONE, val) && ++ FIELD_GET(CMN_ANA_ROPLL_AFC_DONE, val), ++ 0, 1000); + if (ret) { -+ dev_err(udphy->dev, -+ "rockchip_hdptx_phy_set_rate failed\n"); ++ dev_err(udphy->dev, "ROPLL is not lock, set_rate failed\n"); + return ret; + } + } + -+ if (opts->dp.set_voltages && cfg->dp_phy_set_voltages) { -+ ret = cfg->dp_phy_set_voltages(udphy, &opts->dp); -+ if (ret) { -+ dev_err(udphy->dev, -+ "rockchip_dp_phy_set_voltages failed\n"); -+ return ret; ++ if (dp->set_voltages) { ++ for (i = 0; i < dp->lanes; i++) { ++ lane = udphy->dp_lane_sel[i]; ++ switch (dp->link_rate) { ++ case 1620: ++ case 2700: ++ regmap_update_bits(udphy->pma_regmap, ++ TRSV_ANA_TX_CLK_OFFSET_N(lane), ++ LN_ANA_TX_SER_TXCLK_INV, ++ FIELD_PREP(LN_ANA_TX_SER_TXCLK_INV, ++ udphy->lane_mux_sel[lane])); ++ break; ++ ++ case 5400: ++ case 8100: ++ regmap_update_bits(udphy->pma_regmap, ++ TRSV_ANA_TX_CLK_OFFSET_N(lane), ++ LN_ANA_TX_SER_TXCLK_INV, ++ FIELD_PREP(LN_ANA_TX_SER_TXCLK_INV, 0x0)); ++ break; ++ } ++ ++ rk_udphy_dp_set_voltage(udphy, udphy->bw, dp->voltage[i], ++ dp->pre[i], lane); + } + } + + return 0; +} + -+static const struct phy_ops rockchip_dp_phy_ops = { -+ .power_on = rockchip_dp_phy_power_on, -+ .power_off = rockchip_dp_phy_power_off, -+ .configure = rockchip_dp_phy_configure, ++static const struct phy_ops rk_udphy_dp_phy_ops = { ++ .init = rk_udphy_dp_phy_init, ++ .exit = rk_udphy_dp_phy_exit, ++ .power_on = rk_udphy_dp_phy_power_on, ++ .power_off = rk_udphy_dp_phy_power_off, ++ .configure = rk_udphy_dp_phy_configure, + .owner = THIS_MODULE, +}; + -+static int rockchip_u3phy_init(struct phy *phy) ++static int rk_udphy_usb3_phy_init(struct phy *phy) +{ -+ struct rockchip_udphy *udphy = phy_get_drvdata(phy); ++ struct rk_udphy *udphy = phy_get_drvdata(phy); + int ret = 0; + + mutex_lock(&udphy->mutex); + /* DP only or high-speed, disable U3 port */ + if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) { -+ udphy_u3_port_disable(udphy, true); ++ rk_udphy_u3_port_disable(udphy, true); + goto unlock; + } + -+ ret = udphy_power_on(udphy, UDPHY_MODE_USB); ++ ret = rk_udphy_power_on(udphy, UDPHY_MODE_USB); + +unlock: + mutex_unlock(&udphy->mutex); + return ret; +} + -+static int rockchip_u3phy_exit(struct phy *phy) ++static int rk_udphy_usb3_phy_exit(struct phy *phy) +{ -+ struct rockchip_udphy *udphy = phy_get_drvdata(phy); -+ int ret = 0; ++ struct rk_udphy *udphy = phy_get_drvdata(phy); + + mutex_lock(&udphy->mutex); + /* DP only or high-speed */ + if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) + goto unlock; + -+ ret = udphy_power_off(udphy, UDPHY_MODE_USB); ++ rk_udphy_power_off(udphy, UDPHY_MODE_USB); + +unlock: + mutex_unlock(&udphy->mutex); -+ return ret; ++ return 0; +} + -+static const struct phy_ops rockchip_u3phy_ops = { -+ .init = rockchip_u3phy_init, -+ .exit = rockchip_u3phy_exit, ++static const struct phy_ops rk_udphy_usb3_phy_ops = { ++ .init = rk_udphy_usb3_phy_init, ++ .exit = rk_udphy_usb3_phy_exit, + .owner = THIS_MODULE, +}; + -+static int usbdp_typec_mux_set(struct typec_mux_dev *mux, -+ struct typec_mux_state *state) ++static int rk_udphy_typec_mux_set(struct typec_mux_dev *mux, ++ struct typec_mux_state *state) +{ -+ struct rockchip_udphy *udphy = typec_mux_get_drvdata(mux); -+ const struct rockchip_udphy_cfg *cfg = udphy->cfgs; ++ struct rk_udphy *udphy = typec_mux_get_drvdata(mux); + u8 mode; + + mutex_lock(&udphy->mutex); + + switch (state->mode) { + case TYPEC_DP_STATE_C: -+ fallthrough; + case TYPEC_DP_STATE_E: + udphy->lane_mux_sel[0] = PHY_LANE_MUX_DP; + udphy->lane_mux_sel[1] = PHY_LANE_MUX_DP; @@ -1472,8 +1586,8 @@ index 000000000000..bb0beafb8578 + udphy->lane_mux_sel[3] = PHY_LANE_MUX_DP; + mode = UDPHY_MODE_DP; + break; ++ + case TYPEC_DP_STATE_D: -+ fallthrough; + default: + if (udphy->flip) { + udphy->lane_mux_sel[0] = PHY_LANE_MUX_DP; @@ -1494,24 +1608,19 @@ index 000000000000..bb0beafb8578 + struct typec_displayport_data *data = state->data; + + if (!data) { -+ if (cfg->hpd_event_trigger) -+ cfg->hpd_event_trigger(udphy, false); ++ rk_udphy_dp_hpd_event_trigger(udphy, false); + } else if (data->status & DP_STATUS_IRQ_HPD) { -+ if (cfg->hpd_event_trigger) { -+ cfg->hpd_event_trigger(udphy, false); -+ usleep_range(750, 800); -+ cfg->hpd_event_trigger(udphy, true); -+ } ++ rk_udphy_dp_hpd_event_trigger(udphy, false); ++ usleep_range(750, 800); ++ rk_udphy_dp_hpd_event_trigger(udphy, true); + } else if (data->status & DP_STATUS_HPD_STATE) { + if (udphy->mode != mode) { + udphy->mode = mode; + udphy->mode_change = true; + } -+ if (cfg->hpd_event_trigger) -+ cfg->hpd_event_trigger(udphy, true); ++ rk_udphy_dp_hpd_event_trigger(udphy, true); + } else { -+ if (cfg->hpd_event_trigger) -+ cfg->hpd_event_trigger(udphy, false); ++ rk_udphy_dp_hpd_event_trigger(udphy, false); + } + } + @@ -1519,13 +1628,20 @@ index 000000000000..bb0beafb8578 + return 0; +} + -+static int udphy_setup_typec_mux(struct rockchip_udphy *udphy) ++static void rk_udphy_typec_mux_unregister(void *data) ++{ ++ struct rk_udphy *udphy = data; ++ ++ typec_mux_unregister(udphy->mux); ++} ++ ++static int rk_udphy_setup_typec_mux(struct rk_udphy *udphy) +{ + struct typec_mux_desc mux_desc = {}; + + mux_desc.drvdata = udphy; + mux_desc.fwnode = dev_fwnode(udphy->dev); -+ mux_desc.set = usbdp_typec_mux_set; ++ mux_desc.set = rk_udphy_typec_mux_set; + + udphy->mux = typec_mux_register(udphy->dev, &mux_desc); + if (IS_ERR(udphy->mux)) { @@ -1534,35 +1650,11 @@ index 000000000000..bb0beafb8578 + return PTR_ERR(udphy->mux); + } + -+ return 0; ++ return devm_add_action_or_reset(udphy->dev, rk_udphy_typec_mux_unregister, ++ udphy); +} + -+static void udphy_typec_mux_unregister(void *data) -+{ -+ struct rockchip_udphy *udphy = data; -+ -+ typec_mux_unregister(udphy->mux); -+} -+ -+static u32 udphy_dp_get_max_link_rate(struct rockchip_udphy *udphy, struct device_node *np) -+{ -+ u32 max_link_rate; -+ int ret; -+ -+ ret = of_property_read_u32(np, "max-link-rate", &max_link_rate); -+ if (ret) -+ return 8100; -+ -+ ret = rockchip_dp_phy_verify_link_rate(max_link_rate); -+ if (ret) { -+ dev_warn(udphy->dev, "invalid max-link-rate value:%d\n", max_link_rate); -+ max_link_rate = 8100; -+ } -+ -+ return max_link_rate; -+} -+ -+static const struct regmap_config rockchip_udphy_pma_regmap_cfg = { ++static const struct regmap_config rk_udphy_pma_regmap_cfg = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, @@ -1570,15 +1662,29 @@ index 000000000000..bb0beafb8578 + .max_register = 0x20dc, +}; + -+static int rockchip_udphy_probe(struct platform_device *pdev) ++static struct phy *rk_udphy_phy_xlate(struct device *dev, struct of_phandle_args *args) ++{ ++ struct rk_udphy *udphy = dev_get_drvdata(dev); ++ ++ if (args->args_count == 0) ++ return ERR_PTR(-EINVAL); ++ ++ switch (args->args[0]) { ++ case PHY_TYPE_USB3: ++ return udphy->phy_u3; ++ case PHY_TYPE_DP: ++ return udphy->phy_dp; ++ } ++ ++ return ERR_PTR(-EINVAL); ++} ++ ++static int rk_udphy_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; -+ struct device_node *np = dev->of_node; -+ struct device_node *child_np; + struct phy_provider *phy_provider; + struct resource *res; -+ struct rockchip_udphy *udphy; -+ const struct rockchip_udphy_cfg *phy_cfgs; ++ struct rk_udphy *udphy; + void __iomem *base; + int id, ret; + @@ -1586,431 +1692,127 @@ index 000000000000..bb0beafb8578 + if (!udphy) + return -ENOMEM; + -+ id = of_alias_get_id(dev->of_node, "usbdp"); -+ if (id < 0) -+ id = 0; -+ udphy->id = id; -+ -+ phy_cfgs = device_get_match_data(dev); -+ if (!phy_cfgs) { -+ dev_err(dev, "missing match data\n"); -+ return -EINVAL; -+ } -+ -+ udphy->cfgs = phy_cfgs; ++ udphy->cfgs = device_get_match_data(dev); ++ if (!udphy->cfgs) ++ return dev_err_probe(dev, -EINVAL, "missing match data\n"); + + base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); + if (IS_ERR(base)) + return PTR_ERR(base); + ++ /* find the phy-id from the io address */ ++ udphy->id = -ENODEV; ++ for (id = 0; id < udphy->cfgs->num_phys; id++) { ++ if (res->start == udphy->cfgs->phy_ids[id]) { ++ udphy->id = id; ++ break; ++ } ++ } ++ ++ if (udphy->id < 0) ++ return dev_err_probe(dev, -ENODEV, "no matching device found\n"); ++ + udphy->pma_regmap = devm_regmap_init_mmio(dev, base + UDPHY_PMA, -+ &rockchip_udphy_pma_regmap_cfg); ++ &rk_udphy_pma_regmap_cfg); + if (IS_ERR(udphy->pma_regmap)) + return PTR_ERR(udphy->pma_regmap); + -+ ret = udphy_parse_dt(udphy, dev); ++ udphy->dev = dev; ++ ret = rk_udphy_parse_dt(udphy); + if (ret) + return ret; + -+ ret = udphy_get_initial_status(udphy); ++ ret = rk_udphy_get_initial_status(udphy); + if (ret) + return ret; + + mutex_init(&udphy->mutex); -+ udphy->dev = dev; + platform_set_drvdata(pdev, udphy); + + if (device_property_present(dev, "orientation-switch")) { -+ ret = udphy_setup_orien_switch(udphy); -+ if (ret) -+ return ret; -+ -+ ret = devm_add_action_or_reset(dev, udphy_orien_switch_unregister, udphy); ++ ret = rk_udphy_setup_orien_switch(udphy); + if (ret) + return ret; + } + + if (device_property_present(dev, "mode-switch")) { -+ ret = udphy_setup_typec_mux(udphy); -+ if (ret) -+ return ret; -+ -+ ret = devm_add_action_or_reset(dev, udphy_typec_mux_unregister, udphy); ++ ret = rk_udphy_setup_typec_mux(udphy); + if (ret) + return ret; + } + -+ for_each_available_child_of_node(np, child_np) { -+ struct phy *phy; -+ -+ if (of_node_name_eq(child_np, "dp-port")) { -+ phy = devm_phy_create(dev, child_np, &rockchip_dp_phy_ops); -+ if (IS_ERR(phy)) { -+ dev_err(dev, "failed to create dp phy: %pOFn\n", child_np); -+ goto put_child; -+ } -+ -+ phy_set_bus_width(phy, udphy_dplane_get(udphy)); -+ phy->attrs.max_link_rate = udphy_dp_get_max_link_rate(udphy, child_np); -+ } else if (of_node_name_eq(child_np, "usb3-port")) { -+ phy = devm_phy_create(dev, child_np, &rockchip_u3phy_ops); -+ if (IS_ERR(phy)) { -+ dev_err(dev, "failed to create usb phy: %pOFn\n", child_np); -+ goto put_child; -+ } -+ } else -+ continue; -+ -+ phy_set_drvdata(phy, udphy); ++ udphy->phy_u3 = devm_phy_create(dev, dev->of_node, &rk_udphy_usb3_phy_ops); ++ if (IS_ERR(udphy->phy_u3)) { ++ ret = PTR_ERR(udphy->phy_u3); ++ return dev_err_probe(dev, ret, "failed to create USB3 phy\n"); + } ++ phy_set_drvdata(udphy->phy_u3, udphy); + -+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); ++ udphy->phy_dp = devm_phy_create(dev, dev->of_node, &rk_udphy_dp_phy_ops); ++ if (IS_ERR(udphy->phy_dp)) { ++ ret = PTR_ERR(udphy->phy_dp); ++ return dev_err_probe(dev, ret, "failed to create DP phy\n"); ++ } ++ phy_set_bus_width(udphy->phy_dp, rk_udphy_dplane_get(udphy)); ++ udphy->phy_dp->attrs.max_link_rate = 8100; ++ phy_set_drvdata(udphy->phy_dp, udphy); ++ ++ phy_provider = devm_of_phy_provider_register(dev, rk_udphy_phy_xlate); + if (IS_ERR(phy_provider)) { -+ dev_err(dev, "failed to register phy provider\n"); -+ goto put_child; -+ } -+ -+ return 0; -+ -+put_child: -+ of_node_put(child_np); -+ return ret; -+} -+ -+static int rk3588_udphy_refclk_set(struct rockchip_udphy *udphy) -+{ -+ unsigned long rate; -+ int ret; -+ -+ /* configure phy reference clock */ -+ rate = clk_get_rate(udphy->refclk); -+ dev_dbg(udphy->dev, "refclk freq %ld\n", rate); -+ -+ switch (rate) { -+ case 24000000: -+ ret = regmap_multi_reg_write(udphy->pma_regmap, rk3588_udphy_24m_refclk_cfg, -+ ARRAY_SIZE(rk3588_udphy_24m_refclk_cfg)); -+ if (ret) -+ return ret; -+ break; -+ case 26000000: -+ /* register default is 26MHz */ -+ ret = regmap_multi_reg_write(udphy->pma_regmap, rk3588_udphy_26m_refclk_cfg, -+ ARRAY_SIZE(rk3588_udphy_26m_refclk_cfg)); -+ if (ret) -+ return ret; -+ break; -+ default: -+ dev_err(udphy->dev, "unsupported refclk freq %ld\n", rate); -+ return -EINVAL; ++ ret = PTR_ERR(phy_provider); ++ return dev_err_probe(dev, ret, "failed to register phy provider\n"); + } + + return 0; +} + -+static int rk3588_udphy_status_check(struct rockchip_udphy *udphy) ++static int __maybe_unused rk_udphy_resume(struct device *dev) +{ -+ unsigned int val; -+ int ret; -+ -+ /* LCPLL check */ -+ if (udphy->mode & UDPHY_MODE_USB) { -+ ret = regmap_read_poll_timeout(udphy->pma_regmap, CMN_ANA_LCPLL_DONE_OFFSET, -+ val, (val & CMN_ANA_LCPLL_AFC_DONE) && -+ (val & CMN_ANA_LCPLL_LOCK_DONE), 200, 100000); -+ if (ret) { -+ dev_err(udphy->dev, "cmn ana lcpll lock timeout\n"); -+ return ret; -+ } -+ -+ if (!udphy->flip) { -+ ret = regmap_read_poll_timeout(udphy->pma_regmap, -+ TRSV_LN0_MON_RX_CDR_DONE_OFFSET, val, -+ val & TRSV_LN0_MON_RX_CDR_LOCK_DONE, -+ 200, 100000); -+ if (ret) -+ dev_err(udphy->dev, "trsv ln0 mon rx cdr lock timeout\n"); -+ } else { -+ ret = regmap_read_poll_timeout(udphy->pma_regmap, -+ TRSV_LN2_MON_RX_CDR_DONE_OFFSET, val, -+ val & TRSV_LN2_MON_RX_CDR_LOCK_DONE, -+ 200, 100000); -+ if (ret) -+ dev_err(udphy->dev, "trsv ln2 mon rx cdr lock timeout\n"); -+ } -+ } -+ -+ return 0; -+} -+ -+static int rk3588_udphy_init(struct rockchip_udphy *udphy) -+{ -+ const struct rockchip_udphy_cfg *cfg = udphy->cfgs; -+ int ret; -+ -+ /* enable rx lfps for usb */ -+ if (udphy->mode & UDPHY_MODE_USB) -+ grfreg_write(udphy->udphygrf, &cfg->grfcfg.rx_lfps, true); -+ -+ /* Step 1: power on pma and deassert apb rstn */ -+ grfreg_write(udphy->udphygrf, &cfg->grfcfg.low_pwrn, true); -+ -+ udphy_reset_deassert(udphy, "pma_apb"); -+ udphy_reset_deassert(udphy, "pcs_apb"); -+ -+ /* Step 2: set init sequence and phy refclk */ -+ ret = regmap_multi_reg_write(udphy->pma_regmap, rk3588_udphy_init_sequence, -+ ARRAY_SIZE(rk3588_udphy_init_sequence)); -+ if (ret) { -+ dev_err(udphy->dev, "init sequence set error %d\n", ret); -+ goto assert_apb; -+ } -+ -+ ret = rk3588_udphy_refclk_set(udphy); -+ if (ret) { -+ dev_err(udphy->dev, "refclk set error %d\n", ret); -+ goto assert_apb; -+ } -+ -+ /* Step 3: configure lane mux */ -+ regmap_update_bits(udphy->pma_regmap, CMN_LANE_MUX_AND_EN_OFFSET, -+ CMN_DP_LANE_MUX_ALL | CMN_DP_LANE_EN_ALL, -+ FIELD_PREP(CMN_DP_LANE_MUX_N(3), udphy->lane_mux_sel[3]) | -+ FIELD_PREP(CMN_DP_LANE_MUX_N(2), udphy->lane_mux_sel[2]) | -+ FIELD_PREP(CMN_DP_LANE_MUX_N(1), udphy->lane_mux_sel[1]) | -+ FIELD_PREP(CMN_DP_LANE_MUX_N(0), udphy->lane_mux_sel[0]) | -+ FIELD_PREP(CMN_DP_LANE_EN_ALL, 0)); -+ -+ /* Step 4: deassert init rstn and wait for 200ns from datasheet */ -+ if (udphy->mode & UDPHY_MODE_USB) -+ udphy_reset_deassert(udphy, "init"); -+ -+ if (udphy->mode & UDPHY_MODE_DP) { -+ regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET, -+ CMN_DP_INIT_RSTN, -+ FIELD_PREP(CMN_DP_INIT_RSTN, 0x1)); -+ } -+ -+ udelay(1); -+ -+ /* Step 5: deassert cmn/lane rstn */ -+ if (udphy->mode & UDPHY_MODE_USB) { -+ udphy_reset_deassert(udphy, "cmn"); -+ udphy_reset_deassert(udphy, "lane"); -+ } -+ -+ /* Step 6: wait for lock done of pll */ -+ ret = rk3588_udphy_status_check(udphy); -+ if (ret) -+ goto assert_phy; -+ -+ return 0; -+ -+assert_phy: -+ udphy_reset_assert(udphy, "init"); -+ udphy_reset_assert(udphy, "cmn"); -+ udphy_reset_assert(udphy, "lane"); -+ -+assert_apb: -+ udphy_reset_assert(udphy, "pma_apb"); -+ udphy_reset_assert(udphy, "pcs_apb"); -+ return ret; -+} -+ -+static int rk3588_udphy_hpd_event_trigger(struct rockchip_udphy *udphy, bool hpd) -+{ -+ const struct rockchip_udphy_cfg *cfg = udphy->cfgs; -+ -+ udphy->dp_sink_hpd_sel = true; -+ udphy->dp_sink_hpd_cfg = hpd; -+ -+ grfreg_write(udphy->vogrf, &cfg->vogrfcfg[udphy->id].hpd_trigger, hpd); -+ -+ return 0; -+} -+ -+static int rk3588_udphy_dplane_enable(struct rockchip_udphy *udphy, int dp_lanes) -+{ -+ int i; -+ u32 val = 0; -+ -+ for (i = 0; i < dp_lanes; i++) -+ val |= BIT(udphy->dp_lane_sel[i]); -+ -+ regmap_update_bits(udphy->pma_regmap, CMN_LANE_MUX_AND_EN_OFFSET, CMN_DP_LANE_EN_ALL, -+ FIELD_PREP(CMN_DP_LANE_EN_ALL, val)); -+ -+ if (!dp_lanes) -+ regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET, -+ CMN_DP_CMN_RSTN, FIELD_PREP(CMN_DP_CMN_RSTN, 0x0)); -+ -+ return 0; -+} -+ -+static int rk3588_udphy_dplane_select(struct rockchip_udphy *udphy) -+{ -+ u32 value = 0; -+ -+ switch (udphy->mode) { -+ case UDPHY_MODE_DP: -+ value |= 2 << udphy->dp_lane_sel[2] * 2; -+ value |= 3 << udphy->dp_lane_sel[3] * 2; -+ fallthrough; -+ case UDPHY_MODE_DP_USB: -+ value |= 0 << udphy->dp_lane_sel[0] * 2; -+ value |= 1 << udphy->dp_lane_sel[1] * 2; -+ break; -+ case UDPHY_MODE_USB: -+ break; -+ default: -+ break; -+ } -+ -+ regmap_write(udphy->vogrf, udphy->id ? RK3588_GRF_VO0_CON2 : RK3588_GRF_VO0_CON0, -+ ((DP_AUX_DIN_SEL | DP_AUX_DOUT_SEL | DP_LANE_SEL_ALL) << 16) | -+ FIELD_PREP(DP_AUX_DIN_SEL, udphy->dp_aux_din_sel) | -+ FIELD_PREP(DP_AUX_DOUT_SEL, udphy->dp_aux_dout_sel) | value); -+ -+ return 0; -+} -+ -+static int rk3588_dp_phy_set_rate(struct rockchip_udphy *udphy, -+ struct phy_configure_opts_dp *dp) -+{ -+ u32 val; -+ int ret; -+ -+ regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET, -+ CMN_DP_CMN_RSTN, FIELD_PREP(CMN_DP_CMN_RSTN, 0x0)); -+ -+ switch (dp->link_rate) { -+ case 1620: -+ udphy->bw = DP_BW_RBR; -+ break; -+ case 2700: -+ udphy->bw = DP_BW_HBR; -+ break; -+ case 5400: -+ udphy->bw = DP_BW_HBR2; -+ break; -+ case 8100: -+ udphy->bw = DP_BW_HBR3; -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ regmap_update_bits(udphy->pma_regmap, CMN_DP_LINK_OFFSET, CMN_DP_TX_LINK_BW, -+ FIELD_PREP(CMN_DP_TX_LINK_BW, udphy->bw)); -+ regmap_update_bits(udphy->pma_regmap, CMN_SSC_EN_OFFSET, CMN_ROPLL_SSC_EN, -+ FIELD_PREP(CMN_ROPLL_SSC_EN, dp->ssc)); -+ regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET, CMN_DP_CMN_RSTN, -+ FIELD_PREP(CMN_DP_CMN_RSTN, 0x1)); -+ -+ ret = regmap_read_poll_timeout(udphy->pma_regmap, CMN_ANA_ROPLL_DONE_OFFSET, val, -+ FIELD_GET(CMN_ANA_ROPLL_LOCK_DONE, val) && -+ FIELD_GET(CMN_ANA_ROPLL_AFC_DONE, val), -+ 0, 1000); -+ if (ret) { -+ dev_err(udphy->dev, "ROPLL is not lock\n"); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static void rk3588_dp_phy_set_voltage(struct rockchip_udphy *udphy, u8 bw, -+ u32 voltage, u32 pre, u32 lane) -+{ -+ u32 offset = 0x800 * lane; -+ u32 val; -+ const struct rockchip_udphy_cfg *cfg = udphy->cfgs; -+ const struct dp_tx_drv_ctrl (*dp_ctrl)[4]; -+ -+ dp_ctrl = udphy->mux ? cfg->dp_tx_ctrl_cfg_typec[bw] : cfg->dp_tx_ctrl_cfg[bw]; -+ val = dp_ctrl[voltage][pre].trsv_reg0204; -+ regmap_write(udphy->pma_regmap, 0x0810 + offset, val); -+ -+ val = dp_ctrl[voltage][pre].trsv_reg0205; -+ regmap_write(udphy->pma_regmap, 0x0814 + offset, val); -+ -+ val = dp_ctrl[voltage][pre].trsv_reg0206; -+ regmap_write(udphy->pma_regmap, 0x0818 + offset, val); -+ -+ val = dp_ctrl[voltage][pre].trsv_reg0207; -+ regmap_write(udphy->pma_regmap, 0x081c + offset, val); -+} -+ -+static int rk3588_dp_phy_set_voltages(struct rockchip_udphy *udphy, -+ struct phy_configure_opts_dp *dp) -+{ -+ u32 i, lane; -+ -+ for (i = 0; i < dp->lanes; i++) { -+ lane = udphy->dp_lane_sel[i]; -+ switch (dp->link_rate) { -+ case 1620: -+ case 2700: -+ regmap_update_bits(udphy->pma_regmap, TRSV_ANA_TX_CLK_OFFSET_N(lane), -+ LN_ANA_TX_SER_TXCLK_INV, -+ FIELD_PREP(LN_ANA_TX_SER_TXCLK_INV, -+ udphy->lane_mux_sel[lane])); -+ break; -+ case 5400: -+ case 8100: -+ regmap_update_bits(udphy->pma_regmap, TRSV_ANA_TX_CLK_OFFSET_N(lane), -+ LN_ANA_TX_SER_TXCLK_INV, -+ FIELD_PREP(LN_ANA_TX_SER_TXCLK_INV, 0x0)); -+ break; -+ } -+ -+ rk3588_dp_phy_set_voltage(udphy, udphy->bw, dp->voltage[i], dp->pre[i], lane); -+ } -+ -+ return 0; -+} -+ -+static int __maybe_unused udphy_resume(struct device *dev) -+{ -+ struct rockchip_udphy *udphy = dev_get_drvdata(dev); -+ const struct rockchip_udphy_cfg *cfg = udphy->cfgs; ++ struct rk_udphy *udphy = dev_get_drvdata(dev); + + if (udphy->dp_sink_hpd_sel) -+ cfg->hpd_event_trigger(udphy, udphy->dp_sink_hpd_cfg); ++ rk_udphy_dp_hpd_event_trigger(udphy, udphy->dp_sink_hpd_cfg); + + return 0; +} + -+static const struct dev_pm_ops udphy_pm_ops = { -+ SET_LATE_SYSTEM_SLEEP_PM_OPS(NULL, udphy_resume) ++static const struct dev_pm_ops rk_udphy_pm_ops = { ++ SET_LATE_SYSTEM_SLEEP_PM_OPS(NULL, rk_udphy_resume) +}; + -+static const char * const rk3588_udphy_rst_l[] = { ++static const char * const rk_udphy_rst_list[] = { + "init", "cmn", "lane", "pcs_apb", "pma_apb" +}; + -+static const struct rockchip_udphy_cfg rk3588_udphy_cfgs = { -+ .num_rsts = ARRAY_SIZE(rk3588_udphy_rst_l), -+ .rst_list = rk3588_udphy_rst_l, ++static const struct rk_udphy_cfg rk3588_udphy_cfgs = { ++ .num_phys = 2, ++ .phy_ids = { ++ 0xfed80000, ++ 0xfed90000, ++ }, ++ .num_rsts = ARRAY_SIZE(rk_udphy_rst_list), ++ .rst_list = rk_udphy_rst_list, + .grfcfg = { + /* u2phy-grf */ -+ .bvalid_phy_con = { 0x0008, 1, 0, 0x2, 0x3 }, -+ .bvalid_grf_con = { 0x0010, 3, 2, 0x2, 0x3 }, ++ .bvalid_phy_con = RK_UDPHY_GEN_GRF_REG(0x0008, 1, 0, 0x2, 0x3), ++ .bvalid_grf_con = RK_UDPHY_GEN_GRF_REG(0x0010, 3, 2, 0x2, 0x3), + + /* usb-grf */ -+ .usb3otg0_cfg = { 0x001c, 15, 0, 0x1100, 0x0188 }, -+ .usb3otg1_cfg = { 0x0034, 15, 0, 0x1100, 0x0188 }, ++ .usb3otg0_cfg = RK_UDPHY_GEN_GRF_REG(0x001c, 15, 0, 0x1100, 0x0188), ++ .usb3otg1_cfg = RK_UDPHY_GEN_GRF_REG(0x0034, 15, 0, 0x1100, 0x0188), + + /* usbdpphy-grf */ -+ .low_pwrn = { 0x0004, 13, 13, 0, 1 }, -+ .rx_lfps = { 0x0004, 14, 14, 0, 1 }, ++ .low_pwrn = RK_UDPHY_GEN_GRF_REG(0x0004, 13, 13, 0, 1), ++ .rx_lfps = RK_UDPHY_GEN_GRF_REG(0x0004, 14, 14, 0, 1), + }, + .vogrfcfg = { + { -+ .hpd_trigger = { 0x0000, 11, 10, 1, 3 }, ++ .hpd_trigger = RK_UDPHY_GEN_GRF_REG(0x0000, 11, 10, 1, 3), ++ .dp_lane_reg = 0x0000, + }, + { -+ .hpd_trigger = { 0x0008, 11, 10, 1, 3 }, ++ .hpd_trigger = RK_UDPHY_GEN_GRF_REG(0x0008, 11, 10, 1, 3), ++ .dp_lane_reg = 0x0008, + }, + }, + .dp_tx_ctrl_cfg = { @@ -2025,60 +1827,180 @@ index 000000000000..bb0beafb8578 + rk3588_dp_tx_drv_ctrl_hbr2, + rk3588_dp_tx_drv_ctrl_hbr3, + }, -+ .combophy_init = rk3588_udphy_init, -+ .dp_phy_set_rate = rk3588_dp_phy_set_rate, -+ .dp_phy_set_voltages = rk3588_dp_phy_set_voltages, -+ .hpd_event_trigger = rk3588_udphy_hpd_event_trigger, -+ .dplane_enable = rk3588_udphy_dplane_enable, -+ .dplane_select = rk3588_udphy_dplane_select, +}; + -+static const struct of_device_id rockchip_udphy_dt_match[] = { ++static const struct of_device_id rk_udphy_dt_match[] = { + { + .compatible = "rockchip,rk3588-usbdp-phy", + .data = &rk3588_udphy_cfgs + }, + { /* sentinel */ } +}; ++MODULE_DEVICE_TABLE(of, rk_udphy_dt_match); + -+MODULE_DEVICE_TABLE(of, rockchip_udphy_dt_match); -+ -+static struct platform_driver rockchip_udphy_driver = { -+ .probe = rockchip_udphy_probe, ++static struct platform_driver rk_udphy_driver = { ++ .probe = rk_udphy_probe, + .driver = { + .name = "rockchip-usbdp-phy", -+ .of_match_table = rockchip_udphy_dt_match, -+ .pm = &udphy_pm_ops, ++ .of_match_table = rk_udphy_dt_match, ++ .pm = &rk_udphy_pm_ops, + }, +}; -+ -+module_platform_driver(rockchip_udphy_driver); ++module_platform_driver(rk_udphy_driver); + +MODULE_AUTHOR("Frank Wang "); +MODULE_AUTHOR("Zhang Yubing "); +MODULE_DESCRIPTION("Rockchip USBDP Combo PHY driver"); +MODULE_LICENSE("GPL"); -- -Armbian +2.43.1 -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 + +From c6da9bab1bb1597f22e4861c5358d3ee695bd14e Mon Sep 17 00:00:00 2001 From: Sebastian Reichel -Date: Tue, 25 Apr 2023 17:49:04 +0200 -Subject: arm64: dts: rockchip: rk3588s: Add USBDP phy nodes +Date: Fri, 16 Feb 2024 18:01:18 +0100 +Subject: [PATCH 03/10] arm64: defconfig: enable Rockchip Samsung USBDP PHY -Add both USB3-Displayport PHYs from RK3588. +The USBDP Phy is used by RK3588 to handle the Dual-Role USB3 +controllers. The Phy also supports Displayport Alt-Mode, but +the necessary DRM driver has not yet been merged. Signed-off-by: Sebastian Reichel --- - arch/arm64/boot/dts/rockchip/rk3588.dtsi | 62 ++++++++ - arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 73 ++++++++++ - 2 files changed, 135 insertions(+) + arch/arm64/configs/defconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig +index e6cf3e5d63c3..07890b86777e 100644 +--- a/arch/arm64/configs/defconfig ++++ b/arch/arm64/configs/defconfig +@@ -1492,6 +1492,7 @@ CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=m + CONFIG_PHY_ROCKCHIP_PCIE=m + CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y + CONFIG_PHY_ROCKCHIP_TYPEC=y ++CONFIG_PHY_ROCKCHIP_USBDP=m + CONFIG_PHY_SAMSUNG_UFS=y + CONFIG_PHY_UNIPHIER_USB2=y + CONFIG_PHY_UNIPHIER_USB3=y +-- +2.43.1 + + +From 55040a7a1e5d20d2e2ce55c2b8613c560e793b36 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Fri, 16 Feb 2024 18:01:19 +0100 +Subject: [PATCH 04/10] arm64: dts: rockchip: fix usb2phy nodename for rk3588 + +usb2-phy should be named usb2phy according to the DT binding, +so let's fix it up accordingly. + +Signed-off-by: Sebastian Reichel +--- + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +index 36b1b7acfe6a..38e075b7b661 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +@@ -542,7 +542,7 @@ usb2phy2_grf: syscon@fd5d8000 { + #address-cells = <1>; + #size-cells = <1>; + +- u2phy2: usb2-phy@8000 { ++ u2phy2: usb2phy@8000 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0x8000 0x10>; + interrupts = ; +@@ -567,7 +567,7 @@ usb2phy3_grf: syscon@fd5dc000 { + #address-cells = <1>; + #size-cells = <1>; + +- u2phy3: usb2-phy@c000 { ++ u2phy3: usb2phy@c000 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0xc000 0x10>; + interrupts = ; +-- +2.43.1 + + +From 8a8a7ea9b8e1230976fbcff2703530afff58f347 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Fri, 16 Feb 2024 18:01:20 +0100 +Subject: [PATCH 05/10] arm64: dts: rockchip: reorder usb2phy properties for + rk3588 + +Reorder common DT properties alphabetically for usb2phy, according +to latest DT style rules. + +Signed-off-by: Sebastian Reichel +--- + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 16 ++++++++-------- + 1 file changed, 8 insertions(+), 8 deletions(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +index 38e075b7b661..8708436dd545 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +@@ -545,13 +545,13 @@ usb2phy2_grf: syscon@fd5d8000 { + u2phy2: usb2phy@8000 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0x8000 0x10>; +- interrupts = ; +- resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>; +- reset-names = "phy", "apb"; ++ #clock-cells = <0>; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy2"; +- #clock-cells = <0>; ++ interrupts = ; ++ resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>; ++ reset-names = "phy", "apb"; + status = "disabled"; + + u2phy2_host: host-port { +@@ -570,13 +570,13 @@ usb2phy3_grf: syscon@fd5dc000 { + u2phy3: usb2phy@c000 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0xc000 0x10>; +- interrupts = ; +- resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>; +- reset-names = "phy", "apb"; ++ #clock-cells = <0>; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy3"; +- #clock-cells = <0>; ++ interrupts = ; ++ resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>; ++ reset-names = "phy", "apb"; + status = "disabled"; + + u2phy3_host: host-port { +-- +2.43.1 + + +From 01ece028e3068010990e2e2582007305f58b3ab6 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Fri, 16 Feb 2024 18:01:21 +0100 +Subject: [PATCH 06/10] arm64: dts: rockchip: add USBDP phys on rk3588 + +Add both USB3-DisplayPort PHYs to RK3588 SoC DT. + +Signed-off-by: Sebastian Reichel +--- + arch/arm64/boot/dts/rockchip/rk3588.dtsi | 52 +++++++++++++++++++ + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 63 +++++++++++++++++++++++ + 2 files changed, 115 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi -index 5519c1430cb7..c26288ec75ce 100644 +index 5519c1430cb7..4fdd047c9eb9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi -@@ -17,6 +17,37 @@ pipe_phy1_grf: syscon@fd5c0000 { +@@ -17,6 +17,36 @@ pipe_phy1_grf: syscon@fd5c0000 { reg = <0x0 0xfd5c0000 0x0 0x100>; }; @@ -2088,22 +2010,21 @@ index 5519c1430cb7..c26288ec75ce 100644 + }; + + usb2phy1_grf: syscon@fd5d4000 { -+ compatible = "rockchip,rk3588-usb2phy-grf", "syscon", -+ "simple-mfd"; ++ compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; + reg = <0x0 0xfd5d4000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + -+ u2phy1: usb2-phy@4000 { ++ u2phy1: usb2phy@4000 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0x4000 0x10>; -+ interrupts = ; -+ resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>; -+ reset-names = "phy", "apb"; ++ #clock-cells = <0>; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy1"; -+ #clock-cells = <0>; ++ interrupts = ; ++ resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>; ++ reset-names = "phy", "apb"; + status = "disabled"; + + u2phy1_otg: otg-port { @@ -2116,17 +2037,14 @@ index 5519c1430cb7..c26288ec75ce 100644 i2s8_8ch: i2s@fddc8000 { compatible = "rockchip,rk3588-i2s-tdm"; reg = <0x0 0xfddc8000 0x0 0x1000>; -@@ -310,6 +341,37 @@ sata-port@0 { +@@ -310,6 +340,28 @@ sata-port@0 { }; }; + usbdp_phy1: phy@fed90000 { + compatible = "rockchip,rk3588-usbdp-phy"; + reg = <0x0 0xfed90000 0x0 0x10000>; -+ rockchip,u2phy-grf = <&usb2phy1_grf>; -+ rockchip,usb-grf = <&usb_grf>; -+ rockchip,usbdpphy-grf = <&usbdpphy1_grf>; -+ rockchip,vo-grf = <&vo0_grf>; ++ #phy-cells = <1>; + clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, + <&cru CLK_USBDP_PHY1_IMMORTAL>, + <&cru PCLK_USBDPPHY1>, @@ -2138,27 +2056,44 @@ index 5519c1430cb7..c26288ec75ce 100644 + <&cru SRST_USBDP_COMBO_PHY1_PCS>, + <&cru SRST_P_USBDPPHY1>; + reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; ++ rockchip,u2phy-grf = <&usb2phy1_grf>; ++ rockchip,usb-grf = <&usb_grf>; ++ rockchip,usbdpphy-grf = <&usbdpphy1_grf>; ++ rockchip,vo-grf = <&vo0_grf>; + status = "disabled"; -+ -+ usbdp_phy1_dp: dp-port { -+ #phy-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ usbdp_phy1_u3: usb3-port { -+ #phy-cells = <0>; -+ status = "disabled"; -+ }; + }; + combphy1_ps: phy@fee10000 { compatible = "rockchip,rk3588-naneng-combphy"; reg = <0x0 0xfee10000 0x0 0x100>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -index 8aa0499f9b03..e5f013c6db1a 100644 +index 8708436dd545..069aef13fcd4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -@@ -489,6 +489,37 @@ pipe_phy2_grf: syscon@fd5c4000 { +@@ -516,11 +516,22 @@ vop_grf: syscon@fd5a4000 { + reg = <0x0 0xfd5a4000 0x0 0x2000>; + }; + ++ vo0_grf: syscon@fd5a6000 { ++ compatible = "rockchip,rk3588-vo-grf", "syscon"; ++ reg = <0x0 0xfd5a6000 0x0 0x2000>; ++ clocks = <&cru PCLK_VO0GRF>; ++ }; ++ + vo1_grf: syscon@fd5a8000 { + compatible = "rockchip,rk3588-vo-grf", "syscon"; + reg = <0x0 0xfd5a8000 0x0 0x100>; + }; + ++ usb_grf: syscon@fd5ac000 { ++ compatible = "rockchip,rk3588-usb-grf", "syscon"; ++ reg = <0x0 0xfd5ac000 0x0 0x4000>; ++ }; ++ + php_grf: syscon@fd5b0000 { + compatible = "rockchip,rk3588-php-grf", "syscon"; + reg = <0x0 0xfd5b0000 0x0 0x1000>; +@@ -536,6 +547,36 @@ pipe_phy2_grf: syscon@fd5c4000 { reg = <0x0 0xfd5c4000 0x0 0x100>; }; @@ -2168,22 +2103,21 @@ index 8aa0499f9b03..e5f013c6db1a 100644 + }; + + usb2phy0_grf: syscon@fd5d0000 { -+ compatible = "rockchip,rk3588-usb2phy-grf", "syscon", -+ "simple-mfd"; ++ compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; + reg = <0x0 0xfd5d0000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + -+ u2phy0: usb2-phy@0 { ++ u2phy0: usb2phy@0 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0x0 0x10>; -+ interrupts = ; -+ resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>; -+ reset-names = "phy", "apb"; ++ #clock-cells = <0>; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy0"; -+ #clock-cells = <0>; ++ interrupts = ; ++ resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>; ++ reset-names = "phy", "apb"; + status = "disabled"; + + u2phy0_otg: otg-port { @@ -2196,35 +2130,14 @@ index 8aa0499f9b03..e5f013c6db1a 100644 usb2phy2_grf: syscon@fd5d8000 { compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; reg = <0x0 0xfd5d8000 0x0 0x4000>; -@@ -514,6 +545,17 @@ u2phy2_host: host-port { - }; - }; - -+ vo0_grf: syscon@fd5a6000 { -+ compatible = "rockchip,rk3588-vo-grf", "syscon"; -+ reg = <0x0 0xfd5a6000 0x0 0x2000>; -+ clocks = <&cru PCLK_VO0GRF>; -+ }; -+ -+ usb_grf: syscon@fd5ac000 { -+ compatible = "rockchip,rk3588-usb-grf", "syscon"; -+ reg = <0x0 0xfd5ac000 0x0 0x4000>; -+ }; -+ - usb2phy3_grf: syscon@fd5dc000 { - compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; - reg = <0x0 0xfd5dc000 0x0 0x4000>; -@@ -2244,6 +2286,37 @@ dmac2: dma-controller@fed10000 { +@@ -2360,6 +2401,28 @@ dmac2: dma-controller@fed10000 { #dma-cells = <1>; }; + usbdp_phy0: phy@fed80000 { + compatible = "rockchip,rk3588-usbdp-phy"; + reg = <0x0 0xfed80000 0x0 0x10000>; -+ rockchip,u2phy-grf = <&usb2phy0_grf>; -+ rockchip,usb-grf = <&usb_grf>; -+ rockchip,usbdpphy-grf = <&usbdpphy0_grf>; -+ rockchip,vo-grf = <&vo0_grf>; ++ #phy-cells = <1>; + clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, + <&cru CLK_USBDP_PHY0_IMMORTAL>, + <&cru PCLK_USBDPPHY0>, @@ -2236,40 +2149,36 @@ index 8aa0499f9b03..e5f013c6db1a 100644 + <&cru SRST_USBDP_COMBO_PHY0_PCS>, + <&cru SRST_P_USBDPPHY0>; + reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; ++ rockchip,u2phy-grf = <&usb2phy0_grf>; ++ rockchip,usb-grf = <&usb_grf>; ++ rockchip,usbdpphy-grf = <&usbdpphy0_grf>; ++ rockchip,vo-grf = <&vo0_grf>; + status = "disabled"; -+ -+ usbdp_phy0_dp: dp-port { -+ #phy-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ usbdp_phy0_u3: usb3-port { -+ #phy-cells = <0>; -+ status = "disabled"; -+ }; + }; + combphy0_ps: phy@fee00000 { compatible = "rockchip,rk3588-naneng-combphy"; reg = <0x0 0xfee00000 0x0 0x100>; -- -Armbian +2.43.1 -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 + +From 9339fe0c98e9753e2b35f572accd2efd54cf8a3f Mon Sep 17 00:00:00 2001 From: Sebastian Reichel -Date: Tue, 18 Jul 2023 19:05:38 +0200 -Subject: arm64: dts: rockchip: rk3588s: Add USB3 DRD controllers +Date: Fri, 16 Feb 2024 18:01:22 +0100 +Subject: [PATCH 07/10] arm64: dts: rockchip: add USB3 DRD controllers on + rk3588 Add both USB3 dual-role controllers to the RK3588 devicetree. Signed-off-by: Sebastian Reichel --- - arch/arm64/boot/dts/rockchip/rk3588.dtsi | 20 +++++++++ - arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 22 ++++++++++ + arch/arm64/boot/dts/rockchip/rk3588.dtsi | 20 ++++++++++++++++++++ + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 22 ++++++++++++++++++++++ 2 files changed, 42 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi -index c26288ec75ce..900ac0300f23 100644 +index 4fdd047c9eb9..5984016b5f96 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi @@ -7,6 +7,26 @@ @@ -2283,8 +2192,8 @@ index c26288ec75ce..900ac0300f23 100644 + clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>, + <&cru ACLK_USB3OTG1>; + clock-names = "ref_clk", "suspend_clk", "bus_clk"; -+ dr_mode = "host"; -+ phys = <&u2phy1_otg>, <&usbdp_phy1_u3>; ++ dr_mode = "otg"; ++ phys = <&u2phy1_otg>, <&usbdp_phy1 PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi_wide"; + power-domains = <&power RK3588_PD_USB>; @@ -2300,10 +2209,10 @@ index c26288ec75ce..900ac0300f23 100644 compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon"; reg = <0x0 0xfd5b8000 0x0 0x10000>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -index e5f013c6db1a..bc94f8307722 100644 +index 069aef13fcd4..7ac68ffc3f67 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -@@ -399,6 +399,28 @@ scmi_shmem: sram@0 { +@@ -436,6 +436,28 @@ scmi_shmem: sram@0 { }; }; @@ -2315,7 +2224,7 @@ index e5f013c6db1a..bc94f8307722 100644 + <&cru ACLK_USB3OTG0>; + clock-names = "ref_clk", "suspend_clk", "bus_clk"; + dr_mode = "otg"; -+ phys = <&u2phy0_otg>, <&usbdp_phy0_u3>; ++ phys = <&u2phy0_otg>, <&usbdp_phy0 PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi_wide"; + power-domains = <&power RK3588_PD_USB>; @@ -2333,23 +2242,24 @@ index e5f013c6db1a..bc94f8307722 100644 compatible = "rockchip,rk3588-ehci", "generic-ehci"; reg = <0x0 0xfc800000 0x0 0x40000>; -- -Armbian +2.43.1 -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 + +From b28adcc5e665b94d2b19dc528baf925ea52f16e8 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel -Date: Wed, 26 Apr 2023 21:18:43 +0200 -Subject: arm64: dts: rockchip: rk3588-evb1: add USB3 +Date: Fri, 16 Feb 2024 18:01:23 +0100 +Subject: [PATCH 08/10] arm64: dts: rockchip: add USB3 to rk3588-evb1 -Add support for the boards USB3 type A, as well as its Type-C -connector. +Add support for the board's USB3 connectors. It has 1x USB Type-A +and 1x USB Type-C. Signed-off-by: Sebastian Reichel --- - arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts | 144 ++++++++++ - 1 file changed, 144 insertions(+) + .../boot/dts/rockchip/rk3588-evb1-v10.dts | 143 ++++++++++++++++++ + 1 file changed, 143 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts -index b9d789d57862..4953d9310953 100644 +index ac7c677b0fb9..0e82dbb4c5ff 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts @@ -9,6 +9,7 @@ @@ -2360,7 +2270,7 @@ index b9d789d57862..4953d9310953 100644 #include "rk3588.dtsi" / { -@@ -167,6 +168,18 @@ vcc5v0_usb: vcc5v0-usb-regulator { +@@ -224,6 +225,18 @@ vcc5v0_usb: vcc5v0-usb-regulator { regulator-max-microvolt = <5000000>; vin-supply = <&vcc5v0_usbdcin>; }; @@ -2379,7 +2289,7 @@ index b9d789d57862..4953d9310953 100644 }; &combphy0_ps { -@@ -227,6 +240,56 @@ &gmac0_rgmii_clk +@@ -284,6 +297,56 @@ &gmac0_rgmii_clk &i2c2 { status = "okay"; @@ -2398,7 +2308,7 @@ index b9d789d57862..4953d9310953 100644 + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; -+ try-power-role = "sink"; ++ try-power-role = "source"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; @@ -2436,7 +2346,7 @@ index b9d789d57862..4953d9310953 100644 hym8563: rtc@51 { compatible = "haoyu,hym8563"; reg = <0x51>; -@@ -313,6 +376,16 @@ vcc5v0_host_en: vcc5v0-host-en { +@@ -410,6 +473,16 @@ vcc5v0_host_en: vcc5v0-host-en { rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; }; }; @@ -2453,7 +2363,7 @@ index b9d789d57862..4953d9310953 100644 }; &pwm2 { -@@ -943,6 +1016,22 @@ &sata0 { +@@ -1040,6 +1113,22 @@ &sata0 { status = "okay"; }; @@ -2476,7 +2386,7 @@ index b9d789d57862..4953d9310953 100644 &u2phy2 { status = "okay"; }; -@@ -981,3 +1070,58 @@ &usb_host1_ehci { +@@ -1078,3 +1167,57 @@ &usb_host1_ehci { &usb_host1_ohci { status = "okay"; }; @@ -2504,19 +2414,17 @@ index b9d789d57862..4953d9310953 100644 + }; +}; + -+&usbdp_phy0_u3 { -+ status = "okay"; -+}; -+ +&usbdp_phy1 { ++ /* ++ * USBDP PHY1 is wired to a female USB3 Type-A connector. Additionally ++ * the differential pairs 2+3 and the aux channel are wired to a RTD2166, ++ * which converts the DP signal into VGA. This is exposed on the ++ * board via a female VGA connector. ++ */ + rockchip,dp-lane-mux = <2 3>; + status = "okay"; +}; + -+&usbdp_phy1_u3 { -+ status = "okay"; -+}; -+ +&usb_host0_xhci { + dr_mode = "otg"; + usb-role-switch; @@ -2533,10 +2441,11 @@ index b9d789d57862..4953d9310953 100644 +}; + +&usb_host1_xhci { ++ dr_mode = "host"; + status = "okay"; +}; -- -Armbian +2.43.1 From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel @@ -2583,23 +2492,24 @@ index bfb6f9481e87..190c1edaad77 100644 err = PTR_ERR(port->role_sw); goto out_destroy_wq; -- -Armbian +2.43.1 -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 + +From 40a6e7ead1c34bc74c08e9bb0888ba098e0e7edd Mon Sep 17 00:00:00 2001 From: Sebastian Reichel -Date: Tue, 25 Jul 2023 16:30:46 +0200 -Subject: arm64: dts: rockchip: rk3588s-rock5a: add upper USB3 port +Date: Fri, 16 Feb 2024 18:01:24 +0100 +Subject: [PATCH 09/10] arm64: dts: rockchip: add upper USB3 port to rock-5a Enable full support (XHCI, EHCI, OHCI) for the upper USB3 port from -Radxa Rock 5 Model A. +Radxa Rock 5 Model A. The lower one is already supported. Signed-off-by: Sebastian Reichel --- - arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 22 ++++++++++ - 1 file changed, 22 insertions(+) + .../boot/dts/rockchip/rk3588s-rock-5a.dts | 18 ++++++++++++++++++ + 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts -index 6fb03294576c..a6ec5e770e71 100644 +index 2002fd0221fa..149058352f4e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts @@ -698,6 +698,14 @@ regulator-state-mem { @@ -2617,7 +2527,7 @@ index 6fb03294576c..a6ec5e770e71 100644 &u2phy2 { status = "okay"; }; -@@ -721,6 +729,15 @@ &uart2 { +@@ -721,6 +729,11 @@ &uart2 { status = "okay"; }; @@ -2625,15 +2535,11 @@ index 6fb03294576c..a6ec5e770e71 100644 + status = "okay"; + rockchip,dp-lane-mux = <2 3>; +}; -+ -+&usbdp_phy0_u3 { -+ status = "okay"; -+}; + &usb_host0_ehci { status = "okay"; pinctrl-names = "default"; -@@ -731,6 +748,11 @@ &usb_host0_ohci { +@@ -731,6 +744,11 @@ &usb_host0_ohci { status = "okay"; }; @@ -2646,26 +2552,27 @@ index 6fb03294576c..a6ec5e770e71 100644 status = "okay"; }; -- -Armbian +2.43.1 -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 + +From d1e42f568c8b70480724ac27ffe9af645311f1e5 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel -Date: Tue, 25 Jul 2023 17:18:17 +0200 -Subject: arm64: dts: rockchip: rk3588-rock5b: add lower USB3 port +Date: Fri, 16 Feb 2024 18:01:25 +0100 +Subject: [PATCH 10/10] arm64: dts: rockchip: add lower USB3 port to rock-5b Enable full support (XHCI, EHCI, OHCI) for the lower USB3 port from -Radxa Rock 5 Model B. +Radxa Rock 5 Model B. The upper one is already supported. Signed-off-by: Sebastian Reichel --- - arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 20 ++++++++++ - 1 file changed, 20 insertions(+) + arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 17 +++++++++++++++++ + 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -index 61b937beca7f..bd38c67b6c76 100644 +index 9b7bf6cec8bd..d14e8f451ae9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -@@ -735,6 +735,14 @@ &uart2 { +@@ -743,6 +743,14 @@ &uart2 { status = "okay"; }; @@ -2680,26 +2587,23 @@ index 61b937beca7f..bd38c67b6c76 100644 &u2phy2 { status = "okay"; }; -@@ -754,6 +762,14 @@ &u2phy3_host { +@@ -762,6 +770,10 @@ &u2phy3_host { status = "okay"; }; +&usbdp_phy1 { + status = "okay"; +}; -+ -+&usbdp_phy1_u3 { -+ status = "okay"; -+}; + &usb_host0_ehci { status = "okay"; }; -@@ -770,6 +786,10 @@ &usb_host1_ohci { +@@ -778,6 +790,11 @@ &usb_host1_ohci { status = "okay"; }; +&usb_host1_xhci { ++ dr_mode = "host"; + status = "okay"; +}; + @@ -2707,200 +2611,5 @@ index 61b937beca7f..bd38c67b6c76 100644 status = "okay"; }; -- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Tue, 25 Jul 2023 18:35:56 +0200 -Subject: arm64: dts: rockchip: rk3588-rock5b: add USB-C support - -Add support for using the Radxa Rock 5 Model B USB-C port for USB in -OHCI, EHCI or XHCI mode. Displayport AltMode is not yet supported. - -Signed-off-by: Sebastian Reichel ---- - arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 119 ++++++++++ - 1 file changed, 119 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -index bd38c67b6c76..419d0202f7fc 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -@@ -4,6 +4,7 @@ - - #include - #include -+#include - #include "rk3588.dtsi" - - / { -@@ -59,6 +60,15 @@ fan: pwm-fan { - #cooling-cells = <2>; - }; - -+ vcc12v_dcin: vcc12v-dcin-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc12v_dcin"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <12000000>; -+ regulator-max-microvolt = <12000000>; -+ }; -+ - vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator { - compatible = "regulator-fixed"; - enable-active-high; -@@ -117,6 +127,7 @@ vcc5v0_sys: vcc5v0-sys-regulator { - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc12v_dcin>; - }; - - vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { -@@ -214,6 +225,61 @@ regulator-state-mem { - }; - }; - -+&i2c4 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c4m1_xfer>; -+ status = "okay"; -+ -+ usbc0: usb-typec@22 { -+ compatible = "fcs,fusb302"; -+ reg = <0x22>; -+ interrupt-parent = <&gpio3>; -+ interrupts = ; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&usbc0_int>; -+ vbus-supply = <&vcc12v_dcin>; -+ status = "okay"; -+ -+ usb_con: connector { -+ compatible = "usb-c-connector"; -+ label = "USB-C"; -+ data-role = "dual"; -+ power-role = "sink"; -+ try-power-role = "sink"; -+ op-sink-microwatt = <1000000>; -+ sink-pdos = -+ , -+ ; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ reg = <0>; -+ usbc0_hs: endpoint { -+ remote-endpoint = <&usb_host0_xhci_drd_sw>; -+ }; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ usbc0_ss: endpoint { -+ remote-endpoint = <&usbdp_phy0_typec_ss>; -+ }; -+ }; -+ -+ port@2 { -+ reg = <2>; -+ usbc0_sbu: endpoint { -+ remote-endpoint = <&usbdp_phy0_typec_sbu>; -+ }; -+ }; -+ }; -+ }; -+ }; -+}; -+ - &i2c6 { - status = "okay"; - -@@ -343,6 +409,10 @@ usb { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; - }; -+ -+ usbc0_int: usbc0-int { -+ rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; - }; - }; - -@@ -735,6 +805,14 @@ &uart2 { - status = "okay"; - }; - -+&u2phy0 { -+ status = "okay"; -+}; -+ -+&u2phy0_otg { -+ status = "okay"; -+}; -+ - &u2phy1 { - status = "okay"; - }; -@@ -770,6 +848,33 @@ &usbdp_phy1_u3 { - status = "okay"; - }; - -+&usbdp_phy0 { -+ orientation-switch; -+ mode-switch; -+ sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; -+ sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; -+ status = "okay"; -+ -+ port { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ usbdp_phy0_typec_ss: endpoint@0 { -+ reg = <0>; -+ remote-endpoint = <&usbc0_ss>; -+ }; -+ -+ usbdp_phy0_typec_sbu: endpoint@1 { -+ reg = <1>; -+ remote-endpoint = <&usbc0_sbu>; -+ }; -+ }; -+}; -+ -+&usbdp_phy0_u3 { -+ status = "okay"; -+}; -+ - &usb_host0_ehci { - status = "okay"; - }; -@@ -778,6 +883,20 @@ &usb_host0_ohci { - status = "okay"; - }; - -+&usb_host0_xhci { -+ usb-role-switch; -+ status = "okay"; -+ -+ port { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ usb_host0_xhci_drd_sw: endpoint { -+ remote-endpoint = <&usbc0_hs>; -+ }; -+ }; -+}; -+ - &usb_host1_ehci { - status = "okay"; - }; --- -Armbian +2.43.1 diff --git a/patch/kernel/rockchip-rk3588-edge/0026-Add-missing-nodes-to-Orange-Pi-5.patch b/patch/kernel/rockchip-rk3588-edge/0026-Add-missing-nodes-to-Orange-Pi-5.patch index 14839fcc73..066d7f7d2c 100644 --- a/patch/kernel/rockchip-rk3588-edge/0026-Add-missing-nodes-to-Orange-Pi-5.patch +++ b/patch/kernel/rockchip-rk3588-edge/0026-Add-missing-nodes-to-Orange-Pi-5.patch @@ -1,14 +1,14 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From 455c18d58092dab508cf7585d9c863a9c4bd5fe1 Mon Sep 17 00:00:00 2001 From: Muhammed Efe Cetin Date: Thu, 16 Nov 2023 18:09:07 +0300 -Subject: arm64: dts: Add missing nodes to Orange Pi 5 +Subject: [PATCH] arm64: dts: Add missing nodes to Orange Pi 5 --- - arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts | 228 +++++++++- - 1 file changed, 227 insertions(+), 1 deletion(-) + .../boot/dts/rockchip/rk3588s-orangepi-5.dts | 215 +++++++++++++++++- + 1 file changed, 214 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts -index e3a839a12dc6..ced3371f73c5 100644 +index 25de4362af38..f5e86d99084d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts @@ -6,6 +6,8 @@ @@ -204,7 +204,7 @@ index e3a839a12dc6..ced3371f73c5 100644 }; &saradc { -@@ -363,7 +493,7 @@ regulator-state-mem { +@@ -364,7 +494,7 @@ regulator-state-mem { }; }; @@ -213,7 +213,7 @@ index e3a839a12dc6..ced3371f73c5 100644 regulator-name = "vdd_cpu_lit_s0"; regulator-always-on; regulator-boot-on; -@@ -624,6 +754,14 @@ &tsadc { +@@ -625,6 +755,14 @@ &tsadc { status = "okay"; }; @@ -228,7 +228,7 @@ index e3a839a12dc6..ced3371f73c5 100644 &u2phy2 { status = "okay"; }; -@@ -649,10 +787,56 @@ &usb_host0_ehci { +@@ -650,10 +788,48 @@ &usb_host0_ehci { status = "okay"; }; @@ -254,14 +254,6 @@ index e3a839a12dc6..ced3371f73c5 100644 + }; + }; +}; -+ -+&usbdp_phy0_dp { -+ status = "okay"; -+}; -+ -+&usbdp_phy0_u3 { -+ status = "okay"; -+}; + &usb_host0_ohci { status = "okay"; @@ -285,16 +277,11 @@ index e3a839a12dc6..ced3371f73c5 100644 &usb_host1_ehci { status = "okay"; }; -@@ -660,3 +844,45 @@ &usb_host1_ehci { - &usb_host1_ohci { +@@ -665,3 +841,40 @@ &usb_host1_ohci { + &usb_host2_xhci { status = "okay"; }; + -+&usb_host2_xhci { -+ dr_mode = "host"; -+ status = "okay"; -+}; -+ +&hdmi0 { + enable-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + status = "okay"; @@ -331,7 +318,6 @@ index e3a839a12dc6..ced3371f73c5 100644 + remote-endpoint = <&hdmi0_in_vp0>; + }; +}; -\ No newline at end of file -- -Armbian +2.43.1 diff --git a/patch/kernel/rockchip-rk3588-edge/0027-arm64-dts-Add-missing-nodes-to-Orange-Pi-5-Plus.patch b/patch/kernel/rockchip-rk3588-edge/0027-arm64-dts-Add-missing-nodes-to-Orange-Pi-5-Plus.patch index 380fbc6f7e..c9d430124f 100644 --- a/patch/kernel/rockchip-rk3588-edge/0027-arm64-dts-Add-missing-nodes-to-Orange-Pi-5-Plus.patch +++ b/patch/kernel/rockchip-rk3588-edge/0027-arm64-dts-Add-missing-nodes-to-Orange-Pi-5-Plus.patch @@ -1,14 +1,14 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From 54a207592a425697c5b81fa486062d10a551d223 Mon Sep 17 00:00:00 2001 From: Muhammed Efe Cetin Date: Thu, 16 Nov 2023 18:15:09 +0300 -Subject: arm64: dts: Add missing nodes to Orange Pi 5 Plus +Subject: [PATCH] arm64: dts: Add missing nodes to Orange Pi 5 Plus --- - arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts | 198 +++++++++- - 1 file changed, 197 insertions(+), 1 deletion(-) + .../dts/rockchip/rk3588-orangepi-5-plus.dts | 189 +++++++++++++++++- + 1 file changed, 188 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts -index 298c183d6f4f..87803e6e0fa7 100644 +index 3e660ff6cd5f..69cdc966d602 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts @@ -10,6 +10,7 @@ @@ -19,7 +19,7 @@ index 298c183d6f4f..87803e6e0fa7 100644 #include "rk3588.dtsi" / { -@@ -159,6 +160,17 @@ daicodec: simple-audio-card,codec { +@@ -158,6 +159,17 @@ daicodec: simple-audio-card,codec { }; }; @@ -37,7 +37,7 @@ index 298c183d6f4f..87803e6e0fa7 100644 vcc3v3_pcie30: vcc3v3-pcie30-regulator { compatible = "regulator-fixed"; enable-active-high; -@@ -200,6 +212,18 @@ vcc5v0_sys: vcc5v0-sys-regulator { +@@ -199,6 +211,18 @@ vcc5v0_sys: vcc5v0-sys-regulator { regulator-max-microvolt = <5000000>; }; @@ -56,7 +56,7 @@ index 298c183d6f4f..87803e6e0fa7 100644 vcc5v0_usb20: vcc5v0-usb20-regulator { compatible = "regulator-fixed"; enable-active-high; -@@ -227,34 +251,42 @@ &combphy2_psu { +@@ -226,34 +250,42 @@ &combphy2_psu { &cpu_b0 { cpu-supply = <&vdd_cpu_big0_s0>; @@ -99,7 +99,7 @@ index 298c183d6f4f..87803e6e0fa7 100644 }; &i2c0 { -@@ -312,6 +344,53 @@ hym8563: rtc@51 { +@@ -311,6 +343,53 @@ hym8563: rtc@51 { pinctrl-0 = <&hym8563_int>; wakeup-source; }; @@ -153,7 +153,7 @@ index 298c183d6f4f..87803e6e0fa7 100644 }; &i2c7 { -@@ -409,6 +488,14 @@ hp_detect: hp-detect { +@@ -408,6 +487,14 @@ hp_detect: hp-detect { }; usb { @@ -168,7 +168,7 @@ index 298c183d6f4f..87803e6e0fa7 100644 vcc5v0_usb20_en: vcc5v0-usb20-en { rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; }; -@@ -536,7 +623,7 @@ regulator-state-mem { +@@ -535,7 +622,7 @@ regulator-state-mem { }; }; @@ -177,7 +177,7 @@ index 298c183d6f4f..87803e6e0fa7 100644 regulator-name = "vdd_cpu_lit_s0"; regulator-always-on; regulator-boot-on; -@@ -803,6 +890,22 @@ &tsadc { +@@ -802,6 +889,22 @@ &tsadc { status = "okay"; }; @@ -200,7 +200,7 @@ index 298c183d6f4f..87803e6e0fa7 100644 &u2phy2 { status = "okay"; }; -@@ -831,6 +934,44 @@ &uart9 { +@@ -830,6 +933,35 @@ &uart9 { status = "okay"; }; @@ -228,24 +228,15 @@ index 298c183d6f4f..87803e6e0fa7 100644 + }; +}; + -+&usbdp_phy0_u3 { -+ status = "okay"; -+}; -+ +&usbdp_phy1 { + rockchip,dp-lane-mux = <2 3>; + status = "okay"; +}; -+ -+&usbdp_phy1_u3 { -+ status = "okay"; -+}; -+ + &usb_host0_ehci { status = "okay"; }; -@@ -839,6 +980,20 @@ &usb_host0_ohci { +@@ -838,6 +970,20 @@ &usb_host0_ohci { status = "okay"; }; @@ -266,7 +257,7 @@ index 298c183d6f4f..87803e6e0fa7 100644 &usb_host1_ehci { status = "okay"; }; -@@ -846,3 +1001,44 @@ &usb_host1_ehci { +@@ -845,3 +991,44 @@ &usb_host1_ehci { &usb_host1_ohci { status = "okay"; }; @@ -312,5 +303,5 @@ index 298c183d6f4f..87803e6e0fa7 100644 + }; +}; -- -Armbian +2.43.1 diff --git a/patch/kernel/rockchip-rk3588-edge/0030-Add-HDMI-and-VOP2-to-Rock-5-series.patch b/patch/kernel/rockchip-rk3588-edge/0030-Add-HDMI-and-VOP2-to-Rock-5-series.patch deleted file mode 100644 index de61442021..0000000000 --- a/patch/kernel/rockchip-rk3588-edge/0030-Add-HDMI-and-VOP2-to-Rock-5-series.patch +++ /dev/null @@ -1,155 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Muhammed Efe Cetin -Date: Sat, 2 Dec 2023 12:32:54 +0300 -Subject: Add HDMI and VOP2 to Rock 5 series - ---- - arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 49 ++++++++++ - arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 49 ++++++++++ - 2 files changed, 98 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -index 9ee415e6f498..1b741b5ca81b 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts -@@ -5,6 +5,7 @@ - #include - #include - #include -+#include - #include "rk3588.dtsi" - - / { -@@ -60,6 +61,17 @@ fan: pwm-fan { - #cooling-cells = <2>; - }; - -+ hdmi-con { -+ compatible = "hdmi-connector"; -+ type = "a"; -+ -+ port { -+ hdmi_con_in: endpoint { -+ remote-endpoint = <&hdmi0_out_con>; -+ }; -+ }; -+ }; -+ - vcc12v_dcin: vcc12v-dcin-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc12v_dcin"; -@@ -920,3 +932,40 @@ &usb_host1_xhci { - &usb_host2_xhci { - status = "okay"; - }; -+ -+&hdmi0 { -+ enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; -+ status = "okay"; -+}; -+ -+ -+&hdptxphy_hdmi0 { -+ status = "okay"; -+}; -+ -+&vop_mmu { -+ status = "okay"; -+}; -+ -+&hdmi0_in { -+ hdmi0_in_vp0: endpoint { -+ remote-endpoint = <&vp0_out_hdmi0>; -+ }; -+}; -+ -+&hdmi0_out { -+ hdmi0_out_con: endpoint { -+ remote-endpoint = <&hdmi_con_in>; -+ }; -+}; -+ -+&vop { -+ status = "okay"; -+}; -+ -+&vp0 { -+ vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { -+ reg = ; -+ remote-endpoint = <&hdmi0_in_vp0>; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts -index 58c58ec03a7f..783a11493cd2 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts -@@ -5,6 +5,7 @@ - #include - #include - #include -+#include - #include "rk3588s.dtsi" - - / { -@@ -56,6 +57,17 @@ fan: pwm-fan { - #cooling-cells = <2>; - }; - -+ hdmi-con { -+ compatible = "hdmi-connector"; -+ type = "a"; -+ -+ port { -+ hdmi_con_in: endpoint { -+ remote-endpoint = <&hdmi0_out_con>; -+ }; -+ }; -+ }; -+ - vcc12v_dcin: vcc12v-dcin-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc12v_dcin"; -@@ -772,3 +784,40 @@ &usb_host1_ohci { - &usb_host2_xhci { - status = "okay"; - }; -+ -+&hdmi0 { -+ enable-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; -+ status = "okay"; -+}; -+ -+ -+&hdptxphy_hdmi0 { -+ status = "okay"; -+}; -+ -+&vop_mmu { -+ status = "okay"; -+}; -+ -+&hdmi0_in { -+ hdmi0_in_vp0: endpoint { -+ remote-endpoint = <&vp0_out_hdmi0>; -+ }; -+}; -+ -+&hdmi0_out { -+ hdmi0_out_con: endpoint { -+ remote-endpoint = <&hdmi_con_in>; -+ }; -+}; -+ -+&vop { -+ status = "okay"; -+}; -+ -+&vp0 { -+ vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { -+ reg = ; -+ remote-endpoint = <&hdmi0_in_vp0>; -+ }; -+}; --- -Armbian - diff --git a/patch/kernel/rockchip-rk3588-edge/0032-arm64-dts-rock-5b-Slow-down-emmc-to-hs200-and-add-ts.patch b/patch/kernel/rockchip-rk3588-edge/0030-arm64-dts-rock-5b-Slow-down-emmc-to-hs200-and-add-ts.patch similarity index 100% rename from patch/kernel/rockchip-rk3588-edge/0032-arm64-dts-rock-5b-Slow-down-emmc-to-hs200-and-add-ts.patch rename to patch/kernel/rockchip-rk3588-edge/0030-arm64-dts-rock-5b-Slow-down-emmc-to-hs200-and-add-ts.patch diff --git a/patch/kernel/rockchip-rk3588-edge/0031-Add-HDMI-and-VOP2-to-Rock-5A.patch b/patch/kernel/rockchip-rk3588-edge/0031-Add-HDMI-and-VOP2-to-Rock-5A.patch new file mode 100644 index 0000000000..a8271f299e --- /dev/null +++ b/patch/kernel/rockchip-rk3588-edge/0031-Add-HDMI-and-VOP2-to-Rock-5A.patch @@ -0,0 +1,82 @@ +From 77b6e6e4d1d1791e2dcfb7014601a4d727a2bce9 Mon Sep 17 00:00:00 2001 +From: Muhammed Efe Cetin +Date: Tue, 27 Feb 2024 16:04:42 +0300 +Subject: [PATCH] Add HDMI and VOP2 to Rock 5A + +--- + .../boot/dts/rockchip/rk3588s-rock-5a.dts | 48 +++++++++++++++++++ + 1 file changed, 48 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts +index a9ad9d2d54ae..e62eacbd54f6 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts +@@ -5,6 +5,7 @@ + #include + #include + #include ++#include + #include "rk3588s.dtsi" + + / { +@@ -56,6 +57,17 @@ fan: pwm-fan { + #cooling-cells = <2>; + }; + ++ hdmi-con { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi_con_in: endpoint { ++ remote-endpoint = <&hdmi0_out_con>; ++ }; ++ }; ++ }; ++ + vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; +@@ -768,3 +780,39 @@ &usb_host1_ohci { + &usb_host2_xhci { + status = "okay"; + }; ++ ++&hdmi0 { ++ enable-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; ++ status = "okay"; ++}; ++ ++&hdptxphy_hdmi0 { ++ status = "okay"; ++}; ++ ++&vop_mmu { ++ status = "okay"; ++}; ++ ++&hdmi0_in { ++ hdmi0_in_vp0: endpoint { ++ remote-endpoint = <&vp0_out_hdmi0>; ++ }; ++}; ++ ++&hdmi0_out { ++ hdmi0_out_con: endpoint { ++ remote-endpoint = <&hdmi_con_in>; ++ }; ++}; ++ ++&vop { ++ status = "okay"; ++}; ++ ++&vp0 { ++ vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { ++ reg = ; ++ remote-endpoint = <&hdmi0_in_vp0>; ++ }; ++}; +-- +2.43.1 + diff --git a/patch/kernel/rockchip-rk3588-edge/0032-Add-HDMI-and-VOP2-to-Rock-5B.patch b/patch/kernel/rockchip-rk3588-edge/0032-Add-HDMI-and-VOP2-to-Rock-5B.patch new file mode 100644 index 0000000000..f65b5f8c58 --- /dev/null +++ b/patch/kernel/rockchip-rk3588-edge/0032-Add-HDMI-and-VOP2-to-Rock-5B.patch @@ -0,0 +1,82 @@ +From f1cc29e5eb612607c6c2bf3a4a479018220e8632 Mon Sep 17 00:00:00 2001 +From: Muhammed Efe Cetin +Date: Tue, 27 Feb 2024 16:08:14 +0300 +Subject: [PATCH] Add HDMI and VOP2 to Rock 5B + +--- + .../boot/dts/rockchip/rk3588-rock-5b.dts | 48 +++++++++++++++++++ + 1 file changed, 48 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +index 8daf44c2e57c..e1aca314b901 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +@@ -4,6 +4,7 @@ + + #include + #include ++#include + #include "rk3588.dtsi" + + / { +@@ -65,6 +66,17 @@ rfkill { + shutdown-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + }; + ++ hdmi-con { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi_con_in: endpoint { ++ remote-endpoint = <&hdmi0_out_con>; ++ }; ++ }; ++ }; ++ + vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator { + compatible = "regulator-fixed"; + enable-active-high; +@@ -809,3 +821,39 @@ &usb_host1_xhci { + &usb_host2_xhci { + status = "okay"; + }; ++ ++&hdmi0 { ++ enable-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; ++ status = "okay"; ++}; ++ ++&hdptxphy_hdmi0 { ++ status = "okay"; ++}; ++ ++&vop_mmu { ++ status = "okay"; ++}; ++ ++&hdmi0_in { ++ hdmi0_in_vp0: endpoint { ++ remote-endpoint = <&vp0_out_hdmi0>; ++ }; ++}; ++ ++&hdmi0_out { ++ hdmi0_out_con: endpoint { ++ remote-endpoint = <&hdmi_con_in>; ++ }; ++}; ++ ++&vop { ++ status = "okay"; ++}; ++ ++&vp0 { ++ vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { ++ reg = ; ++ remote-endpoint = <&hdmi0_in_vp0>; ++ }; ++}; +-- +2.43.1 + diff --git a/patch/kernel/rockchip-rk3588-edge/dt/rk3588-hinlink-h88k.dts b/patch/kernel/rockchip-rk3588-edge/dt/rk3588-hinlink-h88k.dts index 9a1c7f950f..f7776d1e30 100644 --- a/patch/kernel/rockchip-rk3588-edge/dt/rk3588-hinlink-h88k.dts +++ b/patch/kernel/rockchip-rk3588-edge/dt/rk3588-hinlink-h88k.dts @@ -793,10 +793,6 @@ status = "okay"; }; -&usbdp_phy1_u3 { - status = "okay"; -}; - &usb_host0_ehci { status = "okay"; }; diff --git a/patch/kernel/rockchip-rk3588-edge/dt/rk3588s-nanopi-r6s.dts b/patch/kernel/rockchip-rk3588-edge/dt/rk3588s-nanopi-r6s.dts index 273dada5bc..6667be1880 100644 --- a/patch/kernel/rockchip-rk3588-edge/dt/rk3588s-nanopi-r6s.dts +++ b/patch/kernel/rockchip-rk3588-edge/dt/rk3588s-nanopi-r6s.dts @@ -838,10 +838,6 @@ status = "okay"; }; -&usbdp_phy0_u3 { - status = "okay"; -}; - &hdmi0 { enable-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; status = "okay";