From 36db4a668d01abca216d1d747903ef08cda0776c Mon Sep 17 00:00:00 2001 From: Tonymac32 Date: Thu, 21 Sep 2017 06:02:37 +0000 Subject: [PATCH] rockchip Dev hdmi fix vopl and vopb entries were still 32 bit in the dtsi after the rest had been migrated to 64 bit. --- .../rockchip-dev/9008_vop_fix_64bit.patch | 58 +++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 patch/kernel/rockchip-dev/9008_vop_fix_64bit.patch diff --git a/patch/kernel/rockchip-dev/9008_vop_fix_64bit.patch b/patch/kernel/rockchip-dev/9008_vop_fix_64bit.patch new file mode 100644 index 0000000000..5bb69b2491 --- /dev/null +++ b/patch/kernel/rockchip-dev/9008_vop_fix_64bit.patch @@ -0,0 +1,58 @@ +diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi +index 8f980d7..f3e0ff4 100644 +--- a/arch/arm/boot/dts/rk3288.dtsi ++++ b/arch/arm/boot/dts/rk3288.dtsi +@@ -990,7 +990,7 @@ + + vopb: vop@ff930000 { + compatible = "rockchip,rk3288-vop"; +- reg = <0xff930000 0x19c>, <0xff931000 0x1000>; ++ reg = <0x0 0xff930000 0x0 0x19c>, <0x0 0xff931000 0x0 0x1000>; + interrupts = ; + clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; +@@ -1038,7 +1038,7 @@ + + vopl: vop@ff940000 { + compatible = "rockchip,rk3288-vop"; +- reg = <0xff940000 0x19c>, <0xff941000 0x1000>; ++ reg = <0x0 0xff940000 0x0 0x19c>, <0x0 0xff941000 0x0 0x1000>; + interrupts = ; + clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; +@@ -1114,7 +1114,7 @@ + + lvds: lvds@ff96c000 { + compatible = "rockchip,rk3288-lvds"; +- reg = <0xff96c000 0x4000>; ++ reg = <0x0 0xff96c000 0x0 0x4000>; + clocks = <&cru PCLK_LVDS_PHY>; + clock-names = "pclk_lvds"; + pinctrl-names = "lcdc"; +@@ -1224,7 +1224,7 @@ + + vpu: video-codec@ff9a0000 { + compatible = "rockchip,rk3288-vpu"; +- reg = <0xff9a0000 0x800>; ++ reg = <0x0 0xff9a0000 0x0 0x800>; + interrupts = , + ; + interrupt-names = "vepu", "vdpu"; +@@ -1239,7 +1239,7 @@ + + vpu_service: vpu-service@ff9a0000 { + compatible = "rockchip,vpu_service"; +- reg = <0xff9a0000 0x800>; ++ reg = <0x0 0xff9a0000 0x0 0x800>; + interrupts = , + ; + interrupt-names = "irq_enc", "irq_dec"; +@@ -1259,7 +1259,7 @@ + + hevc_service: hevc-service@ff9c0000 { + compatible = "rockchip,hevc_service"; +- reg = <0xff9c0000 0x400>; ++ reg = <0x0 0xff9c0000 0x0 0x400>; + interrupts = ; + interrupt-names = "irq_dec"; + clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,