From 35dddeab3114cfd16d4237079191a27e4e7f6d83 Mon Sep 17 00:00:00 2001 From: Gunjan Gupta Date: Fri, 30 Jun 2023 01:27:04 +0530 Subject: [PATCH] patch: kernel: allwinner: add patches for 6.4 kernel --- ...d-dump_reg-and-sunxi-sysinfo-drivers.patch | 1551 + ...to-fix-uwe5622-bluetooth-MAC-address.patch | 611 + .../Bananapro-add-AXP209-regulators.patch | 72 + .../Compile-the-pwm-overlay.patch | 24 + ...ding-for-DWC3-controller-on-Allwinne.patch | 64 + .../Fix-compile-error-node-not-found.patch | 68 + .../Fix-include-uapi-spi-spidev-module.patch | 26 + ...media-uapi-hevc-tiles-and-num_slices.patch | 37 + ...FIG_SHELL-fix-for-builddeb-packaging.patch | 27 + ...i-h6-pwm-settings-to-its-own-overlay.patch | 70 + ....h-and-uapi-linux-ipx.h-header-files.patch | 287 + .../Rollback-r_rsb-to-r_i2c.patch | 32 + ...pi-hevc-add-fields-needed-for-rkvdec.patch | 66 + ...dd-initial-support-for-orangepi3-lts.patch | 610 + ...lwinner-h6-Support-ac200-audio-codec.patch | 1875 + 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mode 100644 patch/kernel/archive/sunxi-6.4/patches.megous/usb-typec-fusb302-Fix-register-definitions.patch create mode 100644 patch/kernel/archive/sunxi-6.4/patches.megous/usb-typec-fusb302-Make-tcpm-fusb302-logs-less-polluted-by-PD-co.patch create mode 100644 patch/kernel/archive/sunxi-6.4/patches.megous/usb-typec-fusb302-More-useful-of-logging-status-on-interrupt.patch create mode 100644 patch/kernel/archive/sunxi-6.4/patches.megous/usb-typec-fusb302-Retry-reading-of-CC-pins-status-if-activity-i.patch create mode 100644 patch/kernel/archive/sunxi-6.4/patches.megous/usb-typec-fusb302-Set-the-current-before-enabling-pullups.patch create mode 100644 patch/kernel/archive/sunxi-6.4/patches.megous/usb-typec-fusb302-Slightly-increase-wait-time-for-BC1.2-result.patch create mode 100644 patch/kernel/archive/sunxi-6.4/patches.megous/usb-typec-fusb302-Update-VBUS-state-even-if-VBUS-interrupt-is-n.patch create mode 100644 patch/kernel/archive/sunxi-6.4/patches.megous/usb-typec-tcpm-Fix-PD-devices-capabilities-registration.patch create mode 100644 patch/kernel/archive/sunxi-6.4/patches.megous/usb-typec-tcpm-Unregister-altmodes-before-registering-new-ones.patch create mode 100644 patch/kernel/archive/sunxi-6.4/patches.megous/usb-typec-typec-extcon-Add-typec-extcon-bridge-driver.patch create mode 100644 patch/kernel/archive/sunxi-6.4/patches.megous/usb-typec-typec-extcon-Allow-to-force-reset-on-each-mux-change.patch create mode 100644 patch/kernel/archive/sunxi-6.4/patches.megous/usb-typec-typec-extcon-Enable-debugging-for-now.patch create mode 100644 patch/kernel/archive/sunxi-6.4/patches.megous/video-fbdev-eInk-display-driver-for-A13-based-PocketBooks.patch create mode 100644 patch/kernel/archive/sunxi-6.4/patches.megous/video-pwm_bl-Allow-to-change-lth_brightness-via-sysfs.patch create mode 100644 patch/kernel/archive/sunxi-6.4/series.armbian create mode 100644 patch/kernel/archive/sunxi-6.4/series.conf create mode 100644 patch/kernel/archive/sunxi-6.4/series.fixes create mode 100644 patch/kernel/archive/sunxi-6.4/series.megous diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/Add-dump_reg-and-sunxi-sysinfo-drivers.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/Add-dump_reg-and-sunxi-sysinfo-drivers.patch new file mode 100644 index 0000000000..26e757c4f1 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/Add-dump_reg-and-sunxi-sysinfo-drivers.patch @@ -0,0 +1,1551 @@ +From 8d2ca284c7221670320d9a1dc50d1c8588dae6e4 Mon Sep 17 00:00:00 2001 +From: afaulkner420 +Date: Fri, 25 Mar 2022 19:28:00 +0000 +Subject: [PATCH 142/153] Add dump_reg and sunxi-sysinfo drivers + +--- + drivers/char/Kconfig | 2 + + drivers/char/Makefile | 2 + + drivers/char/dump_reg/Kconfig | 21 + + drivers/char/dump_reg/Makefile | 2 + + drivers/char/dump_reg/dump_reg.c | 888 +++++++++++++++++++++ + drivers/char/dump_reg/dump_reg.h | 132 +++ + drivers/char/dump_reg/dump_reg_misc.c | 209 +++++ + drivers/char/sunxi-sysinfo/Kconfig | 10 + + drivers/char/sunxi-sysinfo/Makefile | 5 + + drivers/char/sunxi-sysinfo/sunxi-sysinfo.c | 177 +++++ + 10 files changed, 1449 insertions(+) + create mode 100644 drivers/char/dump_reg/Kconfig + create mode 100644 drivers/char/dump_reg/Makefile + create mode 100644 drivers/char/dump_reg/dump_reg.c + create mode 100644 drivers/char/dump_reg/dump_reg.h + create mode 100644 drivers/char/dump_reg/dump_reg_misc.c + create mode 100644 drivers/char/sunxi-sysinfo/Kconfig + create mode 100644 drivers/char/sunxi-sysinfo/Makefile + create mode 100644 drivers/char/sunxi-sysinfo/sunxi-sysinfo.c + +diff --git a/drivers/char/Kconfig b/drivers/char/Kconfig +index 30fe9848d..89c4180cf 100644 +--- a/drivers/char/Kconfig ++++ b/drivers/char/Kconfig +@@ -132,6 +132,8 @@ config POWERNV_OP_PANEL + If unsure, say M here to build it as a module called powernv-op-panel. + + source "drivers/char/ipmi/Kconfig" ++source "drivers/char/sunxi-sysinfo/Kconfig" ++source "drivers/char/dump_reg/Kconfig" + + config DS1620 + tristate "NetWinder thermometer support" +diff --git a/drivers/char/Makefile b/drivers/char/Makefile +index 1b35d1724..f7b466d42 100644 +--- a/drivers/char/Makefile ++++ b/drivers/char/Makefile +@@ -11,6 +11,7 @@ obj-$(CONFIG_VIRTIO_CONSOLE) += virtio_console.o + obj-$(CONFIG_MSPEC) += mspec.o + obj-$(CONFIG_UV_MMTIMER) += uv_mmtimer.o + obj-$(CONFIG_IBM_BSR) += bsr.o ++obj-$(CONFIG_ARCH_SUNXI) += sunxi-sysinfo/ + + obj-$(CONFIG_PRINTER) += lp.o + +@@ -45,3 +46,4 @@ obj-$(CONFIG_PS3_FLASH) += ps3flash.o + obj-$(CONFIG_XILLYBUS_CLASS) += xillybus/ + obj-$(CONFIG_POWERNV_OP_PANEL) += powernv-op-panel.o + obj-$(CONFIG_ADI) += adi.o ++obj-$(CONFIG_DUMP_REG) += dump_reg/ +diff --git a/drivers/char/dump_reg/Kconfig b/drivers/char/dump_reg/Kconfig +new file mode 100644 +index 000000000..dbf24c59f +--- /dev/null ++++ b/drivers/char/dump_reg/Kconfig +@@ -0,0 +1,21 @@ ++# ++# dump reg config. ++# ++ ++config DUMP_REG ++ tristate "dump reg driver for sunxi platform" ++ default y ++ help ++ Say y here if you want to support dump regs module. ++ The dump regs module is used to dump regs of any devices ++ if you want it, When in doubt, say "Y". ++ ++config DUMP_REG_MISC ++ tristate "dump reg misc driver" ++ depends on DUMP_REG ++ default y ++ help ++ Add misc driver support, you can use dump regs function ++ via ("/sys/class/...") sysfs interface. ++ When in doubt, say "Y". ++ +diff --git a/drivers/char/dump_reg/Makefile b/drivers/char/dump_reg/Makefile +new file mode 100644 +index 000000000..e953f413b +--- /dev/null ++++ b/drivers/char/dump_reg/Makefile +@@ -0,0 +1,2 @@ ++obj-$(CONFIG_DUMP_REG) += dump_reg.o ++obj-$(CONFIG_DUMP_REG_MISC) += dump_reg_misc.o +diff --git a/drivers/char/dump_reg/dump_reg.c b/drivers/char/dump_reg/dump_reg.c +new file mode 100644 +index 000000000..8c227b08d +--- /dev/null ++++ b/drivers/char/dump_reg/dump_reg.c +@@ -0,0 +1,888 @@ ++/* ++ * dump registers sysfs driver ++ * ++ * Copyright(c) 2015-2018 Allwinnertech Co., Ltd. ++ * http://www.allwinnertech.com ++ * ++ * Author: Liugang ++ * Xiafeng ++ * Martin ++ * Lewis ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "dump_reg.h" ++ ++/* the register and vaule to be test by dump_reg */ ++static u32 test_addr; ++static u32 test_size; ++static struct class *dump_class; ++ ++/* Access in byte mode ? 1: byte-mode, 0: word-mode */ ++static unsigned int rw_byte_mode; ++ ++/* for dump_reg class */ ++static struct dump_addr dump_para; ++static struct write_group *wt_group; ++static struct compare_group *cmp_group; ++ ++static u32 _read(void __iomem *vaddr) ++{ ++ if (rw_byte_mode) ++ return (u32)readb(vaddr); ++ else ++ return readl(vaddr); ++} ++ ++static void _write(u32 val, void __iomem *vaddr) ++{ ++ if (rw_byte_mode) ++ writeb((u8)val, vaddr); ++ else ++ writel(val, vaddr); ++} ++ ++static void __iomem *_io_remap(unsigned long paddr, size_t size) ++{ ++ return ioremap(paddr, size); ++} ++ ++static void _io_unmap(void __iomem *vaddr) ++{ ++ iounmap(vaddr); ++} ++ ++static void __iomem *_mem_remap(unsigned long paddr, size_t size) ++{ ++ return (void __iomem *)phys_to_virt(paddr); ++} ++ ++/* ++ * Convert a physical address (which is already mapped) to virtual address ++ */ ++static void __iomem *_get_vaddr(struct dump_addr *dump_addr, unsigned long uaddr) ++{ ++ unsigned long offset = uaddr - dump_addr->uaddr_start; ++ return (void __iomem *)(dump_addr->vaddr_start + offset); ++} ++ ++const struct dump_struct dump_table[] = { ++ { ++ .addr_start = SUNXI_IO_PHYS_START, ++ .addr_end = SUNXI_IO_PHYS_END, ++ .remap = _io_remap, ++ .unmap = _io_unmap, ++ .get_vaddr = _get_vaddr, ++ .read = _read, ++ .write = _write, ++ }, ++ { ++ .addr_start = SUNXI_PLAT_PHYS_START, ++ .addr_end = SUNXI_PLAT_PHYS_END, ++ .remap = _mem_remap, ++ .unmap = NULL, ++ .get_vaddr = _get_vaddr, ++ .read = _read, ++ .write = _write, ++ }, ++#if defined(SUNXI_IOMEM_START) ++ { ++ .addr_start = SUNXI_IOMEM_START, ++ .addr_end = SUNXI_IOMEM_END, ++ .remap = NULL, /* .remap = NULL: uaddr is a virtual address */ ++ .unmap = NULL, ++ .get_vaddr = _get_vaddr, ++ .read = _read, ++ .write = _write, ++ }, ++#endif ++ { ++ .addr_start = SUNXI_MEM_PHYS_START, ++ .addr_end = SUNXI_MEM_PHYS_END, ++ .remap = NULL, /* .remap = NULL: uaddr is a virtual address */ ++ .unmap = NULL, ++ .get_vaddr = _get_vaddr, ++ .read = _read, ++ .write = _write, ++ }, ++}; ++EXPORT_SYMBOL(dump_table); ++ ++/** ++ * __addr_valid - check if @uaddr is valid. ++ * @uaddr: addr to judge. ++ * ++ * return index if @addr is valid, -ENXIO if not. ++ */ ++int __addr_valid(unsigned long uaddr) ++{ ++ int i; ++ ++ for (i = 0; i < ARRAY_SIZE(dump_table); i++) ++ if (uaddr >= dump_table[i].addr_start && ++ uaddr <= dump_table[i].addr_end) ++ return i; ++ return -ENXIO; ++} ++EXPORT_SYMBOL(__addr_valid); ++ ++/** ++ * __dump_regs_ex - dump a range of registers' value, copy to buf. ++ * @dump_addr: start and end address of registers. ++ * @buf: store the dump info. ++ * @buf_size: buf size ++ * ++ * return bytes written to buf, <=0 indicate err ++ */ ++ssize_t __dump_regs_ex(struct dump_addr *dump_addr, char *buf, ssize_t buf_size) ++{ ++ int index; ++ ssize_t cnt = 0; ++ unsigned long uaddr; ++ unsigned long remap_size; ++ const struct dump_struct *dump; ++ ++ /* Make the address 4-bytes aligned */ ++ dump_addr->uaddr_start &= (~0x3UL); ++ dump_addr->uaddr_end &= (~0x3UL); ++ remap_size = dump_addr->uaddr_end - dump_addr->uaddr_start + 4; ++ ++ index = __addr_valid(dump_addr->uaddr_start); ++ if ((index < 0) || (index != __addr_valid(dump_addr->uaddr_end)) || ++ (buf == NULL)) { ++ pr_err("%s(): Invalid para: index=%d, start=0x%lx, end=0x%lx, buf=0x%p\n", ++ __func__, index, dump_addr->uaddr_start, dump_addr->uaddr_end, buf); ++ return -EIO; ++ } ++ ++ dump = &dump_table[index]; ++ if (dump->remap) { ++ dump_addr->vaddr_start = dump->remap(dump_addr->uaddr_start, remap_size); ++ if (!dump_addr->vaddr_start) { ++ pr_err("%s(): remap failed\n", __func__); ++ return -EIO; ++ } ++ } else /* if (dump->remap = NULL), then treat uaddr as a virtual address */ ++ dump_addr->vaddr_start = (void __iomem *)dump_addr->uaddr_start; ++ ++ if (dump_addr->uaddr_start == dump_addr->uaddr_end) { ++ cnt = sprintf(buf, "0x%08x\n", dump->read(dump_addr->vaddr_start)); ++ goto out; ++ } ++ ++ for (uaddr = (dump_addr->uaddr_start & ~0x0F); uaddr <= dump_addr->uaddr_end; ++ uaddr += 4) { ++ if (!(uaddr & 0x0F)) ++ cnt += snprintf(buf + cnt, buf_size - cnt, ++ "\n" PRINT_ADDR_FMT ":", uaddr); ++ ++ if (cnt >= buf_size) { ++ pr_warn("Range too large, strings buffer overflow\n"); ++ cnt = buf_size; ++ goto out; ++ } ++ ++ if (uaddr < dump_addr->uaddr_start) /* Don't show unused uaddr */ ++ /* "0x12345678 ", 11 space */ ++ cnt += snprintf(buf + cnt, buf_size - cnt, " "); ++ else ++ cnt += snprintf(buf + cnt, buf_size - cnt, " 0x%08x", ++ dump->read(dump->get_vaddr(dump_addr, uaddr))); ++ } ++ cnt += snprintf(buf + cnt, buf_size - cnt, "\n"); ++ ++ pr_debug("%s(): start=0x%lx, end=0x%lx, return=%zd\n", __func__, ++ dump_addr->uaddr_start, dump_addr->uaddr_end, cnt); ++ ++out: ++ if (dump->unmap) ++ dump->unmap(dump_addr->vaddr_start); ++ ++ return cnt; ++} ++EXPORT_SYMBOL(__dump_regs_ex); ++ ++/** ++ * __parse_dump_str - parse the input string for dump attri. ++ * @buf: the input string, eg: "0x01c20000,0x01c20300". ++ * @size: buf size. ++ * @start: store the start reg's addr parsed from buf, eg 0x01c20000. ++ * @end: store the end reg's addr parsed from buf, eg 0x01c20300. ++ * ++ * return 0 if success, otherwise failed. ++ */ ++int __parse_dump_str(const char *buf, size_t size, ++ unsigned long *start, unsigned long *end) ++{ ++ char *ptr = NULL; ++ char *ptr2 = (char *)buf; ++ int ret = 0, times = 0; ++ ++ /* Support single address mode, some time it haven't ',' */ ++next: ++ /* ++ * Default dump only one register(*start =*end). ++ * If ptr is not NULL, we will cover the default value of end. ++ */ ++ if (times == 1) ++ *start = *end; ++ ++ if (!ptr2 || (ptr2 - buf) >= size) ++ goto out; ++ ++ ptr = ptr2; ++ ptr2 = strnchr(ptr, size - (ptr - buf), ','); ++ if (ptr2) { ++ *ptr2 = '\0'; ++ ptr2++; ++ } ++ ++ ptr = strim(ptr); ++ if (!strlen(ptr)) ++ goto next; ++ ++ ret = kstrtoul(ptr, 16, end); ++ if (!ret) { ++ times++; ++ goto next; ++ } else ++ pr_warn("String syntax errors: \"%s\"\n", ptr); ++ ++out: ++ return ret; ++} ++EXPORT_SYMBOL(__parse_dump_str); ++ ++/** ++ * __write_show - dump a register's value, copy to buf. ++ * @pgroup: the addresses to read. ++ * @buf: store the dump info. ++ * ++ * return bytes written to buf, <=0 indicate err. ++ */ ++ssize_t __write_show(struct write_group *pgroup, char *buf, ssize_t len) ++{ ++#define WR_DATA_FMT PRINT_ADDR_FMT" 0x%08x %s" ++ ++ int i = 0; ++ ssize_t cnt = 0; ++ unsigned long reg = 0; ++ u32 val; ++ u8 rval_buf[16]; ++ struct dump_addr dump_addr; ++ ++ if (!pgroup) { ++ pr_err("%s,%d err, pgroup is NULL!\n", __func__, __LINE__); ++ goto end; ++ } ++ ++ cnt += snprintf(buf, len - cnt, WR_PRINT_FMT); ++ if (cnt > len) { ++ cnt = -EINVAL; ++ goto end; ++ } ++ ++ for (i = 0; i < pgroup->num; i++) { ++ reg = pgroup->pitem[i].reg_addr; ++ val = pgroup->pitem[i].val; ++ dump_addr.uaddr_start = reg; ++ dump_addr.uaddr_end = reg; ++ if (__dump_regs_ex(&dump_addr, rval_buf, sizeof(rval_buf)) < 0) ++ return -EINVAL; ++ ++ cnt += ++ snprintf(buf + cnt, len - cnt, WR_DATA_FMT, reg, val, ++ rval_buf); ++ if (cnt > len) { ++ cnt = len; ++ goto end; ++ } ++ } ++ ++end: ++ return cnt; ++} ++EXPORT_SYMBOL(__write_show); ++ ++/** ++ * __parse_write_str - parse the input string for write attri. ++ * @str: string to be parsed, eg: "0x01c20818 0x55555555". ++ * @reg_addr: store the reg address. eg: 0x01c20818. ++ * @val: store the expect value. eg: 0x55555555. ++ * ++ * return 0 if success, otherwise failed. ++ */ ++static int __parse_write_str(char *str, unsigned long *reg_addr, u32 *val) ++{ ++ char *ptr = str; ++ char *tstr = NULL; ++ int ret = 0; ++ ++ /* ++ * Skip the leading whitespace, find the true split symbol. ++ * And it must be 'address value'. ++ */ ++ tstr = strim(str); ++ ptr = strchr(tstr, ' '); ++ if (!ptr) ++ return -EINVAL; ++ ++ /* ++ * Replaced split symbol with a %NUL-terminator temporary. ++ * Will be fixed at end. ++ */ ++ *ptr = '\0'; ++ ret = kstrtoul(tstr, 16, reg_addr); ++ if (ret) ++ goto out; ++ ++ ret = kstrtou32(skip_spaces(ptr + 1), 16, val); ++ ++out: ++ return ret; ++} ++ ++/** ++ * __write_item_init - init for write attri. parse input string, ++ * and construct write struct. ++ * @ppgroup: store the struct allocated, the struct contains items parsed from ++ * input buf. ++ * @buf: input string, eg: "0x01c20800 0x00000031,0x01c20818 0x55555555,...". ++ * @size: buf size. ++ * ++ * return 0 if success, otherwise failed. ++ */ ++int __write_item_init(struct write_group **ppgroup, const char *buf, ++ size_t size) ++{ ++ char *ptr, *ptr2; ++ unsigned long addr = 0; ++ u32 val; ++ struct write_group *pgroup; ++ ++ /* alloc item buffer */ ++ pgroup = kmalloc(sizeof(struct write_group), GFP_KERNEL); ++ if (!pgroup) ++ return -ENOMEM; ++ ++ pgroup->pitem = kmalloc(sizeof(struct write_item) * MAX_WRITE_ITEM, ++ GFP_KERNEL); ++ if (!pgroup->pitem) { ++ kfree(pgroup); ++ return -ENOMEM; ++ } ++ ++ pgroup->num = 0; ++ ptr = (char *)buf; ++ do { ++ ptr2 = strchr(ptr, ','); ++ if (ptr2) ++ *ptr2 = '\0'; ++ ++ if (!__parse_write_str(ptr, &addr, &val)) { ++ pgroup->pitem[pgroup->num].reg_addr = addr; ++ pgroup->pitem[pgroup->num].val = val; ++ pgroup->num++; ++ } else ++ pr_err("%s: Failed to parse string: %s\n", __func__, ++ ptr); ++ ++ if (!ptr2) ++ break; ++ ++ ptr = ptr2 + 1; ++ *ptr2 = ','; ++ ++ } while (pgroup->num <= MAX_WRITE_ITEM); ++ ++ /* free buffer if no valid item */ ++ if (pgroup->num == 0) { ++ kfree(pgroup->pitem); ++ kfree(pgroup); ++ return -EINVAL; ++ } ++ ++ *ppgroup = pgroup; ++ return 0; ++} ++EXPORT_SYMBOL(__write_item_init); ++ ++/** ++ * __write_item_deinit - reled_addrse memory that cred_addrted by ++ * __write_item_init. ++ * @pgroup: the write struct allocated in __write_item_init. ++ */ ++void __write_item_deinit(struct write_group *pgroup) ++{ ++ if (pgroup != NULL) { ++ if (pgroup->pitem != NULL) ++ kfree(pgroup->pitem); ++ kfree(pgroup); ++ } ++} ++EXPORT_SYMBOL(__write_item_deinit); ++ ++/** ++ * __compare_regs_ex - dump a range of registers' value, copy to buf. ++ * @pgroup: addresses of registers. ++ * @buf: store the dump info. ++ * ++ * return bytes written to buf, <= 0 indicate err. ++ */ ++ssize_t __compare_regs_ex(struct compare_group *pgroup, char *buf, ++ ssize_t len) ++{ ++#define CMP_DATAO_FMT PRINT_ADDR_FMT" 0x%08x 0x%08x 0x%08x OK\n" ++#define CMP_DATAE_FMT PRINT_ADDR_FMT" 0x%08x 0x%08x 0x%08x ERR\n" ++ ++ int i; ++ ssize_t cnt = 0; ++ unsigned long reg; ++ u32 expect, actual, mask; ++ u8 actualb[16]; ++ struct dump_addr dump_addr; ++ ++ if (!pgroup) { ++ pr_err("%s,%d err, pgroup is NULL!\n", __func__, __LINE__); ++ goto end; ++ } ++ ++ cnt += snprintf(buf, len - cnt, CMP_PRINT_FMT); ++ if (cnt > len) { ++ cnt = -EINVAL; ++ goto end; ++ } ++ ++ for (i = 0; i < pgroup->num; i++) { ++ reg = pgroup->pitem[i].reg_addr; ++ expect = pgroup->pitem[i].val_expect; ++ dump_addr.uaddr_start = reg; ++ dump_addr.uaddr_end = reg; ++ if (__dump_regs_ex(&dump_addr, actualb, sizeof(actualb)) < 0) ++ return -EINVAL; ++ ++ if (kstrtou32(actualb, 16, &actual)) ++ return -EINVAL; ++ ++ mask = pgroup->pitem[i].val_mask; ++ if ((actual & mask) == (expect & mask)) ++ cnt += ++ snprintf(buf + cnt, len - cnt, CMP_DATAO_FMT, reg, ++ expect, actual, mask); ++ else ++ cnt += ++ snprintf(buf + cnt, len - cnt, CMP_DATAE_FMT, reg, ++ expect, actual, mask); ++ if (cnt > len) { ++ cnt = -EINVAL; ++ goto end; ++ } ++ } ++ ++end: ++ return cnt; ++} ++EXPORT_SYMBOL(__compare_regs_ex); ++ ++/** ++ * __parse_compare_str - parse the input string for compare attri. ++ * @str: string to be parsed, eg: "0x01c20000 0x80000011 0x00000011". ++ * @reg_addr: store the reg address. eg: 0x01c20000. ++ * @val_expect: store the expect value. eg: 0x80000011. ++ * @val_mask: store the mask value. eg: 0x00000011. ++ * ++ * return 0 if success, otherwise failed. ++ */ ++static int __parse_compare_str(char *str, unsigned long *reg_addr, ++ u32 *val_expect, u32 *val_mask) ++{ ++ unsigned long result_addr[3] = { 0 }; ++ char *ptr = str; ++ char *ptr2 = NULL; ++ int i, ret = 0; ++ ++ for (i = 0; i < ARRAY_SIZE(result_addr); i++) { ++ ptr = skip_spaces(ptr); ++ ptr2 = strchr(ptr, ' '); ++ if (ptr2) ++ *ptr2 = '\0'; ++ ++ ret = kstrtoul(ptr, 16, &result_addr[i]); ++ if (!ptr2) ++ break; ++ ++ *ptr2 = ' '; ++ ++ if (ret) ++ break; ++ ++ ptr = ptr2 + 1; ++ } ++ ++ *reg_addr = result_addr[0]; ++ *val_expect = (u32) result_addr[1]; ++ *val_mask = (u32) result_addr[2]; ++ ++ return ret; ++} ++ ++/** ++ * __compare_item_init - init for compare attri. parse input string, ++ * and construct compare struct. ++ * @ppgroup: store the struct allocated, the struct contains items parsed from ++ * input buf. ++ * @buf: input string, ++ * eg: "0x01c20000 0x80000011 0x00000011,0x01c20004 0x0000c0a4 0x0000c0a0,...". ++ * @size: buf size. ++ * ++ * return 0 if success, otherwise failed. ++ */ ++int __compare_item_init(struct compare_group **ppgroup, ++ const char *buf, size_t size) ++{ ++ char *ptr, *ptr2; ++ unsigned long addr = 0; ++ u32 val_expect = 0, val_mask = 0; ++ struct compare_group *pgroup = NULL; ++ ++ /* alloc item buffer */ ++ pgroup = kmalloc(sizeof(struct compare_group), GFP_KERNEL); ++ if (pgroup == NULL) ++ return -EINVAL; ++ ++ pgroup->pitem = kmalloc(sizeof(struct compare_item) * MAX_COMPARE_ITEM, ++ GFP_KERNEL); ++ if (pgroup->pitem == NULL) { ++ kfree(pgroup); ++ return -EINVAL; ++ } ++ ++ pgroup->num = 0; ++ ++ /* get item from buf */ ++ ptr = (char *)buf; ++ do { ++ ptr2 = strchr(ptr, ','); ++ if (ptr2) ++ *ptr2 = '\0'; ++ ++ if (!__parse_compare_str(ptr, &addr, &val_expect, &val_mask)) { ++ pgroup->pitem[pgroup->num].reg_addr = addr; ++ pgroup->pitem[pgroup->num].val_expect = val_expect; ++ pgroup->pitem[pgroup->num].val_mask = val_mask; ++ pgroup->num++; ++ } else ++ pr_err("%s: Failed to parse string: %s\n", __func__, ++ ptr); ++ ++ if (!ptr2) ++ break; ++ ++ *ptr2 = ','; ++ ptr = ptr2 + 1; ++ ++ } while (pgroup->num <= MAX_COMPARE_ITEM); ++ ++ /* free buffer if no valid item */ ++ if (pgroup->num == 0) { ++ kfree(pgroup->pitem); ++ kfree(pgroup); ++ return -EINVAL; ++ } ++ *ppgroup = pgroup; ++ ++ return 0; ++} ++EXPORT_SYMBOL(__compare_item_init); ++ ++/** ++ * __compare_item_deinit - reled_addrse memory that cred_addrted by ++ * __compare_item_init. ++ * @pgroup: the compare struct allocated in __compare_item_init. ++ */ ++void __compare_item_deinit(struct compare_group *pgroup) ++{ ++ if (pgroup) { ++ kfree(pgroup->pitem); ++ kfree(pgroup); ++ } ++} ++EXPORT_SYMBOL(__compare_item_deinit); ++ ++/** ++ * dump_show - show func of dump attribute. ++ * @dev: class ptr. ++ * @attr: attribute ptr. ++ * @buf: the input buf which contain the start and end reg. ++ * eg: "0x01c20000,0x01c20100\n". ++ * ++ * return size written to the buf, otherwise failed. ++ */ ++static ssize_t ++dump_show(const struct class *class, const struct class_attribute *attr, char *buf) ++{ ++ return __dump_regs_ex(&dump_para, buf, PAGE_SIZE); ++} ++ ++static ssize_t ++dump_store(const struct class *class, const struct class_attribute *attr, ++ const char *buf, size_t count) ++{ ++ int index; ++ unsigned long start_reg = 0; ++ unsigned long end_reg = 0; ++ ++ if (__parse_dump_str(buf, count, &start_reg, &end_reg)) { ++ pr_err("%s,%d err, invalid para!\n", __func__, __LINE__); ++ goto err; ++ } ++ ++ index = __addr_valid(start_reg); ++ if ((index < 0) || (index != __addr_valid(end_reg))) { ++ pr_err("%s,%d err, invalid para!\n", __func__, __LINE__); ++ goto err; ++ } ++ ++ dump_para.uaddr_start = start_reg; ++ dump_para.uaddr_end = end_reg; ++ pr_debug("%s,%d, start_reg:" PRINT_ADDR_FMT ", end_reg:" PRINT_ADDR_FMT ++ "\n", __func__, __LINE__, start_reg, end_reg); ++ ++ return count; ++ ++err: ++ dump_para.uaddr_start = 0; ++ dump_para.uaddr_end = 0; ++ ++ return -EINVAL; ++} ++ ++static ssize_t ++write_show(const struct class *class, const struct class_attribute *attr, char *buf) ++{ ++ /* display write result */ ++ return __write_show(wt_group, buf, PAGE_SIZE); ++} ++ ++static ssize_t ++write_store(const struct class *class, const struct class_attribute *attr, ++ const char *buf, size_t count) ++{ ++ int i; ++ int index; ++ unsigned long reg; ++ u32 val; ++ const struct dump_struct *dump; ++ struct dump_addr dump_addr; ++ ++ /* free if not NULL */ ++ if (wt_group) { ++ __write_item_deinit(wt_group); ++ wt_group = NULL; ++ } ++ ++ /* parse input buf for items that will be dumped */ ++ if (__write_item_init(&wt_group, buf, count) < 0) ++ return -EINVAL; ++ ++ /** ++ * write reg ++ * it is better if the regs been remaped and unmaped only once, ++ * but we map everytime for the range between min and max address ++ * maybe too large. ++ */ ++ for (i = 0; i < wt_group->num; i++) { ++ reg = wt_group->pitem[i].reg_addr; ++ dump_addr.uaddr_start = reg; ++ val = wt_group->pitem[i].val; ++ index = __addr_valid(reg); ++ dump = &dump_table[index]; ++ if (dump->remap) ++ dump_addr.vaddr_start = dump->remap(reg, 4); ++ else ++ dump_addr.vaddr_start = (void __iomem *)reg; ++ dump->write(val, dump->get_vaddr(&dump_addr, reg)); ++ if (dump->unmap) ++ dump->unmap(dump_addr.vaddr_start); ++ } ++ ++ return count; ++} ++ ++static ssize_t ++compare_show(const struct class *class, const struct class_attribute *attr, char *buf) ++{ ++ /* dump the items */ ++ return __compare_regs_ex(cmp_group, buf, PAGE_SIZE); ++} ++ ++static ssize_t ++compare_store(const struct class *class, const struct class_attribute *attr, ++ const char *buf, size_t count) ++{ ++ /* free if struct not null */ ++ if (cmp_group) { ++ __compare_item_deinit(cmp_group); ++ cmp_group = NULL; ++ } ++ ++ /* parse input buf for items that will be dumped */ ++ if (__compare_item_init(&cmp_group, buf, count) < 0) ++ return -EINVAL; ++ ++ return count; ++} ++ ++static ssize_t ++rw_byte_show(const struct class *class, const struct class_attribute *attr, char *buf) ++{ ++ return sprintf(buf, "read/write mode: %u(%s)\n", rw_byte_mode, ++ rw_byte_mode ? "byte" : "word"); ++} ++ ++static ssize_t ++rw_byte_store(const struct class *class, const struct class_attribute *attr, ++ const char *buf, size_t count) ++{ ++ unsigned long value; ++ int ret; ++ ++ ret = kstrtoul(buf, 10, &value); ++ if (!ret && (value > 1)) { ++ pr_err("%s,%d err, invalid para!\n", __func__, __LINE__); ++ goto out; ++ } ++ rw_byte_mode = value; ++out: ++ return count; ++} ++ ++static ssize_t ++test_show(const struct class *class, const struct class_attribute *attr, char *buf) ++{ ++ return sprintf(buf, "addr:0x%08x\nsize:0x%08x\n", test_addr, test_size); ++} ++ ++static ssize_t ++help_show(const struct class *class, const struct class_attribute *attr, char *buf) ++{ ++ const char *info = ++ "dump single register: echo {addr} > dump; cat dump\n" ++ "dump multi registers: echo {start-addr},{end-addr} > dump; cat dump\n" ++ "write single register: echo {addr} {val} > write; cat write\n" ++ "write multi registers: echo {addr1} {val1},{addr2} {val2},... > write; cat write\n" ++ "compare single register: echo {addr} {expect-val} {mask} > compare; cat compare\n" ++ "compare multi registers: echo {addr1} {expect-val1} {mask1},{addr2} {expect-val2} {mask2},... > compare; cat compare\n" ++ "byte-access mode: echo 1 > rw_byte\n" ++ "word-access mode (default): echo 0 > rw_byte\n" ++ "show test address info: cat test\n"; ++ return sprintf(buf, info); ++} ++ ++static struct class_attribute dump_class_attrs[] = { ++ __ATTR(dump, S_IWUSR | S_IRUGO, dump_show, dump_store), ++ __ATTR(write, S_IWUSR | S_IRUGO, write_show, write_store), ++ __ATTR(compare, S_IWUSR | S_IRUGO, compare_show, compare_store), ++ __ATTR(rw_byte, S_IWUSR | S_IRUGO, rw_byte_show, rw_byte_store), ++ __ATTR(test, S_IRUGO, test_show, NULL), ++ __ATTR(help, S_IRUGO, help_show, NULL), ++}; ++ ++static const struct of_device_id sunxi_dump_reg_match[] = { ++ {.compatible = "allwinner,sunxi-dump-reg", }, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, sunxi_dump_reg_match); ++ ++static int sunxi_dump_reg_probe(struct platform_device *pdev) ++{ ++ struct resource *res; ++ struct device *dev = &pdev->dev; ++ ++ int err; ++ int i; ++ ++ /* sys/class/sunxi_dump */ ++ dump_class = class_create("sunxi_dump"); ++ if (IS_ERR(dump_class)) { ++ pr_err("%s:%u class_create() failed\n", __func__, __LINE__); ++ return PTR_ERR(dump_class); ++ } ++ ++ /* sys/class/sunxi_dump/xxx */ ++ for (i = 0; i < ARRAY_SIZE(dump_class_attrs); i++) { ++ err = class_create_file(dump_class, &dump_class_attrs[i]); ++ if (err) { ++ pr_err("%s:%u class_create_file() failed. err=%d\n", __func__, __LINE__, err); ++ while (i--) { ++ class_remove_file(dump_class, &dump_class_attrs[i]); ++ } ++ class_destroy(dump_class); ++ dump_class = NULL; ++ return err; ++ } ++ } ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (!res) { ++ dev_err(dev, "Fail to get IORESOURCE_MEM \n"); ++ goto error; ++ } ++ ++ test_addr = res->start; ++ test_size = resource_size(res); ++ ++ return 0; ++error: ++ dev_err(dev, "sunxi_dump_reg probe error\n"); ++ return -1; ++} ++ ++static int sunxi_dump_reg_remove(struct platform_device *pdev) ++{ ++ int i; ++ ++ for (i = 0; i < ARRAY_SIZE(dump_class_attrs); i++) { ++ class_remove_file(dump_class, &dump_class_attrs[i]); ++ } ++ ++ class_destroy(dump_class); ++ return 0; ++} ++ ++static struct platform_driver sunxi_dump_reg_driver = { ++ .probe = sunxi_dump_reg_probe, ++ .remove = sunxi_dump_reg_remove, ++ .driver = { ++ .name = "dump_reg", ++ .owner = THIS_MODULE, ++ .of_match_table = sunxi_dump_reg_match, ++ }, ++}; ++ ++module_platform_driver(sunxi_dump_reg_driver); ++ ++MODULE_ALIAS("dump reg driver"); ++MODULE_ALIAS("platform:dump reg"); ++MODULE_LICENSE("GPL v2"); ++MODULE_VERSION("1.0.3"); ++MODULE_AUTHOR("xiafeng "); ++MODULE_AUTHOR("Martin "); ++MODULE_AUTHOR("liuyu "); ++MODULE_DESCRIPTION("dump registers driver"); +diff --git a/drivers/char/dump_reg/dump_reg.h b/drivers/char/dump_reg/dump_reg.h +new file mode 100644 +index 000000000..85af5c96e +--- /dev/null ++++ b/drivers/char/dump_reg/dump_reg.h +@@ -0,0 +1,132 @@ ++/* ++ * dump registers head file ++ * ++ * (C) Copyright 2015-2018 ++ * Reuuimlla Technology Co., Ltd. ++ * Liugang ++ * Xiafeng ++ * Martin ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ */ ++#ifndef _DUMP_REG_H_ ++#define _DUMP_REG_H_ ++ ++/* BROM/SRAM/peripheral-registers space */ ++#define SUNXI_IO_PHYS_START (0x01000000UL) ++#define SUNXI_IO_PHYS_END (SUNXI_IO_PHYS_START + SZ_128M + SZ_16M -1) ++ ++/* DRAM space (Only map the first 1GB) */ ++#define SUNXI_PLAT_PHYS_START (0x40000000UL) ++#define SUNXI_PLAT_PHYS_END (SUNXI_PLAT_PHYS_START + SZ_1G - 1) ++ ++#if IS_ENABLED(CONFIG_ARM64) ++/* Virtual address space 1 */ ++#define SUNXI_IOMEM_START (0xffffff8000000000UL) ++#define SUNXI_IOMEM_END (SUNXI_IOMEM_START + SZ_2G) ++/* Virtual address space 2 */ ++#define SUNXI_MEM_PHYS_START (0xffffffc000000000UL) ++#define SUNXI_MEM_PHYS_END (SUNXI_MEM_PHYS_START + SZ_2G) ++/* Print format */ ++#define PRINT_ADDR_FMT "0x%016lx" ++#define CMP_PRINT_FMT "reg expect actual mask result\n" ++#define WR_PRINT_FMT "reg to_write after_write\n" ++#else ++/* Virtual address space 2 */ ++#define SUNXI_MEM_PHYS_START PAGE_OFFSET ++#define SUNXI_MEM_PHYS_END (SUNXI_MEM_PHYS_START + SZ_1G - 1) ++/* Print format */ ++#define PRINT_ADDR_FMT "0x%08lx" ++#define CMP_PRINT_FMT "reg expect actual mask result\n" ++#define WR_PRINT_FMT "reg to_write after_write\n" ++#endif ++ ++/* Item count */ ++#define MAX_COMPARE_ITEM 64 ++#define MAX_WRITE_ITEM 64 ++ ++struct dump_addr { ++ /* User specified address. Maybe physical or virtual address */ ++ unsigned long uaddr_start; ++ unsigned long uaddr_end; ++ /* Virtual address */ ++ void __iomem *vaddr_start; ++}; ++ ++struct dump_struct { ++ unsigned long addr_start; ++ unsigned long addr_end; ++ /* some registers' operate method maybe different */ ++ void __iomem *(*remap)(unsigned long paddr, size_t size); ++ void (*unmap)(void __iomem *vaddr); ++ void __iomem *(*get_vaddr)(struct dump_addr *dump_addr, unsigned long uaddr); ++ u32 (*read)(void __iomem *vaddr); ++ void (*write)(u32 val, void __iomem *vaddr); ++}; ++ ++/** ++ * compare_item - reg compare item struct ++ * @reg_addr: reg address. ++ * @val_expect: expected value, provided by caller. ++ * @val_mask: mask value, provided by caller. only mask bits will be compared. ++ */ ++struct compare_item { ++ unsigned long reg_addr; ++ u32 val_expect; ++ u32 val_mask; ++}; ++ ++/** ++ * compare_group - reg compare group struct ++ * @num: pitem element count. cannot exceed MAX_COMPARE_ITEM. ++ * @pitem: items that will be compared, provided by caller. ++ */ ++struct compare_group { ++ u32 num; ++ u32 reserve; ++ struct compare_item *pitem; ++}; ++ ++/** ++ * write_item - reg write item struct ++ * @reg_addr: reg address. ++ * @val: value to write ++ */ ++struct write_item { ++ unsigned long reg_addr; ++ u32 val; ++ u32 reserve; ++}; ++ ++/** ++ * write_group - reg write group struct ++ * @num: pitem element count. cannot exceed MAX_WRITE_ITEM. ++ * @pitem: items that will be write, provided by caller. ++ */ ++struct write_group { ++ u32 num; ++ u32 reserve; ++ struct write_item *pitem; ++}; ++ ++extern const struct dump_struct dump_table[4]; ++ ++int __addr_valid(unsigned long addr); ++ssize_t __dump_regs_ex(struct dump_addr *reg, char *buf, ssize_t len); ++int __parse_dump_str(const char *buf, size_t size, ++ unsigned long *start, unsigned long *end); ++ssize_t __write_show(struct write_group *pgroup, char *buf, ssize_t len); ++int __write_item_init(struct write_group **ppgroup, const char *buf, ++ size_t size); ++void __write_item_deinit(struct write_group *pgroup); ++ssize_t __compare_regs_ex(struct compare_group *pgroup, char *buf, ++ ssize_t len); ++int __compare_item_init(struct compare_group **ppgroup, ++ const char *buf, size_t size); ++void __compare_item_deinit(struct compare_group *pgroup); ++ ++#endif /* _DUMP_REG_H_ */ +diff --git a/drivers/char/dump_reg/dump_reg_misc.c b/drivers/char/dump_reg/dump_reg_misc.c +new file mode 100644 +index 000000000..238ddd147 +--- /dev/null ++++ b/drivers/char/dump_reg/dump_reg_misc.c +@@ -0,0 +1,209 @@ ++/* ++ * misc dump registers driver - ++ * User space application could use dump-reg functions through file operations ++ * (open/read/write/close) to the sysfs node created by this driver. ++ * ++ * Copyright(c) 2015-2018 Allwinnertech Co., Ltd. ++ * http://www.allwinnertech.com ++ * ++ * Author: Liugang ++ * Xiafeng ++ * Martin ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "dump_reg.h" ++ ++/* for dump_reg misc driver */ ++static struct dump_addr misc_dump_para; ++static struct write_group *misc_wt_group; ++static struct compare_group *misc_cmp_group; ++ ++static ssize_t ++misc_dump_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ return __dump_regs_ex(&misc_dump_para, buf, PAGE_SIZE); ++} ++ ++static ssize_t ++misc_dump_store(struct device *dev, struct device_attribute *attr, ++ const char *buf, size_t size) ++{ ++ int index; ++ unsigned long start_reg = 0; ++ unsigned long end_reg = 0; ++ ++ if (__parse_dump_str(buf, size, &start_reg, &end_reg)) { ++ pr_err("%s,%d err, invalid para!\n", __func__, __LINE__); ++ goto err; ++ } ++ ++ index = __addr_valid(start_reg); ++ if ((index < 0) || (index != __addr_valid(end_reg))) { ++ pr_err("%s,%d err, invalid para!\n", __func__, __LINE__); ++ goto err; ++ } ++ ++ misc_dump_para.uaddr_start = start_reg; ++ misc_dump_para.uaddr_end = end_reg; ++ pr_debug("%s,%d, start_reg:" PRINT_ADDR_FMT ", end_reg:" PRINT_ADDR_FMT ++ "\n", __func__, __LINE__, start_reg, end_reg); ++ ++ return size; ++ ++err: ++ misc_dump_para.uaddr_start = 0; ++ misc_dump_para.uaddr_end = 0; ++ ++ return -EINVAL; ++} ++ ++static ssize_t ++misc_write_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ /* display write result */ ++ return __write_show(misc_wt_group, buf, PAGE_SIZE); ++} ++ ++static ssize_t ++misc_write_store(struct device *dev, struct device_attribute *attr, ++ const char *buf, size_t size) ++{ ++ int i; ++ int index; ++ unsigned long reg; ++ u32 val; ++ const struct dump_struct *dump; ++ struct dump_addr dump_addr; ++ ++ /* free if not NULL */ ++ if (misc_wt_group) { ++ __write_item_deinit(misc_wt_group); ++ misc_wt_group = NULL; ++ } ++ ++ /* parse input buf for items that will be dumped */ ++ if (__write_item_init(&misc_wt_group, buf, size) < 0) ++ return -EINVAL; ++ ++ /** ++ * write reg ++ * it is better if the regs been remaped and unmaped only once, ++ * but we map everytime for the range between min and max address ++ * maybe too large. ++ */ ++ for (i = 0; i < misc_wt_group->num; i++) { ++ reg = misc_wt_group->pitem[i].reg_addr; ++ dump_addr.uaddr_start = reg; ++ val = misc_wt_group->pitem[i].val; ++ index = __addr_valid(reg); ++ dump = &dump_table[index]; ++ if (dump->remap) ++ dump_addr.vaddr_start = dump->remap(reg, 4); ++ else ++ dump_addr.vaddr_start = (void __iomem *)reg; ++ dump->write(val, dump->get_vaddr(&dump_addr, reg)); ++ if (dump->unmap) ++ dump->unmap(dump_addr.vaddr_start); ++ } ++ ++ return size; ++} ++ ++static ssize_t ++misc_compare_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ /* dump the items */ ++ return __compare_regs_ex(misc_cmp_group, buf, PAGE_SIZE); ++} ++ ++static ssize_t ++misc_compare_store(struct device *dev, struct device_attribute *attr, ++ const char *buf, size_t size) ++{ ++ /* free if struct not null */ ++ if (misc_cmp_group) { ++ __compare_item_deinit(misc_cmp_group); ++ misc_cmp_group = NULL; ++ } ++ ++ /* parse input buf for items that will be dumped */ ++ if (__compare_item_init(&misc_cmp_group, buf, size) < 0) ++ return -EINVAL; ++ ++ return size; ++} ++ ++static DEVICE_ATTR(dump, S_IWUSR | S_IRUGO, misc_dump_show, misc_dump_store); ++static DEVICE_ATTR(write, S_IWUSR | S_IRUGO, misc_write_show, misc_write_store); ++static DEVICE_ATTR(compare, S_IWUSR | S_IRUGO, misc_compare_show, ++ misc_compare_store); ++ ++static struct attribute *misc_attributes[] = { /* files under '/sys/devices/virtual/misc/sunxi-reg/rw/' */ ++ &dev_attr_dump.attr, ++ &dev_attr_write.attr, ++ &dev_attr_compare.attr, ++ NULL, ++}; ++ ++static struct attribute_group misc_attribute_group = { ++ .name = "rw", /* directory: '/sys/devices/virtual/misc/sunxi-reg/rw/' */ ++ .attrs = misc_attributes, ++}; ++ ++static struct miscdevice dump_reg_dev = { ++ .minor = MISC_DYNAMIC_MINOR, ++ .name = "sunxi-reg", /* device node: '/dev/sunxi-reg' */ ++}; ++ ++static int __init misc_dump_reg_init(void) ++{ ++ int err; ++ ++ pr_info("misc dump reg init\n"); ++ err = misc_register(&dump_reg_dev); ++ if (err) { ++ pr_err("dump register driver as misc device error!\n"); ++ goto exit; ++ } ++ ++ err = sysfs_create_group(&dump_reg_dev.this_device->kobj, ++ &misc_attribute_group); ++ if (err) ++ pr_err("dump register sysfs create group failed!\n"); ++ ++exit: ++ return err; ++} ++ ++static void __exit misc_dump_reg_exit(void) ++{ ++ pr_info("misc dump reg exit\n"); ++ ++ sysfs_remove_group(&(dump_reg_dev.this_device->kobj), ++ &misc_attribute_group); ++ misc_deregister(&dump_reg_dev); ++} ++ ++module_init(misc_dump_reg_init); ++module_exit(misc_dump_reg_exit); ++ ++MODULE_ALIAS("misc dump reg driver"); ++MODULE_LICENSE("GPL v2"); ++MODULE_VERSION("1.0.1"); ++MODULE_AUTHOR("xiafeng "); ++MODULE_DESCRIPTION("misc dump registers driver"); +diff --git a/drivers/char/sunxi-sysinfo/Kconfig b/drivers/char/sunxi-sysinfo/Kconfig +new file mode 100644 +index 000000000..9b6e2f06d +--- /dev/null ++++ b/drivers/char/sunxi-sysinfo/Kconfig +@@ -0,0 +1,10 @@ ++# ++# sunxi system information driver. ++# ++ ++config SUNXI_SYS_INFO ++ tristate "sunxi system info driver" ++ default y ++ help ++ This driver is used for query system information. ++ If you don't know whether need it, please select y. +diff --git a/drivers/char/sunxi-sysinfo/Makefile b/drivers/char/sunxi-sysinfo/Makefile +new file mode 100644 +index 000000000..188696592 +--- /dev/null ++++ b/drivers/char/sunxi-sysinfo/Makefile +@@ -0,0 +1,5 @@ ++# ++# Makefile for sunxi system information driver ++# ++ ++obj-$(CONFIG_SUNXI_SYS_INFO) += sunxi-sysinfo.o +diff --git a/drivers/char/sunxi-sysinfo/sunxi-sysinfo.c b/drivers/char/sunxi-sysinfo/sunxi-sysinfo.c +new file mode 100644 +index 000000000..349b92bf1 +--- /dev/null ++++ b/drivers/char/sunxi-sysinfo/sunxi-sysinfo.c +@@ -0,0 +1,177 @@ ++/* ++ * Based on drivers/char/sunxi-sysinfo/sunxi-sysinfo.c ++ * ++ * Copyright (C) 2015 Allwinnertech Ltd. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program. If not, see . ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++extern int sunxi_get_soc_chipid(unsigned char *chipid); ++extern int sunxi_get_serial(unsigned char *serial); ++ ++struct sunxi_info_quirks { ++ char * platform_name; ++}; ++ ++static const struct sunxi_info_quirks sun5i_h6_info_quirks = { ++ .platform_name = "sun50i-h6", ++}; ++ ++static const struct sunxi_info_quirks sun5i_h616_info_quirks = { ++ .platform_name = "sun50i-h616", ++}; ++ ++struct sunxi_info_quirks *quirks; ++ ++static int soc_info_open(struct inode *inode, struct file *file) ++{ ++ return 0; ++} ++ ++static int soc_info_release(struct inode *inode, struct file *file) ++{ ++ return 0; ++} ++ ++static const struct file_operations soc_info_ops = { ++ .owner = THIS_MODULE, ++ .open = soc_info_open, ++ .release = soc_info_release, ++}; ++ ++struct miscdevice soc_info_device = { ++ .minor = MISC_DYNAMIC_MINOR, ++ .name = "sunxi_soc_info", ++ .fops = &soc_info_ops, ++}; ++ ++static ssize_t sys_info_show(const struct class *class, ++ const struct class_attribute *attr, char *buf) ++{ ++ int i; ++ int databuf[4] = {0}; ++ char tmpbuf[129] = {0}; ++ size_t size = 0; ++ ++ /* platform */ ++ size += sprintf(buf + size, "sunxi_platform : %s\n", quirks->platform_name); ++ ++ /* chipid */ ++ sunxi_get_soc_chipid((u8 *)databuf); ++ ++ for (i = 0; i < 4; i++) ++ sprintf(tmpbuf + i*8, "%08x", databuf[i]); ++ tmpbuf[128] = 0; ++ size += sprintf(buf + size, "sunxi_chipid : %s\n", tmpbuf); ++ ++ /* serial */ ++ sunxi_get_serial((u8 *)databuf); ++ for (i = 0; i < 4; i++) ++ sprintf(tmpbuf + i*8, "%08x", databuf[i]); ++ tmpbuf[128] = 0; ++ size += sprintf(buf + size, "sunxi_serial : %s\n", tmpbuf); ++ ++ return size; ++} ++ ++static struct class_attribute info_class_attrs[] = { ++ __ATTR(sys_info, 0644, sys_info_show, NULL), ++}; ++ ++static struct class info_class = { ++ .name = "sunxi_info", ++}; ++ ++static const struct of_device_id sunxi_info_match[] = { ++ { ++ .compatible = "allwinner,sun50i-h6-sys-info", ++ .data = &sun5i_h6_info_quirks, ++ }, ++ { ++ .compatible = "allwinner,sun50i-h616-sys-info", ++ .data = &sun5i_h616_info_quirks, ++ }, ++ {} ++}; ++ ++static int sunxi_info_probe(struct platform_device *pdev) ++{ ++ int i, ret = 0; ++ ++ quirks = of_device_get_match_data(&pdev->dev); ++ if (quirks == NULL) { ++ dev_err(&pdev->dev, "Failed to determine the quirks to use\n"); ++ return -ENODEV; ++ } ++ ++ ret = class_register(&info_class); ++ if (ret != 0) ++ return ret; ++ ++ /* need some class specific sysfs attributes */ ++ for (i = 0; i < ARRAY_SIZE(info_class_attrs); i++) { ++ ret = class_create_file(&info_class, &info_class_attrs[i]); ++ if (ret) ++ goto out_class_create_file_failed; ++ } ++ ++ ret = misc_register(&soc_info_device); ++ if (ret != 0) { ++ pr_err("%s: misc_register() failed!(%d)\n", __func__, ret); ++ class_unregister(&info_class); ++ return ret; ++ } ++ ++ return ret; ++ ++out_class_create_file_failed: ++ class_unregister(&info_class); ++ ++ return ret; ++} ++ ++static int sunxi_info_remove(struct platform_device *pdev) ++{ ++ misc_deregister(&soc_info_device); ++ class_unregister(&info_class); ++ ++ return 0; ++} ++ ++static struct platform_driver sunxi_info_driver = { ++ .probe = sunxi_info_probe, ++ .remove = sunxi_info_remove, ++ .driver = { ++ .name = "sunxi_info", ++ .owner = THIS_MODULE, ++ .of_match_table = sunxi_info_match, ++ }, ++}; ++module_platform_driver(sunxi_info_driver); ++ ++MODULE_LICENSE("GPL v2"); ++MODULE_AUTHOR("xiafeng"); ++MODULE_DESCRIPTION("sunxi sys info."); +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/Add-sunxi-addr-driver-Used-to-fix-uwe5622-bluetooth-MAC-address.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/Add-sunxi-addr-driver-Used-to-fix-uwe5622-bluetooth-MAC-address.patch new file mode 100644 index 0000000000..3a977bd25d --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/Add-sunxi-addr-driver-Used-to-fix-uwe5622-bluetooth-MAC-address.patch @@ -0,0 +1,611 @@ +From 04b13d9bc720de2ed1a18202cbc80078769fd11d Mon Sep 17 00:00:00 2001 +From: afaulkner420 +Date: Fri, 25 Mar 2022 20:18:18 +0000 +Subject: [PATCH] Add sunxi-addr driver - Used to fix uwe5622 bluetooth MAC + addresses + +--- + drivers/misc/Kconfig | 1 + + drivers/misc/Makefile | 1 + + drivers/misc/sunxi-addr/Kconfig | 6 + + drivers/misc/sunxi-addr/Makefile | 5 + + drivers/misc/sunxi-addr/sha256.c | 178 +++++++++++++ + drivers/misc/sunxi-addr/sunxi-addr.c | 357 +++++++++++++++++++++++++++ + 6 files changed, 548 insertions(+) + create mode 100644 drivers/misc/sunxi-addr/Kconfig + create mode 100644 drivers/misc/sunxi-addr/Makefile + create mode 100644 drivers/misc/sunxi-addr/sha256.c + create mode 100644 drivers/misc/sunxi-addr/sunxi-addr.c + +diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig +index 45b005f50..2bbf4483d 100644 +--- a/drivers/misc/Kconfig ++++ b/drivers/misc/Kconfig +@@ -569,4 +569,5 @@ source "drivers/misc/cardreader/Kconfig" + source "drivers/misc/uacce/Kconfig" + source "drivers/misc/pvpanic/Kconfig" + source "drivers/misc/mchp_pci1xxxx/Kconfig" ++source "drivers/misc/sunxi-addr/Kconfig" + endmenu +diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile +index d342afc4d..695fb7af8 100644 +--- a/drivers/misc/Makefile ++++ b/drivers/misc/Makefile +@@ -67,3 +67,4 @@ obj-$(CONFIG_VCPU_STALL_DETECTOR) += vcpu_stall_detector.o + obj-$(CONFIG_TMR_MANAGER) += xilinx_tmr_manager.o + obj-$(CONFIG_TMR_INJECT) += xilinx_tmr_inject.o + obj-$(CONFIG_MODEM_POWER) += modem-power.o ++obj-$(CONFIG_SUNXI_ADDR_MGT) += sunxi-addr/ +diff --git a/drivers/misc/sunxi-addr/Kconfig b/drivers/misc/sunxi-addr/Kconfig +new file mode 100644 +index 000000000..801dd2c02 +--- /dev/null ++++ b/drivers/misc/sunxi-addr/Kconfig +@@ -0,0 +1,6 @@ ++config SUNXI_ADDR_MGT ++ tristate "Allwinner Network MAC Addess Manager" ++ depends on BT || ETHERNET || WLAN ++ depends on NVMEM_SUNXI_SID ++ help ++ allwinner network mac address management +diff --git a/drivers/misc/sunxi-addr/Makefile b/drivers/misc/sunxi-addr/Makefile +new file mode 100644 +index 000000000..f01fd4783 +--- /dev/null ++++ b/drivers/misc/sunxi-addr/Makefile +@@ -0,0 +1,5 @@ ++# ++# Makefile for wifi mac addr manager drivers ++# ++sunxi_addr-objs := sunxi-addr.o sha256.o ++obj-$(CONFIG_SUNXI_ADDR_MGT) += sunxi_addr.o +diff --git a/drivers/misc/sunxi-addr/sha256.c b/drivers/misc/sunxi-addr/sha256.c +new file mode 100644 +index 000000000..78825810c +--- /dev/null ++++ b/drivers/misc/sunxi-addr/sha256.c +@@ -0,0 +1,178 @@ ++/* ++ * Local implement of sha256. ++ * ++ * Copyright (C) 2013 Allwinner. ++ * ++ * This file is licensed under the terms of the GNU General Public ++ * License version 2. This program is licensed "as is" without any ++ * warranty of any kind, whether express or implied. ++ */ ++#include ++#include ++ ++/****************************** MACROS ******************************/ ++#define ROTRIGHT(a, b) (((a) >> (b)) | ((a) << (32 - (b)))) ++#define CH(x, y, z) (((x) & (y)) ^ (~(x) & (z))) ++#define MAJ(x, y, z) (((x) & (y)) ^ ((x) & (z)) ^ ((y) & (z))) ++#define EP0(x) (ROTRIGHT(x, 2) ^ ROTRIGHT(x, 13) ^ ROTRIGHT(x, 22)) ++#define EP1(x) (ROTRIGHT(x, 6) ^ ROTRIGHT(x, 11) ^ ROTRIGHT(x, 25)) ++#define SIG0(x) (ROTRIGHT(x, 7) ^ ROTRIGHT(x, 18) ^ ((x) >> 3)) ++#define SIG1(x) (ROTRIGHT(x, 17) ^ ROTRIGHT(x, 19) ^ ((x) >> 10)) ++ ++/**************************** VARIABLES *****************************/ ++static const uint32_t k[64] = { ++ 0x428a2f98, 0x71374491, 0xb5c0fbcf, 0xe9b5dba5, ++ 0x3956c25b, 0x59f111f1, 0x923f82a4, 0xab1c5ed5, ++ 0xd807aa98, 0x12835b01, 0x243185be, 0x550c7dc3, ++ 0x72be5d74, 0x80deb1fe, 0x9bdc06a7, 0xc19bf174, ++ 0xe49b69c1, 0xefbe4786, 0x0fc19dc6, 0x240ca1cc, ++ 0x2de92c6f, 0x4a7484aa, 0x5cb0a9dc, 0x76f988da, ++ 0x983e5152, 0xa831c66d, 0xb00327c8, 0xbf597fc7, ++ 0xc6e00bf3, 0xd5a79147, 0x06ca6351, 0x14292967, ++ 0x27b70a85, 0x2e1b2138, 0x4d2c6dfc, 0x53380d13, ++ 0x650a7354, 0x766a0abb, 0x81c2c92e, 0x92722c85, ++ 0xa2bfe8a1, 0xa81a664b, 0xc24b8b70, 0xc76c51a3, ++ 0xd192e819, 0xd6990624, 0xf40e3585, 0x106aa070, ++ 0x19a4c116, 0x1e376c08, 0x2748774c, 0x34b0bcb5, ++ 0x391c0cb3, 0x4ed8aa4a, 0x5b9cca4f, 0x682e6ff3, ++ 0x748f82ee, 0x78a5636f, 0x84c87814, 0x8cc70208, ++ 0x90befffa, 0xa4506ceb, 0xbef9a3f7, 0xc67178f2 ++}; ++ ++struct sha256_ctx { ++ uint8_t data[64]; /* current 512-bit chunk of message data, just like a buffer */ ++ uint32_t datalen; /* sign the data length of current chunk */ ++ uint64_t bitlen; /* the bit length of the total message */ ++ uint32_t state[8]; /* store the middle state of hash abstract */ ++}; ++ ++/*********************** FUNCTION DEFINITIONS ***********************/ ++static void sha256_transform(struct sha256_ctx *ctx, const uint8_t *data) ++{ ++ uint32_t a, b, c, d, e, f, g, h, i, j, t1, t2, m[64]; ++ ++ /* initialization */ ++ for (i = 0, j = 0; i < 16; ++i, j += 4) ++ m[i] = (data[j] << 24) | (data[j + 1] << 16) | ++ (data[j + 2] << 8) | (data[j + 3]); ++ for ( ; i < 64; ++i) ++ m[i] = SIG1(m[i - 2]) + m[i - 7] + SIG0(m[i - 15]) + m[i - 16]; ++ ++ a = ctx->state[0]; ++ b = ctx->state[1]; ++ c = ctx->state[2]; ++ d = ctx->state[3]; ++ e = ctx->state[4]; ++ f = ctx->state[5]; ++ g = ctx->state[6]; ++ h = ctx->state[7]; ++ ++ for (i = 0; i < 64; ++i) { ++ t1 = h + EP1(e) + CH(e, f, g) + k[i] + m[i]; ++ t2 = EP0(a) + MAJ(a, b, c); ++ h = g; ++ g = f; ++ f = e; ++ e = d + t1; ++ d = c; ++ c = b; ++ b = a; ++ a = t1 + t2; ++ } ++ ++ ctx->state[0] += a; ++ ctx->state[1] += b; ++ ctx->state[2] += c; ++ ctx->state[3] += d; ++ ctx->state[4] += e; ++ ctx->state[5] += f; ++ ctx->state[6] += g; ++ ctx->state[7] += h; ++} ++ ++static void sha256_init(struct sha256_ctx *ctx) ++{ ++ ctx->datalen = 0; ++ ctx->bitlen = 0; ++ ctx->state[0] = 0x6a09e667; ++ ctx->state[1] = 0xbb67ae85; ++ ctx->state[2] = 0x3c6ef372; ++ ctx->state[3] = 0xa54ff53a; ++ ctx->state[4] = 0x510e527f; ++ ctx->state[5] = 0x9b05688c; ++ ctx->state[6] = 0x1f83d9ab; ++ ctx->state[7] = 0x5be0cd19; ++} ++ ++static void sha256_update(struct sha256_ctx *ctx, const uint8_t *data, size_t len) ++{ ++ uint32_t i; ++ ++ for (i = 0; i < len; ++i) { ++ ctx->data[ctx->datalen] = data[i]; ++ ctx->datalen++; ++ if (ctx->datalen == 64) { ++ /* 64 byte = 512 bit means the buffer ctx->data has ++ * fully stored one chunk of message, ++ * so do the sha256 hash map for the current chunk. ++ */ ++ sha256_transform(ctx, ctx->data); ++ ctx->bitlen += 512; ++ ctx->datalen = 0; ++ } ++ } ++} ++ ++static void sha256_final(struct sha256_ctx *ctx, uint8_t *hash) ++{ ++ uint32_t i; ++ ++ i = ctx->datalen; ++ ++ /* Pad whatever data is left in the buffer. */ ++ if (ctx->datalen < 56) { ++ ctx->data[i++] = 0x80; /* pad 10000000 = 0x80 */ ++ while (i < 56) ++ ctx->data[i++] = 0x00; ++ } else { ++ ctx->data[i++] = 0x80; ++ while (i < 64) ++ ctx->data[i++] = 0x00; ++ sha256_transform(ctx, ctx->data); ++ memset(ctx->data, 0, 56); ++ } ++ ++ /* Append to the padding the total message's length in bits and transform. */ ++ ctx->bitlen += ctx->datalen * 8; ++ ctx->data[63] = ctx->bitlen; ++ ctx->data[62] = ctx->bitlen >> 8; ++ ctx->data[61] = ctx->bitlen >> 16; ++ ctx->data[60] = ctx->bitlen >> 24; ++ ctx->data[59] = ctx->bitlen >> 32; ++ ctx->data[58] = ctx->bitlen >> 40; ++ ctx->data[57] = ctx->bitlen >> 48; ++ ctx->data[56] = ctx->bitlen >> 56; ++ sha256_transform(ctx, ctx->data); ++ ++ /* copying the final state to the output hash(use big endian). */ ++ for (i = 0; i < 4; ++i) { ++ hash[i] = (ctx->state[0] >> (24 - i * 8)) & 0x000000ff; ++ hash[i + 4] = (ctx->state[1] >> (24 - i * 8)) & 0x000000ff; ++ hash[i + 8] = (ctx->state[2] >> (24 - i * 8)) & 0x000000ff; ++ hash[i + 12] = (ctx->state[3] >> (24 - i * 8)) & 0x000000ff; ++ hash[i + 16] = (ctx->state[4] >> (24 - i * 8)) & 0x000000ff; ++ hash[i + 20] = (ctx->state[5] >> (24 - i * 8)) & 0x000000ff; ++ hash[i + 24] = (ctx->state[6] >> (24 - i * 8)) & 0x000000ff; ++ hash[i + 28] = (ctx->state[7] >> (24 - i * 8)) & 0x000000ff; ++ } ++} ++ ++int hmac_sha256(const uint8_t *plaintext, ssize_t psize, uint8_t *output) ++{ ++ struct sha256_ctx ctx; ++ ++ sha256_init(&ctx); ++ sha256_update(&ctx, plaintext, psize); ++ sha256_final(&ctx, output); ++ return 0; ++} +diff --git a/drivers/misc/sunxi-addr/sunxi-addr.c b/drivers/misc/sunxi-addr/sunxi-addr.c +new file mode 100644 +index 000000000..a812e4e82 +--- /dev/null ++++ b/drivers/misc/sunxi-addr/sunxi-addr.c +@@ -0,0 +1,357 @@ ++/* ++ * The driver of SUNXI NET MAC ADDR Manager. ++ * ++ * Copyright (C) 2013 Allwinner. ++ * ++ * This file is licensed under the terms of the GNU General Public ++ * License version 2. This program is licensed "as is" without any ++ * warranty of any kind, whether express or implied. ++ */ ++#define DEBUG ++ ++#include ++#include ++#include ++#include ++#include ++ ++#define ADDR_MGT_DBG(fmt, arg...) printk(KERN_DEBUG "[ADDR_MGT] %s: " fmt "\n",\ ++ __func__, ## arg) ++#define ADDR_MGT_ERR(fmt, arg...) printk(KERN_ERR "[ADDR_MGT] %s: " fmt "\n",\ ++ __func__, ## arg) ++ ++#define MODULE_CUR_VERSION "v1.0.9" ++ ++#define MATCH_STR_LEN 20 ++#define ADDR_VAL_LEN 6 ++#define ADDR_STR_LEN 18 ++#define ID_LEN 16 ++#define HASH_LEN 32 ++ ++#define TYPE_ANY 0 ++#define TYPE_BURN 1 ++#define TYPE_IDGEN 2 ++#define TYPE_USER 3 ++#define TYPE_RAND 4 ++ ++#define ADDR_FMT_STR 0 ++#define ADDR_FMT_VAL 1 ++ ++#define IS_TYPE_INVALID(x) ((x < TYPE_ANY) || (x > TYPE_RAND)) ++ ++#define ADDR_CLASS_ATTR_ADD(name) \ ++static ssize_t addr_##name##_show(const struct class *class, \ ++ const struct class_attribute *attr, char *buffer) \ ++{ \ ++ char addr[ADDR_STR_LEN]; \ ++ if (IS_TYPE_INVALID(get_addr_by_name(ADDR_FMT_STR, addr, #name))) \ ++ return 0; \ ++ return sprintf(buffer, "%.17s\n", addr); \ ++} \ ++static ssize_t addr_##name##_store(const struct class *class, \ ++ const struct class_attribute *attr, \ ++ const char *buffer, size_t count) \ ++{ \ ++ if (count != ADDR_STR_LEN) { \ ++ ADDR_MGT_ERR("Length wrong."); \ ++ return -EINVAL; \ ++ } \ ++ set_addr_by_name(TYPE_USER, ADDR_FMT_STR, buffer, #name); \ ++ return count; \ ++} \ ++static CLASS_ATTR_RW(addr_##name); ++ ++struct addr_mgt_info { ++ unsigned int type_def; ++ unsigned int type_cur; ++ unsigned int flag; ++ char *addr; ++ char *name; ++}; ++ ++static struct addr_mgt_info info[] = { ++ {TYPE_ANY, TYPE_ANY, 1, NULL, "wifi"}, ++ {TYPE_ANY, TYPE_ANY, 0, NULL, "bt" }, ++ {TYPE_ANY, TYPE_ANY, 1, NULL, "eth" }, ++}; ++ ++extern int hmac_sha256(const uint8_t *plaintext, ssize_t psize, uint8_t *output); ++extern int sunxi_get_soc_chipid(unsigned char *chipid); ++ ++static int addr_parse(int fmt, const char *addr, int check) ++{ ++ char val_buf[ADDR_VAL_LEN]; ++ char cmp_buf[ADDR_VAL_LEN]; ++ int ret = ADDR_VAL_LEN; ++ ++ if (fmt == ADDR_FMT_STR) ++ ret = sscanf(addr, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx", ++ &val_buf[0], &val_buf[1], &val_buf[2], ++ &val_buf[3], &val_buf[4], &val_buf[5]); ++ else ++ memcpy(val_buf, addr, ADDR_VAL_LEN); ++ ++ if (ret != ADDR_VAL_LEN) ++ return -1; ++ ++ if (check && (val_buf[0] & 0x3)) ++ return -1; ++ ++ memset(cmp_buf, 0x00, ADDR_VAL_LEN); ++ if (memcmp(val_buf, cmp_buf, ADDR_VAL_LEN) == 0) ++ return -1; ++ ++ memset(cmp_buf, 0xFF, ADDR_VAL_LEN); ++ if (memcmp(val_buf, cmp_buf, ADDR_VAL_LEN) == 0) ++ return -1; ++ ++ return 0; ++} ++ ++static struct addr_mgt_info *addr_find_by_name(char *name) ++{ ++ int i = 0; ++ for (i = 0; i < ARRAY_SIZE(info); i++) { ++ if (strcmp(info[i].name, name) == 0) ++ return &info[i]; ++ } ++ return NULL; ++} ++ ++static int get_addr_by_name(int fmt, char *addr, char *name) ++{ ++ struct addr_mgt_info *t; ++ ++ t = addr_find_by_name(name); ++ if (t == NULL) { ++ ADDR_MGT_ERR("can't find addr named: %s", name); ++ return -1; ++ } ++ ++ if (IS_TYPE_INVALID(t->type_cur)) { ++ ADDR_MGT_ERR("addr type invalid"); ++ return -1; ++ } ++ ++ if (addr_parse(ADDR_FMT_VAL, t->addr, t->flag)) { ++ ADDR_MGT_ERR("addr parse fail(%s)", t->addr); ++ return -1; ++ } ++ ++ if (fmt == ADDR_FMT_STR) ++ sprintf(addr, "%02X:%02X:%02X:%02X:%02X:%02X", ++ t->addr[0], t->addr[1], t->addr[2], ++ t->addr[3], t->addr[4], t->addr[5]); ++ else ++ memcpy(addr, t->addr, ADDR_VAL_LEN); ++ ++ return t->type_cur; ++} ++ ++static int set_addr_by_name(int type, int fmt, const char *addr, char *name) ++{ ++ struct addr_mgt_info *t; ++ ++ t = addr_find_by_name(name); ++ if (t == NULL) { ++ ADDR_MGT_ERR("can't find addr named: %s", name); ++ return -1; ++ } ++ ++ if (addr_parse(fmt, addr, t->flag)) { ++ ADDR_MGT_ERR("addr parse fail(%s)", addr); ++ return -1; ++ } ++ ++ t->type_cur = type; ++ if (fmt == ADDR_FMT_STR) ++ sscanf(addr, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx", ++ &t->addr[0], &t->addr[1], &t->addr[2], ++ &t->addr[3], &t->addr[4], &t->addr[5]); ++ else ++ memcpy(t->addr, addr, ADDR_VAL_LEN); ++ ++ return 0; ++} ++ ++int get_custom_mac_address(int fmt, char *name, char *addr) ++{ ++ return get_addr_by_name(fmt, addr, name); ++} ++EXPORT_SYMBOL_GPL(get_custom_mac_address); ++ ++static int addr_factory(struct device_node *np, ++ int idx, int type, char *mac, char *name) ++{ ++ int ret, i; ++ char match[MATCH_STR_LEN]; ++ const char *p; ++ char id[ID_LEN], hash[HASH_LEN], cmp_buf[ID_LEN]; ++ struct timespec64 curtime; ++ ++ switch (type) { ++ case TYPE_BURN: ++ sprintf(match, "addr_%s", name); ++ ret = of_property_read_string_index(np, match, 0, &p); ++ if (ret) ++ return -1; ++ ++ ret = sscanf(p, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx", ++ &mac[0], &mac[1], &mac[2], ++ &mac[3], &mac[4], &mac[5]); ++ ++ if (ret != ADDR_VAL_LEN) ++ return -1; ++ break; ++ case TYPE_IDGEN: ++ if (idx > HASH_LEN / ADDR_VAL_LEN - 1) ++ return -1; ++ if (sunxi_get_soc_chipid(id)) ++ return -1; ++ memset(cmp_buf, 0x00, ID_LEN); ++ if (memcmp(id, cmp_buf, ID_LEN) == 0) ++ return -1; ++ if (hmac_sha256(id, ID_LEN, hash)) ++ return -1; ++ memcpy(mac, &hash[idx * ADDR_VAL_LEN], ADDR_VAL_LEN); ++ break; ++ case TYPE_RAND: ++ for (i = 0; i < ADDR_VAL_LEN; i++) { ++ ktime_get_real_ts64(&curtime); ++ mac[i] = (char)curtime.tv_nsec; ++ } ++ break; ++ default: ++ ADDR_MGT_ERR("unsupport type: %d", type); ++ return -1; ++ } ++ return 0; ++} ++ ++static int addr_init(struct platform_device *pdev) ++{ ++ struct device_node *np = pdev->dev.of_node; ++ int type, i, j; ++ char match[MATCH_STR_LEN]; ++ char addr[ADDR_VAL_LEN]; ++ int type_tab[] = {TYPE_BURN, TYPE_IDGEN, TYPE_RAND}; ++ ++ /* init addr type and value */ ++ for (i = 0; i < ARRAY_SIZE(info); i++) { ++ sprintf(match, "type_addr_%s", info[i].name); ++ if (of_property_read_u32(np, match, &type)) { ++ ADDR_MGT_DBG("Failed to get type_def_%s, use default: %d", ++ info[i].name, info[i].type_def); ++ } else { ++ info[i].type_def = type; ++ info[i].type_cur = type; ++ } ++ ++ if (IS_TYPE_INVALID(info[i].type_def)) ++ return -1; ++ if (info[i].type_def != TYPE_ANY) { ++ if (addr_factory(np, i, info[i].type_def, addr, info[i].name)) ++ return -1; ++ } else { ++ for (j = 0; j < ARRAY_SIZE(type_tab); j++) { ++ if (!addr_factory(np, i, type_tab[j], addr, info[i].name)) { ++ info[i].type_cur = type_tab[j]; ++ break; ++ } ++ } ++ } ++ ++ if (info[i].flag) ++ addr[0] &= 0xFC; ++ ++ if (addr_parse(ADDR_FMT_VAL, addr, info[i].flag)) ++ return -1; ++ else { ++ info[i].addr = devm_kzalloc(&pdev->dev, ADDR_VAL_LEN, GFP_KERNEL); ++ memcpy(info[i].addr, addr, ADDR_VAL_LEN); ++ } ++ } ++ return 0; ++} ++ ++static ssize_t summary_show(const struct class *class, ++ const struct class_attribute *attr, char *buffer) ++{ ++ int i = 0, ret = 0; ++ ++ ret += sprintf(&buffer[ret], "name cfg cur address\n"); ++ for (i = 0; i < ARRAY_SIZE(info); i++) { ++ ret += sprintf(&buffer[ret], ++ "%4s %d %d %02X:%02X:%02X:%02X:%02X:%02X\n", ++ info[i].name, info[i].type_def, info[i].type_cur, ++ info[i].addr[0], info[i].addr[1], info[i].addr[2], ++ info[i].addr[3], info[i].addr[4], info[i].addr[5]); ++ } ++ return ret; ++} ++static CLASS_ATTR_RO(summary); ++ ++ADDR_CLASS_ATTR_ADD(wifi); ++ADDR_CLASS_ATTR_ADD(bt); ++ADDR_CLASS_ATTR_ADD(eth); ++ ++static struct attribute *addr_class_attrs[] = { ++ &class_attr_summary.attr, ++ &class_attr_addr_wifi.attr, ++ &class_attr_addr_bt.attr, ++ &class_attr_addr_eth.attr, ++ NULL ++}; ++ATTRIBUTE_GROUPS(addr_class); ++ ++static struct class addr_class = { ++ .name = "addr_mgt", ++ .class_groups = addr_class_groups, ++}; ++ ++static const struct of_device_id addr_mgt_ids[] = { ++ { .compatible = "allwinner,sunxi-addr_mgt" }, ++ { /* Sentinel */ } ++}; ++ ++static int addr_mgt_probe(struct platform_device *pdev) ++{ ++ int status; ++ ++ ADDR_MGT_DBG("module version: %s", MODULE_CUR_VERSION); ++ status = class_register(&addr_class); ++ if (status < 0) { ++ ADDR_MGT_ERR("class register error, status: %d.", status); ++ return -1; ++ } ++ ++ if (addr_init(pdev)) { ++ ADDR_MGT_ERR("failed to init addr."); ++ class_unregister(&addr_class); ++ return -1; ++ } ++ ADDR_MGT_DBG("success."); ++ return 0; ++} ++ ++static int addr_mgt_remove(struct platform_device *pdev) ++{ ++ class_unregister(&addr_class); ++ return 0; ++} ++ ++static struct platform_driver addr_mgt_driver = { ++ .probe = addr_mgt_probe, ++ .remove = addr_mgt_remove, ++ .driver = { ++ .owner = THIS_MODULE, ++ .name = "sunxi-addr-mgt", ++ .of_match_table = addr_mgt_ids, ++ }, ++}; ++ ++module_platform_driver_probe(addr_mgt_driver, addr_mgt_probe); ++ ++MODULE_AUTHOR("Allwinnertech"); ++MODULE_DESCRIPTION("Network MAC Addess Manager"); ++MODULE_LICENSE("GPL"); +-- +2.34.1 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/Bananapro-add-AXP209-regulators.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/Bananapro-add-AXP209-regulators.patch new file mode 100644 index 0000000000..5daece34ce --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/Bananapro-add-AXP209-regulators.patch @@ -0,0 +1,72 @@ +From 6587b78573f0d6ad63586ae964c0882acb3c391f Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Tue, 12 Apr 2022 21:14:36 +0300 +Subject: [PATCH 069/153] Bananapro add AXP209 regulators + +Author: Heiko Jehmlich +Signed-off-by: Heiko Jehmlich +--- + arch/arm/boot/dts/sun7i-a20-bananapro.dts | 50 +++++++++++++++++++++++ + 1 file changed, 50 insertions(+) + +diff --git a/arch/arm/boot/dts/sun7i-a20-bananapro.dts b/arch/arm/boot/dts/sun7i-a20-bananapro.dts +index 3a34fb39a..d5bc59060 100644 +--- a/arch/arm/boot/dts/sun7i-a20-bananapro.dts ++++ b/arch/arm/boot/dts/sun7i-a20-bananapro.dts +@@ -257,3 +257,53 @@ &usbphy { + ®_ahci_5v { + status = "okay"; + }; ++ ++#include "axp209.dtsi" ++ ++&ac_power_supply { ++ status = "okay"; ++}; ++ ++&battery_power_supply { ++ status = "okay"; ++}; ++ ++®_dcdc2 { ++ regulator-always-on; ++ regulator-min-microvolt = <1000000>; ++ regulator-max-microvolt = <1450000>; ++ regulator-name = "vdd-cpu"; ++}; ++ ++®_dcdc3 { ++ regulator-always-on; ++ regulator-min-microvolt = <1000000>; ++ regulator-max-microvolt = <1400000>; ++ regulator-name = "vdd-int-dll"; ++}; ++ ++®_ldo1 { ++ regulator-name = "vdd-rtc"; ++}; ++ ++®_ldo2 { ++ regulator-always-on; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-name = "avcc"; ++}; ++ ++®_ldo3 { ++ regulator-always-on; ++ regulator-min-microvolt = <2800000>; ++ regulator-max-microvolt = <2800000>; ++ regulator-name = "vddio-csi0"; ++ regulator-ramp-delay = <1600>; ++}; ++ ++®_ldo4 { ++ regulator-always-on; /* required for SATA */ ++ regulator-min-microvolt = <2800000>; ++ regulator-max-microvolt = <2800000>; ++ regulator-name = "vddio-csi1"; ++}; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/Compile-the-pwm-overlay.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/Compile-the-pwm-overlay.patch new file mode 100644 index 0000000000..b359f23973 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/Compile-the-pwm-overlay.patch @@ -0,0 +1,24 @@ +From 2c31f82c392f07ebf32916c54dee6bffdcb3b3d7 Mon Sep 17 00:00:00 2001 +From: afaulkner420 +Date: Fri, 25 Mar 2022 19:26:16 +0000 +Subject: [PATCH 116/153] Compile the pwm overlay + +--- + arch/arm64/boot/dts/allwinner/overlay/Makefile | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm64/boot/dts/allwinner/overlay/Makefile b/arch/arm64/boot/dts/allwinner/overlay/Makefile +index 87f5addec..7cabe8f42 100644 +--- a/arch/arm64/boot/dts/allwinner/overlay/Makefile ++++ b/arch/arm64/boot/dts/allwinner/overlay/Makefile +@@ -38,6 +38,7 @@ dtbo-$(CONFIG_ARCH_SUNXI) += \ + sun50i-h6-i2c0.dtbo \ + sun50i-h6-i2c1.dtbo \ + sun50i-h6-i2c2.dtbo \ ++ sun50i-h6-pwm.dtbo \ + sun50i-h6-ruart.dtbo \ + sun50i-h6-spi-add-cs1.dtbo \ + sun50i-h6-spi-jedec-nor.dtbo \ +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/Doc-dt-bindings-usb-add-binding-for-DWC3-controller-on-Allwinne.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/Doc-dt-bindings-usb-add-binding-for-DWC3-controller-on-Allwinne.patch new file mode 100644 index 0000000000..183d56da49 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/Doc-dt-bindings-usb-add-binding-for-DWC3-controller-on-Allwinne.patch @@ -0,0 +1,64 @@ +From 7b6f3bd96b2507e209847d06ece1ecdb21f9abf7 Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Mon, 25 Dec 2017 12:08:01 +0800 +Subject: [PATCH 003/153] Doc:dt-bindings:usb: add binding for DWC3 controller + on Allwinner SoC + +The Allwinner H6 SoC uses DWC3 controller for USB3. + +Add its device tree binding document. + +Signed-off-by: Icenowy Zheng +--- + .../bindings/usb/allwinner,dwc3.txt | 39 +++++++++++++++++++ + 1 file changed, 39 insertions(+) + create mode 100644 Documentation/devicetree/bindings/usb/allwinner,dwc3.txt + +diff --git a/Documentation/devicetree/bindings/usb/allwinner,dwc3.txt b/Documentation/devicetree/bindings/usb/allwinner,dwc3.txt +new file mode 100644 +index 000000000..3f7714636 +--- /dev/null ++++ b/Documentation/devicetree/bindings/usb/allwinner,dwc3.txt +@@ -0,0 +1,39 @@ ++Allwinner SuperSpeed DWC3 USB SoC controller ++ ++Required properties: ++- compatible: should contain "allwinner,sun50i-h6-dwc3" for H6 SoC ++- clocks: A list of phandle + clock-specifier pairs for the ++ clocks listed in clock-names ++- clock-names: Should contain the following: ++ "bus" The bus clock of the DWC3 part ++- resets: A list of phandle + reset-specifier pairs for the ++ resets listed in reset-names ++- reset-names: Should contain the following: ++ "bus" The bus reset of the DWC3 part ++ ++Required child node: ++A child node must exist to represent the core DWC3 IP block. The name of ++the node is not important. The content of the node is defined in dwc3.txt. ++ ++Phy documentation is provided in the following places: ++Documentation/devicetree/bindings/phy/sun50i-usb3-phy.txt ++ ++Example device nodes: ++ usb3: usb@5200000 { ++ compatible = "allwinner,sun50i-h6-dwc3"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ clocks = <&ccu CLK_BUS_XHCI>; ++ clock-names = "bus"; ++ resets = <&ccu RST_BUS_XHCI>; ++ reset-names = "bus"; ++ ++ dwc3: dwc3 { ++ compatible = "snps,dwc3"; ++ reg = <0x5200000 0x10000>; ++ interrupts = ; ++ phys = <&usb3phy>; ++ phy-names = "usb3-phy"; ++ }; ++ }; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/Fix-compile-error-node-not-found.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/Fix-compile-error-node-not-found.patch new file mode 100644 index 0000000000..93c946b51a --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/Fix-compile-error-node-not-found.patch @@ -0,0 +1,68 @@ +From 8655074e6ee44514de32f3721d8c6479ae6c2991 Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Thu, 3 Feb 2022 21:22:16 +0300 +Subject: [PATCH 135/153] Fix compile error node not found + +Error: arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts:47.1-4 Label or path de not found +Error: arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts:70.1-6 Label or path hdmi not found +Error: arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts:75.1-10 Label or path hdmi_out not found +FATAL ERROR: Syntax error parsing input tree +make[2]: *** [scripts/Makefile.lib:365: arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dtb] Error 1 +--- + .../dts/allwinner/sun50i-h616-x96-mate.dts | 26 ------------------- + 1 file changed, 26 deletions(-) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts +index f4a8241db..31c8bf0e1 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts +@@ -23,17 +23,6 @@ chosen { + stdout-path = "serial0:115200n8"; + }; + +- connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_con_in: endpoint { +- remote-endpoint = <&hdmi_out_con>; +- }; +- }; +- }; +- + reg_vcc5v: vcc5v { + /* board wide 5V supply directly from the DC input */ + compatible = "regulator-fixed"; +@@ -44,10 +33,6 @@ reg_vcc5v: vcc5v { + }; + }; + +-&de { +- status = "okay"; +-}; +- + &ehci0 { + status = "okay"; + }; +@@ -67,17 +52,6 @@ &emac1 { + status = "okay"; + }; + +-&hdmi { +- hvcc-supply = <®_bldo1>; +- status = "okay"; +-}; +- +-&hdmi_out { +- hdmi_out_con: endpoint { +- remote-endpoint = <&hdmi_con_in>; +- }; +-}; +- + &ir { + status = "okay"; + }; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/Fix-include-uapi-spi-spidev-module.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/Fix-include-uapi-spi-spidev-module.patch new file mode 100644 index 0000000000..a4efb345ce --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/Fix-include-uapi-spi-spidev-module.patch @@ -0,0 +1,26 @@ +From 99c48fe621d0154952cbf76ede528ef93c1fa1d9 Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Thu, 28 Apr 2022 15:45:14 +0300 +Subject: [PATCH 140/153] Fix include uapi spi spidev module + +--- + drivers/spi/spidev.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/drivers/spi/spidev.c b/drivers/spi/spidev.c +index 0f85ef9b9..7a6109908 100644 +--- a/drivers/spi/spidev.c ++++ b/drivers/spi/spidev.c +@@ -21,8 +21,7 @@ + #include + #include + +-#include +-#include ++#include + + #include + +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/HACK-media-uapi-hevc-tiles-and-num_slices.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/HACK-media-uapi-hevc-tiles-and-num_slices.patch new file mode 100644 index 0000000000..85eb471527 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/HACK-media-uapi-hevc-tiles-and-num_slices.patch @@ -0,0 +1,37 @@ +From a0336ec2aa6ea38d4b2c9a2100b67fd6d09005cd Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Sat, 23 May 2020 15:07:15 +0000 +Subject: [PATCH 038/170] HACK: media: uapi: hevc: tiles and num_slices + +--- + include/media/hevc-ctrls.h | 7 +++++-- + 1 file changed, 5 insertions(+), 2 deletions(-) + +diff --git a/include/media/hevc-ctrls.h b/include/media/hevc-ctrls.h +index a536dab3f..c8618dc68 100644 +--- a/include/media/hevc-ctrls.h ++++ b/include/media/hevc-ctrls.h +@@ -83,7 +83,8 @@ struct v4l2_ctrl_hevc_sps { + __u8 chroma_format_idc; + __u8 sps_max_sub_layers_minus1; + +- __u8 padding[6]; ++ __u8 num_slices; ++ __u8 padding[5]; + + __u64 flags; + }; +@@ -208,7 +209,9 @@ struct v4l2_ctrl_hevc_slice_params { + __u16 short_term_ref_pic_set_size; + __u16 long_term_ref_pic_set_size; + +- __u8 padding[4]; ++ __u32 num_entry_point_offsets; ++ __u32 entry_point_offset_minus1[256]; ++ __u8 padding[8]; + + /* ISO/IEC 23008-2, ITU-T Rec. H.265: Weighted prediction parameter */ + struct v4l2_hevc_pred_weight_table pred_weight_table; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/Makefile-CONFIG_SHELL-fix-for-builddeb-packaging.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/Makefile-CONFIG_SHELL-fix-for-builddeb-packaging.patch new file mode 100644 index 0000000000..aebf697aec --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/Makefile-CONFIG_SHELL-fix-for-builddeb-packaging.patch @@ -0,0 +1,27 @@ +From ff17e34683a9e98f80365fe5995ebfdc3d6aac0b Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Wed, 2 Feb 2022 11:28:14 +0300 +Subject: [PATCH 108/153] Makefile: CONFIG_SHELL fix for builddeb packaging + +--- + Makefile | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/Makefile b/Makefile +index f26824f36..9d16e7725 100644 +--- a/Makefile ++++ b/Makefile +@@ -440,7 +440,9 @@ KCONFIG_CONFIG ?= .config + export KCONFIG_CONFIG + + # SHELL used by kbuild +-CONFIG_SHELL := sh ++CONFIG_SHELL := $(shell if [ -x "$$BASH" ]; then echo $$BASH; \ ++ else if [ -x /bin/bash ]; then echo /bin/bash; \ ++ else echo sh; fi ; fi) + + HOST_LFS_CFLAGS := $(shell getconf LFS_CFLAGS 2>/dev/null) + HOST_LFS_LDFLAGS := $(shell getconf LFS_LDFLAGS 2>/dev/null) +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/Move-sun50i-h6-pwm-settings-to-its-own-overlay.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/Move-sun50i-h6-pwm-settings-to-its-own-overlay.patch new file mode 100644 index 0000000000..81f134a31f --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/Move-sun50i-h6-pwm-settings-to-its-own-overlay.patch @@ -0,0 +1,70 @@ +From eaf1fe09892c1ba3e6d8dae8cf06c8c3ddacd06a Mon Sep 17 00:00:00 2001 +From: afaulkner420 +Date: Fri, 25 Mar 2022 19:23:56 +0000 +Subject: [PATCH 115/153] Move sun50i-h6-pwm settings to its own overlay + +--- + .../allwinner/overlay/sun50i-h6-fixup.scr-cmd | 14 ----------- + .../dts/allwinner/overlay/sun50i-h6-pwm.dts | 25 +++++++++++++++++++ + 2 files changed, 25 insertions(+), 14 deletions(-) + create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-pwm.dts + +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-fixup.scr-cmd b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-fixup.scr-cmd +index d8e79ba45..f757db7aa 100644 +--- a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-fixup.scr-cmd ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-fixup.scr-cmd +@@ -54,20 +54,6 @@ if test "${param_pps_falling_edge}" = "1"; then + fdt set /pps@0 assert-falling-edge + fi + +-for f in ${overlays}; do +- if test "${f}" = "pwm"; then +- setenv bootargs_new "" +- for arg in ${bootargs}; do +- if test "${arg}" = "console=ttyS0,115200"; then +- echo "Warning: Disabling ttyS0 console due to enabled PWM overlay" +- else +- setenv bootargs_new "${bootargs_new} ${arg}" +- fi +- done +- setenv bootargs "${bootargs_new}" +- fi +-done +- + if test -n "${param_w1_pin}"; then + setenv tmp_bank "${param_w1_pin}" + setenv tmp_pin "${param_w1_pin}" +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-pwm.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-pwm.dts +new file mode 100644 +index 000000000..a8aa74ed1 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-pwm.dts +@@ -0,0 +1,25 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h6-pwm"; ++ ++ fragment@0 { ++ target = <&pio>; ++ __overlay__ { ++ pwm_pin: pwm-pin { ++ pins = "PD22"; ++ function = "pwm"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&pwm>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm_pin>; ++ status = "okay"; ++ }; ++ }; ++}; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/Revert-net-Remove-net-ipx.h-and-uapi-linux-ipx.h-header-files.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/Revert-net-Remove-net-ipx.h-and-uapi-linux-ipx.h-header-files.patch new file mode 100644 index 0000000000..0ed5a97310 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/Revert-net-Remove-net-ipx.h-and-uapi-linux-ipx.h-header-files.patch @@ -0,0 +1,287 @@ +From c236bce6061008d751231fbb0c4cb1af949a48ca Mon Sep 17 00:00:00 2001 +From: Igor Pecovnik +Date: Sat, 6 Nov 2021 19:15:23 +0100 +Subject: [PATCH 002/153] Revert "net: Remove net/ipx.h and uapi/linux/ipx.h + header files" + +This reverts commit 6c9b40844751ea30c72f7a2f92f4d704bc6b2927. +--- + include/net/ipx.h | 171 +++++++++++++++++++++++++++++++++++++++ + include/uapi/linux/ipx.h | 87 ++++++++++++++++++++ + 2 files changed, 258 insertions(+) + create mode 100644 include/net/ipx.h + create mode 100644 include/uapi/linux/ipx.h + +diff --git a/include/net/ipx.h b/include/net/ipx.h +new file mode 100644 +index 000000000..9d1342807 +--- /dev/null ++++ b/include/net/ipx.h +@@ -0,0 +1,171 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++#ifndef _NET_INET_IPX_H_ ++#define _NET_INET_IPX_H_ ++/* ++ * The following information is in its entirety obtained from: ++ * ++ * Novell 'IPX Router Specification' Version 1.10 ++ * Part No. 107-000029-001 ++ * ++ * Which is available from ftp.novell.com ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++struct ipx_address { ++ __be32 net; ++ __u8 node[IPX_NODE_LEN]; ++ __be16 sock; ++}; ++ ++#define ipx_broadcast_node "\377\377\377\377\377\377" ++#define ipx_this_node "\0\0\0\0\0\0" ++ ++#define IPX_MAX_PPROP_HOPS 8 ++ ++struct ipxhdr { ++ __be16 ipx_checksum __packed; ++#define IPX_NO_CHECKSUM cpu_to_be16(0xFFFF) ++ __be16 ipx_pktsize __packed; ++ __u8 ipx_tctrl; ++ __u8 ipx_type; ++#define IPX_TYPE_UNKNOWN 0x00 ++#define IPX_TYPE_RIP 0x01 /* may also be 0 */ ++#define IPX_TYPE_SAP 0x04 /* may also be 0 */ ++#define IPX_TYPE_SPX 0x05 /* SPX protocol */ ++#define IPX_TYPE_NCP 0x11 /* $lots for docs on this (SPIT) */ ++#define IPX_TYPE_PPROP 0x14 /* complicated flood fill brdcast */ ++ struct ipx_address ipx_dest __packed; ++ struct ipx_address ipx_source __packed; ++}; ++ ++/* From af_ipx.c */ ++extern int sysctl_ipx_pprop_broadcasting; ++ ++struct ipx_interface { ++ /* IPX address */ ++ __be32 if_netnum; ++ unsigned char if_node[IPX_NODE_LEN]; ++ refcount_t refcnt; ++ ++ /* physical device info */ ++ struct net_device *if_dev; ++ struct datalink_proto *if_dlink; ++ __be16 if_dlink_type; ++ ++ /* socket support */ ++ unsigned short if_sknum; ++ struct hlist_head if_sklist; ++ spinlock_t if_sklist_lock; ++ ++ /* administrative overhead */ ++ int if_ipx_offset; ++ unsigned char if_internal; ++ unsigned char if_primary; ++ ++ struct list_head node; /* node in ipx_interfaces list */ ++}; ++ ++struct ipx_route { ++ __be32 ir_net; ++ struct ipx_interface *ir_intrfc; ++ unsigned char ir_routed; ++ unsigned char ir_router_node[IPX_NODE_LEN]; ++ struct list_head node; /* node in ipx_routes list */ ++ refcount_t refcnt; ++}; ++ ++struct ipx_cb { ++ u8 ipx_tctrl; ++ __be32 ipx_dest_net; ++ __be32 ipx_source_net; ++ struct { ++ __be32 netnum; ++ int index; ++ } last_hop; ++}; ++ ++#include ++ ++struct ipx_sock { ++ /* struct sock has to be the first member of ipx_sock */ ++ struct sock sk; ++ struct ipx_address dest_addr; ++ struct ipx_interface *intrfc; ++ __be16 port; ++#ifdef CONFIG_IPX_INTERN ++ unsigned char node[IPX_NODE_LEN]; ++#endif ++ unsigned short type; ++ /* ++ * To handle special ncp connection-handling sockets for mars_nwe, ++ * the connection number must be stored in the socket. ++ */ ++ unsigned short ipx_ncp_conn; ++}; ++ ++static inline struct ipx_sock *ipx_sk(struct sock *sk) ++{ ++ return (struct ipx_sock *)sk; ++} ++ ++#define IPX_SKB_CB(__skb) ((struct ipx_cb *)&((__skb)->cb[0])) ++ ++#define IPX_MIN_EPHEMERAL_SOCKET 0x4000 ++#define IPX_MAX_EPHEMERAL_SOCKET 0x7fff ++ ++extern struct list_head ipx_routes; ++extern rwlock_t ipx_routes_lock; ++ ++extern struct list_head ipx_interfaces; ++struct ipx_interface *ipx_interfaces_head(void); ++extern spinlock_t ipx_interfaces_lock; ++ ++extern struct ipx_interface *ipx_primary_net; ++ ++int ipx_proc_init(void); ++void ipx_proc_exit(void); ++ ++const char *ipx_frame_name(__be16); ++const char *ipx_device_name(struct ipx_interface *intrfc); ++ ++static __inline__ void ipxitf_hold(struct ipx_interface *intrfc) ++{ ++ refcount_inc(&intrfc->refcnt); ++} ++ ++void ipxitf_down(struct ipx_interface *intrfc); ++struct ipx_interface *ipxitf_find_using_net(__be32 net); ++int ipxitf_send(struct ipx_interface *intrfc, struct sk_buff *skb, char *node); ++__be16 ipx_cksum(struct ipxhdr *packet, int length); ++int ipxrtr_add_route(__be32 network, struct ipx_interface *intrfc, ++ unsigned char *node); ++void ipxrtr_del_routes(struct ipx_interface *intrfc); ++int ipxrtr_route_packet(struct sock *sk, struct sockaddr_ipx *usipx, ++ struct msghdr *msg, size_t len, int noblock); ++int ipxrtr_route_skb(struct sk_buff *skb); ++struct ipx_route *ipxrtr_lookup(__be32 net); ++int ipxrtr_ioctl(unsigned int cmd, void __user *arg); ++ ++static __inline__ void ipxitf_put(struct ipx_interface *intrfc) ++{ ++ if (refcount_dec_and_test(&intrfc->refcnt)) ++ ipxitf_down(intrfc); ++} ++ ++static __inline__ void ipxrtr_hold(struct ipx_route *rt) ++{ ++ refcount_inc(&rt->refcnt); ++} ++ ++static __inline__ void ipxrtr_put(struct ipx_route *rt) ++{ ++ if (refcount_dec_and_test(&rt->refcnt)) ++ kfree(rt); ++} ++#endif /* _NET_INET_IPX_H_ */ +diff --git a/include/uapi/linux/ipx.h b/include/uapi/linux/ipx.h +new file mode 100644 +index 000000000..3168137ad +--- /dev/null ++++ b/include/uapi/linux/ipx.h +@@ -0,0 +1,87 @@ ++/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ ++#ifndef _IPX_H_ ++#define _IPX_H_ ++#include /* for compatibility with glibc netipx/ipx.h */ ++#include ++#include ++#include ++#define IPX_NODE_LEN 6 ++#define IPX_MTU 576 ++ ++#if __UAPI_DEF_SOCKADDR_IPX ++struct sockaddr_ipx { ++ __kernel_sa_family_t sipx_family; ++ __be16 sipx_port; ++ __be32 sipx_network; ++ unsigned char sipx_node[IPX_NODE_LEN]; ++ __u8 sipx_type; ++ unsigned char sipx_zero; /* 16 byte fill */ ++}; ++#endif /* __UAPI_DEF_SOCKADDR_IPX */ ++ ++/* ++ * So we can fit the extra info for SIOCSIFADDR into the address nicely ++ */ ++#define sipx_special sipx_port ++#define sipx_action sipx_zero ++#define IPX_DLTITF 0 ++#define IPX_CRTITF 1 ++ ++#if __UAPI_DEF_IPX_ROUTE_DEFINITION ++struct ipx_route_definition { ++ __be32 ipx_network; ++ __be32 ipx_router_network; ++ unsigned char ipx_router_node[IPX_NODE_LEN]; ++}; ++#endif /* __UAPI_DEF_IPX_ROUTE_DEFINITION */ ++ ++#if __UAPI_DEF_IPX_INTERFACE_DEFINITION ++struct ipx_interface_definition { ++ __be32 ipx_network; ++ unsigned char ipx_device[16]; ++ unsigned char ipx_dlink_type; ++#define IPX_FRAME_NONE 0 ++#define IPX_FRAME_SNAP 1 ++#define IPX_FRAME_8022 2 ++#define IPX_FRAME_ETHERII 3 ++#define IPX_FRAME_8023 4 ++#define IPX_FRAME_TR_8022 5 /* obsolete */ ++ unsigned char ipx_special; ++#define IPX_SPECIAL_NONE 0 ++#define IPX_PRIMARY 1 ++#define IPX_INTERNAL 2 ++ unsigned char ipx_node[IPX_NODE_LEN]; ++}; ++#endif /* __UAPI_DEF_IPX_INTERFACE_DEFINITION */ ++ ++#if __UAPI_DEF_IPX_CONFIG_DATA ++struct ipx_config_data { ++ unsigned char ipxcfg_auto_select_primary; ++ unsigned char ipxcfg_auto_create_interfaces; ++}; ++#endif /* __UAPI_DEF_IPX_CONFIG_DATA */ ++ ++/* ++ * OLD Route Definition for backward compatibility. ++ */ ++ ++#if __UAPI_DEF_IPX_ROUTE_DEF ++struct ipx_route_def { ++ __be32 ipx_network; ++ __be32 ipx_router_network; ++#define IPX_ROUTE_NO_ROUTER 0 ++ unsigned char ipx_router_node[IPX_NODE_LEN]; ++ unsigned char ipx_device[16]; ++ unsigned short ipx_flags; ++#define IPX_RT_SNAP 8 ++#define IPX_RT_8022 4 ++#define IPX_RT_BLUEBOOK 2 ++#define IPX_RT_ROUTED 1 ++}; ++#endif /* __UAPI_DEF_IPX_ROUTE_DEF */ ++ ++#define SIOCAIPXITFCRT (SIOCPROTOPRIVATE) ++#define SIOCAIPXPRISLT (SIOCPROTOPRIVATE + 1) ++#define SIOCIPXCFGDATA (SIOCPROTOPRIVATE + 2) ++#define SIOCIPXNCPCONN (SIOCPROTOPRIVATE + 3) ++#endif /* _IPX_H_ */ +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/Rollback-r_rsb-to-r_i2c.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/Rollback-r_rsb-to-r_i2c.patch new file mode 100644 index 0000000000..cb3bdd68f4 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/Rollback-r_rsb-to-r_i2c.patch @@ -0,0 +1,32 @@ +From 6bdb276a08c82541b6c408b9b3cdf432ed8bb3de Mon Sep 17 00:00:00 2001 +From: Ukhellfire +Date: Fri, 1 Apr 2022 09:44:19 +0100 +Subject: [PATCH 149/153] Rollback r_rsb to r_i2c + +--- + arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3-lts.dts | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3-lts.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3-lts.dts +index cc5a73026..0b07f8ca2 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3-lts.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3-lts.dts +@@ -208,12 +208,12 @@ &pio { + vcc-pg-supply = <®_vcc_wifi_io>; + }; + +-&r_rsb { ++&r_i2c { + status = "okay"; + +- axp805: pmic@745 { ++ axp805: pmic@36 { + compatible = "x-powers,axp805", "x-powers,axp806"; +- reg = <0x745>; ++ reg = <0x36>; + interrupt-parent = <&r_intc>; + interrupts = ; + interrupt-controller; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/WIP-media-uapi-hevc-add-fields-needed-for-rkvdec.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/WIP-media-uapi-hevc-add-fields-needed-for-rkvdec.patch new file mode 100644 index 0000000000..41ed3b0db5 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/WIP-media-uapi-hevc-add-fields-needed-for-rkvdec.patch @@ -0,0 +1,66 @@ +From 4ca80443bbab08aede430ab4f13e2818836f19b5 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Sat, 23 May 2020 15:03:46 +0000 +Subject: [PATCH 037/170] WIP: media: uapi: hevc: add fields needed for rkvdec + +NOTE: these fields are used by rkvdec hevc backend + +Signed-off-by: Jonas Karlman +--- + include/media/hevc-ctrls.h | 12 ++++++++++-- + 1 file changed, 10 insertions(+), 2 deletions(-) + +diff --git a/include/media/hevc-ctrls.h b/include/media/hevc-ctrls.h +index 01ccda48d..a536dab3f 100644 +--- a/include/media/hevc-ctrls.h ++++ b/include/media/hevc-ctrls.h +@@ -58,6 +58,8 @@ enum v4l2_mpeg_video_hevc_start_code { + /* The controls are not stable at the moment and will likely be reworked. */ + struct v4l2_ctrl_hevc_sps { + /* ISO/IEC 23008-2, ITU-T Rec. H.265: Sequence parameter set */ ++ __u8 video_parameter_set_id; ++ __u8 seq_parameter_set_id; + __u16 pic_width_in_luma_samples; + __u16 pic_height_in_luma_samples; + __u8 bit_depth_luma_minus8; +@@ -81,6 +83,8 @@ struct v4l2_ctrl_hevc_sps { + __u8 chroma_format_idc; + __u8 sps_max_sub_layers_minus1; + ++ __u8 padding[6]; ++ + __u64 flags; + }; + +@@ -108,6 +112,7 @@ struct v4l2_ctrl_hevc_sps { + + struct v4l2_ctrl_hevc_pps { + /* ISO/IEC 23008-2, ITU-T Rec. H.265: Picture parameter set */ ++ __u8 pic_parameter_set_id; + __u8 num_extra_slice_header_bits; + __u8 num_ref_idx_l0_default_active_minus1; + __u8 num_ref_idx_l1_default_active_minus1; +@@ -123,7 +128,7 @@ struct v4l2_ctrl_hevc_pps { + __s8 pps_tc_offset_div2; + __u8 log2_parallel_merge_level_minus2; + +- __u8 padding[4]; ++ __u8 padding; + __u64 flags; + }; + +@@ -200,7 +205,10 @@ struct v4l2_ctrl_hevc_slice_params { + __u8 ref_idx_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; + __u8 ref_idx_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; + +- __u8 padding; ++ __u16 short_term_ref_pic_set_size; ++ __u16 long_term_ref_pic_set_size; ++ ++ __u8 padding[4]; + + /* ISO/IEC 23008-2, ITU-T Rec. H.265: Weighted prediction parameter */ + struct v4l2_hevc_pred_weight_table pred_weight_table; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/add-initial-support-for-orangepi3-lts.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/add-initial-support-for-orangepi3-lts.patch new file mode 100644 index 0000000000..a79386ca66 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/add-initial-support-for-orangepi3-lts.patch @@ -0,0 +1,610 @@ +From c697fff6d002b50d264dc9d1b3c2731cf991e854 Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Sat, 16 Apr 2022 11:51:35 +0300 +Subject: [PATCH 146/153] add initial support for orangepi3-lts + +--- + arch/arm64/boot/dts/allwinner/Makefile | 1 + + .../allwinner/sun50i-h6-orangepi-3-lts.dts | 398 ++++++++++++++++++ + arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 101 ++++- + 3 files changed, 487 insertions(+), 13 deletions(-) + create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3-lts.dts + +diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile +index ea455f120..92a30f72f 100644 +--- a/arch/arm64/boot/dts/allwinner/Makefile ++++ b/arch/arm64/boot/dts/allwinner/Makefile +@@ -42,6 +42,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus2.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-beelink-gs1.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-3.dtb ++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-3-lts.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-lite2.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-one-plus.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64.dtb +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3-lts.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3-lts.dts +new file mode 100644 +index 000000000..cc5a73026 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3-lts.dts +@@ -0,0 +1,398 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++// Copyright (C) 2019 OndÅ™ej Jirman ++ ++/dts-v1/; ++ ++#include "sun50i-h6.dtsi" ++#include "sun50i-h6-cpu-opp.dtsi" ++ ++#include ++ ++/ { ++ model = "OrangePi 3 LTS"; ++ compatible = "xunlong,orangepi-3-lts", "allwinner,sun50i-h6"; ++ ++ aliases { ++ serial0 = &uart0; ++ serial1 = &uart1; ++ serial9 = &r_uart; ++ ethernet0 = &emac; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ connector { ++ compatible = "hdmi-connector"; ++ ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */ ++ type = "a"; ++ ++ port { ++ hdmi_con_in: endpoint { ++ remote-endpoint = <&hdmi_out_con>; ++ }; ++ }; ++ }; ++ ++ ext_osc32k: ext_osc32k_clk { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <32768>; ++ clock-output-names = "ext_osc32k"; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ status { ++ label = "green-led"; ++ gpios = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */ ++ default-state = "on"; ++ }; ++ ++ power { ++ label = "red-led"; ++ gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */ ++ }; ++ }; ++ ++ reg_vcc5v: vcc5v { ++ /* board wide 5V supply directly from the DC jack */ ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc-5v"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ }; ++ ++ reg_gmac_3v3: gmac-3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc-gmac-3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ startup-delay-us = <100000>; ++ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ }; ++ ++ reg_vcc33_wifi: vcc33-wifi { ++ /* Always on 3.3V regulator for WiFi and BT */ ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc33-wifi"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ enable-active-high; ++ gpio = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */ ++ }; ++ ++ reg_vcc_wifi_io: vcc-wifi-io { ++ /* Always on 1.8V/300mA regulator for WiFi and BT IO */ ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc-wifi-io"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ vin-supply = <®_vcc33_wifi>; ++ }; ++ ++ wifi_pwrseq: wifi-pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ clocks = <&rtc 1>; ++ clock-names = "ext_clock"; ++ reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */ ++ post-power-on-delay-ms = <200>; ++ }; ++}; ++ ++&cpu0 { ++ cpu-supply = <®_dcdca>; ++}; ++ ++&de { ++ status = "okay"; ++}; ++ ++&dwc3 { ++ status = "okay"; ++}; ++ ++&ehci0 { ++ status = "okay"; ++}; ++ ++&ehci3 { ++ status = "okay"; ++}; ++ ++&gpu { ++ mali-supply = <®_dcdcc>; ++ status = "okay"; ++}; ++ ++&hdmi { ++ status = "okay"; ++}; ++ ++&hdmi_out { ++ hdmi_out_con: endpoint { ++ remote-endpoint = <&hdmi_con_in>; ++ }; ++}; ++ ++&emac { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&ext_rgmii_pins>; ++ phy-mode = "rgmii-id"; ++ phy-handle = <&ext_rgmii_phy>; ++ phy-supply = <®_gmac_3v3>; ++ allwinner,rx-delay-ps = <200>; ++ allwinner,tx-delay-ps = <300>; ++ status = "okay"; ++}; ++ ++&mdio { ++ ext_rgmii_phy: ethernet-phy@1 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <1>; ++ ++ reset-gpios = <&pio 3 14 GPIO_ACTIVE_LOW>; /* PD14 */ ++ reset-assert-us = <15000>; ++ reset-deassert-us = <40000>; ++ }; ++}; ++ ++&i2s1 { ++ status = "okay"; ++}; ++ ++&mmc0 { ++ vmmc-supply = <®_cldo1>; ++ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ ++ bus-width = <4>; ++ status = "okay"; ++}; ++ ++&mmc1 { ++ vmmc-supply = <®_vcc33_wifi>; ++ vqmmc-supply = <®_vcc_wifi_io>; ++ mmc-pwrseq = <&wifi_pwrseq>; ++ bus-width = <4>; ++ non-removable; ++ status = "okay"; ++}; ++ ++&mmc2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc2_pins>; ++ vmmc-supply = <®_cldo1>; ++ vqmmc-supply = <®_bldo2>; ++ bus-width = <8>; ++ non-removable; ++ cap-mmc-hw-reset; ++ mmc-hs200-1_8v; ++ status = "okay"; ++}; ++ ++&ohci0 { ++ status = "okay"; ++}; ++ ++&ohci3 { ++ status = "okay"; ++}; ++ ++&pio { ++ vcc-pc-supply = <®_bldo2>; ++ vcc-pd-supply = <®_cldo1>; ++ vcc-pg-supply = <®_vcc_wifi_io>; ++}; ++ ++&r_rsb { ++ status = "okay"; ++ ++ axp805: pmic@745 { ++ compatible = "x-powers,axp805", "x-powers,axp806"; ++ reg = <0x745>; ++ interrupt-parent = <&r_intc>; ++ interrupts = ; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ x-powers,self-working-mode; ++ vina-supply = <®_vcc5v>; ++ vinb-supply = <®_vcc5v>; ++ vinc-supply = <®_vcc5v>; ++ vind-supply = <®_vcc5v>; ++ vine-supply = <®_vcc5v>; ++ aldoin-supply = <®_vcc5v>; ++ bldoin-supply = <®_vcc5v>; ++ cldoin-supply = <®_vcc5v>; ++ ++ regulators { ++ reg_aldo1: aldo1 { ++ regulator-always-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-pl-led-ir"; ++ }; ++ ++ reg_aldo2: aldo2 { ++ regulator-always-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc33-audio-tv-ephy-mac"; ++ regulator-enable-ramp-delay = <100000>; ++ }; ++ ++ /* ALDO3 is shorted to CLDO1 */ ++ reg_aldo3: aldo3 { ++ regulator-always-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc33-io-pd-emmc-sd-usb-uart-1"; ++ }; ++ ++ reg_bldo1: bldo1 { ++ regulator-always-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc18-dram-bias-pll"; ++ }; ++ ++ reg_bldo2: bldo2 { ++ regulator-always-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc-efuse-pcie-hdmi-pc"; ++ }; ++ ++ reg_blod3: bldo3 { ++ regulator-always-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc-wifi-io-pm-pg"; ++ }; ++ ++ bldo4 { ++ /* unused */ ++ }; ++ ++ reg_cldo1: cldo1 { ++ regulator-always-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc33-io-pd-emmc-sd-usb-uart-2"; ++ }; ++ ++ cldo2 { ++ /* unused */ ++ }; ++ ++ cldo3 { ++ /* unused */ ++ }; ++ ++ reg_dcdca: dcdca { ++ regulator-always-on; ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <1160000>; ++ regulator-ramp-delay = <2500>; ++ regulator-name = "vdd-cpu"; ++ }; ++ ++ reg_dcdcc: dcdcc { ++ regulator-enable-ramp-delay = <32000>; ++ regulator-min-microvolt = <810000>; ++ regulator-max-microvolt = <1080000>; ++ regulator-ramp-delay = <2500>; ++ regulator-name = "vdd-gpu"; ++ }; ++ ++ reg_dcdcd: dcdcd { ++ regulator-always-on; ++ regulator-min-microvolt = <960000>; ++ regulator-max-microvolt = <960000>; ++ regulator-name = "vdd-sys"; ++ }; ++ ++ reg_dcdce: dcdce { ++ regulator-always-on; ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1200000>; ++ regulator-name = "vcc-dram"; ++ }; ++ ++ sw { ++ /* unused */ ++ }; ++ }; ++ }; ++}; ++ ++&pwm { ++ status = "okay"; ++}; ++ ++&ac200_pwm_clk { ++ status = "okay"; ++}; ++ ++&i2s3 { ++ status = "okay"; ++}; ++ ++&i2c3 { ++ status = "okay"; ++}; ++ ++&r_ir { ++ status = "okay"; ++}; ++ ++&rtc { ++ clocks = <&ext_osc32k>; ++}; ++ ++&sound_hdmi { ++ status = "okay"; ++}; ++ ++&sound_ac200 { ++ status = "okay"; ++}; ++ ++/delete-node/ &spi0; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_ph_pins>; ++ status = "okay"; ++}; ++ ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; ++ uart-has-rtscts; ++ status = "disabled"; ++}; ++ ++&usb2otg { ++ /* ++ * This board doesn't have a controllable VBUS even though it ++ * does have an ID pin. Using it as anything but a USB host is ++ * unsafe. ++ */ ++ dr_mode = "host"; ++ status = "okay"; ++}; ++ ++&usb2phy { ++ usb0_id_det-gpios = <&pio 2 15 GPIO_ACTIVE_HIGH>; /* PC15 */ ++ usb0_vbus-supply = <®_vcc5v>; ++ usb3_vbus-supply = <®_vcc5v>; ++ status = "okay"; ++}; ++ ++&usb3phy { ++ status = "okay"; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +index e6fd95b6f..ed54c2c11 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +@@ -92,6 +92,13 @@ osc24M: osc24M_clk { + clock-output-names = "osc24M"; + }; + ++ ext_osc32k: ext_osc32k_clk { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <32768>; ++ clock-output-names = "ext_osc32k"; ++ }; ++ + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = , +@@ -127,6 +134,28 @@ cpu { + }; + }; + ++ sound_ac200: sound_ac200 { ++ status = "disabled"; ++ compatible = "simple-audio-card"; ++ simple-audio-card,format = "i2s"; ++ simple-audio-card,frame-master = <&i2s3_master>; ++ simple-audio-card,bitclock-master = <&i2s3_master>; ++ simple-audio-card,name = "allwinner,ac200-codec"; ++ simple-audio-card,mclk-fs = <512>; ++ i2s3_master: simple-audio-card,cpu { ++ sound-dai = <&i2s3>; ++ system-clock-frequency = <22579200>; ++ dai-tdm-slot-num = <2>; ++ dai-tdm-slot-width = <32>; ++ }; ++ simple-audio-card,codec { ++ sound-dai = <&ac200_codec>; ++ system-clock-frequency = <22579200>; ++ dai-tdm-slot-num = <2>; ++ dai-tdm-slot-width = <32>; ++ }; ++ }; ++ + timer { + compatible = "arm,armv8-timer"; + arm,no-tick-in-suspend; +@@ -383,7 +412,6 @@ pwm: pwm@300a000 { + pio: pinctrl@300b000 { + compatible = "allwinner,sun50i-h6-pinctrl"; + reg = <0x0300b000 0x400>; +- interrupt-parent = <&r_intc>; + interrupts = , + , + , +@@ -533,6 +561,11 @@ uart3_rts_cts_pins: uart3-rts-cts-pins { + pins = "PD25", "PD26"; + function = "uart3"; + }; ++ ++ i2s3_pins: i2s3-pins { ++ pins = "PB12", "PB13", "PB14", "PB15", "PB16"; ++ function = "i2s3"; ++ }; + }; + + iommu: iommu@30f0000 { +@@ -731,6 +764,7 @@ i2c3: i2c@5002c00 { + ac200: mfd@10 { + compatible = "x-powers,ac200"; + reg = <0x10>; ++ clocks = <&ac200_pwm_clk>; + interrupt-parent = <&pio>; + interrupts = <1 20 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; +@@ -738,11 +772,16 @@ ac200: mfd@10 { + + ac200_ephy: phy { + compatible = "x-powers,ac200-ephy"; +- clocks = <&ac200_pwm_clk>; + nvmem-cells = <&ephy_calibration>; + nvmem-cell-names = "calibration"; + status = "disabled"; + }; ++ ++ ac200_codec: codec { ++ #sound-dai-cells = <0>; ++ compatible = "x-powers,ac200-codec"; ++ status = "okay"; ++ }; + }; + }; + +@@ -779,6 +818,21 @@ i2s1: i2s@5091000 { + status = "disabled"; + }; + ++ i2s3: i2s@508f000 { ++ #sound-dai-cells = <0>; ++ compatible = "allwinner,sun50i-h6-i2s"; ++ reg = <0x0508f000 0x1000>; ++ interrupts = ; ++ clocks = <&ccu CLK_BUS_I2S3>, <&ccu CLK_I2S3>; ++ clock-names = "apb", "mod"; ++ dmas = <&dma 6>, <&dma 6>; ++ resets = <&ccu RST_BUS_I2S3>; ++ dma-names = "rx", "tx"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2s3_pins>; ++ status = "disabled"; ++ }; ++ + spdif: spdif@5093000 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun50i-h6-spdif"; +@@ -1074,6 +1128,7 @@ rtc: rtc@7000000 { + interrupts = , + ; + clock-output-names = "osc32k", "osc32k-out", "iosc"; ++ clocks = <&ext_osc32k>; + #clock-cells = <1>; + }; + +@@ -1140,17 +1195,18 @@ r_uart_pins: r-uart-pins { + }; + + r_ir: ir@7040000 { +- compatible = "allwinner,sun50i-h6-ir", +- "allwinner,sun6i-a31-ir"; +- reg = <0x07040000 0x400>; +- interrupts = ; +- clocks = <&r_ccu CLK_R_APB1_IR>, +- <&r_ccu CLK_IR>; +- clock-names = "apb", "ir"; +- resets = <&r_ccu RST_R_APB1_IR>; +- pinctrl-names = "default"; +- pinctrl-0 = <&r_ir_rx_pin>; +- status = "disabled"; ++ compatible = "allwinner,sun50i-h6-ir", ++ "allwinner,sun6i-a31-ir"; ++ reg = <0x07040000 0x400>; ++ interrupt-parent = <&r_intc>; ++ interrupts = ; ++ clocks = <&r_ccu CLK_R_APB1_IR>, ++ <&r_ccu CLK_IR>; ++ clock-names = "apb", "ir"; ++ resets = <&r_ccu RST_R_APB1_IR>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&r_ir_rx_pin>; ++ status = "disabled"; + }; + + r_i2c: i2c@7081400 { +@@ -1192,6 +1248,25 @@ ths: thermal-sensor@5070400 { + nvmem-cell-names = "calibration"; + #thermal-sensor-cells = <1>; + }; ++ ++ sunxi-info { ++ compatible = "allwinner,sun50i-h6-sys-info"; ++ status = "okay"; ++ }; ++ ++ addr_mgt: addr-mgt { ++ compatible = "allwinner,sunxi-addr_mgt"; ++ type_addr_wifi = <0x2>; ++ type_addr_bt = <0x2>; ++ type_addr_eth = <0x2>; ++ status = "okay"; ++ }; ++ ++ dump_reg: dump_reg@20000 { ++ compatible = "allwinner,sunxi-dump-reg"; ++ reg = <0x0 0x03001000 0x0 0x0f20>; ++ status = "okay"; ++ }; + }; + + thermal-zones { +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/allwinner-h6-Support-ac200-audio-codec.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/allwinner-h6-Support-ac200-audio-codec.patch new file mode 100644 index 0000000000..18705af0f6 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/allwinner-h6-Support-ac200-audio-codec.patch @@ -0,0 +1,1875 @@ +From 08d8881e87cf80b9fe04361dde8cc7a592884499 Mon Sep 17 00:00:00 2001 +From: afaulkner420 +Date: Fri, 25 Mar 2022 20:33:02 +0000 +Subject: [PATCH 144/153] allwinner: h6: Support ac200 audio codec + +--- + drivers/mfd/Makefile | 2 +- + drivers/mfd/{ac200.c => sunxi-ac200.c} | 16 +- + include/linux/mfd/ac200.h | 2 + + sound/soc/codecs/Kconfig | 8 + + sound/soc/codecs/Makefile | 2 + + sound/soc/codecs/acx00.c | 1371 ++++++++++++++++++++++++ + sound/soc/codecs/acx00.h | 356 ++++++ + 7 files changed, 1755 insertions(+), 2 deletions(-) + rename drivers/mfd/{ac200.c => sunxi-ac200.c} (93%) + create mode 100644 sound/soc/codecs/acx00.c + create mode 100644 sound/soc/codecs/acx00.h + +diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile +index b2e69fbce..0e4a09539 100644 +--- a/drivers/mfd/Makefile ++++ b/drivers/mfd/Makefile +@@ -141,7 +141,7 @@ obj-$(CONFIG_MFD_DA9052_SPI) += da9052-spi.o + obj-$(CONFIG_MFD_DA9052_I2C) += da9052-i2c.o + + obj-$(CONFIG_MFD_AC100) += ac100.o +-obj-$(CONFIG_MFD_AC200) += ac200.o ++obj-$(CONFIG_MFD_AC200) += sunxi-ac200.o + obj-$(CONFIG_MFD_AXP20X) += axp20x.o + obj-$(CONFIG_MFD_AXP20X_I2C) += axp20x-i2c.o + obj-$(CONFIG_MFD_AXP20X_RSB) += axp20x-rsb.o +diff --git a/drivers/mfd/ac200.c b/drivers/mfd/sunxi-ac200.c +similarity index 93% +rename from drivers/mfd/ac200.c +rename to drivers/mfd/sunxi-ac200.c +index 570573790..368a54587 100644 +--- a/drivers/mfd/ac200.c ++++ b/drivers/mfd/sunxi-ac200.c +@@ -41,6 +41,7 @@ static const struct regmap_range_cfg ac200_range_cfg[] = { + }; + + static const struct regmap_config ac200_regmap_config = { ++ .name = "ac200", + .reg_bits = 8, + .val_bits = 16, + .ranges = ac200_range_cfg, +@@ -75,6 +76,10 @@ static const struct mfd_cell ac200_cells[] = { + .resources = ephy_resource, + .of_compatible = "x-powers,ac200-ephy", + }, ++ { ++ .name = "acx00-codec", ++ .of_compatible = "x-powers,ac200-codec", ++ }, + }; + + static int ac200_i2c_probe(struct i2c_client *i2c, +@@ -97,8 +102,17 @@ static int ac200_i2c_probe(struct i2c_client *i2c, + return ret; + } + +- /* do a reset to put chip in a known state */ ++ ac200->clk = devm_clk_get(dev, NULL); ++ if (IS_ERR(ac200->clk)) { ++ dev_err(dev, "Can't obtain the clock!\n"); ++ return PTR_ERR(ac200->clk); ++ } + ++ ret = clk_prepare_enable(ac200->clk); ++ if (ret) ++ return ret; ++ ++ /* do a reset to put chip in a known state */ + ret = regmap_write(ac200->regmap, AC200_SYS_CONTROL, 0); + if (ret) + return ret; +diff --git a/include/linux/mfd/ac200.h b/include/linux/mfd/ac200.h +index 0c677094a..c8c140226 100644 +--- a/include/linux/mfd/ac200.h ++++ b/include/linux/mfd/ac200.h +@@ -9,6 +9,7 @@ + #define __LINUX_MFD_AC200_H + + #include ++#include + + /* interface registers (can be accessed from any page) */ + #define AC200_TWI_CHANGE_TO_RSB 0x3E +@@ -201,6 +202,7 @@ + #define AC200_IC_CHARA1 0xA1F2 + + struct ac200_dev { ++ struct clk *clk; + struct regmap *regmap; + struct regmap_irq_chip_data *regmap_irqc; + }; +diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig +index 944d0ea1a..359c515ef 100644 +--- a/sound/soc/codecs/Kconfig ++++ b/sound/soc/codecs/Kconfig +@@ -2170,4 +2170,12 @@ config SND_SOC_LPASS_TX_MACRO + select SND_SOC_LPASS_MACRO_COMMON + tristate "Qualcomm TX Macro in LPASS(Low Power Audio SubSystem)" + ++config SND_SOC_ACX00 ++ tristate "ACX00 Codec" ++ select MFD_ACX00 ++ default n ++ help ++ ACX00 now used as SUN50IW6 internal Codec, Connect Through I2S0. ++ Say Y or M if you want to add support internal audio codec. ++ + endmenu +diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile +index e2d463a31..ccb2a0fe4 100644 +--- a/sound/soc/codecs/Makefile ++++ b/sound/soc/codecs/Makefile +@@ -347,6 +347,7 @@ snd-soc-wm-hubs-objs := wm_hubs.o + snd-soc-wsa881x-objs := wsa881x.o + snd-soc-wsa883x-objs := wsa883x.o + snd-soc-zl38060-objs := zl38060.o ++snd-soc-acx00-objs := acx00.o + # Amp + snd-soc-max9877-objs := max9877.o + snd-soc-max98504-objs := max98504.o +@@ -709,6 +710,7 @@ obj-$(CONFIG_SND_SOC_WM_HUBS) += snd-soc-wm-hubs.o + obj-$(CONFIG_SND_SOC_WSA881X) += snd-soc-wsa881x.o + obj-$(CONFIG_SND_SOC_WSA883X) += snd-soc-wsa883x.o + obj-$(CONFIG_SND_SOC_ZL38060) += snd-soc-zl38060.o ++obj-$(CONFIG_SND_SOC_ACX00) += snd-soc-acx00.o + + # Amp + obj-$(CONFIG_SND_SOC_MAX9877) += snd-soc-max9877.o +diff --git a/sound/soc/codecs/acx00.c b/sound/soc/codecs/acx00.c +new file mode 100644 +index 000000000..ab7467e4e +--- /dev/null ++++ b/sound/soc/codecs/acx00.c +@@ -0,0 +1,1371 @@ ++/* ++ * acx00.c -- ACX00 ALSA Soc Audio Codec driver ++ * ++ * (C) Copyright 2010-2016 Allwinnertech Technology., Ltd. ++ * ++ * Author: Wolfgang Huang ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "acx00.h" ++ ++ ++#define ACX00_DEF_VOL 0x9F9F ++#undef ACX00_DAPM_LINEOUT ++ ++struct acx00_priv { ++ struct ac200_dev *acx00; /* parent mfd device struct */ ++ struct snd_soc_component *component; ++ struct clk *clk; ++ unsigned int sample_rate; ++ unsigned int fmt; ++ unsigned int enable; ++ unsigned int spk_gpio; ++ unsigned int switch_gpio; ++ bool spk_gpio_used; ++ struct mutex mutex; ++ struct delayed_work spk_work; ++ struct delayed_work resume_work; ++}; ++ ++struct sample_rate { ++ unsigned int samplerate; ++ unsigned int rate_bit; ++}; ++ ++static const struct sample_rate sample_rate_conv[] = { ++ {44100, 7}, ++ {48000, 8}, ++ {8000, 0}, ++ {32000, 6}, ++ {22050, 4}, ++ {24000, 5}, ++ {16000, 3}, ++ {11025, 1}, ++ {12000, 2}, ++ {192000, 10}, ++ {96000, 9}, ++}; ++ ++void __iomem *io_stat_addr; ++ ++static const DECLARE_TLV_DB_SCALE(i2s_mixer_adc_tlv, -600, 600, 1); ++static const DECLARE_TLV_DB_SCALE(i2s_mixer_dac_tlv, -600, 600, 1); ++static const DECLARE_TLV_DB_SCALE(dac_mixer_adc_tlv, -600, 600, 1); ++static const DECLARE_TLV_DB_SCALE(dac_mixer_dac_tlv, -600, 600, 1); ++static const DECLARE_TLV_DB_SCALE(line_out_tlv, -450, 150, 0); ++static const DECLARE_TLV_DB_SCALE(mic_out_tlv, -450, 150, 0); ++static const DECLARE_TLV_DB_SCALE(phoneout_tlv, -450, 150, 0); ++static const DECLARE_TLV_DB_SCALE(adc_input_tlv, -450, 150, 0); ++static const DECLARE_TLV_DB_SCALE(lineout_tlv, -4800, 150, 1); ++static const unsigned int mic_boost_tlv[] = { ++ TLV_DB_RANGE_HEAD(2), ++ 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), ++ 1, 7, TLV_DB_SCALE_ITEM(2400, 300, 0), ++}; ++ ++static const struct snd_kcontrol_new acx00_codec_controls[] = { ++ SOC_DOUBLE_TLV("I2S Mixer ADC Volume", AC_I2S_MIXER_GAIN, ++ I2S_MIXERL_GAIN_ADC, I2S_MIXERR_GAIN_ADC, ++ 0x1, 0, i2s_mixer_adc_tlv), ++ SOC_DOUBLE_TLV("I2S Mixer DAC Volume", AC_I2S_MIXER_GAIN, ++ I2S_MIXERL_GAIN_DAC, I2S_MIXERR_GAIN_DAC, ++ 0x1, 0, i2s_mixer_dac_tlv), ++ SOC_DOUBLE_TLV("DAC Mixer ADC Volume", AC_DAC_MIXER_GAIN, ++ DAC_MIXERL_GAIN_ADC, DAC_MIXERR_GAIN_ADC, ++ 0x1, 0, dac_mixer_adc_tlv), ++ SOC_DOUBLE_TLV("DAC Mxier DAC Volume", AC_DAC_MIXER_GAIN, ++ DAC_MIXERL_GAIN_DAC, DAC_MIXERR_GAIN_DAC, ++ 0x1, 0, dac_mixer_dac_tlv), ++ SOC_SINGLE_TLV("Line Out Mixer Volume", AC_OUT_MIXER_CTL, ++ OUT_MIXER_LINE_VOL, 0x7, 0, line_out_tlv), ++ SOC_DOUBLE_TLV("MIC Out Mixer Volume", AC_OUT_MIXER_CTL, ++ OUT_MIXER_MIC1_VOL, OUT_MIXER_MIC2_VOL, ++ 0x7, 0, mic_out_tlv), ++ SOC_SINGLE_TLV("ADC Input Volume", AC_ADC_MIC_CTL, ++ ADC_GAIN, 0x07, 0, adc_input_tlv), ++ SOC_SINGLE_TLV("Master Volume", AC_LINEOUT_CTL, ++ LINEOUT_VOL, 0x1f, 0, lineout_tlv), ++ SOC_SINGLE_TLV("MIC1 Boost Volume", AC_ADC_MIC_CTL, ++ MIC1_BOOST, 0x07, 0, mic_boost_tlv), ++ SOC_SINGLE_TLV("MIC2 Boost Volume", AC_ADC_MIC_CTL, ++ MIC2_BOOST, 0x07, 0, mic_boost_tlv), ++}; ++ ++/* Enable I2S & DAC clk, then enable the DAC digital part */ ++static int acx00_playback_event(struct snd_soc_dapm_widget *w, ++ struct snd_kcontrol *k, int event) ++{ ++ struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); ++ ++ switch (event) { ++ case SND_SOC_DAPM_POST_PMU: ++ snd_soc_component_update_bits(component, AC_SYS_CLK_CTL, ++ (0x1<dapm); ++ ++ switch (event) { ++ case SND_SOC_DAPM_POST_PMU: ++ snd_soc_component_update_bits(component, AC_SYS_CLK_CTL, ++ (0x1<spk_gpio, 1); ++} ++ ++static int acx00_lineout_event(struct snd_soc_dapm_widget *w, ++ struct snd_kcontrol *k, int event) ++{ ++ struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); ++ struct acx00_priv *priv = snd_soc_component_get_drvdata(component); ++ ++ switch (event) { ++ case SND_SOC_DAPM_POST_PMU: ++ if (!priv->enable) { ++ snd_soc_component_update_bits(priv->component, AC_LINEOUT_CTL, ++ (1<component, AC_LINEOUT_CTL, ++ (1<enable = 1; ++ } ++#ifdef ACX00_DAPM_LINEOUT ++ snd_soc_component_update_bits(component, AC_LINEOUT_CTL, ++ (1<spk_gpio_used) { ++ if (spk_delay == 0) { ++ gpio_set_value(priv->spk_gpio, 1); ++ /* ++ * time delay to wait spk pa work fine, ++ * general setting 50ms ++ */ ++ mdelay(50); ++ } else ++ schedule_delayed_work(&priv->spk_work, ++ msecs_to_jiffies(spk_delay)); ++ } ++ break; ++ case SND_SOC_DAPM_PRE_PMD: ++ mdelay(50); ++ if (priv->spk_gpio_used) { ++ gpio_set_value(priv->spk_gpio, 0); ++ msleep(50); ++ } ++#ifdef ACX00_DAPM_LINEOUT ++ snd_soc_component_update_bits(component, AC_LINEOUT_CTL, ++ (1<regmap, reg, &val); ++ ++ if (ret < 0) ++ return ret; ++ else ++ return val; ++} ++ ++int acx00_reg_write(struct ac200_dev *acx00, unsigned short reg, unsigned short val) ++{ ++ return regmap_write(acx00->regmap, reg, val); ++} ++ ++static void acx00_codec_init(struct snd_soc_component *component) ++{ ++ struct acx00_priv *priv = snd_soc_component_get_drvdata(component); ++ ++ acx00_reg_write(priv->acx00, 0x50, 0x82b1); ++ acx00_reg_write(priv->acx00, 0xc, 0xce01); ++ ++ /* acx00_codec sysctl init */ ++ acx00_reg_write(priv->acx00, 0x0010, 0x03); ++ acx00_reg_write(priv->acx00, 0x0012, 0x01); ++ ++ /* The bit3 need to setup to 1 for bias current. */ ++ snd_soc_component_update_bits(component, AC_MICBIAS_CTL, ++ (0x1 << ADDA_BIAS_CUR), (0x1 << ADDA_BIAS_CUR)); ++ ++ /* enable the output & global enable bit */ ++ snd_soc_component_update_bits(component, AC_I2S_CTL, ++ (1<spk_gpio_used) { ++ snd_soc_component_update_bits(priv->component, AC_LINEOUT_CTL, ++ (1<component, AC_LINEOUT_CTL, ++ (1<enable = 1; ++ } ++#ifndef ACX00_DAPM_LINEOUT ++ snd_soc_component_update_bits(component, AC_LINEOUT_CTL, (1<component; ++ int i; ++ ++ switch (params_format(params)) { ++ case SNDRV_PCM_FORMAT_S16_LE: ++ snd_soc_component_update_bits(component, AC_I2S_FMT0, ++ (7<dev, "unrecognized format support\n"); ++ break; ++ } ++ for (i = 0; i < ARRAY_SIZE(sample_rate_conv); i++) { ++ if (sample_rate_conv[i].samplerate == params_rate(params)) { ++ snd_soc_component_update_bits(component, AC_SYS_SR_CTL, ++ (SYS_SR_MASK<component; ++ ++ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { ++ /* codec clk & FRM master */ ++ case SND_SOC_DAIFMT_CBM_CFM: ++ snd_soc_component_update_bits(component, AC_I2S_CLK, ++ (0x1<dev, "format setting failed\n"); ++ break; ++ } ++ ++ switch (fmt & SND_SOC_DAIFMT_INV_MASK) { ++ case SND_SOC_DAIFMT_NB_NF: ++ snd_soc_component_update_bits(component, AC_I2S_FMT1, ++ (0x1<dev, "invert clk setting failed\n"); ++ return -EINVAL; ++ } ++ return 0; ++} ++ ++static int acx00_codec_dai_set_clkdiv(struct snd_soc_dai *codec_dai, ++ int clk_id, int clk_div) ++{ ++ struct acx00_priv *priv = snd_soc_dai_get_drvdata(codec_dai); ++ struct snd_soc_component *component = priv->component; ++ unsigned int bclk_div; ++ /* ++ * when PCM mode, setting as 64fs, when I2S mode as 32fs, ++ * then two channel, then just as 64fs ++ */ ++ unsigned int div_ratio = clk_div / 64; ++ ++ switch (div_ratio) { ++ case 1: ++ bclk_div = I2S_BCLK_DIV_1; ++ break; ++ case 2: ++ bclk_div = I2S_BCLK_DIV_2; ++ break; ++ case 4: ++ bclk_div = I2S_BCLK_DIV_3; ++ break; ++ case 6: ++ bclk_div = I2S_BCLK_DIV_4; ++ break; ++ case 8: ++ bclk_div = I2S_BCLK_DIV_5; ++ break; ++ case 12: ++ bclk_div = I2S_BCLK_DIV_6; ++ break; ++ case 16: ++ bclk_div = I2S_BCLK_DIV_7; ++ break; ++ case 24: ++ bclk_div = I2S_BCLK_DIV_8; ++ break; ++ case 32: ++ bclk_div = I2S_BCLK_DIV_9; ++ break; ++ case 48: ++ bclk_div = I2S_BCLK_DIV_10; ++ break; ++ case 64: ++ bclk_div = I2S_BCLK_DIV_11; ++ break; ++ case 96: ++ bclk_div = I2S_BCLK_DIV_12; ++ break; ++ case 128: ++ bclk_div = I2S_BCLK_DIV_13; ++ break; ++ case 176: ++ bclk_div = I2S_BCLK_DIV_14; ++ break; ++ case 192: ++ bclk_div = I2S_BCLK_DIV_15; ++ break; ++ default: ++ dev_err(component->dev, "setting blck div failed\n"); ++ break; ++ } ++ ++ snd_soc_component_update_bits(component, AC_I2S_CLK, ++ (I2S_BCLK_DIV_MASK<component; ++ return 0; ++} ++ ++static int acx00_codec_prepare(struct snd_pcm_substream *substream, ++ struct snd_soc_dai *codec_dai) ++{ ++ struct snd_soc_component *component = codec_dai->component; ++ ++ snd_soc_component_update_bits(component, AC_SYS_CLK_CTL, ++ (0x1<stream == SNDRV_PCM_STREAM_PLAYBACK) { ++ if (acx00_loop_en) ++ snd_soc_component_update_bits(component, AC_I2S_FMT0, ++ (0x1<component; ++ ++ if (mute) ++ snd_soc_component_write(component, AC_I2S_DAC_VOL, 0); ++ else ++ snd_soc_component_write(component, AC_I2S_DAC_VOL, ACX00_DEF_VOL); ++ return 0; ++} ++ ++static void acx00_codec_shutdown(struct snd_pcm_substream *substream, ++ struct snd_soc_dai *dai) ++{ ++ struct snd_soc_component *component = dai->component; ++ ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ++ acx00_codec_txctrl_enable(component, 0); ++ else ++ acx00_codec_rxctrl_enable(component, 0); ++} ++ ++static const struct snd_soc_dai_ops acx00_codec_dai_ops = { ++ .hw_params = acx00_codec_hw_params, ++ .shutdown = acx00_codec_shutdown, ++// .digital_mute = acx00_codec_digital_mute, ++ .set_sysclk = acx00_codec_dai_set_sysclk, ++ .set_fmt = acx00_codec_dai_set_fmt, ++ .set_clkdiv = acx00_codec_dai_set_clkdiv, ++ .startup = acx00_codec_startup, ++ .trigger = acx00_codec_trigger, ++ .prepare = acx00_codec_prepare, ++}; ++ ++static struct snd_soc_dai_driver acx00_codec_dai[] = { ++ { ++ .name = "acx00-dai", ++ .playback = { ++ .stream_name = "Playback", ++ .channels_min = 1, ++ .channels_max = 2, ++ .rates = SNDRV_PCM_RATE_8000_192000 ++ | SNDRV_PCM_RATE_KNOT, ++ .formats = SNDRV_PCM_FMTBIT_S16_LE ++ | SNDRV_PCM_FMTBIT_S24_LE ++ | SNDRV_PCM_FMTBIT_S32_LE, ++ }, ++ ++ .capture = { ++ .stream_name = "Capture", ++ .channels_min = 1, ++ .channels_max = 2, ++ .rates = SNDRV_PCM_RATE_8000_192000 ++ | SNDRV_PCM_RATE_KNOT, ++ .formats = SNDRV_PCM_FMTBIT_S16_LE ++ | SNDRV_PCM_FMTBIT_S24_LE ++ | SNDRV_PCM_FMTBIT_S32_LE, ++ }, ++ ++ .ops = &acx00_codec_dai_ops, ++ }, ++}; ++ ++static void acx00_codec_resume_work(struct work_struct *work) ++{ ++ struct acx00_priv *priv = container_of(work, ++ struct acx00_priv, resume_work.work); ++ ++ acx00_codec_init(priv->component); ++} ++ ++static int acx00_codec_probe(struct snd_soc_component *component) ++{ ++ struct acx00_priv *priv = snd_soc_component_get_drvdata(component); ++ struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); ++ int ret = 0; ++ ++ mutex_init(&priv->mutex); ++ ++ priv->component = component; ++#if 0 ++ /* Add virtual switch */ ++ ret = snd_soc_add_component_controls(component, acx00_codec_controls, ++ ARRAY_SIZE(acx00_codec_controls)); ++ if (ret) { ++ pr_err("[audio-codec] Failed to register audio mode control, will continue without it.\n"); ++ } ++ snd_soc_dapm_new_controls(dapm, acx00_codec_dapm_widgets, ARRAY_SIZE(acx00_codec_dapm_widgets)); ++ snd_soc_dapm_add_routes(dapm, acx00_codec_dapm_routes, ARRAY_SIZE(acx00_codec_dapm_routes)); ++#endif ++ /* using late_initcall to wait 120ms acx00-core to make chip reset */ ++ acx00_codec_init(component); ++ INIT_DELAYED_WORK(&priv->spk_work, acx00_spk_enable); ++ INIT_DELAYED_WORK(&priv->resume_work, acx00_codec_resume_work); ++ return 0; ++} ++ ++static void acx00_codec_remove(struct snd_soc_component *component) ++{ ++ struct acx00_priv *priv = snd_soc_component_get_drvdata(component); ++ ++ cancel_delayed_work_sync(&priv->spk_work); ++ cancel_delayed_work_sync(&priv->resume_work); ++} ++ ++static unsigned int acx00_codec_read(struct snd_soc_component *component, ++ unsigned int reg) ++{ ++ unsigned int data; ++ struct acx00_priv *priv = snd_soc_component_get_drvdata(component); ++ ++ /* Device I/O API */ ++ data = acx00_reg_read(priv->acx00, reg); ++ return data; ++} ++ ++static int acx00_codec_write(struct snd_soc_component *component, ++ unsigned int reg, unsigned int value) ++{ ++ struct acx00_priv *priv = snd_soc_component_get_drvdata(component); ++ ++ return acx00_reg_write(priv->acx00, reg, value); ++} ++ ++static int sunxi_gpio_iodisable(u32 gpio) ++{ ++ char pin_name[8]; ++ u32 config, ret; ++#if 0 ++ sunxi_gpio_to_name(gpio, pin_name); ++ config = 7 << 16; ++ ret = pin_config_set(SUNXI_PINCTRL, pin_name, config); ++#endif ++ return ret; ++} ++ ++static int acx00_codec_suspend(struct snd_soc_component *component) ++{ ++ struct acx00_priv *priv = snd_soc_component_get_drvdata(component); ++ ++ pr_debug("Enter %s\n", __func__); ++ ++ clk_disable_unprepare(priv->clk); ++ ++ /* PA_CTRL first setting low state, then make it iodisabled */ ++ if (priv->spk_gpio_used) { ++ sunxi_gpio_iodisable(priv->spk_gpio); ++ msleep(30); ++ } ++ ++ /* ++ * when codec suspend, then the register reset, if auto reset produce ++ * Pop & Click noise, then we should cut down the LINEOUT in this town. ++ */ ++ if (priv->enable) { ++ snd_soc_component_update_bits(component, AC_LINEOUT_CTL, ++ (1<component, AC_LINEOUT_CTL, ++ (1<component, AC_LINEOUT_CTL, ++ (1<enable = 0; ++ } ++ ++ pr_debug("Exit %s\n", __func__); ++ ++ return 0; ++} ++ ++static int acx00_codec_resume(struct snd_soc_component *component) ++{ ++ struct acx00_priv *priv = snd_soc_component_get_drvdata(component); ++ ++ pr_debug("Enter %s\n", __func__); ++ ++ if (clk_prepare_enable(priv->clk)) { ++ dev_err(component->dev, "codec resume clk failed\n"); ++ return -EBUSY; ++ } ++ ++ schedule_delayed_work(&priv->resume_work, msecs_to_jiffies(300)); ++ ++ if (priv->spk_gpio_used) { ++ gpio_direction_output(priv->spk_gpio, 1); ++ gpio_set_value(priv->spk_gpio, 0); ++ } ++ ++ pr_debug("Exit %s\n", __func__); ++ ++ return 0; ++} ++ ++ ++static int acx00_codec_set_bias_level(struct snd_soc_component *component, ++ enum snd_soc_bias_level level) ++{ ++ component->dapm.bias_level = level; ++ return 0; ++} ++ ++struct label { ++ const char *name; ++ int value; ++}; ++ ++#define LABEL(constant) { #constant, constant } ++#define LABEL_END { NULL, -1 } ++ ++static struct label reg_labels[] = { ++ LABEL(AC_SYS_CLK_CTL), ++ LABEL(AC_SYS_MOD_RST), ++ LABEL(AC_SYS_SR_CTL), ++ LABEL(AC_I2S_CTL), ++ LABEL(AC_I2S_CLK), ++ LABEL(AC_I2S_FMT0), ++ LABEL(AC_I2S_FMT1), ++ LABEL(AC_I2S_MIXER_SRC), ++ LABEL(AC_I2S_MIXER_GAIN), ++ LABEL(AC_I2S_DAC_VOL), ++ LABEL(AC_I2S_ADC_VOL), ++ LABEL(AC_DAC_CTL), ++ LABEL(AC_DAC_MIXER_SRC), ++ LABEL(AC_DAC_MIXER_GAIN), ++ LABEL(AC_OUT_MIXER_CTL), ++ LABEL(AC_OUT_MIXER_SRC), ++ LABEL(AC_LINEOUT_CTL), ++ LABEL(AC_ADC_CTL), ++ LABEL(AC_MICBIAS_CTL), ++ LABEL(AC_ADC_MIC_CTL), ++ LABEL(AC_ADC_MIXER_SRC), ++ LABEL(AC_BIAS_CTL), ++ LABEL(AC_ANALOG_PROF_CTL), ++ LABEL_END, ++}; ++ ++static ssize_t show_audio_reg(struct device *dev, ++ struct device_attribute *attr, char *buf) ++{ ++ struct acx00_priv *priv = dev_get_drvdata(dev); ++ int count = 0, i = 0; ++ unsigned int reg_val; ++ ++ count += sprintf(buf, "dump audio reg:\n"); ++ ++ while (reg_labels[i].name != NULL) { ++ reg_val = acx00_reg_read(priv->acx00, reg_labels[i].value); ++ count += sprintf(buf + count, "%s 0x%x: 0x%x\n", ++ reg_labels[i].name, (reg_labels[i].value), reg_val); ++ i++; ++ } ++ ++ return count; ++} ++ ++/* ++ * param 1: 0 read;1 write ++ * param 2: 1 digital reg; 2 analog reg ++ * param 3: reg value; ++ * param 4: write value; ++ * read: ++ * echo 0,1,0x00> audio_reg ++ * echo 0,2,0x00> audio_reg ++ * write: ++ * echo 1,1,0x00,0xa > audio_reg ++ * echo 1,2,0x00,0xff > audio_reg ++*/ ++static ssize_t store_audio_reg(struct device *dev, ++ struct device_attribute *attr, const char *buf, size_t count) ++{ ++ int ret; ++ int rw_flag; ++ unsigned int input_reg_val = 0; ++ int input_reg_group = 0; ++ unsigned int input_reg_offset = 0; ++ struct acx00_priv *priv = dev_get_drvdata(dev); ++ ++ ret = sscanf(buf, "%d,%d,0x%x,0x%x", &rw_flag, &input_reg_group, ++ &input_reg_offset, &input_reg_val); ++ dev_info(dev, "ret:%d, reg_group:%d, reg_offset:%d, reg_val:0x%x\n", ++ ret, input_reg_group, input_reg_offset, input_reg_val); ++ ++ if (input_reg_group != 1) { ++ pr_err("not exist reg group\n"); ++ ret = count; ++ goto out; ++ } ++ if (!(rw_flag == 1 || rw_flag == 0)) { ++ pr_err("not rw_flag\n"); ++ ret = count; ++ goto out; ++ } ++ ++ if (rw_flag) { ++ acx00_reg_write(priv->acx00, input_reg_offset, input_reg_val); ++ } else { ++ input_reg_val = acx00_reg_read(priv->acx00, input_reg_offset); ++ dev_info(dev, "\n\n Reg[0x%x] : 0x%04x\n\n", ++ input_reg_offset, input_reg_val); ++ } ++ ret = count; ++ ++out: ++ return ret; ++} ++ ++static DEVICE_ATTR(audio_reg, 0644, show_audio_reg, store_audio_reg); ++ ++static struct attribute *audio_debug_attrs[] = { ++ &dev_attr_audio_reg.attr, ++ NULL, ++}; ++ ++static struct attribute_group audio_debug_attr_group = { ++ .name = "audio_reg_debug", ++ .attrs = audio_debug_attrs, ++}; ++ ++static struct snd_soc_component_driver soc_codec_driver_acx00 = { ++ .probe = acx00_codec_probe, ++ .remove = acx00_codec_remove, ++ .suspend = acx00_codec_suspend, ++ .resume = acx00_codec_resume, ++ .read = acx00_codec_read, ++ .write = acx00_codec_write, ++// .ignore_pmdown_time = 1, ++ .set_bias_level = acx00_codec_set_bias_level, ++ .controls = acx00_codec_controls, ++ .num_controls = ARRAY_SIZE(acx00_codec_controls), ++ .dapm_widgets = acx00_codec_dapm_widgets, ++ .num_dapm_widgets = ARRAY_SIZE(acx00_codec_dapm_widgets), ++ .dapm_routes = acx00_codec_dapm_routes, ++ .num_dapm_routes = ARRAY_SIZE(acx00_codec_dapm_routes), ++}; ++ ++/* through acx00 is part of mfd devices, after the mfd */ ++static int acx00_codec_dev_probe(struct platform_device *pdev) ++{ ++ struct acx00_priv *priv; ++ int ret; ++ struct device_node *np = of_find_compatible_node(NULL, NULL, "allwinner,ac200_codec"); ++ ++ priv = devm_kzalloc(&pdev->dev, sizeof(struct acx00_priv), GFP_KERNEL); ++ if (!priv) { ++ dev_err(&pdev->dev, "acx00 codec priv mem alloc failed\n"); ++ return -ENOMEM; ++ } ++ ++ platform_set_drvdata(pdev, priv); ++ priv->acx00 = dev_get_drvdata(pdev->dev.parent); ++ ++ if (np) { ++ ret = of_get_named_gpio(np, "gpio-spk", 0); ++ if (ret >= 0) { ++ priv->spk_gpio_used = 1; ++ priv->spk_gpio = ret; ++ if (!gpio_is_valid(priv->spk_gpio)) { ++ dev_err(&pdev->dev, "gpio-spk is valid\n"); ++ ret = -EINVAL; ++ goto err_devm_kfree; ++ } else { ++ ret = devm_gpio_request(&pdev->dev, ++ priv->spk_gpio, "SPK"); ++ if (ret) { ++ dev_err(&pdev->dev, ++ "failed request gpio-spk\n"); ++ ret = -EBUSY; ++ goto err_devm_kfree; ++ } else { ++ gpio_direction_output(priv->spk_gpio, ++ 1); ++ gpio_set_value(priv->spk_gpio, 0); ++ } ++ } ++ } else { ++ priv->spk_gpio_used = 0; ++ } ++ ++ ret = of_get_named_gpio(np, "gpio-switch", 0); ++ if (ret >= 0) { ++ priv->switch_gpio = ret; ++ if (!gpio_is_valid(priv->switch_gpio)) { ++ dev_err(&pdev->dev, "gpio-switch is valid\n"); ++ ret = -EINVAL; ++ goto err_devm_kfree; ++ } else { ++ ret = devm_gpio_request(&pdev->dev, priv->switch_gpio, "SWITCH"); ++ if (ret) { ++ dev_err(&pdev->dev, ++ "failed request gpio-switch\n"); ++ ret = -EBUSY; ++ goto err_devm_kfree; ++ } else { ++ gpio_direction_output(priv->switch_gpio, 1); ++ gpio_set_value(priv->switch_gpio, 1); ++ } ++ } ++ } ++ } ++ ++ ret = snd_soc_register_component(&pdev->dev, &soc_codec_driver_acx00, ++ acx00_codec_dai, ARRAY_SIZE(acx00_codec_dai)); ++ ++ if (ret < 0) ++ dev_err(&pdev->dev, "Failed register acx00: %d\n", ret); ++ ++ ret = sysfs_create_group(&pdev->dev.kobj, &audio_debug_attr_group); ++ if (ret) ++ dev_warn(&pdev->dev, "failed to create attr group\n"); ++ ++ return 0; ++ ++err_devm_kfree: ++ devm_kfree(&pdev->dev, priv); ++ return ret; ++} ++ ++/* Mark this space to clear the LINEOUT & gpio */ ++static void acx00_codec_dev_shutdown(struct platform_device *pdev) ++{ ++ struct acx00_priv *priv = platform_get_drvdata(pdev); ++ ++ if (priv->spk_gpio_used) ++ gpio_set_value(priv->spk_gpio, 0); ++} ++ ++static int acx00_codec_dev_remove(struct platform_device *pdev) ++{ ++ struct acx00_priv *priv = platform_get_drvdata(pdev); ++ ++#ifndef ACX00_DAPM_LINEOUT ++ /* ++ snd_soc_component_update_bits(priv->component, AC_LINEOUT_CTL, ++ (1<dev); ++ clk_disable_unprepare(priv->clk); ++ devm_kfree(&pdev->dev, priv); ++ return 0; ++} ++ ++static const struct of_device_id acx00_codec_match[] = { ++ { .compatible = "x-powers,ac200-codec" }, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, acx00_codec_match); ++ ++static struct platform_driver acx00_codec_driver = { ++ .driver = { ++ .name = "acx00-codec", ++ .of_match_table = acx00_codec_match, ++ }, ++ .probe = acx00_codec_dev_probe, ++ .remove = acx00_codec_dev_remove, ++ .shutdown = acx00_codec_dev_shutdown, ++}; ++ ++static int __init acx00_codec_driver_init(void) ++{ ++ return platform_driver_register(&acx00_codec_driver); ++} ++ ++static void __exit acx00_codec_driver_exit(void) ++{ ++ platform_driver_unregister(&acx00_codec_driver); ++} ++late_initcall(acx00_codec_driver_init); ++module_exit(acx00_codec_driver_exit); ++ ++MODULE_LICENSE("GPL"); ++MODULE_DESCRIPTION("SUNXI ASoC ACX00 Codec Driver"); ++MODULE_AUTHOR("wolfgang huang"); ++MODULE_ALIAS("platform:acx00-codec"); +diff --git a/sound/soc/codecs/acx00.h b/sound/soc/codecs/acx00.h +new file mode 100644 +index 000000000..5137cf365 +--- /dev/null ++++ b/sound/soc/codecs/acx00.h +@@ -0,0 +1,356 @@ ++/* ++ * sound\soc\codecs\acx00.h ++ * (C) Copyright 2012-2016 ++ * Allwinner Technology Co., Ltd. ++ * Wolfgang Huang ++ * ++ * some simple description for this code ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ */ ++ ++#ifndef __ACX00_H_ ++#define __ACX00_H_ ++ ++/* ACX00 register offset list */ ++#define AC_SYS_CLK_CTL 0x2000 ++#define AC_SYS_MOD_RST 0x2002 ++#define AC_SYS_SR_CTL 0x2004 ++/* Left blank */ ++#define AC_I2S_CTL 0x2100 ++#define AC_I2S_CLK 0x2102 ++#define AC_I2S_FMT0 0x2104 ++/* Left blank */ ++#define AC_I2S_FMT1 0x2108 ++/* Left blank */ ++#define AC_I2S_MIXER_SRC 0x2114 ++#define AC_I2S_MIXER_GAIN 0x2116 ++#define AC_I2S_DAC_VOL 0x2118 ++#define AC_I2S_ADC_VOL 0x211A ++/* Left blank */ ++#define AC_DAC_CTL 0x2200 ++#define AC_DAC_MIXER_SRC 0x2202 ++#define AC_DAC_MIXER_GAIN 0x2204 ++/* Left blank */ ++#define AC_OUT_MIXER_CTL 0x2220 ++#define AC_OUT_MIXER_SRC 0x2222 ++#define AC_LINEOUT_CTL 0x2224 ++/* Left blank */ ++#define AC_ADC_CTL 0x2300 ++/* Left blank */ ++#define AC_MICBIAS_CTL 0x2310 ++/* Left blank */ ++#define AC_ADC_MIC_CTL 0x2320 ++#define AC_ADC_MIXER_SRC 0x2322 ++/* Left blank */ ++#define AC_BIAS_CTL 0x232A ++#define AC_ANALOG_PROF_CTL 0x232C ++/* Left blank */ ++#define AC_ADC_DAPL_CTRL 0x2500 ++#define AC_ADC_DAPR_CTRL 0x2502 ++#define AC_ADC_DAPLSTA 0x2504 ++#define AC_ADC_DAPRSTA 0x2506 ++#define AC_ADC_DAP_LTL 0x2508 ++#define AC_ADC_DAP_RTL 0x250A ++#define AC_ADC_DAP_LHAC 0x250C ++#define AC_ADC_DAP_LLAC 0x250E ++#define AC_ADC_DAP_RHAC 0x2510 ++#define AC_ADC_DAP_RLAC 0x2512 ++#define AC_ADC_DAP_LDT 0x2514 ++#define AC_ADC_DAP_LAT 0x2516 ++#define AC_ADC_DAP_RDT 0x2518 ++#define AC_ADC_DAP_RAT 0x251A ++#define AC_ADC_DAP_NTH 0x251C ++#define AC_ADC_DAP_LHNAC 0x251E ++#define AC_ADC_DAP_LLNAC 0x2520 ++#define AC_ADC_DAP_RHNAC 0x2522 ++#define AC_ADC_DAP_RLNAC 0x2524 ++#define AC_ADC_DAP_HHPFC 0x2526 ++#define AC_ADC_DAP_LHPFC 0x2528 ++#define AC_ADC_DAP_OPT 0x252A ++/* Left blank */ ++#define AC_AGC_SEL 0x2480 ++/* Left blank */ ++#define AC_ADC_DAPL_CTRL 0x2500 ++#define AC_ADC_DAPR_CTRL 0x2502 ++#define AC_ADC_DAPLSTA 0x2504 ++#define AC_ADC_DAPRSTA 0x2506 ++#define AC_ADC_DAP_LTL 0x2508 ++#define AC_ADC_DAP_RTL 0x250A ++#define AC_ADC_DAP_LHAC 0x250C ++#define AC_ADC_DAP_LLAC 0x250E ++#define AC_ADC_DAP_RHAC 0x2510 ++#define AC_ADC_DAP_RLAC 0x2512 ++#define AC_ADC_DAP_LDT 0x2514 ++#define AC_ADC_DAP_LAT 0x2516 ++#define AC_ADC_DAP_RDT 0x2518 ++#define AC_ADC_DAP_RAT 0x251A ++#define AC_ADC_DAP_NTH 0x251C ++#define AC_ADC_DAP_LHNAC 0x251E ++#define AC_ADC_DAP_LLNAC 0x2520 ++#define AC_ADC_DAP_RHNAC 0x2522 ++#define AC_ADC_DAP_RLNAC 0x2524 ++#define AC_ADC_DAP_HHPFC 0x2526 ++#define AC_ADC_DAP_LHPFC 0x2528 ++#define AC_ADC_DAP_OPT 0x252A ++/* Left blank */ ++#define AC_DRC_SEL 0x2f80 ++/* Left blank */ ++#define AC_DRC_CHAN_CTRL 0x3000 ++#define AC_DRC_HHPFC 0x3002 ++#define AC_DRC_LHPFC 0x3004 ++#define AC_DRC_CTRL 0x3006 ++#define AC_DRC_LPFHAT 0x3008 ++#define AC_DRC_LPFLAT 0x300A ++#define AC_DRC_RPFHAT 0x300C ++#define AC_DRC_RPFLAT 0x300E ++#define AC_DRC_LPFHRT 0x3010 ++#define AC_DRC_LPFLRT 0x3012 ++#define AC_DRC_RPFHRT 0x3014 ++#define AC_DRC_RPFLRT 0x3016 ++#define AC_DRC_LRMSHAT 0x3018 ++#define AC_DRC_LRMSLAT 0x301A ++#define AC_DRC_RRMSHAT 0x301C ++#define AC_DRC_RRMSLAT 0x301E ++#define AC_DRC_HCT 0x3020 ++#define AC_DRC_LCT 0x3022 ++#define AC_DRC_HKC 0x3024 ++#define AC_DRC_LKC 0x3026 ++#define AC_DRC_HOPC 0x3028 ++#define AC_DRC_LOPC 0x302A ++#define AC_DRC_HLT 0x302C ++#define AC_DRC_LLT 0x302E ++#define AC_DRC_HKI 0x3030 ++#define AC_DRC_LKI 0x3032 ++#define AC_DRC_HOPL 0x3034 ++#define AC_DRC_LOPL 0x3036 ++#define AC_DRC_HET 0x3038 ++#define AC_DRC_LET 0x303A ++#define AC_DRC_HKE 0x303C ++#define AC_DRC_LKE 0x303E ++#define AC_DRC_HOPE 0x3040 ++#define AC_DRC_LOPE 0x3042 ++#define AC_DRC_HKN 0x3044 ++#define AC_DRC_LKN 0x3046 ++#define AC_DRC_SFHAT 0x3048 ++#define AC_DRC_SFLAT 0x304A ++#define AC_DRC_SFHRT 0x304C ++#define AC_DRC_SFLRT 0x304E ++#define AC_DRC_MXGHS 0x3050 ++#define AC_DRC_MXGLS 0x3052 ++#define AC_DRC_MNGHS 0x3054 ++#define AC_DRC_MNGLS 0x3056 ++#define AC_DRC_EPSHC 0x3058 ++#define AC_DRC_EPSLC 0x305A ++#define AC_DRC_OPT 0x305C ++#define AC_DRC_HPFHGAIN 0x305E ++#define AC_DRC_HPFLGAIN 0x3060 ++#define AC_DRC_BISTCR 0x3100 ++#define AC_DRC_BISTST 0x3102 ++ ++/* AC_SYS_CLK_CTL : 0x2000 */ ++#define SYS_CLK_I2S 15 ++#define SYS_CLK_AGC 7 ++#define SYS_CLK_DRC 6 ++#define SYS_CLK_ADC 3 ++#define SYS_CLK_DAC 2 ++ ++/* AC_SYS_MOD_RST : 0x2002 */ ++#define MOD_RST_I2S 15 ++#define MOD_RST_AGC 7 ++#define MOD_RST_DRC 6 ++#define MOD_RST_ADC 3 ++#define MOD_RST_DAC 2 ++ ++/* AC_SYS_SR_CTL : 0x2004 */ ++#define SYS_SR_BIT 0 ++#define SYS_SR_MASK 0xF ++#define SYS_SR_BIT_0 0 /* 8000 */ ++#define SYS_SR_BIT_1 1 /* 11025 */ ++#define SYS_SR_BIT_2 2 /* 12000 */ ++#define SYS_SR_BIT_3 3 /* 16000 */ ++#define SYS_SR_BIT_4 4 /* 22050 */ ++#define SYS_SR_BIT_5 5 /* 24000 */ ++#define SYS_SR_BIT_6 6 /* 32000 */ ++#define SYS_SR_BIT_7 7 /* 44100 */ ++#define SYS_SR_BIT_8 8 /* 48000 */ ++#define SYS_SR_BIT_9 9 /* 96000 */ ++#define SYS_SR_BIT_10 10 /* 192000 */ ++ ++/* AC_I2S_CTL : 0x2100 */ ++#define I2S_SDO0_EN 3 ++#define I2S_TX_EN 2 ++#define I2S_RX_EN 1 ++#define I2S_GEN 0 ++ ++/* AC_I2S_CLK : 0x2102 */ ++#define I2S_BCLK_OUT 15 ++#define I2S_LRCK_OUT 14 ++#define I2S_BLCK_DIV 10 ++#define I2S_LRCK_PERIOD 0 ++/* BCLK DIV Define */ ++#define I2S_BCLK_DIV_MASK 0xF ++#define I2S_BCLK_DIV_1 1 ++#define I2S_BCLK_DIV_2 2 ++#define I2S_BCLK_DIV_3 3 ++#define I2S_BCLK_DIV_4 4 ++#define I2S_BCLK_DIV_5 5 ++#define I2S_BCLK_DIV_6 6 ++#define I2S_BCLK_DIV_7 7 ++#define I2S_BCLK_DIV_8 8 ++#define I2S_BCLK_DIV_9 9 ++#define I2S_BCLK_DIV_10 10 ++#define I2S_BCLK_DIV_11 11 ++#define I2S_BCLK_DIV_12 12 ++#define I2S_BCLK_DIV_13 13 ++#define I2S_BCLK_DIV_14 14 ++#define I2S_BCLK_DIV_15 15 ++#define I2S_LRCK_PERIOD_MASK 0x3FF ++ ++/* AC_I2S_FMT0 : 0x2104 */ ++#define I2S_FMT_MODE 14 ++#define I2S_FMT_TX_OFFSET 10 ++#define I2S_FMT_RX_OFFSET 8 ++#define I2S_FMT_SAMPLE 4 ++#define I2S_FMT_SLOT_WIDTH 1 ++#define I2S_FMT_LOOP 0 ++ ++/* AC_I2S_FMT1 : 0x2108 */ ++#define I2S_FMT_BCLK_POLAR 15 ++#define I2S_FMT_LRCK_POLAR 14 ++#define I2S_FMT_EDGE_TRANSFER 13 ++#define I2S_FMT_RX_MLS 11 ++#define I2S_FMT_TX_MLS 10 ++#define I2S_FMT_EXTEND 9 ++#define I2S_FMT_LRCK_WIDTH 4 /* PCM long/short Frame */ ++#define I2S_MFT_RX_PDM 2 ++#define I2S_FMT_TX_PDM 0 ++ ++/* AC_I2S_MIXER_SRC : 0x2114 */ ++#define I2S_MIXERL_SRC_DAC 13 ++#define I2S_MIXERL_SRC_ADC 12 ++#define I2S_MIXERR_SRC_DAC 9 ++#define I2S_MIXERR_SRC_ADC 8 ++ ++/* AC_I2S_MIXER_GAIN : 0x2116 */ ++#define I2S_MIXERL_GAIN_DAC 13 ++#define I2S_MIXERL_GAIN_ADC 12 ++#define I2S_MIXERR_GAIN_DAC 9 ++#define I2S_MIXERR_GAIN_ADC 8 ++ ++ ++/* AC_I2S_DAC_VOL : 0x2118 */ ++#define I2S_DACL_VOL 8 ++#define I2S_DACR_VOL 0 ++ ++/* AC_I2S_ADC_VOL : 0x211A */ ++#define I2S_ADCL_VOL 8 ++#define I2S_ADCR_VOL 0 ++ ++/* AC_DAC_CTL : 0x2200 */ ++#define DAC_CTL_DAC_EN 15 ++#define DAC_CTL_HPF_EN 14 ++#define DAC_CTL_FIR 13 ++#define DAC_CTL_MODQU 8 ++ ++/* AC_DAC_MIXER_SRC : 0x2202 */ ++#define DAC_MIXERL_SRC_DAC 13 ++#define DAC_MIXERL_SRC_ADC 12 ++#define DAC_MIXERR_SRC_DAC 9 ++#define DAC_MIXERR_SRC_ADC 8 ++ ++/* AC_DAC_MIXER_GAIN : 0x2204 */ ++#define DAC_MIXERL_GAIN_DAC 13 ++#define DAC_MIXERL_GAIN_ADC 12 ++#define DAC_MIXERR_GAIN_DAC 9 ++#define DAC_MIXERR_GAIN_ADC 8 ++ ++/* AC_OUT_MIXER_CTL : 0x2220 */ ++#define OUT_MIXER_DACR_EN 15 ++#define OUT_MIXER_DACL_EN 14 ++#define OUT_MIXER_RMIX_EN 13 ++#define OUT_MIXER_LMIX_EN 12 ++#define OUT_MIXER_LINE_VOL 8 ++#define OUT_MIXER_MIC1_VOL 4 ++#define OUT_MIXER_MIC2_VOL 0 ++ ++/* AC_OUT_MIXER_SRC : 0x2222 */ ++#define OUT_MIXERR_SRC_MIC1 14 ++#define OUT_MIXERR_SRC_MIC2 13 ++#define OUT_MIXERR_SRC_PHPN 12 ++#define OUT_MIXERR_SRC_PHP 11 ++#define OUT_MIXERR_SRC_LINER 10 ++#define OUT_MIXERR_SRC_DACR 9 ++#define OUT_MIXERR_SRC_DACL 8 ++#define OUT_MIXERL_SRC_MIC1 6 ++#define OUT_MIXERL_SRC_MIC2 5 ++#define OUT_MIXERL_SRC_PHPN 4 ++#define OUT_MIXERL_SRC_PHN 3 ++#define OUT_MIXERL_SRC_LINEL 2 ++#define OUT_MIXERL_SRC_DACL 1 ++#define OUT_MIXERL_SRC_DACR 0 ++ ++/* AC_LINEOUT_CTL : 0x2224 */ ++#define LINEOUT_EN 15 ++#define LINEL_SRC_EN 14 ++#define LINER_SRC_EN 13 ++#define LINEL_SRC 12 ++#define LINER_SRC 11 ++/* ramp just skip */ ++#define LINE_SLOPE_SEL 8 ++#define LINE_ANTI_TIME 5 ++#define LINEOUT_VOL 0 ++ ++/* AC_ADC_CTL : 0x2300 */ ++#define ADC_EN 15 ++#define ADC_ENDM 14 ++#define ADC_FIR 13 ++#define ADC_DELAY_TIME 2 ++#define ADC_DELAY_EN 1 ++ ++/* AC_MICBIAS_CTL : 0x2310 */ ++#define MMBIAS_EN 15 ++#define MMBIAS_CHOPPER 14 ++#define MMBIAS_CHOP_CLK 12 ++#define MMBIAS_SEL 8 ++#define ADDA_BIAS_CUR 3 ++ ++/* AC_ADC_MIC_CTL : 0x2320 */ ++#define ADCR_EN 15 ++#define ADCL_EN 14 ++#define ADC_GAIN 8 ++#define MIC1_GAIN_EN 7 ++#define MIC1_BOOST 4 ++#define MIC2_GAIN_EN 3 ++#define MIC2_BOOST 0 ++ ++/* AC_ADC_MIXER_SRC : 0x2322 */ ++#define ADC_MIXERR_MIC1 14 ++#define ADC_MIXERR_MIC2 13 ++#define ADC_MIXERR_PHPN 12 ++#define ADC_MIXERR_PHP 11 ++#define ADC_MIXERR_LINER 10 ++#define ADC_MIXERR_MIXR 9 ++#define ADC_MIXERR_MIXL 8 ++#define ADC_MIXERL_MIC1 6 ++#define ADC_MIXERL_MIC2 5 ++#define ADC_MIXERL_PHPN 4 ++#define ADC_MIXERL_PHN 3 ++#define ADC_MIXERL_LINEL 2 ++#define ADC_MIXERL_MIXL 1 ++#define ADC_MIXERL_MIXR 0 ++ ++/* AC_BIAS_CTL : 0x232A */ ++ ++/* AC_ANALOG_PROF_CTL : 0x232C */ ++/* used for current performance measure */ ++ ++/* AC_DLDO_OSC_CTL : 0x2340 */ ++/* AC_ALDO_CTL : 0x2342 */ ++/* used for digital & analog LDO test... etc */ ++ ++#endif +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-arm64-dts-Add-leds-axp20x-charger.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-arm64-dts-Add-leds-axp20x-charger.patch new file mode 100644 index 0000000000..73df1f3931 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-arm64-dts-Add-leds-axp20x-charger.patch @@ -0,0 +1,79 @@ +From 6c096e1d9a48522613f55eafb0a001cf2bdfda34 Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Sun, 23 Jan 2022 16:43:53 +0300 +Subject: [PATCH 051/153] arm:arm64:dts: Add leds axp20x charger + +--- + arch/arm/boot/dts/axp209.dtsi | 5 +++++ + arch/arm/boot/dts/axp22x.dtsi | 5 +++++ + arch/arm/boot/dts/axp81x.dtsi | 5 +++++ + arch/arm64/boot/dts/allwinner/axp803.dtsi | 5 +++++ + 4 files changed, 20 insertions(+) + +diff --git a/arch/arm/boot/dts/axp209.dtsi b/arch/arm/boot/dts/axp209.dtsi +index ca240cd6f..85000fdb4 100644 +--- a/arch/arm/boot/dts/axp209.dtsi ++++ b/arch/arm/boot/dts/axp209.dtsi +@@ -69,6 +69,11 @@ axp_gpio: gpio { + #gpio-cells = <2>; + }; + ++ axp_led: led { ++ compatible = "x-powers,axp20x-led"; ++ status = "disabled"; ++ }; ++ + battery_power_supply: battery-power { + compatible = "x-powers,axp209-battery-power-supply"; + status = "disabled"; +diff --git a/arch/arm/boot/dts/axp22x.dtsi b/arch/arm/boot/dts/axp22x.dtsi +index f79650afd..91c66b245 100644 +--- a/arch/arm/boot/dts/axp22x.dtsi ++++ b/arch/arm/boot/dts/axp22x.dtsi +@@ -62,6 +62,11 @@ axp_adc: adc { + #io-channel-cells = <1>; + }; + ++ axp_led: led { ++ compatible = "x-powers,axp20x-led"; ++ status = "disabled"; ++ }; ++ + battery_power_supply: battery-power { + compatible = "x-powers,axp221-battery-power-supply"; + status = "disabled"; +diff --git a/arch/arm/boot/dts/axp81x.dtsi b/arch/arm/boot/dts/axp81x.dtsi +index a4b1be159..9a432a0dc 100644 +--- a/arch/arm/boot/dts/axp81x.dtsi ++++ b/arch/arm/boot/dts/axp81x.dtsi +@@ -64,6 +64,11 @@ axp_gpio: gpio { + #gpio-cells = <2>; + }; + ++ axp_led: led { ++ compatible = "x-powers,axp20x-led"; ++ status = "disabled"; ++ }; ++ + battery_power_supply: battery-power { + compatible = "x-powers,axp813-battery-power-supply"; + status = "disabled"; +diff --git a/arch/arm64/boot/dts/allwinner/axp803.dtsi b/arch/arm64/boot/dts/allwinner/axp803.dtsi +index 422be59f5..3ad8967a1 100644 +--- a/arch/arm64/boot/dts/allwinner/axp803.dtsi ++++ b/arch/arm64/boot/dts/allwinner/axp803.dtsi +@@ -28,6 +28,11 @@ axp_gpio: gpio { + #gpio-cells = <2>; + }; + ++ axp_led: led { ++ compatible = "x-powers,axp20x-led"; ++ status = "disabled"; ++ }; ++ + battery_power_supply: battery-power { + compatible = "x-powers,axp803-battery-power-supply", + "x-powers,axp813-battery-power-supply"; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-Add-sun8i-h2-plus-nanopi-duo-device.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-Add-sun8i-h2-plus-nanopi-duo-device.patch new file mode 100644 index 0000000000..ae19e44824 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-Add-sun8i-h2-plus-nanopi-duo-device.patch @@ -0,0 +1,196 @@ +From aa17c952e04aeb40a32cc9250daaedc4fcbddcda Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Mon, 24 Jan 2022 15:00:36 +0300 +Subject: [PATCH 058/153] arm:dts: Add sun8i-h2-plus-nanopi-duo device + +--- + arch/arm/boot/dts/Makefile | 1 + + .../arm/boot/dts/sun8i-h2-plus-nanopi-duo.dts | 164 ++++++++++++++++++ + 2 files changed, 165 insertions(+) + create mode 100644 arch/arm/boot/dts/sun8i-h2-plus-nanopi-duo.dts + +diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile +index 0ce63f500..942e3c739 100644 +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -1357,6 +1357,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ + sun8i-a83t-tbs-a711.dtb \ + sun8i-h2-plus-bananapi-m2-zero.dtb \ + sun8i-h2-plus-libretech-all-h3-cc.dtb \ ++ sun8i-h2-plus-nanopi-duo.dtb \ + sun8i-h2-plus-orangepi-r1.dtb \ + sun8i-h2-plus-orangepi-zero.dtb \ + sun8i-h3-bananapi-m2-plus.dtb \ +diff --git a/arch/arm/boot/dts/sun8i-h2-plus-nanopi-duo.dts b/arch/arm/boot/dts/sun8i-h2-plus-nanopi-duo.dts +new file mode 100644 +index 000000000..2b31b8fdd +--- /dev/null ++++ b/arch/arm/boot/dts/sun8i-h2-plus-nanopi-duo.dts +@@ -0,0 +1,164 @@ ++/* ++ * adapted by karabek, 2018 , based on ++ * Copyright (C) 2016 James Pettigrew ++ * Copyright (C) 2016 Milo Kim ++ * ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This file is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License, or (at your option) any later version. ++ * ++ * This file is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++/dts-v1/; ++#include "sun8i-h3-nanopi.dtsi" ++#include ++ ++/ { ++ model = "FriendlyARM NanoPi DUO"; ++ compatible = "friendlyarm,nanopi-duo", "allwinner,sun8i-h3"; ++ ++ aliases { ++ ethernet0 = &emac; ++ ethernet1 = &xr819; ++ }; ++ ++ reg_sy8113b: gpio-regulator { ++ compatible = "regulator-gpio"; ++ regulator-name = "vdd-cpux"; ++ regulator-type = "voltage"; ++ regulator-boot-on; ++ regulator-always-on; ++ regulator-min-microvolt = <1100000>; ++ regulator-max-microvolt = <1300000>; ++ regulator-ramp-delay = <50>; // 50=4ms check ++ ++ gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; // PL6 check ++ enable-active-high; ++ gpios-states = <0x1>; ++ states = <1100000 0x0 ++ 1300000 0x1>; ++ }; ++ ++ reg_vcc_wifi: reg_vcc_wifi { ++ compatible = "regulator-fixed"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc-wifi"; ++ gpio = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; // PL7 WIFI_POWER_EN ++ startup-delay-us = <70000>; ++ enable-active-high; ++ }; ++ ++ wifi_pwrseq: wifi_pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&wifi_en_npi>; ++ reset-gpios = <&pio 6 13 GPIO_ACTIVE_LOW>; // PG13 WL_RESTN ++ post-power-on-delay-ms = <200>; ++ }; ++}; ++ ++&cpu0 { ++ cpu-supply = <®_sy8113b>; ++}; ++ ++&ehci0 { ++ status = "okay"; ++}; ++ ++&emac { ++ phy-handle = <&int_mii_phy>; ++ phy-mode = "mii"; ++ allwinner,leds-active-low; ++ status = "okay"; ++}; ++ ++&mmc1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc1_pins>; ++ vqmmc-supply = <®_vcc_wifi>; ++ vmmc-supply = <®_vcc3v3>; ++ mmc-pwrseq = <&wifi_pwrseq>; ++ bus-width = <4>; ++ non-removable; ++ status = "okay"; ++ ++ xr819: sdio_wifi@1 { ++ reg = <1>; ++ compatible = "xradio,xr819"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&wifi_wake>; ++ interrupt-parent = <&pio>; ++ interrupts = <6 10 IRQ_TYPE_EDGE_RISING>; ++ interrupt-names = "host-wake"; ++ }; ++}; ++ ++&mmc1_pins { ++ bias-pull-up; ++}; ++ ++&ohci0 { ++ status = "okay"; ++}; ++ ++&pio { ++ wifi_en_npi: wifi_en_pin { ++ pins = "PG13"; ++ function = "gpio_out"; ++ }; ++ wifi_wake: wifi_wake@0 { ++ pins = "PG10"; ++ function = "irq"; ++ pull = ; ++ }; ++}; ++ ++&usb_otg { ++ dr_mode = "peripheral"; ++ status = "okay"; ++}; ++ ++&usbphy { ++ /* ++ * USB Type-A port VBUS is always on. However, MicroUSB VBUS can only ++ * power up the board; when it's used as OTG port, this VBUS is ++ * always off even if the board is powered via GPIO pins. ++ */ ++ status = "okay"; ++ usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ ++}; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-Add-sun8i-h2-plus-sunvell-r69-device.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-Add-sun8i-h2-plus-sunvell-r69-device.patch new file mode 100644 index 0000000000..1e6888fb58 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-Add-sun8i-h2-plus-sunvell-r69-device.patch @@ -0,0 +1,257 @@ +From 588df001525f2abbb5dc693c91978ca4448df32c Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Mon, 24 Jan 2022 15:23:33 +0300 +Subject: [PATCH 059/153] arm:dts: Add sun8i-h2-plus-sunvell-r69 device + +--- + arch/arm/boot/dts/Makefile | 1 + + .../boot/dts/sun8i-h2-plus-sunvell-r69.dts | 225 ++++++++++++++++++ + 2 files changed, 226 insertions(+) + create mode 100644 arch/arm/boot/dts/sun8i-h2-plus-sunvell-r69.dts + +diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile +index 942e3c739..32710062a 100644 +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -1360,6 +1360,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ + sun8i-h2-plus-nanopi-duo.dtb \ + sun8i-h2-plus-orangepi-r1.dtb \ + sun8i-h2-plus-orangepi-zero.dtb \ ++ sun8i-h2-plus-sunvell-r69.dtb \ + sun8i-h3-bananapi-m2-plus.dtb \ + sun8i-h3-bananapi-m2-plus-v1.2.dtb \ + sun8i-h3-beelink-x2.dtb \ +diff --git a/arch/arm/boot/dts/sun8i-h2-plus-sunvell-r69.dts b/arch/arm/boot/dts/sun8i-h2-plus-sunvell-r69.dts +new file mode 100644 +index 000000000..bb0c2f72b +--- /dev/null ++++ b/arch/arm/boot/dts/sun8i-h2-plus-sunvell-r69.dts +@@ -0,0 +1,225 @@ ++// SPDX-License-Identifier: (GPL-2.0+ or MIT) ++/* ++ * Based original Sunvell R69 FEX file (2019 karabek) ++ */ ++ ++/dts-v1/; ++#include "sun8i-h3.dtsi" ++#include "sunxi-common-regulators.dtsi" ++ ++#include ++#include ++#include ++ ++/ { ++ model = "Sunvell R69"; ++ compatible = "sunvell,sunvell-r69", "allwinner,sun8i-h2-plus"; ++ ++ aliases { ++ ethernet0 = &emac; ++ ethernet1 = &xr819; ++ serial0 = &uart0; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ connector { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi_con_in: endpoint { ++ remote-endpoint = <&hdmi_out_con>; ++ }; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&leds_opc>, <&leds_r_opc>; ++ ++ pwr_led { ++ label = "sunvell-r69:red:pwr"; ++ gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ status_led { ++ label = "sunvell-r69:blue:status"; ++ gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "heartbeat"; ++ }; ++ }; ++ ++ reg_vdd_cpux: vdd-cpux-regulator { ++ compatible = "regulator-gpio"; ++ regulator-name = "vdd-cpux"; ++ regulator-type = "voltage"; ++ regulator-boot-on; ++ regulator-always-on; ++ regulator-min-microvolt = <1100000>; ++ regulator-max-microvolt = <1300000>; ++ regulator-ramp-delay = <50>; /* 4ms */ ++ ++ gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ ++ enable-active-high; ++ gpios-states = <0x1>; ++ states = <1100000 0x0 ++ 1300000 0x1>; ++ }; ++ ++ reg_vcc_wifi: reg_vcc_wifi { ++ compatible = "regulator-fixed"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-wifi"; ++ gpio = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; ++ startup-delay-us = <70000>; ++ enable-active-high; ++ }; ++ ++ wifi_pwrseq: wifi_pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ reset-gpios = <&r_pio 0 0 GPIO_ACTIVE_LOW>; ++ post-power-on-delay-ms = <200>; ++ }; ++}; ++ ++&cpu0 { ++ cpu-supply = <®_vdd_cpux>; ++}; ++ ++&de { ++ status = "okay"; ++}; ++ ++&ehci0 { ++ status = "okay"; ++}; ++ ++&ehci1 { ++ status = "okay"; ++}; ++ ++&emac { ++ phy-handle = <&int_mii_phy>; ++ phy-mode = "mii"; ++ allwinner,leds-active-low; ++ status = "okay"; ++}; ++ ++&hdmi { ++ status = "okay"; ++}; ++ ++&hdmi_out { ++ hdmi_out_con: endpoint { ++ remote-endpoint = <&hdmi_con_in>; ++ }; ++}; ++ ++&ir { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&r_ir_rx_pin>; /* <&r_ir_rx_pin> */ ++ status = "okay"; ++}; ++ ++&mmc0 { ++ vmmc-supply = <®_vcc3v3>; ++ bus-width = <4>; ++ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ ++ status = "okay"; ++}; ++ ++&mmc1 { ++ vmmc-supply = <®_vcc_wifi>; ++ mmc-pwrseq = <&wifi_pwrseq>; ++ bus-width = <4>; ++ non-removable; ++ status = "okay"; ++ ++ xr819: sdio_wifi@1 { ++ reg = <1>; ++ compatible = "xradio,xr819"; ++ interrupt-parent = <&pio>; ++ interrupts = <0 11 IRQ_TYPE_EDGE_RISING>; ++ interrupt-names = "host-wake"; ++ }; ++}; ++ ++&mmc2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc2_8bit_pins>; ++ vmmc-supply = <®_vcc3v3>; ++ bus-width = <8>; ++ non-removable; ++ cap-mmc-hw-reset; ++ status = "okay"; ++}; ++ ++&mmc2_8bit_pins { ++ /* Increase current from 30mA to 40mA for DDR eMMC */ ++ allwinner,drive = ; ++}; ++ ++&ohci0 { ++ status = "okay"; ++}; ++ ++&ohci1 { ++ status = "okay"; ++}; ++ ++&pio { ++ leds_opc: led_pins { ++ pins = "PA15"; ++ function = "gpio_out"; ++ }; ++}; ++ ++&r_pio { ++ leds_r_opc: led_pins { ++ pins = "PL10"; ++ function = "gpio_out"; ++ }; ++}; ++ ++®_usb0_vbus { ++ gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */ ++ status = "okay"; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pa_pins>; ++ status = "okay"; ++}; ++ ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1_pins>; ++ status = "disabled"; ++}; ++ ++&uart2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart2_pins>; ++ status = "disabled"; ++}; ++ ++&uart3 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart3_pins>; ++ status = "disabled"; ++}; ++ ++&usb_otg { ++ dr_mode = "host"; ++ status = "okay"; ++}; ++ ++&usbphy { ++ status = "okay"; ++}; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-a10-cubiebord-a20-cubietruck-green-LED-mmc0-default-tri.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-a10-cubiebord-a20-cubietruck-green-LED-mmc0-default-tri.patch new file mode 100644 index 0000000000..08b91321b3 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-a10-cubiebord-a20-cubietruck-green-LED-mmc0-default-tri.patch @@ -0,0 +1,39 @@ +From 4d62c12a6d7fac8c7f40010628f411c928597d51 Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Mon, 24 Jan 2022 14:46:11 +0300 +Subject: [PATCH 057/153] arm:dts: a10-cubiebord a20-cubietruck green LED mmc0 + default-trigger + +--- + arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 2 +- + arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 1 + + 2 files changed, 2 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts +index 0645d6064..f97b53c44 100644 +--- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts ++++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts +@@ -83,7 +83,7 @@ led-0 { + led-1 { + label = "cubieboard:green:usr"; + gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; /* LED2 */ +- linux,default-trigger = "heartbeat"; ++ linux,default-trigger = "mmc0"; + }; + }; + }; +diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts +index 525cb7fcc..df428f29b 100644 +--- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts ++++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts +@@ -93,6 +93,7 @@ led-2 { + led-3 { + label = "cubietruck:green:usr"; + gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "mmc0"; + }; + }; + +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-a20-orangepi-and-mini-fix-phy-mode-hdmi.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-a20-orangepi-and-mini-fix-phy-mode-hdmi.patch new file mode 100644 index 0000000000..417f26811f --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-a20-orangepi-and-mini-fix-phy-mode-hdmi.patch @@ -0,0 +1,86 @@ +From d0563a95220f0afeb0c85b79bc831e874d1452d9 Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Mon, 24 Jan 2022 13:18:28 +0300 +Subject: [PATCH 055/153] arm:dts: a20-orangepi and mini fix phy-mode, hdmi + +--- + arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts | 2 +- + arch/arm/boot/dts/sun7i-a20-orangepi.dts | 31 ++++++++++++++++++- + 2 files changed, 31 insertions(+), 2 deletions(-) + +diff --git a/arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts b/arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts +index 84efa01e7..fc87309ae 100644 +--- a/arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts ++++ b/arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts +@@ -121,7 +121,7 @@ &gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_rgmii_pins>; + phy-handle = <&phy1>; +- phy-mode = "rgmii"; ++ phy-mode = "rgmii-id"; + phy-supply = <®_gmac_3v3>; + status = "okay"; + }; +diff --git a/arch/arm/boot/dts/sun7i-a20-orangepi.dts b/arch/arm/boot/dts/sun7i-a20-orangepi.dts +index 5d77f1d98..0c760b0a5 100644 +--- a/arch/arm/boot/dts/sun7i-a20-orangepi.dts ++++ b/arch/arm/boot/dts/sun7i-a20-orangepi.dts +@@ -61,6 +61,17 @@ chosen { + stdout-path = "serial0:115200n8"; + }; + ++ hdmi-connector { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi_con_in: endpoint { ++ remote-endpoint = <&hdmi_out_con>; ++ }; ++ }; ++ }; ++ + leds { + compatible = "gpio-leds"; + +@@ -85,6 +96,14 @@ &ahci { + status = "okay"; + }; + ++&codec { ++ status = "okay"; ++}; ++ ++&de { ++ status = "okay"; ++}; ++ + &ehci0 { + status = "okay"; + }; +@@ -97,11 +116,21 @@ &gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_rgmii_pins>; + phy-handle = <&phy1>; +- phy-mode = "rgmii"; ++ phy-mode = "rgmii-id"; + phy-supply = <®_gmac_3v3>; + status = "okay"; + }; + ++&hdmi { ++ status = "okay"; ++}; ++ ++&hdmi_out { ++ hdmi_out_con: endpoint { ++ remote-endpoint = <&hdmi_con_in>; ++ }; ++}; ++ + &i2c0 { + status = "okay"; + +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-h3-nanopi-neo-Add-regulator-leds-mmc2.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-h3-nanopi-neo-Add-regulator-leds-mmc2.patch new file mode 100644 index 0000000000..8c80e6dc24 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-h3-nanopi-neo-Add-regulator-leds-mmc2.patch @@ -0,0 +1,80 @@ +From 0fd48415d94e247abbd9cc0854af6ae38afcd667 Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Mon, 24 Jan 2022 15:34:01 +0300 +Subject: [PATCH 060/153] arm:dts: h3-nanopi-neo Add regulator, leds, mmc2 + +--- + arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts | 57 +++++++++++++++++++++++ + 1 file changed, 57 insertions(+) + +diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts +index df71fab3c..032849663 100644 +--- a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts ++++ b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts +@@ -49,6 +49,63 @@ / { + aliases { + ethernet0 = &emac; + }; ++ ++ /* Warning: sunxi-5.18: ++ * The leds node is present in the sun8i-h3-nanopi.dtsi file ++ * You will have to fix this situation yourself ++ */ ++ leds { ++ compatible = "gpio-leds"; ++ ++ pwr { ++ label = "nanopi:red:pwr"; ++ gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ ++ linux,default-trigger = "default-on"; ++ }; ++ ++ status { ++ label = "nanopi:green:status"; ++ gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; /* PA10 */ ++ linux,default-trigger = "heartbeat"; ++ }; ++ }; ++ ++ vdd_cpux: gpio-regulator { ++ compatible = "regulator-gpio"; ++ pinctrl-names = "default"; ++ regulator-name = "vdd-cpux"; ++ regulator-type = "voltage"; ++ regulator-boot-on; ++ regulator-always-on; ++ regulator-min-microvolt = <1100000>; ++ regulator-max-microvolt = <1300000>; ++ regulator-ramp-delay = <50>; /* 4ms */ ++ gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ ++ gpios-states = <0x1>; ++ states = <1100000 0x0 ++ 1300000 0x1>; ++ }; ++}; ++ ++&cpu0 { ++ cpu-supply = <&vdd_cpux>; ++}; ++ ++&mmc2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc2_8bit_pins>; ++ vmmc-supply = <®_vcc3v3>; ++ bus-width = <8>; ++ non-removable; ++ cap-mmc-hw-reset; ++ status = "okay"; ++}; ++ ++&mmc2_8bit_pins { ++ /* Increase drive strength for DDR modes */ ++ drive-strength = <40>; ++ /* eMMC is missing pull-ups */ ++ bias-pull-up; + }; + + &ehci0 { +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-h3-nanopi-neo-air-Add-regulator-camera-wifi-bluetooth-o.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-h3-nanopi-neo-air-Add-regulator-camera-wifi-bluetooth-o.patch new file mode 100644 index 0000000000..34b13dc20c --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-h3-nanopi-neo-air-Add-regulator-camera-wifi-bluetooth-o.patch @@ -0,0 +1,197 @@ +From 1efe0eecf0919bfb33af8430521991c57b5b35ef Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Mon, 24 Jan 2022 15:45:43 +0300 +Subject: [PATCH 061/153] arm:dts: h3-nanopi-neo-air Add regulator camera wifi + bluetooth otg + +--- + arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts | 153 ++++++++++++++++++ + 1 file changed, 153 insertions(+) + +diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts +index 9e1a33f94..bff96ae65 100644 +--- a/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts ++++ b/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts +@@ -70,12 +70,92 @@ led-0 { + led-1 { + label = "nanopi:blue:status"; + gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; /* PA10 */ ++ linux,default-trigger = "heartbeat"; + }; + }; + ++ vdd_cpux: gpio-regulator { ++ compatible = "regulator-gpio"; ++ pinctrl-names = "default"; ++ regulator-name = "vdd-cpux"; ++ regulator-type = "voltage"; ++ regulator-boot-on; ++ regulator-always-on; ++ regulator-min-microvolt = <1100000>; ++ regulator-max-microvolt = <1300000>; ++ regulator-ramp-delay = <50>; /* 4ms */ ++ gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ ++ gpios-states = <0x1>; ++ states = <1100000 0x0 ++ 1300000 0x1>; ++ }; ++ + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&wifi_en_npi>; + reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ ++ post-power-on-delay-ms = <200>; ++ }; ++ ++ rfkill_bt { ++ compatible = "rfkill-gpio"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&bt_pwr_pin>; ++ reset-gpios = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */ ++ clocks = <&osc32k>; ++ clock-frequency = <32768>; ++ rfkill-name = "sunxi-bt"; ++ rfkill-type = "bluetooth"; ++ }; ++ ++ cam_xclk: cam-xclk { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <24000000>; ++ clock-output-names = "cam-xclk"; ++ }; ++ ++ reg_cam_avdd: cam-avdd { ++ compatible = "regulator-fixed"; ++ regulator-name = "cam500b-avdd"; ++ regulator-min-microvolt = <2800000>; ++ regulator-max-microvolt = <2800000>; ++ vin-supply = <®_vcc3v3>; ++ }; ++ ++ reg_cam_dovdd: cam-dovdd { ++ compatible = "regulator-fixed"; ++ regulator-name = "cam500b-dovdd"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ vin-supply = <®_vcc3v3>; ++ }; ++ ++ reg_cam_dvdd: cam-dvdd { ++ compatible = "regulator-fixed"; ++ regulator-name = "cam500b-dvdd"; ++ regulator-min-microvolt = <1500000>; ++ regulator-max-microvolt = <1500000>; ++ vin-supply = <®_vcc3v3>; ++ }; ++}; ++ ++&cpu0 { ++ cpu-supply = <&vdd_cpux>; ++}; ++ ++&pio { ++ bt_pwr_pin: bt_pwr_pin@0 { ++ pins = "PG13"; ++ function = "gpio_out"; ++ }; ++}; ++ ++&r_pio { ++ wifi_en_npi: wifi_en_pin { ++ pins = "PL7"; ++ function = "gpio_out"; + }; + }; + +@@ -110,6 +190,74 @@ &mmc2 { + vqmmc-supply = <®_vcc3v3>; + bus-width = <8>; + non-removable; ++ cap-mmc-hw-reset; ++ status = "okay"; ++}; ++ ++&mmc2_8bit_pins { ++ /* Increase drive strength for DDR modes */ ++ drive-strength = <40>; ++ /* eMMC is missing pull-ups */ ++ bias-pull-up; ++}; ++ ++&csi { ++ status = "okay"; ++ ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ /* Parallel bus endpoint */ ++ csi_from_ov5640: endpoint { ++ remote-endpoint = <&ov5640_to_csi>; ++ bus-width = <8>; ++ data-shift = <2>; ++ hsync-active = <1>; /* Active high */ ++ vsync-active = <0>; /* Active low */ ++ data-active = <1>; /* Active high */ ++ pclk-sample = <1>; /* Rising */ ++ }; ++ }; ++}; ++ ++&i2c2 { ++ status = "okay"; ++ ov5640: camera@3c { ++ compatible = "ovti,ov5640"; ++ reg = <0x3c>; ++ clocks = <&cam_xclk>; ++ clock-names = "xclk"; ++ ++ reset-gpios = <&pio 4 14 GPIO_ACTIVE_LOW>; ++ powerdown-gpios = <&pio 4 15 GPIO_ACTIVE_HIGH>; ++ AVDD-supply = <®_cam_avdd>; ++ DOVDD-supply = <®_cam_dovdd>; ++ DVDD-supply = <®_cam_dvdd>; ++ ++ port { ++ ov5640_to_csi: endpoint { ++ remote-endpoint = <&csi_from_ov5640>; ++ bus-width = <8>; ++ data-shift = <2>; ++ hsync-active = <1>; /* Active high */ ++ vsync-active = <0>; /* Active low */ ++ data-active = <1>; /* Active high */ ++ pclk-sample = <1>; /* Rising */ ++ }; ++ }; ++ }; ++}; ++ ++&i2c2_pins { ++ bias-pull-up; ++}; ++ ++&ehci0 { ++ status = "okay"; ++}; ++ ++&ohci0 { + status = "okay"; + }; + +@@ -137,6 +285,11 @@ bluetooth { + }; + }; + ++&usb_otg { ++ dr_mode = "peripheral"; ++ status = "okay"; ++}; ++ + &usbphy { + /* USB VBUS is always on */ + status = "okay"; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-h3-orangepi-2-Add-regulator-vdd-cpu.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-h3-orangepi-2-Add-regulator-vdd-cpu.patch new file mode 100644 index 0000000000..d461033121 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-h3-orangepi-2-Add-regulator-vdd-cpu.patch @@ -0,0 +1,59 @@ +From 922aa8247f8cbdcb08ec78c65cee0959870d84f5 Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Mon, 24 Jan 2022 18:23:18 +0300 +Subject: [PATCH 062/153] arm:dts: h3-orangepi-2 Add regulator vdd cpu + +--- + arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 29 +++++++++++++++++++++++ + 1 file changed, 29 insertions(+) + +diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts +index 2b5890327..bc20c44d1 100644 +--- a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts ++++ b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts +@@ -124,6 +124,10 @@ &de { + status = "okay"; + }; + ++&cpu0 { ++ cpu-supply = <®_vdd_cpux>; ++}; ++ + &ehci1 { + status = "okay"; + }; +@@ -178,6 +182,31 @@ rtl8189: sdio_wifi@1 { + }; + }; + ++&r_i2c { ++ status = "okay"; ++ ++ reg_vdd_cpux: regulator@65 { ++ compatible = "silergy,sy8106a"; ++ reg = <0x65>; ++ regulator-name = "vdd-cpux"; ++ silergy,fixed-microvolt = <1200000>; ++ /* ++ * The datasheet uses 1.1V as the minimum value of VDD-CPUX, ++ * however both the Armbian DVFS table and the official one ++ * have operating points with voltage under 1.1V, and both ++ * DVFS table are known to work properly at the lowest ++ * operating point. ++ * ++ * Use 1.0V as the minimum voltage instead. ++ */ ++ regulator-min-microvolt = <1000000>; ++ regulator-max-microvolt = <1400000>; ++ regulator-ramp-delay = <200>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++}; ++ + ®_usb1_vbus { + gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>; + status = "okay"; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-overlay-Add-Overlays-for-sunxi.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-overlay-Add-Overlays-for-sunxi.patch new file mode 100644 index 0000000000..15fb0aeaa9 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-overlay-Add-Overlays-for-sunxi.patch @@ -0,0 +1,4964 @@ +From e24b1918124a6977614e34a8a8224d1ba70eb2f4 Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Wed, 2 Feb 2022 12:54:05 +0300 +Subject: [PATCH 109/153] arm:dts:overlay Add Overlays for sunxi + +--- + arch/arm/boot/dts/Makefile | 2 + + arch/arm/boot/dts/overlay/Makefile | 97 +++++ + .../dts/overlay/README.sun4i-a10-overlays | 278 ++++++++++++++ + .../dts/overlay/README.sun5i-a13-overlays | 172 +++++++++ + .../dts/overlay/README.sun7i-a20-overlays | 348 ++++++++++++++++++ + .../boot/dts/overlay/README.sun8i-h3-overlays | 250 +++++++++++++ + .../dts/overlay/sun4i-a10-analog-codec.dts | 13 + + arch/arm/boot/dts/overlay/sun4i-a10-can.dts | 15 + + .../boot/dts/overlay/sun4i-a10-fixup.scr-cmd | 124 +++++++ + arch/arm/boot/dts/overlay/sun4i-a10-i2c1.dts | 22 ++ + arch/arm/boot/dts/overlay/sun4i-a10-i2c2.dts | 22 ++ + arch/arm/boot/dts/overlay/sun4i-a10-nand.dts | 103 ++++++ + .../boot/dts/overlay/sun4i-a10-pps-gpio.dts | 29 ++ + arch/arm/boot/dts/overlay/sun4i-a10-pwm.dts | 15 + + .../boot/dts/overlay/sun4i-a10-spdif-out.dts | 38 ++ + .../dts/overlay/sun4i-a10-spi-jedec-nor.dts | 57 +++ + .../boot/dts/overlay/sun4i-a10-spi-spidev.dts | 57 +++ + arch/arm/boot/dts/overlay/sun4i-a10-spi0.dts | 23 ++ + arch/arm/boot/dts/overlay/sun4i-a10-spi1.dts | 22 ++ + arch/arm/boot/dts/overlay/sun4i-a10-spi2.dts | 23 ++ + arch/arm/boot/dts/overlay/sun4i-a10-uart2.dts | 37 ++ + arch/arm/boot/dts/overlay/sun4i-a10-uart3.dts | 47 +++ + arch/arm/boot/dts/overlay/sun4i-a10-uart4.dts | 37 ++ + arch/arm/boot/dts/overlay/sun4i-a10-uart5.dts | 32 ++ + arch/arm/boot/dts/overlay/sun4i-a10-uart6.dts | 32 ++ + arch/arm/boot/dts/overlay/sun4i-a10-uart7.dts | 32 ++ + .../boot/dts/overlay/sun4i-a10-w1-gpio.dts | 29 ++ + .../dts/overlay/sun5i-a13-analog-codec.dts | 13 + + .../boot/dts/overlay/sun5i-a13-fixup.scr-cmd | 48 +++ + arch/arm/boot/dts/overlay/sun5i-a13-i2c1.dts | 22 ++ + arch/arm/boot/dts/overlay/sun5i-a13-i2c2.dts | 22 ++ + arch/arm/boot/dts/overlay/sun5i-a13-nand.dts | 60 +++ + arch/arm/boot/dts/overlay/sun5i-a13-pwm.dts | 15 + + .../dts/overlay/sun5i-a13-spi-jedec-nor.dts | 57 +++ + .../boot/dts/overlay/sun5i-a13-spi-spidev.dts | 57 +++ + arch/arm/boot/dts/overlay/sun5i-a13-spi0.dts | 38 ++ + arch/arm/boot/dts/overlay/sun5i-a13-spi1.dts | 39 ++ + arch/arm/boot/dts/overlay/sun5i-a13-spi2.dts | 22 ++ + arch/arm/boot/dts/overlay/sun5i-a13-uart0.dts | 32 ++ + arch/arm/boot/dts/overlay/sun5i-a13-uart1.dts | 22 ++ + arch/arm/boot/dts/overlay/sun5i-a13-uart2.dts | 22 ++ + arch/arm/boot/dts/overlay/sun5i-a13-uart3.dts | 22 ++ + .../dts/overlay/sun7i-a20-analog-codec.dts | 13 + + arch/arm/boot/dts/overlay/sun7i-a20-can.dts | 15 + + .../boot/dts/overlay/sun7i-a20-fixup.scr-cmd | 143 +++++++ + arch/arm/boot/dts/overlay/sun7i-a20-i2c1.dts | 22 ++ + arch/arm/boot/dts/overlay/sun7i-a20-i2c2.dts | 22 ++ + arch/arm/boot/dts/overlay/sun7i-a20-i2c3.dts | 22 ++ + arch/arm/boot/dts/overlay/sun7i-a20-i2c4.dts | 32 ++ + arch/arm/boot/dts/overlay/sun7i-a20-i2s0.dts | 25 ++ + arch/arm/boot/dts/overlay/sun7i-a20-i2s1.dts | 25 ++ + arch/arm/boot/dts/overlay/sun7i-a20-mmc2.dts | 18 + + arch/arm/boot/dts/overlay/sun7i-a20-nand.dts | 103 ++++++ + .../boot/dts/overlay/sun7i-a20-pps-gpio.dts | 29 ++ + arch/arm/boot/dts/overlay/sun7i-a20-pwm.dts | 15 + + .../boot/dts/overlay/sun7i-a20-spdif-out.dts | 38 ++ + .../dts/overlay/sun7i-a20-spi-add-cs1.dts | 16 + + .../dts/overlay/sun7i-a20-spi-jedec-nor.dts | 57 +++ + .../boot/dts/overlay/sun7i-a20-spi-spidev.dts | 57 +++ + arch/arm/boot/dts/overlay/sun7i-a20-spi0.dts | 23 ++ + arch/arm/boot/dts/overlay/sun7i-a20-spi1.dts | 22 ++ + arch/arm/boot/dts/overlay/sun7i-a20-spi2.dts | 23 ++ + arch/arm/boot/dts/overlay/sun7i-a20-uart2.dts | 32 ++ + arch/arm/boot/dts/overlay/sun7i-a20-uart3.dts | 42 +++ + arch/arm/boot/dts/overlay/sun7i-a20-uart4.dts | 22 ++ + arch/arm/boot/dts/overlay/sun7i-a20-uart5.dts | 22 ++ + arch/arm/boot/dts/overlay/sun7i-a20-uart6.dts | 22 ++ + arch/arm/boot/dts/overlay/sun7i-a20-uart7.dts | 22 ++ + .../boot/dts/overlay/sun7i-a20-w1-gpio.dts | 29 ++ + .../dts/overlay/sun8i-h3-analog-codec.dts | 17 + + arch/arm/boot/dts/overlay/sun8i-h3-cir.dts | 15 + + .../boot/dts/overlay/sun8i-h3-fixup.scr-cmd | 110 ++++++ + arch/arm/boot/dts/overlay/sun8i-h3-i2c0.dts | 20 + + arch/arm/boot/dts/overlay/sun8i-h3-i2c1.dts | 20 + + arch/arm/boot/dts/overlay/sun8i-h3-i2c2.dts | 20 + + .../boot/dts/overlay/sun8i-h3-pps-gpio.dts | 29 ++ + arch/arm/boot/dts/overlay/sun8i-h3-pwm.dts | 39 ++ + .../boot/dts/overlay/sun8i-h3-spdif-out.dts | 38 ++ + .../boot/dts/overlay/sun8i-h3-spi-add-cs1.dts | 41 +++ + .../dts/overlay/sun8i-h3-spi-jedec-nor.dts | 42 +++ + .../boot/dts/overlay/sun8i-h3-spi-spidev.dts | 42 +++ + arch/arm/boot/dts/overlay/sun8i-h3-uart1.dts | 22 ++ + arch/arm/boot/dts/overlay/sun8i-h3-uart2.dts | 22 ++ + arch/arm/boot/dts/overlay/sun8i-h3-uart3.dts | 22 ++ + .../boot/dts/overlay/sun8i-h3-usbhost0.dts | 27 ++ + .../boot/dts/overlay/sun8i-h3-usbhost1.dts | 27 ++ + .../boot/dts/overlay/sun8i-h3-usbhost2.dts | 27 ++ + .../boot/dts/overlay/sun8i-h3-usbhost3.dts | 27 ++ + .../arm/boot/dts/overlay/sun8i-h3-w1-gpio.dts | 29 ++ + arch/arm/boot/dts/overlay/sun8i-r40-i2c2.dts | 20 + + arch/arm/boot/dts/overlay/sun8i-r40-i2c3.dts | 20 + + .../dts/overlay/sun8i-r40-spi-spidev0.dts | 27 ++ + .../dts/overlay/sun8i-r40-spi-spidev1.dts | 27 ++ + arch/arm/boot/dts/overlay/sun8i-r40-uart2.dts | 22 ++ + arch/arm/boot/dts/overlay/sun8i-r40-uart4.dts | 22 ++ + arch/arm/boot/dts/overlay/sun8i-r40-uart5.dts | 22 ++ + arch/arm/boot/dts/overlay/sun8i-r40-uart7.dts | 22 ++ + 97 files changed, 4176 insertions(+) + create mode 100644 arch/arm/boot/dts/overlay/Makefile + create mode 100644 arch/arm/boot/dts/overlay/README.sun4i-a10-overlays + create mode 100644 arch/arm/boot/dts/overlay/README.sun5i-a13-overlays + create mode 100644 arch/arm/boot/dts/overlay/README.sun7i-a20-overlays + create mode 100644 arch/arm/boot/dts/overlay/README.sun8i-h3-overlays + create mode 100644 arch/arm/boot/dts/overlay/sun4i-a10-analog-codec.dts + create mode 100644 arch/arm/boot/dts/overlay/sun4i-a10-can.dts + create mode 100644 arch/arm/boot/dts/overlay/sun4i-a10-fixup.scr-cmd + create mode 100644 arch/arm/boot/dts/overlay/sun4i-a10-i2c1.dts + create mode 100644 arch/arm/boot/dts/overlay/sun4i-a10-i2c2.dts + create mode 100644 arch/arm/boot/dts/overlay/sun4i-a10-nand.dts + create mode 100644 arch/arm/boot/dts/overlay/sun4i-a10-pps-gpio.dts + create mode 100644 arch/arm/boot/dts/overlay/sun4i-a10-pwm.dts + create mode 100644 arch/arm/boot/dts/overlay/sun4i-a10-spdif-out.dts + create mode 100644 arch/arm/boot/dts/overlay/sun4i-a10-spi-jedec-nor.dts + create mode 100644 arch/arm/boot/dts/overlay/sun4i-a10-spi-spidev.dts + create mode 100644 arch/arm/boot/dts/overlay/sun4i-a10-spi0.dts + create mode 100644 arch/arm/boot/dts/overlay/sun4i-a10-spi1.dts + create mode 100644 arch/arm/boot/dts/overlay/sun4i-a10-spi2.dts + create mode 100644 arch/arm/boot/dts/overlay/sun4i-a10-uart2.dts + create mode 100644 arch/arm/boot/dts/overlay/sun4i-a10-uart3.dts + create mode 100644 arch/arm/boot/dts/overlay/sun4i-a10-uart4.dts + create mode 100644 arch/arm/boot/dts/overlay/sun4i-a10-uart5.dts + create mode 100644 arch/arm/boot/dts/overlay/sun4i-a10-uart6.dts + create mode 100644 arch/arm/boot/dts/overlay/sun4i-a10-uart7.dts + create mode 100644 arch/arm/boot/dts/overlay/sun4i-a10-w1-gpio.dts + create mode 100644 arch/arm/boot/dts/overlay/sun5i-a13-analog-codec.dts + create mode 100644 arch/arm/boot/dts/overlay/sun5i-a13-fixup.scr-cmd + create mode 100644 arch/arm/boot/dts/overlay/sun5i-a13-i2c1.dts + create mode 100644 arch/arm/boot/dts/overlay/sun5i-a13-i2c2.dts + create mode 100644 arch/arm/boot/dts/overlay/sun5i-a13-nand.dts + create mode 100644 arch/arm/boot/dts/overlay/sun5i-a13-pwm.dts + create mode 100644 arch/arm/boot/dts/overlay/sun5i-a13-spi-jedec-nor.dts + create mode 100644 arch/arm/boot/dts/overlay/sun5i-a13-spi-spidev.dts + create mode 100644 arch/arm/boot/dts/overlay/sun5i-a13-spi0.dts + create mode 100644 arch/arm/boot/dts/overlay/sun5i-a13-spi1.dts + create mode 100644 arch/arm/boot/dts/overlay/sun5i-a13-spi2.dts + create mode 100644 arch/arm/boot/dts/overlay/sun5i-a13-uart0.dts + create mode 100644 arch/arm/boot/dts/overlay/sun5i-a13-uart1.dts + create mode 100644 arch/arm/boot/dts/overlay/sun5i-a13-uart2.dts + create mode 100644 arch/arm/boot/dts/overlay/sun5i-a13-uart3.dts + create mode 100644 arch/arm/boot/dts/overlay/sun7i-a20-analog-codec.dts + create mode 100644 arch/arm/boot/dts/overlay/sun7i-a20-can.dts + create mode 100644 arch/arm/boot/dts/overlay/sun7i-a20-fixup.scr-cmd + create mode 100644 arch/arm/boot/dts/overlay/sun7i-a20-i2c1.dts + create mode 100644 arch/arm/boot/dts/overlay/sun7i-a20-i2c2.dts + create mode 100644 arch/arm/boot/dts/overlay/sun7i-a20-i2c3.dts + create mode 100644 arch/arm/boot/dts/overlay/sun7i-a20-i2c4.dts + create mode 100644 arch/arm/boot/dts/overlay/sun7i-a20-i2s0.dts + create mode 100644 arch/arm/boot/dts/overlay/sun7i-a20-i2s1.dts + create mode 100644 arch/arm/boot/dts/overlay/sun7i-a20-mmc2.dts + create mode 100644 arch/arm/boot/dts/overlay/sun7i-a20-nand.dts + create mode 100644 arch/arm/boot/dts/overlay/sun7i-a20-pps-gpio.dts + create mode 100644 arch/arm/boot/dts/overlay/sun7i-a20-pwm.dts + create mode 100644 arch/arm/boot/dts/overlay/sun7i-a20-spdif-out.dts + create mode 100644 arch/arm/boot/dts/overlay/sun7i-a20-spi-add-cs1.dts + create mode 100644 arch/arm/boot/dts/overlay/sun7i-a20-spi-jedec-nor.dts + create mode 100644 arch/arm/boot/dts/overlay/sun7i-a20-spi-spidev.dts + create mode 100644 arch/arm/boot/dts/overlay/sun7i-a20-spi0.dts + create mode 100644 arch/arm/boot/dts/overlay/sun7i-a20-spi1.dts + create mode 100644 arch/arm/boot/dts/overlay/sun7i-a20-spi2.dts + create mode 100644 arch/arm/boot/dts/overlay/sun7i-a20-uart2.dts + create mode 100644 arch/arm/boot/dts/overlay/sun7i-a20-uart3.dts + create mode 100644 arch/arm/boot/dts/overlay/sun7i-a20-uart4.dts + create mode 100644 arch/arm/boot/dts/overlay/sun7i-a20-uart5.dts + create mode 100644 arch/arm/boot/dts/overlay/sun7i-a20-uart6.dts + create mode 100644 arch/arm/boot/dts/overlay/sun7i-a20-uart7.dts + create mode 100644 arch/arm/boot/dts/overlay/sun7i-a20-w1-gpio.dts + create mode 100644 arch/arm/boot/dts/overlay/sun8i-h3-analog-codec.dts + create mode 100644 arch/arm/boot/dts/overlay/sun8i-h3-cir.dts + create mode 100644 arch/arm/boot/dts/overlay/sun8i-h3-fixup.scr-cmd + create mode 100644 arch/arm/boot/dts/overlay/sun8i-h3-i2c0.dts + create mode 100644 arch/arm/boot/dts/overlay/sun8i-h3-i2c1.dts + create mode 100644 arch/arm/boot/dts/overlay/sun8i-h3-i2c2.dts + create mode 100644 arch/arm/boot/dts/overlay/sun8i-h3-pps-gpio.dts + create mode 100644 arch/arm/boot/dts/overlay/sun8i-h3-pwm.dts + create mode 100644 arch/arm/boot/dts/overlay/sun8i-h3-spdif-out.dts + create mode 100644 arch/arm/boot/dts/overlay/sun8i-h3-spi-add-cs1.dts + create mode 100644 arch/arm/boot/dts/overlay/sun8i-h3-spi-jedec-nor.dts + create mode 100644 arch/arm/boot/dts/overlay/sun8i-h3-spi-spidev.dts + create mode 100644 arch/arm/boot/dts/overlay/sun8i-h3-uart1.dts + create mode 100644 arch/arm/boot/dts/overlay/sun8i-h3-uart2.dts + create mode 100644 arch/arm/boot/dts/overlay/sun8i-h3-uart3.dts + create mode 100644 arch/arm/boot/dts/overlay/sun8i-h3-usbhost0.dts + create mode 100644 arch/arm/boot/dts/overlay/sun8i-h3-usbhost1.dts + create mode 100644 arch/arm/boot/dts/overlay/sun8i-h3-usbhost2.dts + create mode 100644 arch/arm/boot/dts/overlay/sun8i-h3-usbhost3.dts + create mode 100644 arch/arm/boot/dts/overlay/sun8i-h3-w1-gpio.dts + create mode 100644 arch/arm/boot/dts/overlay/sun8i-r40-i2c2.dts + create mode 100644 arch/arm/boot/dts/overlay/sun8i-r40-i2c3.dts + create mode 100644 arch/arm/boot/dts/overlay/sun8i-r40-spi-spidev0.dts + create mode 100644 arch/arm/boot/dts/overlay/sun8i-r40-spi-spidev1.dts + create mode 100644 arch/arm/boot/dts/overlay/sun8i-r40-uart2.dts + create mode 100644 arch/arm/boot/dts/overlay/sun8i-r40-uart4.dts + create mode 100644 arch/arm/boot/dts/overlay/sun8i-r40-uart5.dts + create mode 100644 arch/arm/boot/dts/overlay/sun8i-r40-uart7.dts + +diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile +index 32710062a..b0f6a635b 100644 +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -1647,3 +1647,5 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ + aspeed-bmc-vegman-n110.dtb \ + aspeed-bmc-vegman-rx20.dtb \ + aspeed-bmc-vegman-sx20.dtb ++ ++subdir-y := overlay +diff --git a/arch/arm/boot/dts/overlay/Makefile b/arch/arm/boot/dts/overlay/Makefile +new file mode 100644 +index 000000000..d2e94f6b7 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/Makefile +@@ -0,0 +1,97 @@ ++# SPDX-License-Identifier: GPL-2.0 ++dtbo-$(CONFIG_MACH_SUN4I) += \ ++ sun4i-a10-analog-codec.dtbo \ ++ sun4i-a10-can.dtbo \ ++ sun4i-a10-i2c1.dtbo \ ++ sun4i-a10-i2c2.dtbo \ ++ sun4i-a10-nand.dtbo \ ++ sun4i-a10-pps-gpio.dtbo \ ++ sun4i-a10-pwm.dtbo \ ++ sun4i-a10-spdif-out.dtbo \ ++ sun4i-a10-spi-jedec-nor.dtbo \ ++ sun4i-a10-spi-spidev.dtbo \ ++ sun4i-a10-uart2.dtbo \ ++ sun4i-a10-uart3.dtbo \ ++ sun4i-a10-uart4.dtbo \ ++ sun4i-a10-uart5.dtbo \ ++ sun4i-a10-uart6.dtbo \ ++ sun4i-a10-uart7.dtbo \ ++ sun4i-a10-w1-gpio.dtbo ++ ++dtbo-$(CONFIG_MACH_SUN5I) += \ ++ sun5i-a13-analog-codec.dtbo \ ++ sun5i-a13-i2c1.dtbo \ ++ sun5i-a13-i2c2.dtbo \ ++ sun5i-a13-nand.dtbo \ ++ sun5i-a13-pwm.dtbo \ ++ sun5i-a13-spi0.dtbo \ ++ sun5i-a13-spi1.dtbo \ ++ sun5i-a13-spi2.dtbo \ ++ sun5i-a13-spi-jedec-nor.dtbo \ ++ sun5i-a13-spi-spidev.dtbo \ ++ sun5i-a13-uart0.dtbo \ ++ sun5i-a13-uart1.dtbo \ ++ sun5i-a13-uart2.dtbo \ ++ sun5i-a13-uart3.dtbo ++ ++dtbo-$(CONFIG_MACH_SUN7I) += \ ++ sun7i-a20-analog-codec.dtbo \ ++ sun7i-a20-can.dtbo \ ++ sun7i-a20-i2c1.dtbo \ ++ sun7i-a20-i2c2.dtbo \ ++ sun7i-a20-i2c3.dtbo \ ++ sun7i-a20-i2c4.dtbo \ ++ sun7i-a20-mmc2.dtbo \ ++ sun7i-a20-nand.dtbo \ ++ sun7i-a20-pps-gpio.dtbo \ ++ sun7i-a20-pwm.dtbo \ ++ sun7i-a20-spdif-out.dtbo \ ++ sun7i-a20-spi-add-cs1.dtbo \ ++ sun7i-a20-spi-jedec-nor.dtbo \ ++ sun7i-a20-spi-spidev.dtbo \ ++ sun7i-a20-uart2.dtbo \ ++ sun7i-a20-uart3.dtbo \ ++ sun7i-a20-uart4.dtbo \ ++ sun7i-a20-uart5.dtbo \ ++ sun7i-a20-uart6.dtbo \ ++ sun7i-a20-uart7.dtbo \ ++ sun7i-a20-w1-gpio.dtbo ++ ++dtbo-$(CONFIG_MACH_SUN8I) += \ ++ sun8i-h3-analog-codec.dtbo \ ++ sun8i-h3-cir.dtbo \ ++ sun8i-h3-i2c0.dtbo \ ++ sun8i-h3-i2c1.dtbo \ ++ sun8i-h3-i2c2.dtbo \ ++ sun8i-h3-pps-gpio.dtbo \ ++ sun8i-h3-pwm.dtbo \ ++ sun8i-h3-spdif-out.dtbo \ ++ sun8i-h3-spi-add-cs1.dtbo \ ++ sun8i-h3-spi-jedec-nor.dtbo \ ++ sun8i-h3-spi-spidev.dtbo \ ++ sun8i-h3-uart1.dtbo \ ++ sun8i-h3-uart2.dtbo \ ++ sun8i-h3-uart3.dtbo \ ++ sun8i-h3-usbhost0.dtbo \ ++ sun8i-h3-usbhost1.dtbo \ ++ sun8i-h3-usbhost2.dtbo \ ++ sun8i-h3-usbhost3.dtbo \ ++ sun8i-h3-w1-gpio.dtbo \ ++ sun8i-r40-i2c2.dtbo \ ++ sun8i-r40-i2c3.dtbo \ ++ sun8i-r40-spi-spidev0.dtbo \ ++ sun8i-r40-spi-spidev1.dtbo \ ++ sun8i-r40-uart2.dtbo \ ++ sun8i-r40-uart4.dtbo \ ++ sun8i-r40-uart5.dtbo \ ++ sun8i-r40-uart7.dtbo ++ ++scr-$(CONFIG_MACH_SUN4I) += sun4i-a10-fixup.scr ++scr-$(CONFIG_MACH_SUN5I) += sun5i-a13-fixup.scr ++scr-$(CONFIG_MACH_SUN7I) += sun7i-a20-fixup.scr ++scr-$(CONFIG_MACH_SUN8I) += sun8i-h3-fixup.scr ++ ++dtbotxt-$(CONFIG_MACH_SUN4I) += README.sun4i-a10-overlays ++dtbotxt-$(CONFIG_MACH_SUN5I) += README.sun5i-a13-overlays ++dtbotxt-$(CONFIG_MACH_SUN7I) += README.sun7i-a20-overlays ++dtbotxt-$(CONFIG_MACH_SUN8I) += README.sun8i-h3-overlays +diff --git a/arch/arm/boot/dts/overlay/README.sun4i-a10-overlays b/arch/arm/boot/dts/overlay/README.sun4i-a10-overlays +new file mode 100644 +index 000000000..e0795f13d +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/README.sun4i-a10-overlays +@@ -0,0 +1,278 @@ ++This document describes overlays provided in the kernel packages ++For generic Armbian overlays documentation please see ++https://docs.armbian.com/User-Guide_Allwinner_overlays/ ++ ++### Platform: ++ ++sun4i-a10 (Allwinner A10) ++ ++### Platform details: ++ ++Supported pin banks: PB, PC, PD, PE, PG, PH, PI ++ ++SPI controller 0 have 2 exposed hardware CS, ++other SPI controllers have only one hardware CS ++Reference: A10 User manual section 17.4.13, A10 datasheet section 5.2 ++ ++I2C bus 0 is used for the AXP209 PMIC ++ ++### Provided overlays: ++ ++- analog-codec ++- can ++- i2c1 ++- i2c2 ++- nand ++- pps-gpio ++- pwm ++- spdif-out ++- spi0 ++- spi1 ++- spi2 ++- spi-jedec-nor ++- spi-spidev ++- uart1 ++- uart2 ++- uart3 ++- uart4 ++- uart5 ++- uart6 ++- uart7 ++- w1-gpio ++ ++### Overlay details: ++ ++### analog-codec ++ ++Activates SoC analog codec driver that provides Line Out and Mic In ++functionality ++ ++## can ++ ++Activates SoC CAN controller ++ ++CAN pins (TX, RX): PH20, PH21 ++ ++### i2c1 ++ ++Activates TWI/I2C bus 1 ++ ++I2C1 pins (SCL, SDA): PB18, PB19 ++ ++### i2c2 ++ ++Activates TWI/I2C bus 2 ++ ++I2C2 pins (SCL, SDA): PB20, PB21 ++ ++### nand ++ ++Activates NAND controller ++ ++This overlay should not be used until mainline MLC NAND support ++allows using NAND storage reliably ++ ++### pps-gpio ++ ++Activates pulse-per-second GPIO client ++ ++Parameters: ++ ++param_pps_pin (pin) ++ Pin PPS source is connected to ++ Optional ++ Default: PI15 ++ ++param_pps_falling_edge (bool) ++ Assert by falling edge ++ Optional ++ Default: 0 ++ When set (to 1), assert is indicated by a falling edge ++ (instead of by a rising edge) ++ ++### pwm ++ ++Activates hardware PWM controller ++ ++PWM pins (PWM0, PWM1): PB2, PI3 ++ ++Parameters: ++ ++param_pwm_pins (string) ++ PWM pins activated with this overlay ++ Optional ++ Default: both ++ Supported values: 0, 1, both ++ If set to 0 only PWM0 can be used, ++ if set to 1 then only PWM1 can be used, ++ if set to both (default), both PWM0 and PWM1 can be used ++ ++### spdif-out ++ ++Activates SPDIF/Toslink audio output ++ ++SPDIF pin: PB13 ++ ++### spi0 ++ ++Activates SPI controller 0 to use it with other overlays and sets up the pin multiplexing for it ++ ++SPI 0 pins (MOSI, MISO, SCK, CS0, CS1): PI12, PI13, PI11, PI10, PI14 ++ ++### spi1 ++ ++Activates SPI controller 1 to use it with other overlays and sets up the pin multiplexing for it ++ ++SPI 1 pins (MOSI, MISO, SCK, CS0): PI18, PI19, PI17, PI16 ++ ++### spi2 ++ ++Activates SPI controller 2 to use it with other overlays and sets up the pin multiplexing for it ++ ++SPI 2 pins a (MOSI, MISO, SCK, CS0): PC21, PC22, PC20, PC19 ++SPI 2 pins b (MOSI, MISO, SCK, CS0): PB16, PB17, PB15, PB14 ++ ++Parameters: ++ ++param_spi2_bus_pins (char) ++ SPI bus 2 pinmux variant ++ Optional ++ Default: a ++ Supported values: a, b ++ Determines what pins SPI bus 2 is exposed on if SPI 2 is used ++ ++ ++### spi-jedec-nor ++ ++Activates MTD support for JEDEC compatible SPI NOR flash chips on SPI bus ++supported by the kernel SPI NOR driver ++ ++SPI 0 pins (MOSI, MISO, SCK, CS0, CS1): PI12, PI13, PI11, PI10, PI14 ++SPI 1 pins (MOSI, MISO, SCK, CS0): PI18, PI19, PI17, PI16 ++SPI 2 pins a (MOSI, MISO, SCK, CS0): PC21, PC22, PC20, PC19 ++SPI 2 pins b (MOSI, MISO, SCK, CS0): PB16, PB17, PB15, PB14 ++ ++Parameters: ++ ++param_spinor_spi_bus (int) ++ SPI bus to activate SPI NOR flash support on ++ Required ++ Supported values: 0, 1, 2 ++ ++param_spinor_max_freq (int) ++ Maximum SPI frequency ++ Optional ++ Default: 1000000 ++ Range: 3000 - 100000000 ++ ++### spi-spidev ++ ++Activates SPIdev device node (/dev/spidevX.Y) for userspace SPI access, ++where X is the bus number and Y is the CS number ++ ++SPI 0 pins (MOSI, MISO, SCK, CS0, CS1): PI12, PI13, PI11, PI10, PI14 ++SPI 1 pins (MOSI, MISO, SCK, CS0): PI18, PI19, PI17, PI16 ++SPI 2 pins a (MOSI, MISO, SCK, CS0): PC21, PC22, PC20, PC19 ++SPI 2 pins b (MOSI, MISO, SCK, CS0): PB16, PB17, PB15, PB14 ++ ++Parameters: ++ ++param_spidev_spi_bus (int) ++ SPI bus to activate mcp2515 support on ++ Required ++ Supported values: 0, 1, 2 ++ ++param_spidev_max_freq (int) ++ Maximum SPIdev frequency ++ Optional ++ Default: 1000000 ++ Range: 3000 - 100000000 ++ ++### uart2 ++ ++Activates serial port 2 (/dev/ttyS2) ++ ++UART 2 pins (TX, RX, RTS, CTS): PI18, PI19, PI16, PI17 ++ ++Parameters: ++ ++param_uart2_rtscts (bool) ++ Enable RTS and CTS pins ++ Optional ++ Default: 0 ++ Set to 1 to enable CTS and RTS pins ++ ++### uart3 ++ ++Activates serial port 3 (/dev/ttyS3) ++ ++UART 3 pins a (TX, RX, RTS, CTS): PG6, PG7, PG8, PG9 ++UART 3 pins b (TX, RX, RTS, CTS): PH0, PH1, PH2, PH3 ++ ++Parameters: ++ ++param_uart3_pins (char) ++ Determines what pins UART 3 is exposed on ++ Optional ++ Default: a ++ Supported values: a, b ++ ++param_uart3_rtscts (bool) ++ Enable RTS and CTS pins ++ Optional ++ Default: 0 ++ Set to 1 to enable CTS and RTS pins ++ ++### uart4 ++ ++Activates serial port 4 (/dev/ttyS4) ++ ++UART 4 pins a (TX, RX): PG10, PG11 ++UART 4 pins b (TX, RX): PH4, PH5 ++ ++Parameters: ++ ++param_uart4_pins (char) ++ Determines what pins UART 4 is exposed on ++ Optional ++ Default: a ++ Supported values: a, b ++ ++### uart 5 ++ ++Activates serial port 5 (/dev/ttyS5) ++ ++UART 5 pins (TX, RX): PH6, PH7 ++ ++### uart 6 ++ ++Activates serial port 6 (/dev/ttyS6) ++ ++UART 6 pins (TX, RX): PI12, PI13 ++ ++### uart 7 ++ ++Activates serial port 7 (/dev/ttyS7) ++ ++UART 7 pins (TX, RX): PI20, PI21 ++ ++### w1-gpio ++ ++Activates 1-Wire GPIO master ++Requires an external pull-up resistor on the data pin ++or enabling the internal pull-up ++ ++Parameters: ++ ++param_w1_pin (pin) ++ Data pin for 1-Wire master ++ Optional ++ Default: PI15 ++ ++param_w1_pin_int_pullup (bool) ++ Enable internal pull-up for the data pin ++ Optional ++ Default: 0 ++ Set to 1 to enable the pull-up ++ This option should not be used with multiple sensors or long wires - ++ please use external pull-up resistor instead +diff --git a/arch/arm/boot/dts/overlay/README.sun5i-a13-overlays b/arch/arm/boot/dts/overlay/README.sun5i-a13-overlays +new file mode 100644 +index 000000000..9f9653f09 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/README.sun5i-a13-overlays +@@ -0,0 +1,172 @@ ++This document describes overlays provided in the kernel packages ++For generic Armbian overlays documentation please see ++https://docs.armbian.com/User-Guide_Allwinner_overlays/ ++ ++### Platform: ++ ++sun5i-a13 (Allwinner A13) ++ ++### Platform details: ++ ++I2C bus 0 is used for the AXP209 PMIC ++ ++### Provided overlays: ++ ++- analog-codec ++- i2c1 ++- i2c2 ++- nand ++- pwm ++- spi0 ++- spi1 ++- spi2 ++- spi-jedec-nor ++- spi-spidev ++- uart0 ++- uart1 ++- uart2 ++- uart3 ++ ++### Overlay details: ++ ++### analog-codec ++ ++Activates SoC analog codec driver that provides HP Out and Mic In ++functionality ++ ++### i2c1 ++ ++Activates TWI/I2C bus 1 ++ ++I2C1 pins (SCL, SDA): PB15, PB16 ++ ++### i2c2 ++ ++Activates TWI/I2C bus 2 ++ ++I2C2 pins (SCL, SDA): PB17, PB18 ++ ++### nand ++ ++Activates NAND controller ++ ++This overlay should not be used until mainline MLC NAND support ++allows using NAND storage reliably ++ ++### pwm ++ ++Activates hardware PWM controller ++ ++PWM pins (PWM0): PB2 ++ ++### spi0 ++ ++Activates SPI controller 0 to use it with other overlays and sets up the pin multiplexing for it ++ ++SPI 0 pins (MOSI, MISO, SCK, CS0): PC0, PC1, PC2, PC3 ++ ++### spi1 ++ ++Activates SPI controller 1 to use it with other overlays and sets up the pin multiplexing for it ++ ++SPI 1 pins (MOSI, MISO, SCK, CS0): PG11, PG12, PG10, PG9 ++ ++### spi2 ++ ++Activates SPI controller 2 to use it with other overlays and sets up the pin multiplexing for it ++ ++SPI 2 pins (MOSI, MISO, SCK, CS0): PE2, PE3, PE1, PE0 ++ ++### spi-jedec-nor ++ ++Activates MTD support for JEDEC compatible SPI NOR flash chips on SPI bus ++supported by the kernel SPI NOR driver ++ ++SPI 0 pins (MOSI, MISO, SCK, CS0): PC0, PC1, PC2, PC3 ++SPI 1 pins (MOSI, MISO, SCK, CS0): PG11, PG12, PG10, PG9 ++SPI 2 pins (MOSI, MISO, SCK, CS0): PE2, PE3, PE1, PE0 ++ ++Parameters: ++ ++param_spinor_spi_bus (int) ++ SPI bus to activate SPI NOR flash support on ++ Required ++ Supported values: 0, 1, 2 ++ ++param_spinor_max_freq (int) ++ Maximum SPI frequency ++ Optional ++ Default: 1000000 ++ Range: 3000 - 100000000 ++ ++### spi-spidev ++ ++Activates SPIdev device node (/dev/spidevX.Y) for userspace SPI access, ++where X is the bus number and Y is the CS number ++ ++SPI 0 pins (MOSI, MISO, SCK, CS0): PC0, PC1, PC2, PC3 ++SPI 1 pins (MOSI, MISO, SCK, CS0): PG11, PG12, PG10, PG9 ++SPI 2 pins (MOSI, MISO, SCK, CS0): PE2, PE3, PE1, PE0 ++ ++Parameters: ++ ++param_spidev_spi_bus (int) ++ SPI bus to activate mcp2515 support on ++ Required ++ Supported values: 0, 1, 2 ++ ++param_spidev_max_freq (int) ++ Maximum SPIdev frequency ++ Optional ++ Default: 1000000 ++ Range: 3000 - 100000000 ++ ++### uart 0 ++ ++Activates serial port 0 (/dev/ttyS0) ++ ++UART 0 pins (TX, RX): PF2, PF4 ++ ++### uart 1 ++ ++Activates serial port 1 (/dev/ttyS1) ++ ++UART 1 pins a (TX, RX): PE10, PE11 ++UART 1 pins b (TX, RX): PG3, PG4 ++ ++Parameters: ++ ++param_uart1_pins (char) ++ UART 1 pinmux variant ++ Optional ++ Default: a ++ Supported values: a, b ++ Determines what pins UART 1 is exposed on if UART 1 is used ++ ++### uart2 ++ ++Activates serial port 2 (/dev/ttyS2) ++ ++UART 2 pins (TX, RX, RTS, CTS): PD2, PD3, PD4, PD5 ++ ++Parameters: ++ ++param_uart2_rtscts (bool) ++ Enable RTS and CTS pins ++ Optional ++ Default: 0 ++ Set to 1 to enable CTS and RTS pins ++ ++### uart3 ++ ++Activates serial port 3 (/dev/ttyS3) ++ ++UART 3 pins (TX, RX, RTS, CTS): PG9, PG10, PG12, PG11 ++ ++Parameters: ++ ++param_uart3_rtscts (bool) ++ Enable RTS and CTS pins ++ Optional ++ Default: 0 ++ Set to 1 to enable CTS and RTS pins +diff --git a/arch/arm/boot/dts/overlay/README.sun7i-a20-overlays b/arch/arm/boot/dts/overlay/README.sun7i-a20-overlays +new file mode 100644 +index 000000000..362f87961 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/README.sun7i-a20-overlays +@@ -0,0 +1,348 @@ ++This document describes overlays provided in the kernel packages ++For generic Armbian overlays documentation please see ++https://docs.armbian.com/User-Guide_Allwinner_overlays/ ++ ++### Platform: ++ ++sun7i-a20 (Allwinner A20) ++ ++### Platform details: ++ ++Supported pin banks: PB, PC, PD, PE, PG, PH, PI ++ ++SPI controller 0 have 2 exposed hardware CS, ++other SPI controllers have only one hardware CS ++Reference: A20 Datasheet sections 6.3.5.1, 1.19.2 ++ ++I2C bus 0 is used for the AXP209 PMIC ++ ++### Provided overlays: ++ ++- analog-codec ++- can ++- i2c1 ++- i2c2 ++- i2c3 ++- i2c4 ++- i2s0 ++- i2s1 ++- mmc2 ++- nand ++- pps-gpio ++- pwm ++- spdif-out ++- spi0 ++- spi1 ++- spi2 ++- spi-add-cs1 ++- spi-jedec-nor ++- spi-spidev ++- uart1 ++- uart2 ++- uart3 ++- uart4 ++- uart5 ++- uart6 ++- uart7 ++- w1-gpio ++ ++### Overlay details: ++ ++### analog-codec ++ ++Activates SoC analog codec driver that provides Line Out and Mic In ++functionality ++ ++## can ++ ++Activates SoC CAN controller ++ ++CAN pins (TX, RX): PH20, PH21 ++ ++### i2c1 ++ ++Activates TWI/I2C bus 1 ++ ++I2C1 pins (SCL, SDA): PB18, PB19 ++ ++### i2c2 ++ ++Activates TWI/I2C bus 2 ++ ++I2C2 pins (SCL, SDA): PB20, PB21 ++ ++### i2c3 ++ ++Activates TWI/I2C bus 3 ++ ++I2C3 pins (SCL, SDA): PI0, PI1 ++ ++### i2c4 ++ ++Activates TWI/I2C bus 4 ++ ++I2C4 pins (SCL, SDA): PI2, PI3 ++ ++### i2s0 ++ ++Activates SoC I2S controller 0 ++ ++I2S0 pins (MCLK, BCLK, LRCK, DO0, DO1, DO2, DO3, DI): PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12 ++ ++### i2s1 ++ ++Activates SoC I2S controller 1 ++ ++I2S1 pins (MCLK, BCLK, LRCK, DO, DI): PA9, PA14, PA15, PA16, PA17 ++ ++### mmc2 ++ ++Activates SD/MMC controller 2. To be used on boards with second SD slot, eMMC ++or tSD instead of NAND storage. ++ ++MMC2 pins: PC6, PC7, PC8, PC9, PC10, PC11 ++ ++Parameters: ++ ++param_mmc2_cd_pin (pin) ++ SD/MMC 2 card detect pin ++ Optional ++ Default: PH0 ++ ++param_mmc2_non_removable (bool) ++ Option for non-removable storage options on MMC 2 controller (eMMC or tSD) ++ Optional ++ Default: 0 ++ Set to 1 to use this option ++ ++### nand ++ ++Activates NAND controller ++ ++This overlay should not be used until mainline MLC NAND support ++allows using NAND storage reliably ++ ++### pps-gpio ++ ++Activates pulse-per-second GPIO client ++ ++Parameters: ++ ++param_pps_pin (pin) ++ Pin PPS source is connected to ++ Optional ++ Default: PI15 ++ ++param_pps_falling_edge (bool) ++ Assert by falling edge ++ Optional ++ Default: 0 ++ When set (to 1), assert is indicated by a falling edge ++ (instead of by a rising edge) ++ ++### pwm ++ ++Activates hardware PWM controller ++ ++PWM pins (PWM0, PWM1): PB2, PI3 ++ ++Parameters: ++ ++param_pwm_pins (string) ++ PWM pins activated with this overlay ++ Optional ++ Default: both ++ Supported values: 0, 1, both ++ If set to 0 only PWM0 can be used, ++ if set to 1 then only PWM1 can be used, ++ if set to both (default), both PWM0 and PWM1 can be used ++ ++### spdif-out ++ ++Activates SPDIF/Toslink audio output ++ ++SPDIF pin: PB13 ++ ++### spi0 ++ ++Activates SPI controller 0 to use it with other overlays and sets up the pin multiplexing for it ++ ++SPI 0 pins (MOSI, MISO, SCK, CS0, CS1): PI12, PI13, PI11, PI10, PI14 ++ ++### spi1 ++ ++Activates SPI controller 1 to use it with other overlays and sets up the pin multiplexing for it ++ ++SPI 1 pins (MOSI, MISO, SCK, CS0): PI18, PI19, PI17, PI16 ++ ++### spi2 ++ ++Activates SPI controller 2 to use it with other overlays and sets up the pin multiplexing for it ++ ++SPI 2 pins a (MOSI, MISO, SCK, CS0): PC21, PC22, PC20, PC19 ++SPI 2 pins b (MOSI, MISO, SCK, CS0): PB16, PB17, PB15, PB14 ++ ++Parameters: ++ ++param_spi2_bus_pins (char) ++ SPI bus 2 pinmux variant ++ Optional ++ Default: a ++ Supported values: a, b ++ Determines what pins SPI bus 2 is exposed on if SPI 2 is used ++ ++### spi-add-cs1 ++ ++Activates SPI chip select 1 on SPI controller 0 ++This overlay is required for using chip select 1 with other SPI overlays ++ ++SPI 0 CS1 pin: PI14 ++ ++### spi-jedec-nor ++ ++Activates MTD support for JEDEC compatible SPI NOR flash chips on SPI bus ++supported by the kernel SPI NOR driver ++ ++SPI 0 pins (MOSI, MISO, SCK, CS0, CS1): PI12, PI13, PI11, PI10, PI14 ++SPI 1 pins (MOSI, MISO, SCK, CS0): PI18, PI19, PI17, PI16 ++SPI 2 pins a (MOSI, MISO, SCK, CS0): PC21, PC22, PC20, PC19 ++SPI 2 pins b (MOSI, MISO, SCK, CS0): PB16, PB17, PB15, PB14 ++ ++Parameters: ++ ++param_spinor_spi_bus (int) ++ SPI bus to activate SPI NOR flash support on ++ Required ++ Supported values: 0, 1, 2 ++ ++param_spinor_spi_cs (int) ++ SPI chip select number for SPI NOR connected to SPI bus 0 ++ Optional ++ Default: 0 ++ Supported values: 0, 1 ++ Using chip select 1 on SPI 0 requires using "spi-add-cs1" overlay ++ ++param_spinor_max_freq (int) ++ Maximum SPI frequency ++ Optional ++ Default: 1000000 ++ Range: 3000 - 100000000 ++ ++### spi-spidev ++ ++Activates SPIdev device node (/dev/spidevX.Y) for userspace SPI access, ++where X is the bus number and Y is the CS number ++ ++SPI 0 pins (MOSI, MISO, SCK, CS0, CS1): PI12, PI13, PI11, PI10, PI14 ++SPI 1 pins (MOSI, MISO, SCK, CS0): PI18, PI19, PI17, PI16 ++SPI 2 pins a (MOSI, MISO, SCK, CS0): PC21, PC22, PC20, PC19 ++SPI 2 pins b (MOSI, MISO, SCK, CS0): PB16, PB17, PB15, PB14 ++ ++Parameters: ++ ++param_spidev_spi_bus (int) ++ SPI bus to activate mcp2515 support on ++ Required ++ Supported values: 0, 1, 2 ++ ++param_spidev_spi_cs (int) ++ SPI chip select number for SPIdev on SPI bus 0 ++ Optional ++ Default: 0 ++ Supported values: 0, 1 ++ Using chip select 1 on SPI 0 requires using "spi-add-cs1" overlay ++ ++param_spidev_max_freq (int) ++ Maximum SPIdev frequency ++ Optional ++ Default: 1000000 ++ Range: 3000 - 100000000 ++ ++### uart2 ++ ++Activates serial port 2 (/dev/ttyS2) ++ ++UART 2 pins (TX, RX, RTS, CTS): PI18, PI19, PI16, PI17 ++ ++Parameters: ++ ++param_uart2_rtscts (bool) ++ Enable RTS and CTS pins ++ Optional ++ Default: 0 ++ Set to 1 to enable CTS and RTS pins ++ ++### uart3 ++ ++Activates serial port 3 (/dev/ttyS3) ++ ++UART 3 pins a (TX, RX, RTS, CTS): PG6, PG7, PG8, PG9 ++UART 3 pins b (TX, RX, RTS, CTS): PH0, PH1, PH2, PH3 ++ ++Parameters: ++ ++param_uart3_pins (char) ++ Determines what pins UART 3 is exposed on ++ Optional ++ Default: a ++ Supported values: a, b ++ ++param_uart3_rtscts (bool) ++ Enable RTS and CTS pins ++ Optional ++ Default: 0 ++ Set to 1 to enable CTS and RTS pins ++ ++### uart4 ++ ++Activates serial port 4 (/dev/ttyS4) ++ ++UART 4 pins a (TX, RX): PG10, PG11 ++UART 4 pins b (TX, RX): PH4, PH5 ++ ++Parameters: ++ ++param_uart4_pins (char) ++ Determines what pins UART 4 is exposed on ++ Optional ++ Default: a ++ Supported values: a, b ++ ++### uart 5 ++ ++Activates serial port 5 (/dev/ttyS5) ++ ++UART 5 pins (TX, RX): PH6, PH7 ++ ++### uart 6 ++ ++Activates serial port 6 (/dev/ttyS6) ++ ++UART 6 pins (TX, RX): PI12, PI13 ++ ++### uart 7 ++ ++Activates serial port 7 (/dev/ttyS7) ++ ++UART 7 pins (TX, RX): PI20, PI21 ++ ++### w1-gpio ++ ++Activates 1-Wire GPIO master ++Requires an external pull-up resistor on the data pin ++or enabling the internal pull-up ++ ++Parameters: ++ ++param_w1_pin (pin) ++ Data pin for 1-Wire master ++ Optional ++ Default: PI15 ++ ++param_w1_pin_int_pullup (bool) ++ Enable internal pull-up for the data pin ++ Optional ++ Default: 0 ++ Set to 1 to enable the pull-up ++ This option should not be used with multiple sensors or long wires - ++ please use external pull-up resistor instead +diff --git a/arch/arm/boot/dts/overlay/README.sun8i-h3-overlays b/arch/arm/boot/dts/overlay/README.sun8i-h3-overlays +new file mode 100644 +index 000000000..302973491 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/README.sun8i-h3-overlays +@@ -0,0 +1,250 @@ ++This document describes overlays provided in the kernel packages ++For generic Armbian overlays documentation please see ++https://docs.armbian.com/User-Guide_Allwinner_overlays/ ++ ++### Platform: ++ ++sun8i-h3 (Allwinner H3) ++ ++### Platform details: ++ ++Supported pin banks: PA, PC, PD, PG ++ ++Both SPI controllers have only one hardware CS pin exposed, ++adding fixed software (GPIO) chip selects is possible with a separate overlay ++ ++### Provided overlays: ++ ++- analog-codec ++- cir ++- i2c0 ++- i2c1 ++- i2c2 ++- pps-gpio ++- pwm ++- spdif-out ++- spi-add-cs1 ++- spi-jedec-nor ++- spi-spidev ++- uart1 ++- uart2 ++- uart3 ++- usbhost0 ++- usbhost1 ++- usbhost2 ++- usbhost3 ++- w1-gpio ++ ++### Overlay details: ++ ++### analog-codec ++ ++Activates SoC analog codec driver that provides Line Out and Mic In ++functionality ++ ++### cir ++ ++Activates CIR (Infrared remote) receiver ++ ++CIR pin: PL11 ++ ++### i2c0 ++ ++Activates TWI/I2C bus 0 ++ ++I2C0 pins (SCL, SDA): PA11, PA12 ++ ++### i2c1 ++ ++Activates TWI/I2C bus 1 ++ ++I2C1 pins (SCL, SDA): PA18, PA19 ++ ++### i2c2 ++ ++Activates TWI/I2C bus 2 ++ ++I2C2 pins (SCL, SDA): PE12, PE13 ++ ++On most board this bus is wired to Camera (CSI) socket ++ ++### pps-gpio ++ ++Activates pulse-per-second GPIO client ++ ++Parameters: ++ ++param_pps_pin (pin) ++ Pin PPS source is connected to ++ Optional ++ Default: PD14 ++ ++param_pps_falling_edge (bool) ++ Assert by falling edge ++ Optional ++ Default: 0 ++ When set (to 1), assert is indicated by a falling edge ++ (instead of by a rising edge) ++ ++### pwm ++ ++Activates hardware PWM controller ++ ++PWM pin: PA5 ++ ++Pin PA5 is used as UART0 RX by default, so if this overlay is activated, ++UART0 and kernel console on ttyS0 will be disabled ++ ++### spdif-out ++ ++Activates SPDIF/Toslink audio output ++ ++SPDIF pin: PA17 ++ ++### spi-add-cs1 ++ ++Adds support for using SPI chip select 1 with GPIO for both SPI controllers ++Respective GPIO will be claimed only if controller is enabled by another ++overlay ++This overlay is required for using chip select 1 with other SPI overlays ++Due to the u-boot limitations CS1 pin can't be customized by a parameter, but ++it can be changed by using an edited copy of this overlay ++A total of 4 chip selects can be used with custom overlays (1 HW + 3 GPIO) ++ ++SPI 0 pins (CS1): PA21 ++SPI 1 pins (CS1): PA10 ++ ++### spi-jedec-nor ++ ++Activates MTD support for JEDEC compatible SPI NOR flash chips on SPI bus ++supported by the kernel SPI NOR driver ++ ++SPI 0 pins (MOSI, MISO, SCK, CS): PC0, PC1, PC2, PC3 ++SPI 1 pins (MOSI, MISO, SCK, CS): PA15, PA16, PA14, PA13 ++ ++Parameters: ++ ++param_spinor_spi_bus (int) ++ SPI bus to activate SPI NOR flash support on ++ Required ++ Supported values: 0, 1 ++ ++param_spinor_spi_cs (int) ++ SPI chip select number ++ Optional ++ Default: 0 ++ Supported values: 0, 1 ++ Using chip select 1 requires using "spi-add-cs1" overlay ++ ++param_spinor_max_freq (int) ++ Maximum SPI frequency ++ Optional ++ Default: 1000000 ++ Range: 3000 - 100000000 ++ ++### spi-spidev ++ ++Activates SPIdev device node (/dev/spidevX.Y) for userspace SPI access, ++where X is the bus number and Y is the CS number ++ ++SPI 0 pins (MOSI, MISO, SCK, CS): PC0, PC1, PC2, PC3 ++SPI 1 pins (MOSI, MISO, SCK, CS): PA15, PA16, PA14, PA13 ++ ++Parameters: ++ ++param_spidev_spi_bus (int) ++ SPI bus to activate SPIdev support on ++ Required ++ Supported values: 0, 1 ++ ++param_spidev_spi_cs (int) ++ SPI chip select number ++ Optional ++ Default: 0 ++ Supported values: 0, 1 ++ Using chip select 1 requires using "spi-add-cs1" overlay ++ ++param_spidev_max_freq (int) ++ Maximum SPIdev frequency ++ Optional ++ Default: 1000000 ++ Range: 3000 - 100000000 ++ ++### uart1 ++ ++Activates serial port 1 (/dev/ttyS1) ++ ++UART 1 pins (TX, RX, RTS, CTS): PG6, PG7, PG8, PG9 ++ ++Parameters: ++ ++param_uart1_rtscts (bool) ++ Enable RTS and CTS pins ++ Optional ++ Default: 0 ++ Set to 1 to enable ++ ++### uart2 ++ ++Activates serial port 2 (/dev/ttyS2) ++ ++UART 2 pins (TX, RX, RTS, CTS): PA0, PA1, PA2, PA3 ++ ++Parameters: ++ ++param_uart2_rtscts (bool) ++ Enable RTS and CTS pins ++ Optional ++ Default: 0 ++ Set to 1 to enable CTS and RTS pins ++ ++### uart3 ++ ++Activates serial port 3 (/dev/ttyS3) ++ ++UART 3 pins (TX, RX, RTS, CTS): PA13, PA14, PA15, PA16 ++ ++Parameters: ++ ++param_uart3_rtscts (bool) ++ Enable RTS and CTS pins ++ Optional ++ Default: 0 ++ Set to 1 to enable CTS and RTS pins ++ ++### usbhost0 ++ ++Activates USB host controller 0 ++ ++### usbhost1 ++ ++Activates USB host controller 1 ++ ++### usbhost2 ++ ++Activates USB host controller 2 ++ ++### usbhost3 ++ ++Activates USB host controller 3 ++ ++### w1-gpio ++ ++Activates 1-Wire GPIO master ++Requires an external pull-up resistor on the data pin ++or enabling the internal pull-up ++ ++Parameters: ++ ++param_w1_pin (pin) ++ Data pin for 1-Wire master ++ Optional ++ Default: PD14 ++ ++param_w1_pin_int_pullup (bool) ++ Enable internal pull-up for the data pin ++ Optional ++ Default: 0 ++ Set to 1 to enable the pull-up ++ This option should not be used with multiple devices, parasite power setup ++ or long wires - please use external pull-up resistor instead +diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-analog-codec.dts b/arch/arm/boot/dts/overlay/sun4i-a10-analog-codec.dts +new file mode 100644 +index 000000000..9254e22e0 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun4i-a10-analog-codec.dts +@@ -0,0 +1,13 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun4i-a10"; ++ ++ fragment@0 { ++ target = <&codec>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-can.dts b/arch/arm/boot/dts/overlay/sun4i-a10-can.dts +new file mode 100644 +index 000000000..1a9511d19 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun4i-a10-can.dts +@@ -0,0 +1,15 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun4i-a10"; ++ ++ fragment@0 { ++ target = <&can0>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&can0_ph_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-fixup.scr-cmd b/arch/arm/boot/dts/overlay/sun4i-a10-fixup.scr-cmd +new file mode 100644 +index 000000000..c5614cb95 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun4i-a10-fixup.scr-cmd +@@ -0,0 +1,124 @@ ++# overlays fixup script ++# implements (or rather substitutes) overlay arguments functionality ++# using u-boot scripting, environment variables and "fdt" command ++ ++# setexpr test_var ${tmp_bank} - A ++# works only for hex numbers (A-F) ++ ++setenv decompose_pin 'setexpr tmp_bank sub "P(B|C|D|E|G|H|I)\\d+" "\\1"; ++setexpr tmp_pin sub "P\\S(\\d+)" "\\1"; ++test "${tmp_bank}" = "B" && setenv tmp_bank 1; ++test "${tmp_bank}" = "C" && setenv tmp_bank 2; ++test "${tmp_bank}" = "D" && setenv tmp_bank 3; ++test "${tmp_bank}" = "E" && setenv tmp_bank 4; ++test "${tmp_bank}" = "G" && setenv tmp_bank 6; ++test "${tmp_bank}" = "H" && setenv tmp_bank 7; ++test "${tmp_bank}" = "I" && setenv tmp_bank 8' ++ ++if test -n "${param_spinor_spi_bus}"; then ++ test "${param_spinor_spi_bus}" = "0" && setenv tmp_spi_path "spi@1c05000" ++ test "${param_spinor_spi_bus}" = "1" && setenv tmp_spi_path "spi@1c06000" ++ test "${param_spinor_spi_bus}" = "2" && setenv tmp_spi_path "spi@1c17000" ++ fdt set /soc/${tmp_spi_path} status "okay" ++ fdt set /soc/${tmp_spi_path}/spiflash status "okay" ++ if test -n "${param_spinor_max_freq}"; then ++ fdt set /soc/${tmp_spi_path}/spiflash spi-max-frequency "<${param_spinor_max_freq}>" ++ fi ++ env delete tmp_spi_path ++fi ++ ++if test -n "${param_spidev_spi_bus}"; then ++ test "${param_spidev_spi_bus}" = "0" && setenv tmp_spi_path "spi@1c05000" ++ test "${param_spidev_spi_bus}" = "1" && setenv tmp_spi_path "spi@1c06000" ++ test "${param_spidev_spi_bus}" = "2" && setenv tmp_spi_path "spi@1c17000" ++ fdt set /soc/${tmp_spi_path} status "okay" ++ fdt set /soc/${tmp_spi_path}/spidev status "okay" ++ if test -n "${param_spidev_max_freq}"; then ++ fdt set /soc/${tmp_spi_path}/spidev spi-max-frequency "<${param_spidev_max_freq}>" ++ fi ++ env delete tmp_spi_path ++fi ++ ++if test "${param_spi2_bus_pins}" = "b"; then ++ fdt get value tmp_phandle1 /soc/pinctrl@1c20800/spi2@1 phandle ++ fdt get value tmp_phandle2 /soc/pinctrl@1c20800/spi2_cs0@1 phandle ++ fdt set /soc/spi@1c17000 pinctrl-0 "<${tmp_phandle1}>" ++ fdt set /soc/spi@1c17000 pinctrl-1 "<${tmp_phandle2}>" ++ env delete tmp_phandle1 tmp_phandle2 ++fi ++ ++if test -n "${param_pps_pin}"; then ++ setenv tmp_bank "${param_pps_pin}" ++ setenv tmp_pin "${param_pps_pin}" ++ run decompose_pin ++ fdt set /soc/pinctrl@1c20800/pps_pins pins "${param_pps_pin}" ++ fdt get value tmp_phandle /soc/pinctrl@1c20800 phandle ++ fdt set /pps@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>" ++ env delete tmp_pin tmp_bank tmp_phandle ++fi ++ ++if test "${param_pps_falling_edge}" = "1"; then ++ fdt set /pps@0 assert-falling-edge ++fi ++ ++if test "${param_pwm_pins}" = "0"; then ++ fdt get value tmp_phandle /soc/pinctrl@1c20800/pwm0@0 ++ fdt set /soc/pwm@1c20e00 pinctrl-0 "<${tmp_phandle}>" ++ env delete tmp_phandle ++fi ++ ++if test "${param_pwm_pins}" = "1"; then ++ fdt get value tmp_phandle /soc/pinctrl@1c20800/pwm1@0 ++ fdt set /soc/pwm@1c20e00 pinctrl-0 "<${tmp_phandle}>" ++ env delete tmp_phandle ++fi ++ ++if test -n "${param_w1_pin}"; then ++ setenv tmp_bank "${param_w1_pin}" ++ setenv tmp_pin "${param_w1_pin}" ++ run decompose_pin ++ fdt set /soc/pinctrl@1c20800/w1_pins pins "${param_w1_pin}" ++ fdt get value tmp_phandle /soc/pinctrl@1c20800 phandle ++ fdt set /onewire@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>" ++ env delete tmp_pin tmp_bank tmp_phandle ++fi ++ ++if test "${param_w1_pin_int_pullup}" = "1"; then ++ fdt set /soc/pinctrl@1c20800/w1_pins bias-pull-up ++fi ++ ++if test "${param_uart2_rtscts}" = "1"; then ++ fdt get value tmp_phandle /soc/pinctrl@1c20800/uart2@0 phandle ++ fdt set /soc/serial@1c28800 pinctrl-0 "<${tmp_phandle}>" ++ env delete tmp_phandle ++fi ++ ++if test "${param_uart3_pins}" = "b"; then ++ if test "${param_uart3_rtscts}" = "1"; then ++ fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart3_pins_b phandle ++ fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart3_pins_b_rts_cts phandle ++ fdt set /soc/serial@1c28c00 pinctrl-names "default" "default" ++ fdt set /soc/serial@1c28c00 pinctrl-0 "<${tmp_phandle1}>" ++ fdt set /soc/serial@1c28c00 pinctrl-1 "<${tmp_phandle2}>" ++ env delete tmp_phandle1 tmp_phandle2 ++ else ++ fdt get value tmp_phandle /soc/pinctrl@1c20800/uart3_pins_b phandle ++ fdt set /soc/serial@1c28c00 pinctrl-0 "<${tmp_phandle}>" ++ env delete tmp_phandle ++ fi ++else ++ if test "${param_uart3_rtscts}" = "1"; then ++ fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart3_pins_a phandle ++ fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart3_pins_a_rts_cts phandle ++ fdt set /soc/serial@1c28c00 pinctrl-names "default" "default" ++ fdt set /soc/serial@1c28c00 pinctrl-0 "<${tmp_phandle1}>" ++ fdt set /soc/serial@1c28c00 pinctrl-1 "<${tmp_phandle2}>" ++ env delete tmp_phandle1 tmp_phandle2 ++ fi ++fi ++ ++if test "${param_uart4_pins}" = "b"; then ++ fdt get value tmp_phandle /soc/pinctrl@1c20800/uart4@1 phandle ++ fdt set /soc/serial@1c29000 pinctrl-0 "<${tmp_phandle}>" ++ env delete tmp_phandle ++fi +diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-i2c1.dts b/arch/arm/boot/dts/overlay/sun4i-a10-i2c1.dts +new file mode 100644 +index 000000000..4c104bf4a +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun4i-a10-i2c1.dts +@@ -0,0 +1,22 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun4i-a10"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ i2c1 = "/soc@1c00000/i2c@1c2b000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&i2c1>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c1_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-i2c2.dts b/arch/arm/boot/dts/overlay/sun4i-a10-i2c2.dts +new file mode 100644 +index 000000000..1c2c3e9ac +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun4i-a10-i2c2.dts +@@ -0,0 +1,22 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun4i-a10"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ i2c2 = "/soc@1c00000/i2c@1c2b400"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&i2c2>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c2_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-nand.dts b/arch/arm/boot/dts/overlay/sun4i-a10-nand.dts +new file mode 100644 +index 000000000..f0d4c2f34 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun4i-a10-nand.dts +@@ -0,0 +1,103 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun4i-a10"; ++ ++ fragment@0 { ++ target = <&pio>; ++ __overlay__ { ++ nand_pins_a: nand_pins@0 { ++ pins = "PC0", "PC1", "PC2", ++ "PC5", "PC8", "PC9", "PC10", ++ "PC11", "PC12", "PC13", "PC14", ++ "PC15", "PC16"; ++ function = "nand0"; ++ }; ++ ++ nand_cs0_pins_a: nand_cs@0 { ++ pins = "PC4"; ++ function = "nand0"; ++ }; ++ ++ nand_cs1_pins_a: nand_cs@1 { ++ pins = "PC3"; ++ function = "nand0"; ++ }; ++ ++ nand_cs2_pins_a: nand_cs@2 { ++ pins = "PC17"; ++ function = "nand0"; ++ }; ++ ++ nand_cs3_pins_a: nand_cs@3 { ++ pins = "PC18"; ++ function = "nand0"; ++ }; ++ ++ nand_rb0_pins_a: nand_rb@0 { ++ pins = "PC6"; ++ function = "nand0"; ++ }; ++ ++ nand_rb1_pins_a: nand_rb@1 { ++ pins = "PC7"; ++ function = "nand0"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&nfc>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&nand_pins_a>, <&nand_cs0_pins_a>, <&nand_rb0_pins_a>; ++ status = "okay"; ++ ++ nand@0 { ++ reg = <0>; ++ allwinner,rb = <0>; ++ nand-ecc-mode = "hw"; ++ nand-on-flash-bbt; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ++ partition@0 { ++ label = "SPL"; ++ reg = <0x0 0x0 0x0 0x400000>; ++ }; ++ ++ partition@400000 { ++ label = "SPL.backup"; ++ reg = <0x0 0x400000 0x0 0x400000>; ++ }; ++ ++ partition@800000 { ++ label = "U-Boot"; ++ reg = <0x0 0x800000 0x0 0x400000>; ++ }; ++ ++ partition@c00000 { ++ label = "U-Boot.backup"; ++ reg = <0x0 0xc00000 0x0 0x400000>; ++ }; ++ ++ partition@1000000 { ++ label = "env"; ++ reg = <0x0 0x1000000 0x0 0x400000>; ++ }; ++ ++ partition@1400000 { ++ label = "rootfs"; ++ reg = <0x0 0xa00000 0x01 0xff000000>; ++ }; ++ }; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-pps-gpio.dts b/arch/arm/boot/dts/overlay/sun4i-a10-pps-gpio.dts +new file mode 100644 +index 000000000..6031fc53e +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun4i-a10-pps-gpio.dts +@@ -0,0 +1,29 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun4i-a10"; ++ ++ fragment@0 { ++ target = <&pio>; ++ __overlay__ { ++ pps_pins: pps_pins { ++ pins = "PI15"; ++ function = "gpio_in"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target-path = "/"; ++ __overlay__ { ++ pps@0 { ++ compatible = "pps-gpio"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pps_pins>; ++ gpios = <&pio 8 15 0>; /* PI15 */ ++ status = "okay"; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-pwm.dts b/arch/arm/boot/dts/overlay/sun4i-a10-pwm.dts +new file mode 100644 +index 000000000..ba885004f +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun4i-a10-pwm.dts +@@ -0,0 +1,15 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun4i-a10"; ++ ++ fragment@0 { ++ target = <&pwm>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm0_pin>, <&pwm1_pin>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-spdif-out.dts b/arch/arm/boot/dts/overlay/sun4i-a10-spdif-out.dts +new file mode 100644 +index 000000000..234dfc880 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun4i-a10-spdif-out.dts +@@ -0,0 +1,38 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun4i-a10"; ++ ++ fragment@0 { ++ target = <&spdif>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spdif_tx_pin>; ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target-path = "/"; ++ __overlay__ { ++ sound { ++ compatible = "simple-audio-card"; ++ simple-audio-card,name = "On-board SPDIF"; ++ ++ simple-audio-card,cpu { ++ sound-dai = <&spdif>; ++ }; ++ ++ simple-audio-card,codec { ++ sound-dai = <&spdif_out>; ++ }; ++ }; ++ ++ spdif_out: spdif-out { ++ #sound-dai-cells = <0>; ++ compatible = "linux,spdif-dit"; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-spi-jedec-nor.dts b/arch/arm/boot/dts/overlay/sun4i-a10-spi-jedec-nor.dts +new file mode 100644 +index 000000000..ee4ff6f45 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun4i-a10-spi-jedec-nor.dts +@@ -0,0 +1,57 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun4i-a10"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ spi0 = "/soc@1c00000/spi@1c05000"; ++ spi1 = "/soc@1c00000/spi@1c06000"; ++ spi2 = "/soc@1c00000/spi@1c17000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&spi0>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spiflash@0 { ++ compatible = "jedec,spi-nor"; ++ status = "disabled"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&spi1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spiflash@0 { ++ compatible = "jedec,spi-nor"; ++ status = "disabled"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ }; ++ ++ fragment@3 { ++ target = <&spi2>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spiflash@0 { ++ compatible = "jedec,spi-nor"; ++ status = "disabled"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-spi-spidev.dts b/arch/arm/boot/dts/overlay/sun4i-a10-spi-spidev.dts +new file mode 100644 +index 000000000..eac4f1e2d +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun4i-a10-spi-spidev.dts +@@ -0,0 +1,57 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun4i-a10"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ spi0 = "/soc@1c00000/spi@1c05000"; ++ spi1 = "/soc@1c00000/spi@1c06000"; ++ spi2 = "/soc@1c00000/spi@1c17000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&spi0>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spidev@0 { ++ compatible = "armbian,spi-dev"; ++ status = "disabled"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&spi1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spidev@0 { ++ compatible = "armbian,spi-dev"; ++ status = "disabled"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ }; ++ ++ fragment@3 { ++ target = <&spi2>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spidev@0 { ++ compatible = "armbian,spi-dev"; ++ status = "disabled"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-spi0.dts b/arch/arm/boot/dts/overlay/sun4i-a10-spi0.dts +new file mode 100644 +index 000000000..cad50d8a2 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun4i-a10-spi0.dts +@@ -0,0 +1,23 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun7i-a20"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ spi0 = "/soc@1c00000/spi@1c05000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&spi0>; ++ __overlay__ { ++ status = "okay"; ++ pinctrl-names = "default", "default"; ++ pinctrl-0 = <&spi0_pi_pins>; ++ pinctrl-1 = <&spi0_cs0_pi_pin>; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-spi1.dts b/arch/arm/boot/dts/overlay/sun4i-a10-spi1.dts +new file mode 100644 +index 000000000..8c606d6b0 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun4i-a10-spi1.dts +@@ -0,0 +1,22 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun7i-a20"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ spi1 = "/soc@1c00000/spi@1c06000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&spi1>; ++ __overlay__ { ++ status = "okay"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi1_pins>, <&spi1_cs0_pin>; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-spi2.dts b/arch/arm/boot/dts/overlay/sun4i-a10-spi2.dts +new file mode 100644 +index 000000000..145f28558 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun4i-a10-spi2.dts +@@ -0,0 +1,23 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun7i-a20"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ spi2 = "/soc@1c00000/spi@1c17000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&spi2>; ++ __overlay__ { ++ status = "okay"; ++ pinctrl-names = "default", "default"; ++ pinctrl-0 = <&spi2_pins_a>; ++ pinctrl-1 = <&spi2_cs0_pins_a>; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-uart2.dts b/arch/arm/boot/dts/overlay/sun4i-a10-uart2.dts +new file mode 100644 +index 000000000..89bb44d5a +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun4i-a10-uart2.dts +@@ -0,0 +1,37 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun4i-a10"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ serial2 = "/soc@1c00000/serial@1c28800"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&pio>; ++ __overlay__ { ++ uart2_pins_a: uart2@0 { ++ pins = "PI16", "PI17", "PI18", "PI19"; ++ function = "uart2"; ++ }; ++ ++ uart2_pins_a_2: uart2@1 { ++ pins = "PI18", "PI19"; ++ function = "uart2"; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&uart2>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart2_pins_a_2>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-uart3.dts b/arch/arm/boot/dts/overlay/sun4i-a10-uart3.dts +new file mode 100644 +index 000000000..f599d9208 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun4i-a10-uart3.dts +@@ -0,0 +1,47 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun4i-a10"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ serial3 = "/soc@1c00000/serial@1c28c00"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&pio>; ++ __overlay__ { ++ uart3_pins_a: uart3@0 { ++ pins = "PG6", "PG7"; ++ function = "uart3"; ++ }; ++ ++ uart3_pins_a_rts_cts: uart3@1 { ++ pins = "PG8", "PG9"; ++ function = "uart3"; ++ }; ++ ++ uart3_pins_b: uart3@2 { ++ pins = "PH0", "PH1"; ++ function = "uart3"; ++ }; ++ ++ uart3_pins_b_rts_cts: uart3@3 { ++ pins = "PH2", "PH3"; ++ function = "uart3"; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&uart3>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart3_pins_a>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-uart4.dts b/arch/arm/boot/dts/overlay/sun4i-a10-uart4.dts +new file mode 100644 +index 000000000..b5e562a64 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun4i-a10-uart4.dts +@@ -0,0 +1,37 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun4i-a10"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ serial4 = "/soc@1c00000/serial@1c29000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&pio>; ++ __overlay__ { ++ uart4_pins_a: uart4@0 { ++ pins = "PG10", "PG11"; ++ function = "uart4"; ++ }; ++ ++ uart4_pins_b: uart4@1 { ++ pins = "PH4", "PH5"; ++ function = "uart4"; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&uart4>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart4_pins_a>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-uart5.dts b/arch/arm/boot/dts/overlay/sun4i-a10-uart5.dts +new file mode 100644 +index 000000000..12c3f9699 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun4i-a10-uart5.dts +@@ -0,0 +1,32 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun4i-a10"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ serial5 = "/soc@1c00000/serial@1c29400"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&pio>; ++ __overlay__ { ++ uart5_pins_a: uart5@0 { ++ pins = "PH6", "PH7"; ++ function = "uart5"; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&uart5>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart5_pins_a>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-uart6.dts b/arch/arm/boot/dts/overlay/sun4i-a10-uart6.dts +new file mode 100644 +index 000000000..6be41d505 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun4i-a10-uart6.dts +@@ -0,0 +1,32 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun4i-a10"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ serial6 = "/soc@1c00000/serial@1c29800"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&pio>; ++ __overlay__ { ++ uart6_pins_a: uart6@0 { ++ pins = "PI12", "PI13"; ++ function = "uart6"; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&uart6>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart6_pins_a>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-uart7.dts b/arch/arm/boot/dts/overlay/sun4i-a10-uart7.dts +new file mode 100644 +index 000000000..967f6afbe +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun4i-a10-uart7.dts +@@ -0,0 +1,32 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun4i-a10"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ serial7 = "/soc@1c00000/serial@1c29c00"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&pio>; ++ __overlay__ { ++ uart7_pins_a: uart7@0 { ++ pins = "PI20", "PI21"; ++ function = "uart7"; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&uart7>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart7_pins_a>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-w1-gpio.dts b/arch/arm/boot/dts/overlay/sun4i-a10-w1-gpio.dts +new file mode 100644 +index 000000000..41da08c60 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun4i-a10-w1-gpio.dts +@@ -0,0 +1,29 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun4i-a10"; ++ ++ fragment@0 { ++ target = <&pio>; ++ __overlay__ { ++ w1_pins: w1_pins { ++ pins = "PI15"; ++ function = "gpio_in"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target-path = "/"; ++ __overlay__ { ++ onewire@0 { ++ compatible = "w1-gpio"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&w1_pins>; ++ gpios = <&pio 8 15 0>; /* PI15 */ ++ status = "okay"; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun5i-a13-analog-codec.dts b/arch/arm/boot/dts/overlay/sun5i-a13-analog-codec.dts +new file mode 100644 +index 000000000..60e2717fc +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun5i-a13-analog-codec.dts +@@ -0,0 +1,13 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun4i-a13"; ++ ++ fragment@0 { ++ target = <&codec>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun5i-a13-fixup.scr-cmd b/arch/arm/boot/dts/overlay/sun5i-a13-fixup.scr-cmd +new file mode 100644 +index 000000000..c82590c1a +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun5i-a13-fixup.scr-cmd +@@ -0,0 +1,48 @@ ++# overlays fixup script ++# implements (or rather substitutes) overlay arguments functionality ++# using u-boot scripting, environment variables and "fdt" command ++ ++if test -n "${param_spinor_spi_bus}"; then ++ test "${param_spinor_spi_bus}" = "0" && setenv tmp_spi_path "spi@1c05000" ++ test "${param_spinor_spi_bus}" = "1" && setenv tmp_spi_path "spi@1c06000" ++ test "${param_spinor_spi_bus}" = "2" && setenv tmp_spi_path "spi@1c17000" ++ fdt set /soc/${tmp_spi_path} status "okay" ++ fdt set /soc/${tmp_spi_path}/spiflash status "okay" ++ if test -n "${param_spinor_max_freq}"; then ++ fdt set /soc/${tmp_spi_path}/spiflash spi-max-frequency "<${param_spinor_max_freq}>" ++ fi ++ env delete tmp_spi_path ++fi ++ ++if test -n "${param_spidev_spi_bus}"; then ++ test "${param_spidev_spi_bus}" = "0" && setenv tmp_spi_path "spi@1c05000" ++ test "${param_spidev_spi_bus}" = "1" && setenv tmp_spi_path "spi@1c06000" ++ test "${param_spidev_spi_bus}" = "2" && setenv tmp_spi_path "spi@1c17000" ++ fdt set /soc/${tmp_spi_path} status "okay" ++ fdt set /soc/${tmp_spi_path}/spidev status "okay" ++ if test -n "${param_spidev_max_freq}"; then ++ fdt set /soc/${tmp_spi_path}/spidev spi-max-frequency "<${param_spidev_max_freq}>" ++ fi ++ env delete tmp_spi_path ++fi ++ ++if test "${param_uart1_pins}" = "b"; then ++ fdt get value tmp_phandle /soc/pinctrl@1c28400/uart1@1 phandle ++ fdt set /soc/serial@1c28400 pinctrl-0 "<${tmp_phandle}>" ++ env delete tmp_phandle ++fi ++ ++if test "${param_uart2_rtscts}" = "1"; then ++ fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart2@0 phandle ++ fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart2-cts-rts@0 phandle ++ fdt set /soc/serial@1c28800 pinctrl-0 "<${tmp_phandle1}>, <${tmp_phandle2}>" ++ env delete tmp_phandle1 tmp_phandle2 ++fi ++ ++if test "${param_uart3_rtscts}" = "1"; then ++ fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart3@0 phandle ++ fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart3-cts-rts@0 phandle ++ fdt set /soc/serial@1c28c00 pinctrl-names "default" "default" ++ fdt set /soc/serial@1c28c00 pinctrl-0 "<${tmp_phandle1}>, <${tmp_phandle2}>" ++ env delete tmp_phandle1 tmp_phandle2 ++fi +diff --git a/arch/arm/boot/dts/overlay/sun5i-a13-i2c1.dts b/arch/arm/boot/dts/overlay/sun5i-a13-i2c1.dts +new file mode 100644 +index 000000000..444c32ca0 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun5i-a13-i2c1.dts +@@ -0,0 +1,22 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun5i-a13"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ i2c1 = "/soc@1c00000/i2c@1c2b000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&i2c1>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c1_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun5i-a13-i2c2.dts b/arch/arm/boot/dts/overlay/sun5i-a13-i2c2.dts +new file mode 100644 +index 000000000..7a30681ca +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun5i-a13-i2c2.dts +@@ -0,0 +1,22 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun5i-a13"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ i2c2 = "/soc@1c00000/i2c@1c2b400"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&i2c2>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c2_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun5i-a13-nand.dts b/arch/arm/boot/dts/overlay/sun5i-a13-nand.dts +new file mode 100644 +index 000000000..0c5fc89a1 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun5i-a13-nand.dts +@@ -0,0 +1,60 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun5i-a13"; ++ ++ fragment@0 { ++ target = <&nfc>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&nand_pins>, <&nand_cs0_pin>, <&nand_rb0_pin>; ++ status = "okay"; ++ ++ nand@0 { ++ reg = <0>; ++ allwinner,rb = <0>; ++ nand-ecc-mode = "hw"; ++ nand-on-flash-bbt; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ++ partition@0 { ++ label = "SPL"; ++ reg = <0x0 0x0 0x0 0x400000>; ++ }; ++ ++ partition@400000 { ++ label = "SPL.backup"; ++ reg = <0x0 0x400000 0x0 0x400000>; ++ }; ++ ++ partition@800000 { ++ label = "U-Boot"; ++ reg = <0x0 0x800000 0x0 0x400000>; ++ }; ++ ++ partition@c00000 { ++ label = "U-Boot.backup"; ++ reg = <0x0 0xc00000 0x0 0x400000>; ++ }; ++ ++ partition@1000000 { ++ label = "env"; ++ reg = <0x0 0x1000000 0x0 0x400000>; ++ }; ++ ++ partition@1400000 { ++ label = "rootfs"; ++ reg = <0x0 0xa00000 0x01 0xff000000>; ++ }; ++ }; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun5i-a13-pwm.dts b/arch/arm/boot/dts/overlay/sun5i-a13-pwm.dts +new file mode 100644 +index 000000000..54f5d5123 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun5i-a13-pwm.dts +@@ -0,0 +1,15 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun5i-a13"; ++ ++ fragment@0 { ++ target = <&pwm>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm0_pin>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun5i-a13-spi-jedec-nor.dts b/arch/arm/boot/dts/overlay/sun5i-a13-spi-jedec-nor.dts +new file mode 100644 +index 000000000..8cebb0b98 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun5i-a13-spi-jedec-nor.dts +@@ -0,0 +1,57 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun5i-a13"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ spi0 = "/soc/spi@1c05000"; ++ spi1 = "/soc/spi@1c06000"; ++ spi2 = "/soc/spi@1c17000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&spi0>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spiflash@0 { ++ compatible = "jedec,spi-nor"; ++ status = "disabled"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&spi1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spiflash@0 { ++ compatible = "jedec,spi-nor"; ++ status = "disabled"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ }; ++ ++ fragment@3 { ++ target = <&spi2>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spiflash@0 { ++ compatible = "jedec,spi-nor"; ++ status = "disabled"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun5i-a13-spi-spidev.dts b/arch/arm/boot/dts/overlay/sun5i-a13-spi-spidev.dts +new file mode 100644 +index 000000000..ad0685f8a +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun5i-a13-spi-spidev.dts +@@ -0,0 +1,57 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun5i-a10"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ spi0 = "/soc/spi@1c05000"; ++ spi1 = "/soc/spi@1c06000"; ++ spi2 = "/soc/spi@1c17000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&spi0>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spidev@0 { ++ compatible = "armbian,spi-dev"; ++ status = "disabled"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&spi1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spidev@0 { ++ compatible = "armbian,spi-dev"; ++ status = "disabled"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ }; ++ ++ fragment@3 { ++ target = <&spi2>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spidev@0 { ++ compatible = "armbian,spi-dev"; ++ status = "disabled"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun5i-a13-spi0.dts b/arch/arm/boot/dts/overlay/sun5i-a13-spi0.dts +new file mode 100644 +index 000000000..b23a754c0 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun5i-a13-spi0.dts +@@ -0,0 +1,38 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun5i-a13"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ spi0 = "/soc/spi@1c05000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&pio>; ++ __overlay__ { ++ spi0_pins_a: spi0@0 { ++ pins = "PC0", "PC1", "PC2"; ++ function = "spi0"; ++ }; ++ ++ spi0_cs0_pins_a: spi0-cs0@0 { ++ pins = "PC3"; ++ function = "spi0"; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&spi0>; ++ __overlay__ { ++ status = "okay"; ++ pinctrl-names = "default", "default"; ++ pinctrl-0 = <&spi0_pins_a>; ++ pinctrl-1 = <&spi0_cs0_pins_a>; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun5i-a13-spi1.dts b/arch/arm/boot/dts/overlay/sun5i-a13-spi1.dts +new file mode 100644 +index 000000000..cc0af5db3 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun5i-a13-spi1.dts +@@ -0,0 +1,39 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun5i-a13"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ spi1 = "/soc/spi@1c06000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&pio>; ++ __overlay__ { ++ spi1_pins_a: spi1@0 { ++ pins = "PG10", "PG11", "PG12"; ++ function = "spi1"; ++ }; ++ ++ spi1_cs0_pins_a: spi1-cs0@0 { ++ pins = "PG9"; ++ function = "spi1"; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&spi1>; ++ __overlay__ { ++ status = "okay"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi1_pins_a>, <&spi1_cs0_pins_a>; ++ }; ++ }; ++ ++ ++}; +diff --git a/arch/arm/boot/dts/overlay/sun5i-a13-spi2.dts b/arch/arm/boot/dts/overlay/sun5i-a13-spi2.dts +new file mode 100644 +index 000000000..6cf5c41a9 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun5i-a13-spi2.dts +@@ -0,0 +1,22 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun5i-a13"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ spi2 = "/soc/spi@1c17000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&spi2>; ++ __overlay__ { ++ status = "okay"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi2_pe_pins>, <&spi2_cs0_pe_pin>; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun5i-a13-uart0.dts b/arch/arm/boot/dts/overlay/sun5i-a13-uart0.dts +new file mode 100644 +index 000000000..6edad42bf +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun5i-a13-uart0.dts +@@ -0,0 +1,32 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun5i-a13"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ uart0 = "/soc@1c00000/serial@1c28000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&pio>; ++ __overlay__ { ++ uart0_pa_pins: uart0@0 { ++ pins = "PF2", "PF4"; ++ function = "uart0"; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&uart0>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pa_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun5i-a13-uart1.dts b/arch/arm/boot/dts/overlay/sun5i-a13-uart1.dts +new file mode 100644 +index 000000000..675b701ed +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun5i-a13-uart1.dts +@@ -0,0 +1,22 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun5i-a13"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ uart1 = "/soc@1c00000/serial@1c28400"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&uart1>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1_pe_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun5i-a13-uart2.dts b/arch/arm/boot/dts/overlay/sun5i-a13-uart2.dts +new file mode 100644 +index 000000000..b3c4e3d7a +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun5i-a13-uart2.dts +@@ -0,0 +1,22 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun5i-a13"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ uart2 = "/soc@1c00000/serial@1c28800"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&uart2>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart2_pd_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun5i-a13-uart3.dts b/arch/arm/boot/dts/overlay/sun5i-a13-uart3.dts +new file mode 100644 +index 000000000..15c25d0c5 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun5i-a13-uart3.dts +@@ -0,0 +1,22 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun5i-a13"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ uart3 = "/soc@1c00000/serial@1c28c00"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&uart3>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart3_pg_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-analog-codec.dts b/arch/arm/boot/dts/overlay/sun7i-a20-analog-codec.dts +new file mode 100644 +index 000000000..e1a70c510 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun7i-a20-analog-codec.dts +@@ -0,0 +1,13 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun7i-a20"; ++ ++ fragment@0 { ++ target = <&codec>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-can.dts b/arch/arm/boot/dts/overlay/sun7i-a20-can.dts +new file mode 100644 +index 000000000..65aebcd41 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun7i-a20-can.dts +@@ -0,0 +1,15 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun7i-a20"; ++ ++ fragment@0 { ++ target = <&can0>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&can0_pins_a>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-fixup.scr-cmd b/arch/arm/boot/dts/overlay/sun7i-a20-fixup.scr-cmd +new file mode 100644 +index 000000000..b97042a72 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun7i-a20-fixup.scr-cmd +@@ -0,0 +1,143 @@ ++# overlays fixup script ++# implements (or rather substitutes) overlay arguments functionality ++# using u-boot scripting, environment variables and "fdt" command ++ ++# setexpr test_var ${tmp_bank} - A ++# works only for hex numbers (A-F) ++ ++setenv decompose_pin 'setexpr tmp_bank sub "P(B|C|D|E|G|H|I)\\d+" "\\1"; ++setexpr tmp_pin sub "P\\S(\\d+)" "\\1"; ++test "${tmp_bank}" = "B" && setenv tmp_bank 1; ++test "${tmp_bank}" = "C" && setenv tmp_bank 2; ++test "${tmp_bank}" = "D" && setenv tmp_bank 3; ++test "${tmp_bank}" = "E" && setenv tmp_bank 4; ++test "${tmp_bank}" = "G" && setenv tmp_bank 6; ++test "${tmp_bank}" = "H" && setenv tmp_bank 7; ++test "${tmp_bank}" = "I" && setenv tmp_bank 8' ++ ++if test -n "${param_spinor_spi_bus}"; then ++ test "${param_spinor_spi_bus}" = "0" && setenv tmp_spi_path "spi@1c05000" ++ test "${param_spinor_spi_bus}" = "1" && setenv tmp_spi_path "spi@1c06000" ++ test "${param_spinor_spi_bus}" = "2" && setenv tmp_spi_path "spi@1c17000" ++ fdt set /soc/${tmp_spi_path} status "okay" ++ fdt set /soc/${tmp_spi_path}/spiflash status "okay" ++ if test -n "${param_spinor_max_freq}"; then ++ fdt set /soc/${tmp_spi_path}/spiflash spi-max-frequency "<${param_spinor_max_freq}>" ++ fi ++ if test "${param_spinor_spi_bus}" = "0" && test "${param_spinor_spi_cs}" = "1"; then ++ fdt set /soc/${tmp_spi_path}/spiflash reg "<1>" ++ fi ++ env delete tmp_spi_path ++fi ++ ++if test -n "${param_spidev_spi_bus}"; then ++ test "${param_spidev_spi_bus}" = "0" && setenv tmp_spi_path "spi@1c05000" ++ test "${param_spidev_spi_bus}" = "1" && setenv tmp_spi_path "spi@1c06000" ++ test "${param_spidev_spi_bus}" = "2" && setenv tmp_spi_path "spi@1c17000" ++ fdt set /soc/${tmp_spi_path} status "okay" ++ fdt set /soc/${tmp_spi_path}/spidev status "okay" ++ if test -n "${param_spidev_max_freq}"; then ++ fdt set /soc/${tmp_spi_path}/spidev spi-max-frequency "<${param_spidev_max_freq}>" ++ fi ++ if test "${param_spidev_spi_bus}" = "0" && test "${param_spidev_spi_cs}" = "1"; then ++ fdt set /soc/${tmp_spi_path}/spidev reg "<1>" ++ fi ++ env delete tmp_spi_path ++fi ++ ++if test "${param_spi2_bus_pins}" = "b"; then ++ fdt get value tmp_phandle1 /soc/pinctrl@1c20800/spi2@1 phandle ++ fdt get value tmp_phandle2 /soc/pinctrl@1c20800/spi2_cs0@1 phandle ++ fdt set /soc/spi@1c17000 pinctrl-0 "<${tmp_phandle1}>" ++ fdt set /soc/spi@1c17000 pinctrl-1 "<${tmp_phandle2}>" ++ env delete tmp_phandle1 tmp_phandle2 ++fi ++ ++if test -n "${param_pps_pin}"; then ++ setenv tmp_bank "${param_pps_pin}" ++ setenv tmp_pin "${param_pps_pin}" ++ run decompose_pin ++ fdt set /soc/pinctrl@1c20800/pps_pins pins "${param_pps_pin}" ++ fdt get value tmp_phandle /soc/pinctrl@1c20800 phandle ++ fdt set /pps@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>" ++ env delete tmp_pin tmp_bank tmp_phandle ++fi ++ ++if test "${param_pps_falling_edge}" = "1"; then ++ fdt set /pps@0 assert-falling-edge ++fi ++ ++if test "${param_pwm_pins}" = "0"; then ++ fdt get value tmp_phandle /soc/pinctrl@1c20800/pwm0@0 ++ fdt set /soc/pwm@1c20e00 pinctrl-0 "<${tmp_phandle}>" ++ env delete tmp_phandle ++fi ++ ++if test "${param_pwm_pins}" = "1"; then ++ fdt get value tmp_phandle /soc/pinctrl@1c20800/pwm1@0 ++ fdt set /soc/pwm@1c20e00 pinctrl-0 "<${tmp_phandle}>" ++ env delete tmp_phandle ++fi ++ ++if test -n "${param_w1_pin}"; then ++ setenv tmp_bank "${param_w1_pin}" ++ setenv tmp_pin "${param_w1_pin}" ++ run decompose_pin ++ fdt set /soc/pinctrl@1c20800/w1_pins pins "${param_w1_pin}" ++ fdt get value tmp_phandle /soc/pinctrl@1c20800 phandle ++ fdt set /onewire@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>" ++ env delete tmp_pin tmp_bank tmp_phandle ++fi ++ ++if test -n "${param_mmc2_cd_pin}"; then ++ setenv tmp_bank "${param_mmc2_cd_pin}" ++ setenv tmp_pin "${param_mmc2_cd_pin}" ++ run decompose_pin ++ fdt get value tmp_phandle /soc/pinctrl@1c20800 phandle ++ fdt set /soc/mmc@1c11000 cd-gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 1>" ++fi ++ ++if test "${param_mmc2_non_removable}" = "1"; then ++ fdt rm /soc/mmc@1c11000 cd-gpios ++ fdt set /soc/mmc@1c11000 non-removable ++fi ++ ++if test "${param_w1_pin_int_pullup}" = "1"; then ++ fdt set /soc/pinctrl@1c20800/w1_pins bias-pull-up ++fi ++ ++if test "${param_uart2_rtscts}" = "1"; then ++ fdt get value tmp_phandle /soc/pinctrl@1c20800/uart2-pi-pins phandle ++ fdt set /soc/serial@1c28800 pinctrl-0 "<${tmp_phandle}>" ++ env delete tmp_phandle ++fi ++ ++if test "${param_uart3_pins}" = "b"; then ++ if test "${param_uart3_rtscts}" = "1"; then ++ fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart3-ph-pins phandle ++ fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart3-cts-rts-ph-pins phandle ++ fdt set /soc/serial@1c28c00 pinctrl-names "default" "default" ++ fdt set /soc/serial@1c28c00 pinctrl-0 "<${tmp_phandle1}>" ++ fdt set /soc/serial@1c28c00 pinctrl-1 "<${tmp_phandle2}>" ++ env delete tmp_phandle1 tmp_phandle2 ++ else ++ fdt get value tmp_phandle /soc/pinctrl@1c20800/uart3-ph-pins phandle ++ fdt set /soc/serial@1c28c00 pinctrl-0 "<${tmp_phandle}>" ++ env delete tmp_phandle ++ fi ++else ++ if test "${param_uart3_rtscts}" = "1"; then ++ fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart3-pg-pins phandle ++ fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart3-cts-rts-pg-pins phandle ++ fdt set /soc/serial@1c28c00 pinctrl-names "default" "default" ++ fdt set /soc/serial@1c28c00 pinctrl-0 "<${tmp_phandle1}>" ++ fdt set /soc/serial@1c28c00 pinctrl-1 "<${tmp_phandle2}>" ++ env delete tmp_phandle1 tmp_phandle2 ++ fi ++fi ++ ++if test "${param_uart4_pins}" = "b"; then ++ fdt get value tmp_phandle /soc/pinctrl@1c20800/uart4-pg-pins phandle ++ fdt set /soc/serial@1c29000 pinctrl-0 "<${tmp_phandle}>" ++ env delete tmp_phandle ++fi +diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-i2c1.dts b/arch/arm/boot/dts/overlay/sun7i-a20-i2c1.dts +new file mode 100644 +index 000000000..c5f6e9732 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun7i-a20-i2c1.dts +@@ -0,0 +1,22 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun7i-a20"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ i2c1 = "/soc@1c00000/i2c@1c2b000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&i2c1>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c1_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-i2c2.dts b/arch/arm/boot/dts/overlay/sun7i-a20-i2c2.dts +new file mode 100644 +index 000000000..fa93d1ed9 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun7i-a20-i2c2.dts +@@ -0,0 +1,22 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun7i-a20"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ i2c2 = "/soc@1c00000/i2c@1c2b400"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&i2c2>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c2_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-i2c3.dts b/arch/arm/boot/dts/overlay/sun7i-a20-i2c3.dts +new file mode 100644 +index 000000000..945795c33 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun7i-a20-i2c3.dts +@@ -0,0 +1,22 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun7i-a20"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ i2c3 = "/soc@1c00000/i2c@1c2b800"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&i2c3>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c3_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-i2c4.dts b/arch/arm/boot/dts/overlay/sun7i-a20-i2c4.dts +new file mode 100644 +index 000000000..4fcf08c24 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun7i-a20-i2c4.dts +@@ -0,0 +1,32 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun7i-a20"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ i2c4 = "/soc@1c00000/i2c@1c2c000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&pio>; ++ __overlay__ { ++ i2c4_pins_a: i2c4@0 { ++ pins = "PI2", "PI3"; ++ function = "i2c4"; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&i2c4>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c4_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-i2s0.dts b/arch/arm/boot/dts/overlay/sun7i-a20-i2s0.dts +new file mode 100644 +index 000000000..1a19a2417 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun7i-a20-i2s0.dts +@@ -0,0 +1,25 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun7i-a20"; ++ ++ fragment@0 { ++ target = <&pio>; ++ __overlay__ { ++ i2s0_pins: i2s0 { ++ pins = "PB5", "PB6", "PB7", "PB8", "PB9", "PB10", "PB11", "PB12"; ++ function = "i2s0"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&i2s0>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2s0_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-i2s1.dts b/arch/arm/boot/dts/overlay/sun7i-a20-i2s1.dts +new file mode 100644 +index 000000000..e6f0a22b7 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun7i-a20-i2s1.dts +@@ -0,0 +1,25 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun7i-a20"; ++ ++ fragment@0 { ++ target = <&pio>; ++ __overlay__ { ++ i2s1_pins: i2s1 { ++ pins = "PA9", "PA14", "PA15", "PA16", "PA17"; ++ function = "i2s1"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&i2s1>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2s1_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-mmc2.dts b/arch/arm/boot/dts/overlay/sun7i-a20-mmc2.dts +new file mode 100644 +index 000000000..ede92f243 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun7i-a20-mmc2.dts +@@ -0,0 +1,18 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun7i-a20"; ++ ++ fragment@0 { ++ target = <&mmc2>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc2_pins>; ++ vmmc-supply = <®_vcc3v3>; ++ bus-width = <4>; ++ cd-gpios = <&pio 7 0 1>; /* PH0, active low */ ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-nand.dts b/arch/arm/boot/dts/overlay/sun7i-a20-nand.dts +new file mode 100644 +index 000000000..ffa49cc69 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun7i-a20-nand.dts +@@ -0,0 +1,103 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun7i-a20"; ++ ++ fragment@0 { ++ target = <&pio>; ++ __overlay__ { ++ nand_pins_a: nand_pins@0 { ++ pins = "PC0", "PC1", "PC2", ++ "PC5", "PC8", "PC9", "PC10", ++ "PC11", "PC12", "PC13", "PC14", ++ "PC15", "PC16"; ++ function = "nand0"; ++ }; ++ ++ nand_cs0_pins_a: nand_cs@0 { ++ pins = "PC4"; ++ function = "nand0"; ++ }; ++ ++ nand_cs1_pins_a: nand_cs@1 { ++ pins = "PC3"; ++ function = "nand0"; ++ }; ++ ++ nand_cs2_pins_a: nand_cs@2 { ++ pins = "PC17"; ++ function = "nand0"; ++ }; ++ ++ nand_cs3_pins_a: nand_cs@3 { ++ pins = "PC18"; ++ function = "nand0"; ++ }; ++ ++ nand_rb0_pins_a: nand_rb@0 { ++ pins = "PC6"; ++ function = "nand0"; ++ }; ++ ++ nand_rb1_pins_a: nand_rb@1 { ++ pins = "PC7"; ++ function = "nand0"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&nfc>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&nand_pins_a>, <&nand_cs0_pins_a>, <&nand_rb0_pins_a>; ++ status = "okay"; ++ ++ nand@0 { ++ reg = <0>; ++ allwinner,rb = <0>; ++ nand-ecc-mode = "hw"; ++ nand-on-flash-bbt; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ++ partition@0 { ++ label = "SPL"; ++ reg = <0x0 0x0 0x0 0x400000>; ++ }; ++ ++ partition@400000 { ++ label = "SPL.backup"; ++ reg = <0x0 0x400000 0x0 0x400000>; ++ }; ++ ++ partition@800000 { ++ label = "U-Boot"; ++ reg = <0x0 0x800000 0x0 0x400000>; ++ }; ++ ++ partition@c00000 { ++ label = "U-Boot.backup"; ++ reg = <0x0 0xc00000 0x0 0x400000>; ++ }; ++ ++ partition@1000000 { ++ label = "env"; ++ reg = <0x0 0x1000000 0x0 0x400000>; ++ }; ++ ++ partition@1400000 { ++ label = "rootfs"; ++ reg = <0x0 0xa00000 0x01 0xff000000>; ++ }; ++ }; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-pps-gpio.dts b/arch/arm/boot/dts/overlay/sun7i-a20-pps-gpio.dts +new file mode 100644 +index 000000000..fe3e2bd96 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun7i-a20-pps-gpio.dts +@@ -0,0 +1,29 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun7i-a20"; ++ ++ fragment@0 { ++ target = <&pio>; ++ __overlay__ { ++ pps_pins: pps_pins { ++ pins = "PI15"; ++ function = "gpio_in"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target-path = "/"; ++ __overlay__ { ++ pps@0 { ++ compatible = "pps-gpio"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pps_pins>; ++ gpios = <&pio 8 15 0>; /* PI15 */ ++ status = "okay"; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-pwm.dts b/arch/arm/boot/dts/overlay/sun7i-a20-pwm.dts +new file mode 100644 +index 000000000..b0cfe4dea +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun7i-a20-pwm.dts +@@ -0,0 +1,15 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun7i-a20"; ++ ++ fragment@0 { ++ target = <&pwm>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm0_pin>, <&pwm1_pin>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-spdif-out.dts b/arch/arm/boot/dts/overlay/sun7i-a20-spdif-out.dts +new file mode 100644 +index 000000000..11a09396b +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun7i-a20-spdif-out.dts +@@ -0,0 +1,38 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun7i-a20"; ++ ++ fragment@0 { ++ target = <&spdif>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spdif_tx_pin>; ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target-path = "/"; ++ __overlay__ { ++ sound { ++ compatible = "simple-audio-card"; ++ simple-audio-card,name = "On-board SPDIF"; ++ ++ simple-audio-card,cpu { ++ sound-dai = <&spdif>; ++ }; ++ ++ simple-audio-card,codec { ++ sound-dai = <&spdif_out>; ++ }; ++ }; ++ ++ spdif_out: spdif-out { ++ #sound-dai-cells = <0>; ++ compatible = "linux,spdif-dit"; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-spi-add-cs1.dts b/arch/arm/boot/dts/overlay/sun7i-a20-spi-add-cs1.dts +new file mode 100644 +index 000000000..c0a4ba2b3 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun7i-a20-spi-add-cs1.dts +@@ -0,0 +1,16 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun7i-a20"; ++ ++ fragment@0 { ++ target = <&spi0>; ++ __overlay__ { ++ pinctrl-names = "default", "default", "default"; ++ pinctrl-0 = <&spi0_pi_pins>; ++ pinctrl-1 = <&spi0_cs0_pi_pin>; ++ pinctrl-2 = <&spi0_cs1_pi_pin>; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-spi-jedec-nor.dts b/arch/arm/boot/dts/overlay/sun7i-a20-spi-jedec-nor.dts +new file mode 100644 +index 000000000..b91097eca +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun7i-a20-spi-jedec-nor.dts +@@ -0,0 +1,57 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun7i-a20"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ spi0 = "/soc@1c00000/spi@1c05000"; ++ spi1 = "/soc@1c00000/spi@1c06000"; ++ spi2 = "/soc@1c00000/spi@1c17000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&spi0>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spiflash@0 { ++ compatible = "jedec,spi-nor"; ++ status = "disabled"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&spi1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spiflash@0 { ++ compatible = "jedec,spi-nor"; ++ status = "disabled"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ }; ++ ++ fragment@3 { ++ target = <&spi2>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spiflash@0 { ++ compatible = "jedec,spi-nor"; ++ status = "disabled"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-spi-spidev.dts b/arch/arm/boot/dts/overlay/sun7i-a20-spi-spidev.dts +new file mode 100644 +index 000000000..341fe3229 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun7i-a20-spi-spidev.dts +@@ -0,0 +1,57 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun7i-a20"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ spi0 = "/soc@1c00000/spi@1c05000"; ++ spi1 = "/soc@1c00000/spi@1c06000"; ++ spi2 = "/soc@1c00000/spi@1c17000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&spi0>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spidev@0 { ++ compatible = "armbian,spi-dev"; ++ status = "disabled"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&spi1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spidev@0 { ++ compatible = "armbian,spi-dev"; ++ status = "disabled"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ }; ++ ++ fragment@3 { ++ target = <&spi2>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spidev@0 { ++ compatible = "armbian,spi-dev"; ++ status = "disabled"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-spi0.dts b/arch/arm/boot/dts/overlay/sun7i-a20-spi0.dts +new file mode 100644 +index 000000000..cad50d8a2 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun7i-a20-spi0.dts +@@ -0,0 +1,23 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun7i-a20"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ spi0 = "/soc@1c00000/spi@1c05000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&spi0>; ++ __overlay__ { ++ status = "okay"; ++ pinctrl-names = "default", "default"; ++ pinctrl-0 = <&spi0_pi_pins>; ++ pinctrl-1 = <&spi0_cs0_pi_pin>; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-spi1.dts b/arch/arm/boot/dts/overlay/sun7i-a20-spi1.dts +new file mode 100644 +index 000000000..f0218eb9f +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun7i-a20-spi1.dts +@@ -0,0 +1,22 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun7i-a20"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ spi1 = "/soc@1c00000/spi@1c06000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&spi1>; ++ __overlay__ { ++ status = "okay"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi1_pi_pins>, <&spi1_cs0_pi_pin>; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-spi2.dts b/arch/arm/boot/dts/overlay/sun7i-a20-spi2.dts +new file mode 100644 +index 000000000..effba42b4 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun7i-a20-spi2.dts +@@ -0,0 +1,23 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun7i-a20"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ spi2 = "/soc@1c00000/spi@1c17000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&spi2>; ++ __overlay__ { ++ status = "okay"; ++ pinctrl-names = "default", "default"; ++ pinctrl-0 = <&spi2_pb_pins>; ++ pinctrl-1 = <&spi2_pb_cs0_pin>; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-uart2.dts b/arch/arm/boot/dts/overlay/sun7i-a20-uart2.dts +new file mode 100644 +index 000000000..79d1dca7a +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun7i-a20-uart2.dts +@@ -0,0 +1,32 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun7i-a20"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ serial2 = "/soc@1c00000/serial@1c28800"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&pio>; ++ __overlay__ { ++ uart2_pins_a_2: uart2@1 { ++ pins = "PI18", "PI19"; ++ function = "uart2"; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&uart2>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart2_pins_a_2>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-uart3.dts b/arch/arm/boot/dts/overlay/sun7i-a20-uart3.dts +new file mode 100644 +index 000000000..703acbcf3 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun7i-a20-uart3.dts +@@ -0,0 +1,42 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun7i-a20"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ serial3 = "/soc@1c00000/serial@1c28c00"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&pio>; ++ __overlay__ { ++ uart3_pins_a_2: uart3@2 { ++ pins = "PG6", "PG7"; ++ function = "uart3"; ++ }; ++ ++ uart3_pins_a_rts_cts: uart3@1 { ++ pins = "PG8", "PG9"; ++ function = "uart3"; ++ }; ++ ++ uart3_pins_b_rts_cts: uart3@3 { ++ pins = "PH2", "PH3"; ++ function = "uart3"; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&uart3>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart3_pins_a_2>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-uart4.dts b/arch/arm/boot/dts/overlay/sun7i-a20-uart4.dts +new file mode 100644 +index 000000000..19180341a +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun7i-a20-uart4.dts +@@ -0,0 +1,22 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun7i-a20"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ serial4 = "/soc@1c00000/serial@1c29000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&uart4>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart4_pg_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-uart5.dts b/arch/arm/boot/dts/overlay/sun7i-a20-uart5.dts +new file mode 100644 +index 000000000..a1369eee2 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun7i-a20-uart5.dts +@@ -0,0 +1,22 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun7i-a20"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ serial5 = "/soc@1c00000/serial@1c29400"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&uart5>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart5_pi_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-uart6.dts b/arch/arm/boot/dts/overlay/sun7i-a20-uart6.dts +new file mode 100644 +index 000000000..fb9efe2a9 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun7i-a20-uart6.dts +@@ -0,0 +1,22 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun7i-a20"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ serial6 = "/soc@1c00000/serial@1c29800"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&uart6>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart6_pi_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-uart7.dts b/arch/arm/boot/dts/overlay/sun7i-a20-uart7.dts +new file mode 100644 +index 000000000..bbdca3ec6 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun7i-a20-uart7.dts +@@ -0,0 +1,22 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun7i-a20"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ serial7 = "/soc@1c00000/serial@1c29c00"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&uart7>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart7_pi_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-w1-gpio.dts b/arch/arm/boot/dts/overlay/sun7i-a20-w1-gpio.dts +new file mode 100644 +index 000000000..7d77606a1 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun7i-a20-w1-gpio.dts +@@ -0,0 +1,29 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun7i-a20"; ++ ++ fragment@0 { ++ target = <&pio>; ++ __overlay__ { ++ w1_pins: w1_pins { ++ pins = "PI15"; ++ function = "gpio_in"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target-path = "/"; ++ __overlay__ { ++ onewire@0 { ++ compatible = "w1-gpio"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&w1_pins>; ++ gpios = <&pio 8 15 0>; /* PI15 */ ++ status = "okay"; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-analog-codec.dts b/arch/arm/boot/dts/overlay/sun8i-h3-analog-codec.dts +new file mode 100644 +index 000000000..36dbc31ae +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun8i-h3-analog-codec.dts +@@ -0,0 +1,17 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun8i-h3"; ++ ++ fragment@0 { ++ target = <&codec>; ++ __overlay__ { ++ allwinner,audio-routing = ++ "Line Out", "LINEOUT", ++ "MIC1", "Mic", ++ "Mic", "MBIAS"; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-cir.dts b/arch/arm/boot/dts/overlay/sun8i-h3-cir.dts +new file mode 100644 +index 000000000..bf4a0eafa +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun8i-h3-cir.dts +@@ -0,0 +1,15 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun8i-h3"; ++ ++ fragment@0 { ++ target = <&ir>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&r_ir_rx_pin>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-fixup.scr-cmd b/arch/arm/boot/dts/overlay/sun8i-h3-fixup.scr-cmd +new file mode 100644 +index 000000000..604fe8bb7 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun8i-h3-fixup.scr-cmd +@@ -0,0 +1,110 @@ ++# overlays fixup script ++# implements (or rather substitutes) overlay arguments functionality ++# using u-boot scripting, environment variables and "fdt" command ++ ++# setexpr test_var ${tmp_bank} - A ++# works only for hex numbers (A-F) ++ ++setenv decompose_pin 'setexpr tmp_bank sub "P(A|C|D|G)\\d+" "\\1"; ++setexpr tmp_pin sub "P\\S(\\d+)" "\\1"; ++test "${tmp_bank}" = "A" && setenv tmp_bank 0; ++test "${tmp_bank}" = "C" && setenv tmp_bank 2; ++test "${tmp_bank}" = "D" && setenv tmp_bank 3; ++test "${tmp_bank}" = "G" && setenv tmp_bank 6' ++ ++if test -n "${param_spinor_spi_bus}"; then ++ test "${param_spinor_spi_bus}" = "0" && setenv tmp_spi_path "spi@1c68000" ++ test "${param_spinor_spi_bus}" = "1" && setenv tmp_spi_path "spi@1c69000" ++ fdt set /soc/${tmp_spi_path} status "okay" ++ fdt set /soc/${tmp_spi_path}/spiflash status "okay" ++ if test -n "${param_spinor_max_freq}"; then ++ fdt set /soc/${tmp_spi_path}/spiflash spi-max-frequency "<${param_spinor_max_freq}>" ++ fi ++ if test "${param_spinor_spi_cs}" = "1"; then ++ fdt set /soc/${tmp_spi_path}/spiflash reg "<1>" ++ fi ++ env delete tmp_spi_path ++fi ++ ++if test -n "${param_spidev_spi_bus}"; then ++ test "${param_spidev_spi_bus}" = "0" && setenv tmp_spi_path "spi@1c68000" ++ test "${param_spidev_spi_bus}" = "1" && setenv tmp_spi_path "spi@1c69000" ++ fdt set /soc/${tmp_spi_path} status "okay" ++ fdt set /soc/${tmp_spi_path}/spidev status "okay" ++ if test -n "${param_spidev_max_freq}"; then ++ fdt set /soc/${tmp_spi_path}/spidev spi-max-frequency "<${param_spidev_max_freq}>" ++ fi ++ if test "${param_spidev_spi_cs}" = "1"; then ++ fdt set /soc/${tmp_spi_path}/spidev reg "<1>" ++ fi ++ env delete tmp_spi_path ++fi ++ ++if test -n "${param_pps_pin}"; then ++ setenv tmp_bank "${param_pps_pin}" ++ setenv tmp_pin "${param_pps_pin}" ++ run decompose_pin ++ fdt set /soc/pinctrl@1c20800/pps_pins pins "${param_pps_pin}" ++ fdt get value tmp_phandle /soc/pinctrl@1c20800 phandle ++ fdt set /pps@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>" ++ env delete tmp_pin tmp_bank tmp_phandle ++fi ++ ++if test "${param_pps_falling_edge}" = "1"; then ++ fdt set /pps@0 assert-falling-edge ++fi ++ ++for f in ${overlays}; do ++ if test "${f}" = "pwm"; then ++ setenv bootargs_new "" ++ for arg in ${bootargs}; do ++ if test "${arg}" = "console=ttyS0,115200"; then ++ echo "Warning: Disabling ttyS0 console due to enabled PWM overlay" ++ else ++ setenv bootargs_new "${bootargs_new} ${arg}" ++ fi ++ done ++ setenv bootargs "${bootargs_new}" ++ fi ++done ++ ++if test -n "${param_w1_pin}"; then ++ setenv tmp_bank "${param_w1_pin}" ++ setenv tmp_pin "${param_w1_pin}" ++ run decompose_pin ++ fdt set /soc/pinctrl@1c20800/w1_pins pins "${param_w1_pin}" ++ fdt get value tmp_phandle /soc/pinctrl@1c20800 phandle ++ fdt set /onewire@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>" ++ env delete tmp_pin tmp_bank tmp_phandle ++fi ++ ++if test "${param_w1_pin_int_pullup}" = "1"; then ++ fdt set /soc/pinctrl@1c20800/w1_pins bias-pull-up ++fi ++ ++if test "${param_uart1_rtscts}" = "1"; then ++ fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart1-pins phandle ++ fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart1-rts-cts-pins phandle ++ fdt set /soc/serial@1c28400 pinctrl-names "default" "default" ++ fdt set /soc/serial@1c28400 pinctrl-0 "<${tmp_phandle1}>" ++ fdt set /soc/serial@1c28400 pinctrl-1 "<${tmp_phandle2}>" ++ env delete tmp_phandle1 tmp_phandle2 ++fi ++ ++if test "${param_uart2_rtscts}" = "1"; then ++ fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart2-pins phandle ++ fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart2-rts-cts-pins phandle ++ fdt set /soc/serial@1c28800 pinctrl-names "default" "default" ++ fdt set /soc/serial@1c28800 pinctrl-0 "<${tmp_phandle1}>" ++ fdt set /soc/serial@1c28800 pinctrl-1 "<${tmp_phandle2}>" ++ env delete tmp_phandle1 tmp_phandle2 ++fi ++ ++if test "${param_uart3_rtscts}" = "1"; then ++ fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart3-pins phandle ++ fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart3-rts-cts-pins phandle ++ fdt set /soc/serial@1c28c00 pinctrl-names "default" "default" ++ fdt set /soc/serial@1c28c00 pinctrl-0 "<${tmp_phandle1}>" ++ fdt set /soc/serial@1c28c00 pinctrl-1 "<${tmp_phandle2}>" ++ env delete tmp_phandle1 tmp_phandle2 ++fi +diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-i2c0.dts b/arch/arm/boot/dts/overlay/sun8i-h3-i2c0.dts +new file mode 100644 +index 000000000..a36ac8667 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun8i-h3-i2c0.dts +@@ -0,0 +1,20 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun8i-h3"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ i2c0 = "/soc/i2c@1c2ac00"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&i2c0>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-i2c1.dts b/arch/arm/boot/dts/overlay/sun8i-h3-i2c1.dts +new file mode 100644 +index 000000000..258c86de0 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun8i-h3-i2c1.dts +@@ -0,0 +1,20 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun8i-h3"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ i2c1 = "/soc/i2c@1c2b000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&i2c1>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-i2c2.dts b/arch/arm/boot/dts/overlay/sun8i-h3-i2c2.dts +new file mode 100644 +index 000000000..a1e328498 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun8i-h3-i2c2.dts +@@ -0,0 +1,20 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun8i-h3"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ i2c2 = "/soc/i2c@1c2b400"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&i2c2>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-pps-gpio.dts b/arch/arm/boot/dts/overlay/sun8i-h3-pps-gpio.dts +new file mode 100644 +index 000000000..16a737b02 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun8i-h3-pps-gpio.dts +@@ -0,0 +1,29 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun8i-h3"; ++ ++ fragment@0 { ++ target = <&pio>; ++ __overlay__ { ++ pps_pins: pps_pins { ++ pins = "PD14"; ++ function = "gpio_in"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target-path = "/"; ++ __overlay__ { ++ pps@0 { ++ compatible = "pps-gpio"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pps_pins>; ++ gpios = <&pio 3 14 0>; /* PD14 */ ++ status = "okay"; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-pwm.dts b/arch/arm/boot/dts/overlay/sun8i-h3-pwm.dts +new file mode 100644 +index 000000000..ed3b8e606 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun8i-h3-pwm.dts +@@ -0,0 +1,39 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun8i-h3"; ++ ++ fragment@0 { ++ target-path = "/chosen"; ++ __overlay__ { ++ /delete-property/ stdout-path; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&uart0>; ++ __overlay__ { ++ status = "disabled"; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&pio>; ++ __overlay__ { ++ pwm0_pin: pwm0 { ++ pins = "PA5"; ++ function = "pwm0"; ++ }; ++ }; ++ }; ++ ++ fragment@3 { ++ target = <&pwm>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm0_pin>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-spdif-out.dts b/arch/arm/boot/dts/overlay/sun8i-h3-spdif-out.dts +new file mode 100644 +index 000000000..35b2d5677 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun8i-h3-spdif-out.dts +@@ -0,0 +1,38 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun8i-h3"; ++ ++ fragment@0 { ++ target = <&spdif>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spdif_tx_pin>; ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target-path = "/"; ++ __overlay__ { ++ sound { ++ compatible = "simple-audio-card"; ++ simple-audio-card,name = "On-board SPDIF"; ++ ++ simple-audio-card,cpu { ++ sound-dai = <&spdif>; ++ }; ++ ++ simple-audio-card,codec { ++ sound-dai = <&spdif_out>; ++ }; ++ }; ++ ++ spdif_out: spdif-out { ++ #sound-dai-cells = <0>; ++ compatible = "linux,spdif-dit"; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-spi-add-cs1.dts b/arch/arm/boot/dts/overlay/sun8i-h3-spi-add-cs1.dts +new file mode 100644 +index 000000000..bd8e25617 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun8i-h3-spi-add-cs1.dts +@@ -0,0 +1,41 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun8i-h3"; ++ ++ fragment@0 { ++ target = <&pio>; ++ __overlay__ { ++ spi0_cs1: spi0_cs1 { ++ pins = "PA21"; ++ function = "gpio_out"; ++ output-high; ++ }; ++ ++ spi1_cs1: spi1_cs1 { ++ pins = "PA10"; ++ function = "gpio_out"; ++ output-high; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&spi0>; ++ __overlay__ { ++ pinctrl-names = "default", "default"; ++ pinctrl-1 = <&spi0_cs1>; ++ cs-gpios = <0>, <&pio 0 21 0>; /* PA21 */ ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&spi1>; ++ __overlay__ { ++ pinctrl-names = "default", "default"; ++ pinctrl-1 = <&spi1_cs1>; ++ cs-gpios = <0>, <&pio 0 10 0>; /* PA10 */ ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-spi-jedec-nor.dts b/arch/arm/boot/dts/overlay/sun8i-h3-spi-jedec-nor.dts +new file mode 100644 +index 000000000..95fa5f2ca +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun8i-h3-spi-jedec-nor.dts +@@ -0,0 +1,42 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun8i-h3"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ spi0 = "/soc/spi@1c68000"; ++ spi1 = "/soc/spi@1c69000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&spi0>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spiflash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ status = "disabled"; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&spi1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spiflash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ status = "disabled"; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-spi-spidev.dts b/arch/arm/boot/dts/overlay/sun8i-h3-spi-spidev.dts +new file mode 100644 +index 000000000..c79beb95e +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun8i-h3-spi-spidev.dts +@@ -0,0 +1,42 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun8i-h3"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ spi0 = "/soc/spi@1c68000"; ++ spi1 = "/soc/spi@1c69000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&spi0>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spidev@0 { ++ compatible = "armbian,spi-dev"; ++ status = "disabled"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&spi1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spidev@0 { ++ compatible = "armbian,spi-dev"; ++ status = "disabled"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-uart1.dts b/arch/arm/boot/dts/overlay/sun8i-h3-uart1.dts +new file mode 100644 +index 000000000..3c10d4db4 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun8i-h3-uart1.dts +@@ -0,0 +1,22 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun8i-h3"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ serial1 = "/soc/serial@1c28400"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&uart1>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-uart2.dts b/arch/arm/boot/dts/overlay/sun8i-h3-uart2.dts +new file mode 100644 +index 000000000..f16e61862 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun8i-h3-uart2.dts +@@ -0,0 +1,22 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun8i-h3"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ serial2 = "/soc/serial@1c28800"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&uart2>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart2_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-uart3.dts b/arch/arm/boot/dts/overlay/sun8i-h3-uart3.dts +new file mode 100644 +index 000000000..b1aef575e +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun8i-h3-uart3.dts +@@ -0,0 +1,22 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun8i-h3"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ serial3 = "/soc/serial@1c28c00"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&uart3>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart3_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-usbhost0.dts b/arch/arm/boot/dts/overlay/sun8i-h3-usbhost0.dts +new file mode 100644 +index 000000000..6bd8aedbe +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun8i-h3-usbhost0.dts +@@ -0,0 +1,27 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun8i-h3"; ++ ++ fragment@0 { ++ target = <&ehci0>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&ohci0>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&usbphy>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-usbhost1.dts b/arch/arm/boot/dts/overlay/sun8i-h3-usbhost1.dts +new file mode 100644 +index 000000000..4c7222b10 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun8i-h3-usbhost1.dts +@@ -0,0 +1,27 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun8i-h3"; ++ ++ fragment@0 { ++ target = <&ehci1>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&ohci1>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&usbphy>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-usbhost2.dts b/arch/arm/boot/dts/overlay/sun8i-h3-usbhost2.dts +new file mode 100644 +index 000000000..2b83ec933 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun8i-h3-usbhost2.dts +@@ -0,0 +1,27 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun8i-h3"; ++ ++ fragment@0 { ++ target = <&ehci2>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&ohci2>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&usbphy>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-usbhost3.dts b/arch/arm/boot/dts/overlay/sun8i-h3-usbhost3.dts +new file mode 100644 +index 000000000..e2f28ab1a +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun8i-h3-usbhost3.dts +@@ -0,0 +1,27 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun8i-h3"; ++ ++ fragment@0 { ++ target = <&ehci3>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&ohci3>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&usbphy>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-w1-gpio.dts b/arch/arm/boot/dts/overlay/sun8i-h3-w1-gpio.dts +new file mode 100644 +index 000000000..f4ccb7fba +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun8i-h3-w1-gpio.dts +@@ -0,0 +1,29 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun8i-h3"; ++ ++ fragment@0 { ++ target = <&pio>; ++ __overlay__ { ++ w1_pins: w1_pins { ++ pins = "PD14"; ++ function = "gpio_in"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target-path = "/"; ++ __overlay__ { ++ onewire@0 { ++ compatible = "w1-gpio"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&w1_pins>; ++ gpios = <&pio 3 14 0>; /* PD14 */ ++ status = "okay"; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun8i-r40-i2c2.dts b/arch/arm/boot/dts/overlay/sun8i-r40-i2c2.dts +new file mode 100644 +index 000000000..a1e328498 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun8i-r40-i2c2.dts +@@ -0,0 +1,20 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun8i-h3"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ i2c2 = "/soc/i2c@1c2b400"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&i2c2>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun8i-r40-i2c3.dts b/arch/arm/boot/dts/overlay/sun8i-r40-i2c3.dts +new file mode 100644 +index 000000000..949a98234 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun8i-r40-i2c3.dts +@@ -0,0 +1,20 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun8i-h3"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ i2c3 = "/soc/i2c@1c2b800"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&i2c3>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun8i-r40-spi-spidev0.dts b/arch/arm/boot/dts/overlay/sun8i-r40-spi-spidev0.dts +new file mode 100644 +index 000000000..fae9c3f75 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun8i-r40-spi-spidev0.dts +@@ -0,0 +1,27 @@ ++/dts-v1/; ++/ { ++ compatible = "allwinner,sun8i-r40"; ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ spi0 = "/soc/spi@1c05000"; ++ }; ++ }; ++ fragment@1 { ++ target = <0xffffffff>; ++ __overlay__ { ++ #address-cells = <0x00000001>; ++ #size-cells = <0x00000000>; ++ status = "okay"; ++ spidev@0 { ++ compatible = "armbian,spi-dev"; ++ status = "okay"; ++ reg = <0x00000000>; ++ spi-max-frequency = <0x000f4240>; ++ }; ++ }; ++ }; ++ __fixups__ { ++ spi0 = "/fragment@1:target:0"; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun8i-r40-spi-spidev1.dts b/arch/arm/boot/dts/overlay/sun8i-r40-spi-spidev1.dts +new file mode 100644 +index 000000000..cb98ddf6b +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun8i-r40-spi-spidev1.dts +@@ -0,0 +1,27 @@ ++/dts-v1/; ++/ { ++ compatible = "allwinner,sun8i-r40"; ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ spi1 = "/soc/spi@1c06000"; ++ }; ++ }; ++ fragment@1 { ++ target = <0xffffffff>; ++ __overlay__ { ++ #address-cells = <0x00000001>; ++ #size-cells = <0x00000000>; ++ status = "okay"; ++ spidev@0 { ++ compatible = "armbian,spi-dev"; ++ status = "okay"; ++ reg = <0x00000000>; ++ spi-max-frequency = <0x000f4240>; ++ }; ++ }; ++ }; ++ __fixups__ { ++ spi1 = "/fragment@1:target:0"; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun8i-r40-uart2.dts b/arch/arm/boot/dts/overlay/sun8i-r40-uart2.dts +new file mode 100644 +index 000000000..2030d6777 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun8i-r40-uart2.dts +@@ -0,0 +1,22 @@ ++/dts-v1/; ++/ { ++ compatible = "allwinner,sun8i-r40"; ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ serial2 = "/soc/serial@1c28800"; ++ }; ++ }; ++ fragment@1 { ++ target = <0xffffffff>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <0xffffffff>; ++ status = "okay"; ++ }; ++ }; ++ __fixups__ { ++ uart2 = "/fragment@1:target:0"; ++ uart2_pi_pins = "/fragment@1/__overlay__:pinctrl-0:0"; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun8i-r40-uart4.dts b/arch/arm/boot/dts/overlay/sun8i-r40-uart4.dts +new file mode 100644 +index 000000000..0d7f934f6 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun8i-r40-uart4.dts +@@ -0,0 +1,22 @@ ++/dts-v1/; ++/ { ++ compatible = "allwinner,sun8i-r40"; ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ serial4 = "/soc/serial@1c29000"; ++ }; ++ }; ++ fragment@1 { ++ target = <0xffffffff>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <0xffffffff>; ++ status = "okay"; ++ }; ++ }; ++ __fixups__ { ++ uart4 = "/fragment@1:target:0"; ++ uart4_ph_pins = "/fragment@1/__overlay__:pinctrl-0:0"; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun8i-r40-uart5.dts b/arch/arm/boot/dts/overlay/sun8i-r40-uart5.dts +new file mode 100644 +index 000000000..e695535af +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun8i-r40-uart5.dts +@@ -0,0 +1,22 @@ ++/dts-v1/; ++/ { ++ compatible = "allwinner,sun8i-r40"; ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ serial5 = "/soc/serial@1c29400"; ++ }; ++ }; ++ fragment@1 { ++ target = <0xffffffff>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <0xffffffff>; ++ status = "okay"; ++ }; ++ }; ++ __fixups__ { ++ uart5 = "/fragment@1:target:0"; ++ uart5_ph_pins = "/fragment@1/__overlay__:pinctrl-0:0"; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun8i-r40-uart7.dts b/arch/arm/boot/dts/overlay/sun8i-r40-uart7.dts +new file mode 100644 +index 000000000..e57259833 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun8i-r40-uart7.dts +@@ -0,0 +1,22 @@ ++/dts-v1/; ++/ { ++ compatible = "allwinner,sun8i-r40"; ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ serial7 = "/soc/serial@1c29c00"; ++ }; ++ }; ++ fragment@1 { ++ target = <0xffffffff>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <0xffffffff>; ++ status = "okay"; ++ }; ++ }; ++ __fixups__ { ++ uart7 = "/fragment@1:target:0"; ++ uart7_pi_pins = "/fragment@1/__overlay__:pinctrl-0:0"; ++ }; ++}; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-overlay-sun8i-h3-cpu-clock-add-overclock.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-overlay-sun8i-h3-cpu-clock-add-overclock.patch new file mode 100644 index 0000000000..e8b9f70a7f --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-overlay-sun8i-h3-cpu-clock-add-overclock.patch @@ -0,0 +1,209 @@ +From d27eca2a3c40f3f477cfb8848f0daf59ef2b8056 Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Wed, 2 Feb 2022 21:29:16 +0300 +Subject: [PATCH 112/153] arm:dts:overlay: sun8i-h3-cpu-clock add overclock + +--- + arch/arm/boot/dts/overlay/Makefile | 3 + + .../sun8i-h3-cpu-clock-1.2GHz-1.3v.dts | 31 +++++++++ + .../sun8i-h3-cpu-clock-1.368GHz-1.3v.dts | 67 +++++++++++++++++++ + .../sun8i-h3-cpu-clock-1.3GHz-1.3v.dts | 61 +++++++++++++++++ + 4 files changed, 162 insertions(+) + create mode 100644 arch/arm/boot/dts/overlay/sun8i-h3-cpu-clock-1.2GHz-1.3v.dts + create mode 100644 arch/arm/boot/dts/overlay/sun8i-h3-cpu-clock-1.368GHz-1.3v.dts + create mode 100644 arch/arm/boot/dts/overlay/sun8i-h3-cpu-clock-1.3GHz-1.3v.dts + +diff --git a/arch/arm/boot/dts/overlay/Makefile b/arch/arm/boot/dts/overlay/Makefile +index d2e94f6b7..23f8c2048 100644 +--- a/arch/arm/boot/dts/overlay/Makefile ++++ b/arch/arm/boot/dts/overlay/Makefile +@@ -60,6 +60,9 @@ dtbo-$(CONFIG_MACH_SUN7I) += \ + dtbo-$(CONFIG_MACH_SUN8I) += \ + sun8i-h3-analog-codec.dtbo \ + sun8i-h3-cir.dtbo \ ++ sun8i-h3-cpu-clock-1.2GHz-1.3v.dtbo \ ++ sun8i-h3-cpu-clock-1.368GHz-1.3v.dtbo \ ++ sun8i-h3-cpu-clock-1.3GHz-1.3v.dtbo \ + sun8i-h3-i2c0.dtbo \ + sun8i-h3-i2c1.dtbo \ + sun8i-h3-i2c2.dtbo \ +diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-cpu-clock-1.2GHz-1.3v.dts b/arch/arm/boot/dts/overlay/sun8i-h3-cpu-clock-1.2GHz-1.3v.dts +new file mode 100644 +index 000000000..b07e694c7 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun8i-h3-cpu-clock-1.2GHz-1.3v.dts +@@ -0,0 +1,31 @@ ++// DT overlay for CPU frequency operating points to up to 1.2GHz at a maximum CPU voltage of 1.3v ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ fragment@0 { ++ target = <&cpu0_opp_table>; ++ ++ __overlay__ { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ ++ // in order to match the existing DT cooling-maps, update the existing OP table in-place ++ // with the new voltages ++ ++ opp-1104000000 { ++ opp-hz = /bits/ 64 <1104000000>; ++ opp-microvolt = <1300000 1300000 1300000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ ++ opp-1200000000 { ++ opp-hz = /bits/ 64 <1200000000>; ++ opp-microvolt = <1300000 1300000 1300000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ }; ++ }; ++}; ++ +diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-cpu-clock-1.368GHz-1.3v.dts b/arch/arm/boot/dts/overlay/sun8i-h3-cpu-clock-1.368GHz-1.3v.dts +new file mode 100644 +index 000000000..e3fd7e5c8 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun8i-h3-cpu-clock-1.368GHz-1.3v.dts +@@ -0,0 +1,67 @@ ++// DT overlay for CPU frequency operating points to 1.3GHz at a maximum CPU voltage of 1.3v ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ fragment@0 { ++ target = <&cpu0_opp_table>; ++ ++ __overlay__ { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ ++ // in order to match the DT cooling-maps, update the existing OP table in-place ++ // with the new voltages ++ ++ opp-1056000000 { ++ opp-hz = /bits/ 64 <1056000000>; ++ opp-microvolt = <1300000 1300000 1300000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ ++ opp-1104000000 { ++ opp-hz = /bits/ 64 <1104000000>; ++ opp-microvolt = <1300000 1300000 1300000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ ++ opp-1152000000 { ++ opp-hz = /bits/ 64 <1152000000>; ++ opp-microvolt = <1300000 1300000 1300000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ ++ opp-1200000000 { ++ opp-hz = /bits/ 64 <1200000000>; ++ opp-microvolt = <1300000 1300000 1300000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ ++ opp-1224000000 { ++ opp-hz = /bits/ 64 <1224000000>; ++ opp-microvolt = <1300000 1300000 1300000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ ++ opp-1248000000 { ++ opp-hz = /bits/ 64 <1248000000>; ++ opp-microvolt = <1300000 1300000 1300000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ ++ opp-1296000000 { ++ opp-hz = /bits/ 64 <1296000000>; ++ opp-microvolt = <1300000 1300000 1300000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ ++ opp-1368000000 { ++ opp-hz = /bits/ 64 <1368000000>; ++ opp-microvolt = <1300000 1300000 1300000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ }; ++ }; ++}; ++ +diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-cpu-clock-1.3GHz-1.3v.dts b/arch/arm/boot/dts/overlay/sun8i-h3-cpu-clock-1.3GHz-1.3v.dts +new file mode 100644 +index 000000000..413222831 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun8i-h3-cpu-clock-1.3GHz-1.3v.dts +@@ -0,0 +1,61 @@ ++// DT overlay for CPU frequency operating points to 1.3GHz at a maximum CPU voltage of 1.3v ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ fragment@0 { ++ target = <&cpu0_opp_table>; ++ ++ __overlay__ { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ ++ // in order to match the DT cooling-maps, update the existing OP table in-place ++ // with the new voltages ++ ++ opp-1056000000 { ++ opp-hz = /bits/ 64 <1056000000>; ++ opp-microvolt = <1300000 1300000 1300000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ ++ opp-1104000000 { ++ opp-hz = /bits/ 64 <1104000000>; ++ opp-microvolt = <1300000 1300000 1300000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ ++ opp-1152000000 { ++ opp-hz = /bits/ 64 <1152000000>; ++ opp-microvolt = <1300000 1300000 1300000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ ++ opp-1200000000 { ++ opp-hz = /bits/ 64 <1200000000>; ++ opp-microvolt = <1300000 1300000 1300000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ ++ opp-1224000000 { ++ opp-hz = /bits/ 64 <1224000000>; ++ opp-microvolt = <1300000 1300000 1300000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ ++ opp-1248000000 { ++ opp-hz = /bits/ 64 <1248000000>; ++ opp-microvolt = <1300000 1300000 1300000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ ++ opp-1296000000 { ++ opp-hz = /bits/ 64 <1296000000>; ++ opp-microvolt = <1300000 1300000 1300000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ }; ++ }; ++}; ++ +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-sun5i-a13-olinuxino-Add-panel-lcd-olinuxino-4.3-needed-.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-sun5i-a13-olinuxino-Add-panel-lcd-olinuxino-4.3-needed-.patch new file mode 100644 index 0000000000..08ab8ce58b --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-sun5i-a13-olinuxino-Add-panel-lcd-olinuxino-4.3-needed-.patch @@ -0,0 +1,133 @@ +From 38c6adabf81eaa1e2c2687591d98fb987f6be080 Mon Sep 17 00:00:00 2001 +From: hehopmajieh +Date: Thu, 19 Mar 2020 10:40:44 +0200 +Subject: [PATCH 119/153] arm:dts:sun5i-a13-olinuxino Add panel + lcd-olinuxino-4.3 needed to fix overlay tests + +--- + arch/arm/boot/dts/sun5i-a13-olinuxino.dts | 79 +++++++++++++---------- + 1 file changed, 44 insertions(+), 35 deletions(-) + +diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts +index fadeae3cd..d015a24c6 100644 +--- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts ++++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts +@@ -48,6 +48,7 @@ + + #include + #include ++#include + + / { + model = "Olimex A13-Olinuxino"; +@@ -72,40 +73,28 @@ led { + }; + }; + +- bridge { +- compatible = "dumb-vga-dac"; ++ lcd_backlight: backlight { ++ compatible = "pwm-backlight"; ++ pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; ++ brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; ++ default-brightness-level = <8>; ++ }; ++ ++ panel: panel { ++ compatible = "olimex,lcd-olinuxino-4.3"; ++ backlight = <&lcd_backlight>; ++ enable-gpios = <&axp_gpio 0 GPIO_ACTIVE_HIGH>; /* AXP GPIO0 */ ++ pinctrl-names = "default"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ port { ++ panel_input: endpoint { ++ remote-endpoint = <&tcon0_out_lcd>; ++ }; ++ }; ++ ++ }; + +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- vga_bridge_in: endpoint { +- remote-endpoint = <&tcon0_out_vga>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- vga_bridge_out: endpoint { +- remote-endpoint = <&vga_con_in>; +- }; +- }; +- }; +- }; +- +- vga { +- compatible = "vga-connector"; +- +- port { +- vga_con_in: endpoint { +- remote-endpoint = <&vga_bridge_out>; +- }; +- }; +- }; + }; + + &be0 { +@@ -130,6 +119,11 @@ axp209: pmic@34 { + + interrupt-controller; + #interrupt-cells = <1>; ++ axp_gpio:gpio{ ++ compatible = "x-powers,axp209-gpio"; ++ gpio-controller; ++ #gpio-cells = <2>; ++ }; + }; + }; + +@@ -221,12 +215,18 @@ &tcon0 { + }; + + &tcon0_out { +- tcon0_out_vga: endpoint@0 { ++ tcon0_out_lcd: endpoint@0 { + reg = <0>; +- remote-endpoint = <&vga_bridge_in>; ++ remote-endpoint = <&panel_input>; + }; + }; + ++&pwm { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm0_pin>; ++ status = "okay"; ++}; ++ + &uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pg_pins>; +@@ -245,3 +245,12 @@ &usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + status = "okay"; + }; ++ ++&rtp { ++ allwinner,ts-attached; ++ #thermal-sensor-cells = <0>; ++ /* sensitive/noisy touch panel */ ++ touchscreen-inverted-x; ++ allwinner,tp-sensitive-adjust = <0>; ++ allwinner,filter-type = <3>; ++}; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-sun5i-a13-olinuxino-micro-add-panel-lcd-olinuxino-4.3.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-sun5i-a13-olinuxino-micro-add-panel-lcd-olinuxino-4.3.patch new file mode 100644 index 0000000000..249260c240 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-sun5i-a13-olinuxino-micro-add-panel-lcd-olinuxino-4.3.patch @@ -0,0 +1,107 @@ +From e164959b426df800902fa268d6e59b08ccf897e0 Mon Sep 17 00:00:00 2001 +From: Mitko Gamishev +Date: Wed, 5 Feb 2020 15:00:25 +0200 +Subject: [PATCH 118/153] arm:dts:sun5i-a13-olinuxino-micro add panel + lcd-olinuxino-4.3 + +--- + .../boot/dts/sun5i-a13-olinuxino-micro.dts | 62 ++++++++++++++++++- + 1 file changed, 60 insertions(+), 2 deletions(-) + +diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts +index bfe1075e6..32874f6a5 100644 +--- a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts ++++ b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts +@@ -44,7 +44,7 @@ + /dts-v1/; + #include "sun5i-a13.dtsi" + #include "sunxi-common-regulators.dtsi" +- ++#include + #include + + / { +@@ -70,6 +70,40 @@ led { + default-state = "on"; + }; + }; ++ ++ backlight: backlight { ++ compatible = "pwm-backlight"; ++ pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; ++ brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; ++ default-brightness-level = <8>; ++ ++ }; ++ ++ panel: panel { ++ compatible = "olimex,lcd-olinuxino-4.3"; ++ backlight = <&backlight>; ++ enable-gpios = <&pio 1 10 GPIO_ACTIVE_HIGH>; /* PB10 */ ++ pinctrl-names = "default"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ port { ++ panel_input: endpoint { ++ remote-endpoint = <&tcon0_out_lcd>; ++ }; ++ }; ++ ++ }; ++ ++ }; ++ ++ ++ ++&be0 { ++ status = "okay"; ++}; ++ ++&codec { ++ status = "okay"; + }; + + &ehci0 { +@@ -117,10 +151,28 @@ ®_usb0_vbus { + }; + + ®_usb1_vbus { +- gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>; ++ gpio = <&pio 2 19 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + ++&tcon0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&lcd_rgb666_pins>; ++ status = "okay"; ++}; ++&tcon0_out { ++ tcon0_out_lcd: endpoint@0 { ++ reg = <0>; ++ remote-endpoint = <&panel_input>; ++ }; ++}; ++ ++&pwm { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm0_pin>; ++ status = "okay"; ++}; ++ + &uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pg_pins>; +@@ -139,3 +191,9 @@ &usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + status = "okay"; + }; ++ ++&rtp { ++ allwinner,ts-attached; ++ touchscreen-inverted-x; ++}; ++ +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-sun7i-a20-Disable-OOB-IRQ-for-brcm-wifi-on-Cubietruck-a.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-sun7i-a20-Disable-OOB-IRQ-for-brcm-wifi-on-Cubietruck-a.patch new file mode 100644 index 0000000000..714ebb41ca --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-sun7i-a20-Disable-OOB-IRQ-for-brcm-wifi-on-Cubietruck-a.patch @@ -0,0 +1,99 @@ +From f95af1ad0a757b083d0aab1a1b4f90c966e1656c Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Sun, 23 Jan 2022 22:32:07 +0300 +Subject: [PATCH 054/153] arm:dts:sun7i-a20 Disable OOB IRQ for brcm-wifi on + Cubietruck and Banana-Pro + +While doing some brcmfmac driver work I needed to test this also on some +devicetree based boards. So I fired up the good old Cubietruck and when +that would not work a Banana Pro. + +With an unmodified 4.17 kernel both boards intermittently would come up +with non working wifi with the following errors: + + brcmfmac: brcmf_sdio_bus_rxctl: resumed on timeout + brcmfmac: brcmf_bus_started: failed: -110 + brcmfmac: brcmf_attach: dongle is not responding: err=-110 + brcmfmac: brcmf_sdio_firmware_callback: brcmf_attach failed + +They would come up this way more often then with actual working wifi, +once this problem happens it seems to require a power-cycle to fix. +Once things work one can safely reboot without hitting the issue. + +I've found that disabling OOB interrupts fixes this. This really is more +of a workaround then a proper fix, but it makes the wifi reliable again +and it does not have much of a downside. + +Using an OOB IRQ instead of the sdio-IRQ mechanism is mostly important to +allow the MMC controller to go into runtime-suspend which is not really an +issue on these boards since they are (usually) not battery powered. + +I've looked at recent brcmfmac and mmc-core changes which may explain this +and I've not found anything. So the most likely culprit is the A20 external +interrupt handling e.g. perhaps it is set to edge instead of level? Either +way I do not have time to further investigate this. + +BugLink: https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=908438 +Signed-off-by: Hans de Goede +--- + arch/arm/boot/dts/sun7i-a20-bananapro.dts | 16 +++++++++++++--- + arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 16 +++++++++++++--- + 2 files changed, 26 insertions(+), 6 deletions(-) + +diff --git a/arch/arm/boot/dts/sun7i-a20-bananapro.dts b/arch/arm/boot/dts/sun7i-a20-bananapro.dts +index e22f0e8bb..e68748076 100644 +--- a/arch/arm/boot/dts/sun7i-a20-bananapro.dts ++++ b/arch/arm/boot/dts/sun7i-a20-bananapro.dts +@@ -162,9 +162,19 @@ &mmc3 { + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; +- interrupt-parent = <&pio>; +- interrupts = <7 15 IRQ_TYPE_LEVEL_LOW>; +- interrupt-names = "host-wake"; ++ /* ++ * OOB interrupt support is broken ATM, often the first irq ++ * does not get seen resulting in the drv probe failing with: ++ * ++ * brcmfmac: brcmf_sdio_bus_rxctl: resumed on timeout ++ * brcmfmac: brcmf_bus_started: failed: -110 ++ * brcmfmac: brcmf_attach: dongle is not responding: err=-110 ++ * brcmfmac: brcmf_sdio_firmware_callback: brcmf_attach failed ++ * ++ * interrupt-parent = <&pio>; ++ * interrupts = <7 15 IRQ_TYPE_LEVEL_LOW>; ++ * interrupt-names = "host-wake"; ++ */ + }; + }; + +diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts +index 52160e368..525cb7fcc 100644 +--- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts ++++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts +@@ -213,9 +213,19 @@ &mmc3 { + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; +- interrupt-parent = <&pio>; +- interrupts = <7 10 IRQ_TYPE_LEVEL_LOW>; /* PH10 / EINT10 */ +- interrupt-names = "host-wake"; ++ /* ++ * OOB interrupt support is broken ATM, often the first irq ++ * does not get seen resulting in the drv probe failing with: ++ * ++ * brcmfmac: brcmf_sdio_bus_rxctl: resumed on timeout ++ * brcmfmac: brcmf_bus_started: failed: -110 ++ * brcmfmac: brcmf_attach: dongle is not responding: err=-110 ++ * brcmfmac: brcmf_sdio_firmware_callback: brcmf_attach failed ++ * ++ * interrupt-parent = <&pio>; ++ * interrupts = <7 10 IRQ_TYPE_LEVEL_LOW>; ++ * interrupt-names = "host-wake"; ++ */ + }; + }; + +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-sun7i-a20-bananapro-add-hdmi-connector-de.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-sun7i-a20-bananapro-add-hdmi-connector-de.patch new file mode 100644 index 0000000000..5503c17af5 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-sun7i-a20-bananapro-add-hdmi-connector-de.patch @@ -0,0 +1,78 @@ +From c48132e824d80c1f1660921965dddc7b14fd8c1a Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Fri, 28 Jan 2022 15:15:19 +0300 +Subject: [PATCH 068/153] arm:dts: sun7i-a20-bananapro add hdmi-connector, de + +--- + arch/arm/boot/dts/sun7i-a20-bananapro.dts | 30 +++++++++++++++++++++++ + 1 file changed, 30 insertions(+) + +diff --git a/arch/arm/boot/dts/sun7i-a20-bananapro.dts b/arch/arm/boot/dts/sun7i-a20-bananapro.dts +index e68748076..3a34fb39a 100644 +--- a/arch/arm/boot/dts/sun7i-a20-bananapro.dts ++++ b/arch/arm/boot/dts/sun7i-a20-bananapro.dts +@@ -60,6 +60,17 @@ chosen { + stdout-path = "serial0:115200n8"; + }; + ++ hdmi-connector { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi_con_in: endpoint { ++ remote-endpoint = <&hdmi_out_con>; ++ }; ++ }; ++ }; ++ + leds { + compatible = "gpio-leds"; + +@@ -91,6 +102,7 @@ reg_gmac_3v3: gmac-3v3 { + }; + + &ahci { ++ target-supply = <®_ahci_5v>; + status = "okay"; + }; + +@@ -98,6 +110,10 @@ &codec { + status = "okay"; + }; + ++&de { ++ status = "okay"; ++}; ++ + &ehci0 { + status = "okay"; + }; +@@ -115,6 +131,16 @@ &gmac { + status = "okay"; + }; + ++&hdmi { ++ status = "okay"; ++}; ++ ++&hdmi_out { ++ hdmi_out_con: endpoint { ++ remote-endpoint = <&hdmi_con_in>; ++ }; ++}; ++ + &i2c0 { + status = "okay"; + +@@ -227,3 +253,7 @@ &usbphy { + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; + }; ++ ++®_ahci_5v { ++ status = "okay"; ++}; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-sun7i-a20-cubietruck-add-alias-uart2.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-sun7i-a20-cubietruck-add-alias-uart2.patch new file mode 100644 index 0000000000..d8a2428baf --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-sun7i-a20-cubietruck-add-alias-uart2.patch @@ -0,0 +1,24 @@ +From ff06f7672c6bbbcfa786bc71f97f79610d891291 Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Fri, 28 Jan 2022 11:38:08 +0300 +Subject: [PATCH 064/153] arm:dts: sun7i-a20-cubietruck add alias uart2 + +--- + arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts +index df428f29b..a3d169c43 100644 +--- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts ++++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts +@@ -55,6 +55,7 @@ / { + + aliases { + serial0 = &uart0; ++ serial2 = &uart2; + }; + + chosen { +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-sun7i-a20-olimex-som-204-evb-olinuxino-micro-decrease-d.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-sun7i-a20-olimex-som-204-evb-olinuxino-micro-decrease-d.patch new file mode 100644 index 0000000000..7b02b38b3e --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-sun7i-a20-olimex-som-204-evb-olinuxino-micro-decrease-d.patch @@ -0,0 +1,55 @@ +From 126800dd0f2a76dd7aeeb74e0cf43c39264344b0 Mon Sep 17 00:00:00 2001 +From: Stefan Saraev +Date: Wed, 24 Jun 2020 20:53:36 +0300 +Subject: [PATCH 123/153] arm:dts:sun7i-a20: + olimex-som(204)-evb,olinuxino-micro decrease dcdc2 min voltage + +fixes some kernel crashes +--- + arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts | 2 +- + arch/arm/boot/dts/sun7i-a20-olimex-som204-evb.dts | 2 +- + arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 2 +- + 3 files changed, 3 insertions(+), 3 deletions(-) + +diff --git a/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts b/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts +index f05ee32bc..e1867190c 100644 +--- a/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts ++++ b/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts +@@ -247,7 +247,7 @@ ®_ahci_5v { + + ®_dcdc2 { + regulator-always-on; +- regulator-min-microvolt = <1000000>; ++ regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; + }; +diff --git a/arch/arm/boot/dts/sun7i-a20-olimex-som204-evb.dts b/arch/arm/boot/dts/sun7i-a20-olimex-som204-evb.dts +index 54af6c180..ae3aa1055 100644 +--- a/arch/arm/boot/dts/sun7i-a20-olimex-som204-evb.dts ++++ b/arch/arm/boot/dts/sun7i-a20-olimex-som204-evb.dts +@@ -218,7 +218,7 @@ ®_ahci_5v { + + ®_dcdc2 { + regulator-always-on; +- regulator-min-microvolt = <1000000>; ++ regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; + }; +diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts +index a1b89b2a2..7077ceea7 100644 +--- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts ++++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts +@@ -268,7 +268,7 @@ &battery_power_supply { + + ®_dcdc2 { + regulator-always-on; +- regulator-min-microvolt = <1000000>; ++ regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; + }; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-sun7i-a20-olinuxino-lime2-enable-audio-codec.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-sun7i-a20-olinuxino-lime2-enable-audio-codec.patch new file mode 100644 index 0000000000..3c04149f7a --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-sun7i-a20-olinuxino-lime2-enable-audio-codec.patch @@ -0,0 +1,27 @@ +From 706175bff4614f00b725ee3d4a0c6dda86b8a8ff Mon Sep 17 00:00:00 2001 +From: Stefan Saraev +Date: Wed, 3 Jun 2020 13:49:44 +0300 +Subject: [PATCH 121/153] arm:dts:sun7i-a20-olinuxino-lime2 enable audio codec + +--- + arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts +index ecb91fb89..e0174ca48 100644 +--- a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts ++++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts +@@ -96,6 +96,10 @@ &ahci { + status = "okay"; + }; + ++&codec { ++ status = "okay"; ++}; ++ + &de { + status = "okay"; + }; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-sun7i-a20-olinuxino-lime2-enable-ldo3-always-on.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-sun7i-a20-olinuxino-lime2-enable-ldo3-always-on.patch new file mode 100644 index 0000000000..8b6884e9a5 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-sun7i-a20-olinuxino-lime2-enable-ldo3-always-on.patch @@ -0,0 +1,29 @@ +From f18352399fc8730cb93459fc20ffd5a2b0741537 Mon Sep 17 00:00:00 2001 +From: hehopmajieh +Date: Tue, 16 Jun 2020 15:40:59 +0300 +Subject: [PATCH 122/153] arm:dts:sun7i-a20-olinuxino-lime2 enable ldo3 + always-on + +--- + arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts +index e0174ca48..ae710f785 100644 +--- a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts ++++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts +@@ -237,10 +237,10 @@ ®_ldo2 { + }; + + ®_ldo3 { ++ regulator-always-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "vddio-csi0"; +- regulator-soft-start; + regulator-ramp-delay = <1600>; + }; + +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-sun7i-a20-olinuxino-micro-emmc-Add-vqmmc-node.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-sun7i-a20-olinuxino-micro-emmc-Add-vqmmc-node.patch new file mode 100644 index 0000000000..f00bf9cd3e --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-sun7i-a20-olinuxino-micro-emmc-Add-vqmmc-node.patch @@ -0,0 +1,24 @@ +From 9be4cefbbac2c5917094399daaf7606aa643dde8 Mon Sep 17 00:00:00 2001 +From: hehopmajieh +Date: Tue, 14 Apr 2020 10:28:16 +0300 +Subject: [PATCH 120/153] arm:dts:sun7i-a20-olinuxino-micro-emmc Add vqmmc node + +--- + arch/arm/boot/dts/sun7i-a20-olinuxino-micro-emmc.dts | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro-emmc.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro-emmc.dts +index 2337b44a8..c79e9ad02 100644 +--- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro-emmc.dts ++++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro-emmc.dts +@@ -55,6 +55,7 @@ mmc2_pwrseq: pwrseq { + + &mmc2 { + vmmc-supply = <®_vcc3v3>; ++ vqmmc-supply = <®_vcc3v3>; + bus-width = <4>; + non-removable; + mmc-pwrseq = <&mmc2_pwrseq>; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-sun8i-h2-plus-orangepi-zero-fix-xradio-interrupt.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-sun8i-h2-plus-orangepi-zero-fix-xradio-interrupt.patch new file mode 100644 index 0000000000..138fcf8719 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-sun8i-h2-plus-orangepi-zero-fix-xradio-interrupt.patch @@ -0,0 +1,36 @@ +From 447f5e3777943f70586637d1e95b37d81e28a37c Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Mon, 7 Feb 2022 19:15:17 +0300 +Subject: [PATCH 139/153] arm:dts: sun8i-h2-plus-orangepi-zero fix xradio + interrupt + +--- + arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts +index 3706216ff..7b42ab8b5 100644 +--- a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts ++++ b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts +@@ -49,6 +49,7 @@ + + #include + #include ++#include + + / { + model = "Xunlong Orange Pi Zero"; +@@ -151,6 +152,10 @@ &mmc1 { + */ + xr819: sdio_wifi@1 { + reg = <1>; ++ compatible = "xradio,xr819"; ++ interrupt-parent = <&pio>; ++ interrupts = <6 10 IRQ_TYPE_EDGE_RISING>; ++ interrupt-names = "host-wake"; + }; + }; + +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-sun8i-h3-add-thermal-zones.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-sun8i-h3-add-thermal-zones.patch new file mode 100644 index 0000000000..dabe77f2f8 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-sun8i-h3-add-thermal-zones.patch @@ -0,0 +1,104 @@ +From f2834595e9b8c624079e1d3c6af878795592991c Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Wed, 2 Feb 2022 21:34:48 +0300 +Subject: [PATCH 124/153] arm:dts:sun8i-h3 add thermal zones + +--- + arch/arm/boot/dts/sun8i-h3.dtsi | 68 ++++++++++++++++++++++++++------- + 1 file changed, 55 insertions(+), 13 deletions(-) + +diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi +index 30d72d3b6..1b02a4c3f 100644 +--- a/arch/arm/boot/dts/sun8i-h3.dtsi ++++ b/arch/arm/boot/dts/sun8i-h3.dtsi +@@ -297,32 +297,74 @@ ths: thermal-sensor@1c25000 { + }; + + thermal-zones { +- cpu_thermal: cpu-thermal { +- polling-delay-passive = <0>; +- polling-delay = <0>; ++ cpu_thermal { ++ /* milliseconds */ ++ polling-delay-passive = <250>; ++ polling-delay = <1000>; + thermal-sensors = <&ths>; + + trips { +- cpu_hot_trip: cpu-hot { ++ cpu_warm: cpu_warm { ++ temperature = <75000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ ++ cpu_hot_pre: cpu_hot_pre { + temperature = <80000>; + hysteresis = <2000>; + type = "passive"; + }; + +- cpu_very_hot_trip: cpu-very-hot { +- temperature = <100000>; +- hysteresis = <0>; ++ cpu_hot: cpu_hot { ++ temperature = <85000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ ++ cpu_very_hot_pre: cpu_very_hot_pre { ++ temperature = <90000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ ++ cpu_very_hot: cpu_very_hot { ++ temperature = <95000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ ++ cpu_crit: cpu_crit { ++ temperature = <105000>; ++ hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { +- cpu-hot-limit { +- trip = <&cpu_hot_trip>; +- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ cpu_warm_limit_cpu { ++ trip = <&cpu_warm>; ++ cooling-device = <&cpu0 THERMAL_NO_LIMIT 2>; ++ }; ++ ++ cpu_hot_pre_limit_cpu { ++ trip = <&cpu_hot_pre>; ++ cooling-device = <&cpu0 2 3>; ++ }; ++ ++ cpu_hot_limit_cpu { ++ trip = <&cpu_hot>; ++ cooling-device = <&cpu0 3 4>; ++ }; ++ ++ cpu_very_hot_pre_limit_cpu { ++ trip = <&cpu_very_hot_pre>; ++ cooling-device = <&cpu0 5 6>; ++ }; ++ ++ cpu_very_hot_limit_cpu { ++ trip = <&cpu_very_hot>; ++ cooling-device = <&cpu0 7 THERMAL_NO_LIMIT>; + }; + }; + }; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-sun8i-h3-bananapi-m2-plus-add-wifi_pwrseq.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-sun8i-h3-bananapi-m2-plus-add-wifi_pwrseq.patch new file mode 100644 index 0000000000..9989ed9822 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-sun8i-h3-bananapi-m2-plus-add-wifi_pwrseq.patch @@ -0,0 +1,25 @@ +From b6ab70e11937660ba3420f6418c9c9ca93de7c88 Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Fri, 28 Jan 2022 15:06:34 +0300 +Subject: [PATCH 067/153] arm:dts:sun8i-h3-bananapi-m2-plus add wifi_pwrseq + +--- + arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts +index 195a75da1..f3f324e66 100644 +--- a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts ++++ b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts +@@ -48,3 +48,8 @@ / { + model = "Banana Pi BPI-M2-Plus H3"; + compatible = "sinovoip,bpi-m2-plus", "allwinner,sun8i-h3"; + }; ++ ++&wifi_pwrseq { ++ clocks = <&rtc 1>; ++ clock-names = "ext_clock"; ++}; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-sun8i-h3-nanopi-add-leds-pio-pins.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-sun8i-h3-nanopi-add-leds-pio-pins.patch new file mode 100644 index 0000000000..40b7ba29b2 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-sun8i-h3-nanopi-add-leds-pio-pins.patch @@ -0,0 +1,60 @@ +From 7f770fb3fa862d2a54a4ae42dda6a3889cea67d3 Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Mon, 24 Jan 2022 14:14:41 +0300 +Subject: [PATCH 056/153] arm:dts: sun8i-h3-nanopi add leds pio pins + +--- + arch/arm/boot/dts/sun8i-h3-nanopi.dtsi | 23 +++++++++++++++++++++++ + 1 file changed, 23 insertions(+) + +diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi b/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi +index cf8413fba..57d5f7513 100644 +--- a/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi ++++ b/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi +@@ -59,6 +59,8 @@ chosen { + + leds { + compatible = "gpio-leds"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&leds_npi>, <&leds_r_npi>; + + led-0 { + label = "nanopi:blue:status"; +@@ -75,6 +77,8 @@ led-1 { + + gpio-keys { + compatible = "gpio-keys"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sw_r_npi>; + + key-0 { + label = "k1"; +@@ -100,6 +104,25 @@ &ohci3 { + status = "okay"; + }; + ++&pio { ++ leds_npi: led_pins { ++ pins = "PA10"; ++ function = "gpio_out"; ++ }; ++}; ++ ++&r_pio { ++ leds_r_npi: led_pins { ++ pins = "PL10"; ++ function = "gpio_out"; ++ }; ++ ++ sw_r_npi: key_pins { ++ pins = "PL3"; ++ function = "gpio_in"; ++ }; ++}; ++ + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pa_pins>; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-sun8i-h3-nanopi-duo2-enable-powerbutton-and-ethernet.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-sun8i-h3-nanopi-duo2-enable-powerbutton-and-ethernet.patch new file mode 100644 index 0000000000..fc1e2db545 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-sun8i-h3-nanopi-duo2-enable-powerbutton-and-ethernet.patch @@ -0,0 +1,63 @@ +From f6f0b76bcfcb1163e304c262207aeb714d16307b Mon Sep 17 00:00:00 2001 +From: Gunjan Gupta +Date: Mon, 26 Jun 2023 13:29:46 +0000 +Subject: [PATCH 1/2] ARM: dts: sun8i: nanopiduo2: Use key-0 as power button + +The onboard button key-0 was not marked as power button. This meant +that once the board was suspended, there was no way to bring it back +to life. Mark key-0 as power button so that it can be used to bring +the board back to life +--- + arch/arm/boot/dts/sun8i-h3-nanopi-duo2.dts | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-duo2.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-duo2.dts +index 343b02b97..4878d27ba 100644 +--- a/arch/arm/boot/dts/sun8i-h3-nanopi-duo2.dts ++++ b/arch/arm/boot/dts/sun8i-h3-nanopi-duo2.dts +@@ -42,8 +42,9 @@ gpio-keys { + + key-0 { + label = "k1"; +- linux,code = ; ++ linux,code = ; + gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; /* PL3 */ ++ wakeup-source; + }; + }; + +-- +2.34.1 + + +From 51af316406c82571be4a30665fbf93cab9caf080 Mon Sep 17 00:00:00 2001 +From: Gunjan Gupta +Date: Mon, 26 Jun 2023 13:53:14 +0000 +Subject: [PATCH 2/2] ARM: dts: sun8i: nanopiduo2: enable ethernet + +NanoPi Duo2 has pinout for ethernet. Lets enable the same in dts +--- + arch/arm/boot/dts/sun8i-h3-nanopi-duo2.dts | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-duo2.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-duo2.dts +index 4878d27ba..8669fd087 100644 +--- a/arch/arm/boot/dts/sun8i-h3-nanopi-duo2.dts ++++ b/arch/arm/boot/dts/sun8i-h3-nanopi-duo2.dts +@@ -105,6 +105,13 @@ &ehci0 { + status = "okay"; + }; + ++&emac { ++ phy-handle = <&int_mii_phy>; ++ phy-mode = "mii"; ++ allwinner,leds-active-low; ++ status = "okay"; ++}; ++ + &mmc0 { + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ +-- +2.34.1 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-sun8i-h3-orangepi-pc-plus-add-wifi_pwrseq.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-sun8i-h3-orangepi-pc-plus-add-wifi_pwrseq.patch new file mode 100644 index 0000000000..cc6b673e43 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-sun8i-h3-orangepi-pc-plus-add-wifi_pwrseq.patch @@ -0,0 +1,33 @@ +From dd1fd9fa33d92210223176a83f1a4d4b3ac27ec2 Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Mon, 7 Feb 2022 19:01:59 +0300 +Subject: [PATCH 137/153] arm:dts: sun8i-h3-orangepi-pc-plus add wifi_pwrseq + +--- + arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts +index babf4cf1b..e1efbf1b1 100644 +--- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts ++++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts +@@ -51,10 +51,16 @@ aliases { + /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */ + ethernet1 = &rtl8189ftv; + }; ++ ++ wifi_pwrseq: wifi_pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 WIFI_EN */ ++ }; + }; + + &mmc1 { + vmmc-supply = <®_vcc3v3>; ++ mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-sun8i-r40-add-clk_out_a-fix-bananam2ultra.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-sun8i-r40-add-clk_out_a-fix-bananam2ultra.patch new file mode 100644 index 0000000000..564721fecd --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-sun8i-r40-add-clk_out_a-fix-bananam2ultra.patch @@ -0,0 +1,40 @@ +From d4670809cffff7aa7fdbeacc707a52cf792cbd5e Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Fri, 28 Jan 2022 15:01:30 +0300 +Subject: [PATCH 066/153] arm:dts: sun8i-r40 add clk_out_a fix bananam2ultra + +--- + arch/arm/boot/dts/sun8i-r40.dtsi | 17 +++++++++++++++++ + 1 file changed, 17 insertions(+) + +diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi +index 83562328b..74c20d840 100644 +--- a/arch/arm/boot/dts/sun8i-r40.dtsi ++++ b/arch/arm/boot/dts/sun8i-r40.dtsi +@@ -75,6 +75,23 @@ osc32k: osc32k { + clock-accuracy = <20000>; + clock-output-names = "ext-osc32k"; + }; ++ ++ osc24M_32k: clk@1 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clock-div = <732>; ++ clock-mult = <1>; ++ clocks = <&osc24M>; ++ clock-output-names = "osc24M_32k"; ++ }; ++ ++ clk_out_a: clk@01c201f0 { ++ #clock-cells = <0>; ++ compatible = "allwinner,sun7i-a20-out-clk"; ++ reg = <0x01c201f0 0x4>; ++ clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>; ++ clock-output-names = "clk_out_a"; ++ }; + }; + + cpus { +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-sun8i-r40-bananapi-m2-ultra-add-codec-analog.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-sun8i-r40-bananapi-m2-ultra-add-codec-analog.patch new file mode 100644 index 0000000000..0a50fb1824 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-sun8i-r40-bananapi-m2-ultra-add-codec-analog.patch @@ -0,0 +1,63 @@ +From 53633e58bb88c21117a0c18d009af3607a8dc340 Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Tue, 25 Jan 2022 21:18:21 +0300 +Subject: [PATCH 063/153] arm:dts: sun8i-r40 bananapi-m2-ultra add codec analog + +--- + .../boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 10 ++++++++++ + arch/arm/boot/dts/sun8i-r40.dtsi | 18 ++++++++++++++++++ + 2 files changed, 28 insertions(+) + +diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts +index 3508633a8..ebb2bd322 100644 +--- a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts ++++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts +@@ -118,6 +118,16 @@ &cpu0 { + cpu-supply = <®_dcdc2>; + }; + ++&codec { ++ allwinner,audio-routing = ++ "Headphone", "HP", ++ "Headphone", "HPCOM", ++ "MIC1", "Mic", ++ "Mic", "MBIAS"; ++ allwinner,codec-analog-controls = <&codec_analog>; ++ status = "okay"; ++}; ++ + &de { + status = "okay"; + }; +diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi +index f4c8e442a..83562328b 100644 +--- a/arch/arm/boot/dts/sun8i-r40.dtsi ++++ b/arch/arm/boot/dts/sun8i-r40.dtsi +@@ -837,6 +837,24 @@ i2s2: i2s@1c22800 { + dma-names = "rx", "tx"; + }; + ++ codec: codec@1c22c00 { ++ #sound-dai-cells = <1>; ++ compatible = "allwinner,sun8i-h3-codec"; ++ reg = <0x01c22c00 0x300>; ++ interrupts = ; ++ clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_CODEC>; ++ clock-names = "apb", "codec"; ++ resets = <&ccu RST_BUS_CODEC>; ++ dmas = <&dma 19>, <&dma 19>; ++ dma-names = "rx", "tx"; ++ status = "disabled"; ++ }; ++ ++ codec_analog: codec-analog@1c22f00 { ++ compatible = "allwinner,sun8i-a23-codec-analog"; ++ reg = <0x01c22f00 0x4>; ++ }; ++ + ths: thermal-sensor@1c24c00 { + compatible = "allwinner,sun8i-r40-ths"; + reg = <0x01c24c00 0x100>; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-sun8i-v3s-s3-pinecube-enable-sound-codec.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-sun8i-v3s-s3-pinecube-enable-sound-codec.patch new file mode 100644 index 0000000000..8b977333b4 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-sun8i-v3s-s3-pinecube-enable-sound-codec.patch @@ -0,0 +1,63 @@ +From 58a85447b472993ee155f2fc88c9914434c3ef42 Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Fri, 28 Jan 2022 12:58:57 +0300 +Subject: [PATCH 065/153] arm:dts: sun8i-v3s/s3-pinecube enable sound codec + +--- + arch/arm/boot/dts/sun8i-s3-pinecube.dts | 14 ++++++++++++++ + arch/arm/boot/dts/sun8i-v3s.dtsi | 14 ++++++++++++++ + 2 files changed, 28 insertions(+) + +diff --git a/arch/arm/boot/dts/sun8i-s3-pinecube.dts b/arch/arm/boot/dts/sun8i-s3-pinecube.dts +index 20966e954..773ad0503 100644 +--- a/arch/arm/boot/dts/sun8i-s3-pinecube.dts ++++ b/arch/arm/boot/dts/sun8i-s3-pinecube.dts +@@ -58,6 +58,20 @@ wifi_pwrseq: wifi_pwrseq { + }; + }; + ++ ++&i2s0 { ++ status = "okay"; ++}; ++ ++&codec { ++ allwinner,audio-routing = ++ "Speaker", "LINEOUT", ++ "MIC1", "Mic", ++ "Mic", "MBIAS"; ++ allwinner,pa-gpios = <&pio 6 6 GPIO_ACTIVE_HIGH>; /* PG6 */ ++ status = "okay"; ++}; ++ + &csi1 { + pinctrl-names = "default"; + pinctrl-0 = <&csi1_8bit_pins>; +diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi +index db194c606..ede2203c9 100644 +--- a/arch/arm/boot/dts/sun8i-v3s.dtsi ++++ b/arch/arm/boot/dts/sun8i-v3s.dtsi +@@ -471,6 +471,20 @@ codec_analog: codec-analog@1c23000 { + reg = <0x01c23000 0x4>; + }; + ++ ++ i2s0: i2s@1c22000 { ++ #sound-dai-cells = <0>; ++ compatible = "allwinner,sun8i-h3-i2s"; ++ reg = <0x01c22000 0x400>; ++ interrupts = ; ++ clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; ++ clock-names = "apb", "mod"; ++ dmas = <&dma 3>, <&dma 3>; ++ resets = <&ccu RST_BUS_I2S0>; /* TODO: Areset/sun8i-v3s-ccu says this isn't available on V3s */ ++ dma-names = "rx", "tx"; ++ status = "disabled"; ++ }; ++ + uart0: serial@1c28000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28000 0x400>; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-sun9i-a80-add-thermal-sensor.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-sun9i-a80-add-thermal-sensor.patch new file mode 100644 index 0000000000..b088c35211 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-sun9i-a80-add-thermal-sensor.patch @@ -0,0 +1,41 @@ +From 814789fb76bd21f25d0323dd08d253fa57de9367 Mon Sep 17 00:00:00 2001 +From: Philipp Rossak +Date: Sat, 27 Jan 2018 21:30:16 +0100 +Subject: [PATCH 052/153] arm:dts: sun9i-a80 add thermal sensor + +As we have gained the support for the thermal sensor in A80, +we can now add its device nodes to the device tree. + +The clocks and the resets are shared between the GPADC and the THS +sensor. + +Signed-off-by: Philipp Rossak +--- + arch/arm/boot/dts/sun9i-a80.dtsi | 11 +++++++++++ + 1 file changed, 11 insertions(+) + +diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi +index 7d3f3300f..14c68bdd1 100644 +--- a/arch/arm/boot/dts/sun9i-a80.dtsi ++++ b/arch/arm/boot/dts/sun9i-a80.dtsi +@@ -941,6 +941,17 @@ ccu: clock@6000000 { + #reset-cells = <1>; + }; + ++ ths: thermal-sensor@6004C00 { ++ compatible = "allwinner,sun9i-a80-ths"; ++ reg = <0x06004C00 0x100>; ++ interrupts = ; ++ clocks = <&ccu CLK_BUS_GPADC>, <&ccu CLK_GPADC>; ++ clock-names = "bus", "mod"; ++ resets = <&ccu RST_BUS_GPADC>; ++ #thermal-sensor-cells = <1>; ++ #io-channel-cells = <0>; ++ }; ++ + timer@6000c00 { + compatible = "allwinner,sun4i-a10-timer"; + reg = <0x06000c00 0xa0>; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-sun9i-a80-add-thermal-zone.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-sun9i-a80-add-thermal-zone.patch new file mode 100644 index 0000000000..60d49793f2 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-sun9i-a80-add-thermal-zone.patch @@ -0,0 +1,54 @@ +From 3683f0071790fbdef59a28d224fdf37a5f456bf5 Mon Sep 17 00:00:00 2001 +From: Philipp Rossak +Date: Sat, 27 Jan 2018 21:39:09 +0100 +Subject: [PATCH 053/153] arm:dts: sun9i-a80 add thermal zone + +This patch adds the thermal zones to the A80. + +Sensor 0 is located besides the big CPU, sensor 1 is located besides the +DRAM, sensor 2 is located besides the GPU and sensor 3 is located besides +the small CPU. + +Signed-off-by: Philipp Rossak +--- + arch/arm/boot/dts/sun9i-a80.dtsi | 26 ++++++++++++++++++++++++++ + 1 file changed, 26 insertions(+) + +diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi +index 14c68bdd1..7b7260f0c 100644 +--- a/arch/arm/boot/dts/sun9i-a80.dtsi ++++ b/arch/arm/boot/dts/sun9i-a80.dtsi +@@ -1261,4 +1261,30 @@ r_rsb: rsb@8003400 { + #size-cells = <0>; + }; + }; ++ ++ thermal-zones { ++ cpu0_thermal: cpu0-thermal { ++ polling-delay-passive = <1000>; ++ polling-delay = <5000>; ++ thermal-sensors = <&ths 0>; ++ }; ++ ++ dram_thermal: dram-thermal { ++ polling-delay-passive = <1000>; ++ polling-delay = <5000>; ++ thermal-sensors = <&ths 1>; ++ }; ++ ++ gpu_thermal: gpu-thermal { ++ polling-delay-passive = <1000>; ++ polling-delay = <5000>; ++ thermal-sensors = <&ths 2>; ++ }; ++ ++ cpu2_thermal: cpu2-thermal { ++ polling-delay-passive = <1000>; ++ polling-delay = <5000>; ++ thermal-sensors = <&ths 3>; ++ }; ++ }; + }; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-sunxi-h3-h5.dtsi-add-i2s0-i2s1-pins.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-sunxi-h3-h5.dtsi-add-i2s0-i2s1-pins.patch new file mode 100644 index 0000000000..9f35e0d9f4 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-sunxi-h3-h5.dtsi-add-i2s0-i2s1-pins.patch @@ -0,0 +1,33 @@ +From 9c674891827958c0c164dab3d91b296010e0ca0a Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Tue, 1 Feb 2022 19:43:08 +0300 +Subject: [PATCH 117/153] arm:dts:sunxi-h3-h5.dtsi add i2s0 i2s1 pins + +--- + arch/arm/boot/dts/sunxi-h3-h5.dtsi | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi +index 5e0b09df9..eb2cf602e 100644 +--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi ++++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi +@@ -464,6 +464,16 @@ i2c2_pins: i2c2-pins { + function = "i2c2"; + }; + ++ i2s0_pins: i2s0-pins { ++ pins = "PA18", "PA19", "PA20", "PA21"; ++ function = "i2s0"; ++ }; ++ ++ i2s1_pins: i2s1-pins { ++ pins = "PG10", "PG11", "PG12", "PG13"; ++ function = "i2s1"; ++ }; ++ + mmc0_pins: mmc0-pins { + pins = "PF0", "PF1", "PF2", "PF3", + "PF4", "PF5"; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-sunxi-h3-h5.dtsi-force-mmc0-bus-width.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-sunxi-h3-h5.dtsi-force-mmc0-bus-width.patch new file mode 100644 index 0000000000..09c9585a88 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm-dts-sunxi-h3-h5.dtsi-force-mmc0-bus-width.patch @@ -0,0 +1,24 @@ +From bddb274d7e7c642c2e98420e5f8486c313411fa3 Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Fri, 28 Jan 2022 16:12:37 +0300 +Subject: [PATCH 070/153] arm:dts: sunxi-h3-h5.dtsi force mmc0 bus-width + +--- + arch/arm/boot/dts/sunxi-h3-h5.dtsi | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi +index d8692f16f..5e0b09df9 100644 +--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi ++++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi +@@ -221,6 +221,7 @@ mmc0: mmc@1c0f000 { + resets = <&ccu RST_BUS_MMC0>; + reset-names = "ahb"; + interrupts = ; ++ bus-width = <0x4>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-Add-sun50i-h5-nanopi-k1-plus-device.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-Add-sun50i-h5-nanopi-k1-plus-device.patch new file mode 100644 index 0000000000..bd39366fff --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-Add-sun50i-h5-nanopi-k1-plus-device.patch @@ -0,0 +1,429 @@ +From 9329c25edf0b747ca66d035e7512491fdd0bc0e5 Mon Sep 17 00:00:00 2001 +From: wuweidong <625769020@qq.com> +Date: Mon, 27 Nov 2017 10:23:51 +0800 +Subject: [PATCH 088/153] arm64:dts: Add sun50i-h5-nanopi-k1-plus device + +--- + arch/arm64/boot/dts/allwinner/Makefile | 1 + + .../allwinner/sun50i-h5-nanopi-k1-plus.dts | 396 ++++++++++++++++++ + 2 files changed, 397 insertions(+) + create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-k1-plus.dts + +diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile +index cb5c98979..2fb04993e 100644 +--- a/arch/arm64/boot/dts/allwinner/Makefile ++++ b/arch/arm64/boot/dts/allwinner/Makefile +@@ -28,6 +28,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo2.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo-plus2.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-r1s-h5.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-pc2.dtb ++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-k1-plus.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-prime.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus2.dtb +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-k1-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-k1-plus.dts +new file mode 100644 +index 000000000..b7045a9ef +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-k1-plus.dts +@@ -0,0 +1,396 @@ ++/* ++ * Copyright (C) 2016 ARM Ltd. ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This file is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License, or (at your option) any later version. ++ * ++ * This file is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++/dts-v1/; ++#include "sun50i-h5.dtsi" ++ ++#include ++#include ++#include ++ ++/ { ++ model = "FriendlyElec NanoPi K1 Plus"; ++ compatible = "friendlyelec,nanopi-k1-plus", "allwinner,sun50i-h5"; ++ ++ reg_vcc3v3: vcc3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ }; ++ ++ aliases { ++ ethernet0 = &emac; ++ serial0 = &uart0; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ connector { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi_con_in: endpoint { ++ remote-endpoint = <&hdmi_out_con>; ++ }; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ status { ++ label = "nanopi:green:status"; ++ gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "heartbeat"; ++ }; ++ pwr { ++ label = "nanopi:red:pwr"; ++ gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; ++ default-state = "on"; ++ }; ++ ++ }; ++ ++ r-gpio-keys { ++ compatible = "gpio-keys"; ++ ++ sw4 { ++ label = "sw4"; ++ linux,code = ; ++ gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ ++ reg_gmac_3v3: gmac-3v3 { ++ compatible = "regulator-fixed"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&gmac_power_pin_nanopi>; ++ regulator-name = "gmac-3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ startup-delay-us = <100000>; ++ enable-active-high; ++ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ reg_usb0_vbus: usb0-vbus { ++ compatible = "regulator-fixed"; ++ regulator-name = "usb0-vbus"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ enable-active-high; ++ gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */ ++ status = "okay"; ++ }; ++ ++ wifi_pwrseq: wifi_pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&wifi_en_npi>; ++ reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ ++ post-power-on-delay-ms = <200>; ++ }; ++ ++ rfkill_bt { ++ compatible = "rfkill-gpio"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&bt_pwr_pin>; ++ reset-gpios = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */ ++ clocks = <&osc32k>; ++ clock-frequency = <32768>; ++ rfkill-name = "sunxi-bt"; ++ rfkill-type = "bluetooth"; ++ }; ++ ++ pcm5102a: pcm5102a-codec { ++ #sound-dai-cells = <0>; ++ compatible = "ti,pcm5102a"; ++ status = "disabled"; ++ }; ++}; ++ ++&cpu0 { ++ cpu-supply = <®_vdd_cpux>; ++}; ++ ++&codec { ++ allwinner,audio-routing = ++ "Line Out", "LINEOUT", ++ "MIC1", "Mic", ++ "Mic", "MBIAS"; ++ status = "okay"; ++}; ++ ++&de { ++ status = "okay"; ++}; ++ ++&ehci0 { ++ status = "okay"; ++}; ++ ++&ehci1 { ++ status = "okay"; ++}; ++ ++&ehci2 { ++ status = "okay"; ++}; ++ ++&ehci3 { ++ status = "okay"; ++}; ++ ++&external_mdio { ++ ext_rgmii_phy: ethernet-phy@1 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <0>; ++ }; ++}; ++ ++&emac { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&emac_rgmii_pins>; ++ phy-supply = <®_gmac_3v3>; ++ phy-handle = <&ext_rgmii_phy>; ++ phy-mode = "rgmii-id"; ++ local-mac-address = [ 00 00 00 00 00 00 ]; ++ allwinner,leds-active-low; ++ status = "okay"; ++}; ++ ++&ir { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&r_ir_rx_pin>; ++ status = "okay"; ++}; ++ ++&mmc0 { ++ vmmc-supply = <®_vcc3v3>; ++ bus-width = <4>; ++ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ ++ status = "okay"; ++}; ++ ++&mmc1 { ++ vmmc-supply = <®_vcc3v3>; ++ vqmmc-supply = <®_vcc3v3>; ++ mmc-pwrseq = <&wifi_pwrseq>; ++ bus-width = <4>; ++ non-removable; ++ status = "okay"; ++ brcmf: bcrmf@1 { ++ reg = <1>; ++ compatible = "brcm,bcm4329-fmac"; ++ }; ++}; ++ ++&mmc2 { ++ vmmc-supply = <®_vcc3v3>; ++ bus-width = <8>; ++ non-removable; ++ cap-mmc-hw-reset; ++ boot_device = <0>; ++ status = "okay"; ++}; ++ ++&mmc2_8bit_pins { ++ /* Increase drive strength for DDR modes */ ++ drive-strength = <40>; ++ /* eMMC is missing pull-ups */ ++ bias-pull-up; ++}; ++ ++&hdmi { ++ status = "okay"; ++}; ++ ++&hdmi_out { ++ hdmi_out_con: endpoint { ++ remote-endpoint = <&hdmi_con_in>; ++ }; ++}; ++ ++ ++&pio { ++ leds_npi: led_pins@0 { ++ pins = "PA10"; ++ function = "gpio_out"; ++ }; ++ gmac_power_pin_nanopi: gmac_power_pin@0 { ++ pins = "PD6"; ++ function = "gpio_out"; ++ }; ++ bt_pwr_pin: bt_pwr_pin@0 { ++ pins = "PG13"; ++ function = "gpio_out"; ++ }; ++ spi0_cs_pins: spi0_cs_pins { ++ pins = "PC3", "PA6"; ++ function = "gpio_out"; ++ }; ++}; ++&r_pio { ++ leds_r_npi: led_pins@0 { ++ pins = "PL10"; ++ function = "gpio_out"; ++ }; ++ vdd_cpux_r_npi: regulator_pins@0 { ++ allwinner,pins = "PL6"; ++ allwinner,function = "gpio_out"; ++ allwinner,drive = ; ++ allwinner,pull = ; ++ }; ++ wifi_en_npi: wifi_en_pin { ++ pins = "PL7"; ++ function = "gpio_out"; ++ }; ++}; ++&ohci0 { ++ status = "okay"; ++}; ++ ++&ohci1 { ++ status = "okay"; ++}; ++ ++&ohci2 { ++ status = "okay"; ++}; ++ ++&ohci3 { ++ status = "okay"; ++}; ++ ++ ++&r_i2c { ++ status = "okay"; ++ reg_vdd_cpux: regulator@65 { ++ compatible = "silergy,sy8106a"; ++ reg = <0x65>; ++ regulator-name = "vdd-cpux"; ++ silergy,fixed-microvolt = <1200000>; ++ /* ++ * The datasheet uses 1.1V as the minimum value of VDD-CPUX, ++ * however both the Armbian DVFS table and the official one ++ * have operating points with voltage under 1.1V, and both ++ * DVFS table are known to work properly at the lowest ++ * operating point. ++ * ++ * Use 1.0V as the minimum voltage instead. ++ */ ++ regulator-min-microvolt = <1000000>; ++ regulator-max-microvolt = <1400000>; ++ regulator-ramp-delay = <200>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++}; ++ ++&spi0 { ++ status = "okay"; ++ spi-flash@0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "jedec,spi-nor"; ++ reg = <0>; /* Chip select 0 */ ++ spi-max-frequency = <10000000>; ++ status = "okay"; ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ partition@0 { ++ label = "uboot"; ++ reg = <0x0 0x100000>; ++ }; ++ partition@100000 { ++ label = "env"; ++ reg = <0x100000 0x100000>; ++ }; ++ }; ++ }; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pa_pins>; ++ status = "okay"; ++}; ++ ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1_pins>; ++ status = "disabled"; ++}; ++ ++&uart2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart2_pins>; ++ status = "disabled"; ++}; ++ ++&uart3 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart3_pins>, <&uart3_rts_cts_pins>; ++ status = "okay"; ++}; ++&usb_otg { ++ dr_mode = "otg"; ++ status = "okay"; ++}; ++ ++&usbphy { ++ /* USB Type-A ports' VBUS is always on */ ++ usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ ++ usb0_vbus-supply = <®_usb0_vbus>; ++ status = "okay"; ++}; ++ ++&i2s0 { ++ sound-dai = <&pcm5102a>; ++ status = "disabled"; ++}; +\ No newline at end of file +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-Add-sun50i-h5-nanopi-m1-plus2-device.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-Add-sun50i-h5-nanopi-m1-plus2-device.patch new file mode 100644 index 0000000000..3d39a9ff5a --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-Add-sun50i-h5-nanopi-m1-plus2-device.patch @@ -0,0 +1,272 @@ +From cd587033bd92dcb45b04f99dea2bf502a1ebd19e Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Mon, 24 Jan 2022 18:54:36 +0300 +Subject: [PATCH 091/153] arm64:dts: Add sun50i-h5-nanopi-m1-plus2 device + +--- + arch/arm64/boot/dts/allwinner/Makefile | 1 + + .../allwinner/sun50i-h5-nanopi-m1-plus2.dts | 240 ++++++++++++++++++ + 2 files changed, 241 insertions(+) + create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-m1-plus2.dts + +diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile +index 47e87b4f9..2fd4e07cb 100644 +--- a/arch/arm64/boot/dts/allwinner/Makefile ++++ b/arch/arm64/boot/dts/allwinner/Makefile +@@ -31,6 +31,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo-core2.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-r1s-h5.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-pc2.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-k1-plus.dtb ++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-m1-plus2.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-prime.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus2.dtb +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-m1-plus2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-m1-plus2.dts +new file mode 100644 +index 000000000..d051382cc +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-m1-plus2.dts +@@ -0,0 +1,240 @@ ++/* ++ * Copyright (C) 2017 Icenowy Zheng ++ * Copyright (C) 2017 Armbian ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This file is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License, or (at your option) any later version. ++ * ++ * This file is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++/dts-v1/; ++#include "sun50i-h5.dtsi" ++ ++#include ++ ++/ { ++ model = "FriendlyARM Nanopi M1 Plus 2"; ++ compatible = "friendlyarm,nanopi-neo2", "allwinner,sun50i-h5"; ++ ++ aliases { ++ ethernet0 = &emac; ++ serial0 = &uart0; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ pwr { ++ label = "nanopi:green:pwr"; ++ gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; ++ default-state = "on"; ++ }; ++ ++ status { ++ label = "nanopi:blue:status"; ++ gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; ++ }; ++ }; ++ ++ reg_gmac_3v3: gmac-3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "gmac-3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ startup-delay-us = <100000>; ++ enable-active-high; ++ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ reg_vcc3v3: vcc3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ }; ++ ++ reg_usb0_vbus: usb0-vbus { ++ compatible = "regulator-fixed"; ++ regulator-name = "usb0-vbus"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ enable-active-high; ++ gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */ ++ status = "okay"; ++ }; ++ ++ wifi_pwrseq: wifi_pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ ++ post-power-on-delay-ms = <50>; ++ }; ++ ++}; ++ ++&ehci0 { ++ status = "okay"; ++}; ++ ++&ehci1 { ++ status = "okay"; ++}; ++ ++&ehci2 { ++ status = "okay"; ++}; ++ ++&ehci3 { ++ status = "okay"; ++}; ++ ++&emac { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&emac_rgmii_pins>; ++ phy-supply = <®_gmac_3v3>; ++ phy-handle = <&ext_rgmii_phy>; ++ phy-mode = "rgmii"; ++ status = "okay"; ++}; ++ ++&mdio { ++ ext_rgmii_phy: ethernet-phy@7 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <7>; ++ }; ++}; ++ ++&mmc0 { ++ vmmc-supply = <®_vcc3v3>; ++ bus-width = <4>; ++ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ ++ status = "okay"; ++}; ++ ++&mmc1 { ++ vmmc-supply = <®_vcc3v3>; ++ vqmmc-supply = <®_vcc3v3>; ++ mmc-pwrseq = <&wifi_pwrseq>; ++ bus-width = <4>; ++ non-removable; ++ status = "okay"; ++ ++ brcmf: brcmf@1 { ++ reg = <1>; ++ compatible = "brcm,bcm4329-fmac"; ++ interrupt-parent = <&pio>; ++ interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 */ ++ interrupt-names = "host-wake"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&wifi_wake>; ++ }; ++}; ++ ++&mmc2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc2_8bit_pins>; ++ vmmc-supply = <®_vcc3v3>; ++ bus-width = <8>; ++ non-removable; ++ cap-mmc-hw-reset; ++ status = "okay"; ++}; ++ ++&de { ++ status = "okay"; ++}; ++ ++&ohci0 { ++ status = "okay"; ++}; ++ ++&ohci1 { ++ status = "okay"; ++}; ++ ++&ohci2 { ++ status = "okay"; ++}; ++ ++&ohci3 { ++ status = "okay"; ++}; ++ ++&hdmi { ++ status = "okay"; ++}; ++ ++&mixer0 { ++ status = "okay"; ++}; ++ ++&r_pio { ++ wifi_wake: wifi_wake@0 { ++ pins = "PL7"; ++ function = "irq"; ++ bias-pull-up; ++ }; ++}; ++ ++&tcon0 { ++ status = "okay"; ++}; ++ ++&r_i2c { ++ status = "okay"; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pa_pins>; ++ status = "okay"; ++}; ++ ++&usb_otg { ++ dr_mode = "peripheral"; ++ status = "okay"; ++}; ++ ++&usbphy { ++ /* USB Type-A port's VBUS is always on */ ++ usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ ++ usb0_vbus-supply = <®_usb0_vbus>; ++ status = "okay"; ++}; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-Add-sun50i-h5-nanopi-neo-core2-device.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-Add-sun50i-h5-nanopi-neo-core2-device.patch new file mode 100644 index 0000000000..ea70cdbc63 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-Add-sun50i-h5-nanopi-neo-core2-device.patch @@ -0,0 +1,242 @@ +From 9d5d85b7c307587b90748650ca811838e0f6c7ab Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Mon, 24 Jan 2022 18:43:42 +0300 +Subject: [PATCH 089/153] arm64:dts: Add sun50i-h5-nanopi-neo-core2 device + +--- + arch/arm64/boot/dts/allwinner/Makefile | 1 + + .../allwinner/sun50i-h5-nanopi-neo-core2.dts | 210 ++++++++++++++++++ + 2 files changed, 211 insertions(+) + create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-core2.dts + +diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile +index 2fb04993e..f3c793236 100644 +--- a/arch/arm64/boot/dts/allwinner/Makefile ++++ b/arch/arm64/boot/dts/allwinner/Makefile +@@ -26,6 +26,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-libretech-all-h3-it.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-libretech-all-h5-cc.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo2.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo-plus2.dtb ++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo-core2.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-r1s-h5.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-pc2.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-k1-plus.dtb +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-core2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-core2.dts +new file mode 100644 +index 000000000..57283cc16 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-core2.dts +@@ -0,0 +1,210 @@ ++/* ++ * Copyright (C) 2017 Antony Antony ++ * Copyright (C) 2016 ARM Ltd. ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This file is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License, or (at your option) any later version. ++ * ++ * This file is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++/dts-v1/; ++#include "sun50i-h5.dtsi" ++ ++#include ++#include ++#include ++ ++/ { ++ model = "FriendlyARM NanoPi NEO Core2"; ++ compatible = "friendlyarm,nanopi-neo-core2", "allwinner,sun50i-h5"; ++ ++ aliases { ++ ethernet0 = &emac; ++ serial0 = &uart0; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ pwr { ++ label = "nanopi:red:pwr"; ++ gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ ++ linux,default-trigger = "default-on"; ++ }; ++ ++ status { ++ label = "nanopi:green:status"; ++ gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; /* PA10 */ ++ linux,default-trigger = "heartbeat"; ++ }; ++ }; ++ ++ reg_gmac_3v3: gmac-3v3 { ++ compatible = "regulator-fixed"; ++ pinctrl-names = "default"; ++ regulator-name = "gmac-3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ startup-delay-us = <100000>; ++ enable-active-high; ++ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ reg_vcc3v3: vcc3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ }; ++ ++ wifi_pwrseq: wifi_pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ pinctrl-names = "default"; ++ reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ ++ post-power-on-delay-ms = <200>; ++ }; ++}; ++ ++&cpu0 { ++ cpu-supply = <&vdd_cpux>; ++}; ++ ++&codec { ++ allwinner,audio-routing = ++ "Line Out", "LINEOUT", ++ "MIC1", "Mic", ++ "Mic", "MBIAS"; ++ status = "okay"; ++}; ++ ++&ehci0 { ++ status = "okay"; ++}; ++ ++&ehci3 { ++ status = "okay"; ++}; ++ ++&emac { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&emac_rgmii_pins>; ++ phy-supply = <®_gmac_3v3>; ++ phy-handle = <&ext_rgmii_phy>; ++ phy-mode = "rgmii-id"; ++ status = "okay"; ++}; ++ ++&external_mdio { ++ ext_rgmii_phy: ethernet-phy@7 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <7>; ++ }; ++}; ++ ++&mmc0 { ++ vmmc-supply = <®_vcc3v3>; ++ bus-width = <4>; ++ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ ++ status = "okay"; ++}; ++ ++&mmc1 { ++ vmmc-supply = <®_vcc3v3>; ++ vqmmc-supply = <®_vcc3v3>; ++ mmc-pwrseq = <&wifi_pwrseq>; ++ bus-width = <4>; ++ non-removable; ++ status = "okay"; ++ ++ brcmf: wifi@1 { ++ reg = <1>; ++ compatible = "brcm,bcm4329-fmac"; ++ }; ++}; ++ ++&mmc2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc2_8bit_pins>; ++ vmmc-supply = <®_vcc3v3>; ++ bus-width = <8>; ++ non-removable; ++ cap-mmc-hw-reset; ++ status = "okay"; ++}; ++ ++&ohci0 { ++ status = "okay"; ++}; ++ ++&ohci3 { ++ status = "okay"; ++}; ++ ++&r_i2c { ++ status = "okay"; ++ ++ vdd_cpux: regulator@65 { ++ compatible = "silergy,sy8106a"; ++ reg = <0x65>; ++ silergy,fixed-microvolt = <1000000>; ++ regulator-min-microvolt = <1000000>; ++ regulator-max-microvolt = <1400000>; ++ regulator-ramp-delay = <200>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pa_pins>; ++ status = "okay"; ++}; ++ ++&usb_otg { ++ dr_mode = "otg"; ++ status = "okay"; ++}; ++ ++&usbphy { ++ /* USB Type-A ports' VBUS is always on */ ++ status = "okay"; ++}; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-Add-sun50i-h5-nanopi-neo2-v1.1-device.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-Add-sun50i-h5-nanopi-neo2-v1.1-device.patch new file mode 100644 index 0000000000..f1920feaba --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-Add-sun50i-h5-nanopi-neo2-v1.1-device.patch @@ -0,0 +1,212 @@ +From 71a8be5024f0474195d647872d7f7db1c0417336 Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Mon, 24 Jan 2022 18:49:55 +0300 +Subject: [PATCH 090/153] arm64:dts: Add sun50i-h5-nanopi-neo2-v1.1 device + +--- + arch/arm64/boot/dts/allwinner/Makefile | 1 + + .../allwinner/sun50i-h5-nanopi-neo2-v1.1.dts | 180 ++++++++++++++++++ + 2 files changed, 181 insertions(+) + create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2-v1.1.dts + +diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile +index f3c793236..47e87b4f9 100644 +--- a/arch/arm64/boot/dts/allwinner/Makefile ++++ b/arch/arm64/boot/dts/allwinner/Makefile +@@ -25,6 +25,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-libretech-all-h3-cc.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-libretech-all-h3-it.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-libretech-all-h5-cc.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo2.dtb ++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo2-v1.1.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo-plus2.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo-core2.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-r1s-h5.dtb +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2-v1.1.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2-v1.1.dts +new file mode 100644 +index 000000000..06ffbbd29 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2-v1.1.dts +@@ -0,0 +1,180 @@ ++/* ++ * Copyright (C) 2017 Icenowy Zheng ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This file is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License, or (at your option) any later version. ++ * ++ * This file is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++/dts-v1/; ++#include "sun50i-h5.dtsi" ++ ++#include ++ ++/ { ++ model = "FriendlyARM NanoPi NEO 2"; ++ compatible = "friendlyarm,nanopi-neo2", "allwinner,sun50i-h5"; ++ ++ aliases { ++ ethernet0 = &emac; ++ serial0 = &uart0; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ pwr { ++ label = "nanopi:red:pwr"; ++ gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ ++ linux,default-trigger = "default-on"; ++ }; ++ ++ status { ++ label = "nanopi:green:status"; ++ gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; /* PA10 */ ++ linux,default-trigger = "heartbeat"; ++ }; ++ }; ++ ++ reg_gmac_3v3: gmac-3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "gmac-3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ startup-delay-us = <100000>; ++ enable-active-high; ++ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ reg_vcc3v3: vcc3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ }; ++ ++ vdd_cpux: gpio-regulator { ++ compatible = "regulator-gpio"; ++ pinctrl-names = "default"; ++ regulator-name = "vdd-cpux"; ++ regulator-type = "voltage"; ++ regulator-boot-on; ++ regulator-always-on; ++ regulator-min-microvolt = <1100000>; ++ regulator-max-microvolt = <1300000>; ++ regulator-ramp-delay = <50>; /* 4ms */ ++ gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ ++ gpios-states = <0x1>; ++ states = <1100000 0x0 ++ 1300000 0x1>; ++ }; ++ ++ reg_usb0_vbus: usb0-vbus { ++ compatible = "regulator-fixed"; ++ regulator-name = "usb0-vbus"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ enable-active-high; ++ gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */ ++ status = "okay"; ++ }; ++}; ++ ++&cpu0 { ++ cpu-supply = <&vdd_cpux>; ++}; ++ ++&ehci0 { ++ status = "okay"; ++}; ++ ++&ehci3 { ++ status = "okay"; ++}; ++ ++&emac { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&emac_rgmii_pins>; ++ phy-supply = <®_gmac_3v3>; ++ phy-handle = <&ext_rgmii_phy>; ++ phy-mode = "rgmii-id"; ++ status = "okay"; ++}; ++ ++&external_mdio { ++ ext_rgmii_phy: ethernet-phy@7 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <7>; ++ }; ++}; ++ ++&mmc0 { ++ vmmc-supply = <®_vcc3v3>; ++ bus-width = <4>; ++ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ ++ status = "okay"; ++}; ++ ++&ohci0 { ++ status = "okay"; ++}; ++ ++&ohci3 { ++ status = "okay"; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pa_pins>; ++ status = "okay"; ++}; ++ ++&usb_otg { ++ dr_mode = "otg"; ++ status = "okay"; ++}; ++ ++&usbphy { ++ /* USB Type-A port's VBUS is always on */ ++ usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ ++ usb0_vbus-supply = <®_usb0_vbus>; ++ status = "okay"; ++}; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-FIXME-a64-olinuxino-add-regulator-audio-mmc.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-FIXME-a64-olinuxino-add-regulator-audio-mmc.patch new file mode 100644 index 0000000000..8849215681 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-FIXME-a64-olinuxino-add-regulator-audio-mmc.patch @@ -0,0 +1,100 @@ +From 18a4dd7285608b834318f4df33401c6763d8104b Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Mon, 24 Jan 2022 14:24:40 +0300 +Subject: [PATCH 087/153] arm64:dts: FIXME: a64-olinuxino add regulator audio + mmc + +Duplicate nodes appeared as a result of patching and this needs +to be fixed and tested on the board +--- + .../dts/allwinner/sun50i-a64-olinuxino.dts | 46 +++++++++++++++++++ + 1 file changed, 46 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts +index 21d0bdc28..636b64a1d 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts +@@ -52,6 +52,13 @@ reg_usb1_vbus: usb1-vbus { + status = "okay"; + }; + ++ reg_vcc3v3: vcc3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ }; ++ + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ +@@ -99,6 +106,10 @@ &ehci1 { + status = "okay"; + }; + ++&mixer0 { ++ status = "okay"; ++}; ++ + &emac { + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; +@@ -159,6 +170,16 @@ rtl8723bs: wifi@1 { + }; + }; + ++&mmc2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc2_pins>; ++ vmmc-supply = <®_vcc3v3>; ++ bus-width = <8>; ++ non-removable; ++ cap-mmc-hw-reset; ++ status = "okay"; ++}; ++ + &ohci0 { + status = "okay"; + }; +@@ -184,6 +205,7 @@ &r_pio { + */ + }; + ++/* FIXME: Duplicate node */ + &pio { + vcc-pa-supply = <®_dcdc1>; + vcc-pb-supply = <®_dcdc1>; +@@ -365,6 +387,30 @@ &sound_hdmi { + status = "okay"; + }; + ++/* FIXME: Duplicate node ++ * &sound { ++ * status = "okay"; ++ * simple-audio-card,widgets = "Microphone", "Internal Microphone Left", ++ * "Microphone", "Internal Microphone Right", ++ * "Headphone", "Headphone Jack"; ++ * simple-audio-card,aux-devs = <&codec_analog>; ++ * simple-audio-card,routing = ++ * "Left DAC", "AIF1 Slot 0 Left", ++ * "Right DAC", "AIF1 Slot 0 Right", ++ * "INL", "LINEOUT", ++ * "INR", "LINEOUT", ++ * "Headphone Jack", "HP", ++ * "AIF1 Slot 0 Left ADC", "Left ADC", ++ * "AIF1 Slot 0 Right ADC", "Right ADC", ++ * "Left ADC", "ADC", ++ * "Right ADC", "ADC", ++ * "Internal Microphone Left", "MBIAS", ++ * "MIC1", "Internal Microphone Left", ++ * "Internal Microphone Right", "HBIAS", ++ * "MIC2", "Internal Microphone Right"; ++ * }; ++ */ ++ + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-allwiner-sun50i-h616.dtsi-add-usb-ehci-ohc.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-allwiner-sun50i-h616.dtsi-add-usb-ehci-ohc.patch new file mode 100644 index 0000000000..f2e02d7f60 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-allwiner-sun50i-h616.dtsi-add-usb-ehci-ohc.patch @@ -0,0 +1,65 @@ +From f27727fa124b3e428601614ee95ebe0dc7162f33 Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Sun, 13 Nov 2022 23:15:38 +0300 +Subject: [PATCH 075/153] arm64: dts: allwiner: sun50i-h616.dtsi: add + usb,ehci,ohci + +--- + arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 11 +++++++++-- + 1 file changed, 9 insertions(+), 2 deletions(-) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +index 74aed0d23..44f8ae11c 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +@@ -58,12 +58,12 @@ reserved-memory { + ranges; + + /* +- * 256 KiB reserved for Trusted Firmware-A (BL31). ++ * 512 KiB reserved for Trusted Firmware-A (BL31). + * This is added by BL31 itself, but some bootloaders fail + * to propagate this into the DTB handed to kernels. + */ + secmon@40000000 { +- reg = <0x0 0x40000000 0x0 0x40000>; ++ reg = <0x0 0x40000000 0x0 0x80000>; + no-map; + }; + }; +@@ -466,6 +466,8 @@ spi0: spi@5010000 { + clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; + clock-names = "ahb", "mod"; + resets = <&ccu RST_BUS_SPI0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi0_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; +@@ -479,6 +481,8 @@ spi1: spi@5011000 { + clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; + clock-names = "ahb", "mod"; + resets = <&ccu RST_BUS_SPI1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi1_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; +@@ -688,11 +692,14 @@ r_ccu: clock@7010000 { + r_pio: pinctrl@7022000 { + compatible = "allwinner,sun50i-h616-r-pinctrl"; + reg = <0x07022000 0x400>; ++ interrupts = ; + clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, + <&rtc CLK_OSC32K>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + #gpio-cells = <3>; ++ interrupt-controller; ++ #interrupt-cells = <3>; + + /omit-if-no-ref/ + r_i2c_pins: r-i2c-pins { +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-allwinner-h616-Add-device-node-for-SID.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-allwinner-h616-Add-device-node-for-SID.patch new file mode 100644 index 0000000000..ba9a1dd989 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-allwinner-h616-Add-device-node-for-SID.patch @@ -0,0 +1,41 @@ +From ce47f52be68065a1fa8e475775c94db5be1a251e Mon Sep 17 00:00:00 2001 +From: Kali Prasad +Date: Sun, 19 Sep 2021 13:30:08 +0530 +Subject: [PATCH 082/153] arm64: dts: allwinner: h616: Add device node for SID + +The device tree binding for H616's SID controller. + +Signed-off-by: Kali Prasad +--- + arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 15 +++++++++++++++ + 1 file changed, 15 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +index 45359b0d3..7ad1982fb 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +@@ -171,6 +171,21 @@ ccu: clock@3001000 { + #reset-cells = <1>; + }; + ++ sid: efuse@3006000 { ++ compatible = "allwinner,sun50i-h616-sid"; ++ reg = <0x03006000 0x1000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ cpu_speed_grade: cpu-speed-grade@00 { ++ reg = <0x00 0x02>; ++ }; ++ ++ ths_calibration: thermal-sensor-calibration@14 { ++ reg = <0x14 0x8>; ++ }; ++ }; ++ + watchdog: watchdog@30090a0 { + compatible = "allwinner,sun50i-h616-wdt", + "allwinner,sun6i-a31-wdt"; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-allwinner-h616-Add-efuse_xlate-cpu-frequency-scaling-v1_6_2.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-allwinner-h616-Add-efuse_xlate-cpu-frequency-scaling-v1_6_2.patch new file mode 100644 index 0000000000..f19cfdc0b2 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-allwinner-h616-Add-efuse_xlate-cpu-frequency-scaling-v1_6_2.patch @@ -0,0 +1,338 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: AGM1968 +Date: Tue, 23 May 2023 16:43:00 +0000 +Subject: arm64-dts-allwinner-h616-Add-efuse_xlate-cpu-frequency-scaling-v1_6_2 + arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp.dtsi + arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts + drivers/cpufreq/cpufreq-dt-platdev.c drivers/cpufreq/sun50i-cpufreq-nvmem.c + +Signed-off-by: AGM1968 +--- + arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp.dtsi | 75 ++++++++ + arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts | 6 + + drivers/cpufreq/cpufreq-dt-platdev.c | 1 + + drivers/cpufreq/sun50i-cpufreq-nvmem.c | 91 +++++++--- + 4 files changed, 149 insertions(+), 24 deletions(-) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp.dtsi +new file mode 100644 +index 000000000000..36f2950367c6 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp.dtsi +@@ -0,0 +1,75 @@ ++//SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++//Testing Version 1 from: AGM1968 ++//Noted: PLL_CPUX = 24 MHz*N/P (WIP) ++ ++/ { ++ cpu_opp_table: opp-table-cpu { ++ compatible = "allwinner,sun50i-h616-operating-points"; ++ nvmem-cells = <&cpu_speed_grade>; ++ opp-shared; ++ ++ opp-480000000 { ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ opp-hz = /bits/ 64 <480000000>; ++ opp-microvolt-speed0 = <820000 820000 1100000>; ++ opp-microvolt-speed1 = <880000 880000 1100000>; ++ opp-microvolt-speed2 = <880000 880000 1100000>; ++ }; ++ ++ opp-600000000 { ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ opp-hz = /bits/ 64 <600000000>; ++ opp-microvolt-speed0 = <820000 820000 1100000>; ++ opp-microvolt-speed1 = <880000 880000 1100000>; ++ opp-microvolt-speed2 = <880000 880000 1100000>; ++ }; ++ ++ opp-792000000 { ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ opp-hz = /bits/ 64 <792000000>; ++ opp-microvolt-speed0 = <860000 860000 1100000>; ++ opp-microvolt-speed1 = <940000 940000 1100000>; ++ opp-microvolt-speed2 = <940000 940000 1100000>; ++ }; ++ ++ opp-1008000000 { ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ opp-hz = /bits/ 64 <1008000000>; ++ opp-microvolt-speed0 = <900000 900000 1100000>; ++ opp-microvolt-speed1 = <1020000 1020000 1100000>; ++ opp-microvolt-speed2 = <1020000 1020000 1100000>; ++ }; ++ ++ opp-1200000000 { ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ opp-hz = /bits/ 64 <1200000000>; ++ opp-microvolt-speed0 = <960000 960000 1100000>; ++ opp-microvolt-speed1 = <1100000 1100000 1100000>; ++ opp-microvolt-speed2 = <1100000 1100000 1100000>; ++ }; ++ ++ opp-1512000000 { ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ opp-hz = /bits/ 64 <1512000000>; ++ opp-microvolt-speed0 = <1100000 1100000 1100000>; ++ opp-microvolt-speed1 = <1100000 1100000 1100000>; ++ opp-microvolt-speed2 = <1100000 1100000 1100000>; ++ }; ++ }; ++}; ++ ++&cpu0 { ++ operating-points-v2 = <&cpu_opp_table>; ++}; ++ ++&cpu1 { ++ operating-points-v2 = <&cpu_opp_table>; ++}; ++ ++&cpu2 { ++ operating-points-v2 = <&cpu_opp_table>; ++}; ++ ++&cpu3 { ++ operating-points-v2 = <&cpu_opp_table>; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts +index 0a24b8571a50..defb8b71f872 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts +@@ -4,10 +4,11 @@ + */ + + /dts-v1/; + + #include "sun50i-h616.dtsi" ++#include "sun50i-h616-cpu-opp.dtsi" + + #include + #include + #include + +@@ -216,10 +217,15 @@ &pio { + vcc-pg-supply = <®_bldo1>; + vcc-ph-supply = <®_aldo1>; + vcc-pi-supply = <®_aldo1>; + }; + ++&cpu0 { ++ cpu-supply = <®_dcdca>; ++ status = "okay"; ++}; ++ + &spi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>, <&spi0_cs0_pin>; + +diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c +index e85703651098..e4fa483c8a84 100644 +--- a/drivers/cpufreq/cpufreq-dt-platdev.c ++++ b/drivers/cpufreq/cpufreq-dt-platdev.c +@@ -100,10 +100,11 @@ static const struct of_device_id allowlist[] __initconst = { + * Machines for which the cpufreq device is *not* created, mostly used for + * platforms using "operating-points-v2" property. + */ + static const struct of_device_id blocklist[] __initconst = { + { .compatible = "allwinner,sun50i-h6", }, ++ { .compatible = "allwinner,sun50i-h616", }, + + { .compatible = "apple,arm-platform", }, + + { .compatible = "arm,vexpress", }, + +diff --git a/drivers/cpufreq/sun50i-cpufreq-nvmem.c b/drivers/cpufreq/sun50i-cpufreq-nvmem.c +index 1acec58c33c3..f8d5c30e56d0 100644 +--- a/drivers/cpufreq/sun50i-cpufreq-nvmem.c ++++ b/drivers/cpufreq/sun50i-cpufreq-nvmem.c +@@ -4,10 +4,13 @@ + * + * The sun50i-cpufreq-nvmem driver reads the efuse value from the SoC to + * provide the OPP framework with required information. + * + * Copyright (C) 2019 Yangtao Li ++ * ++ * ADD efuse_xlate to extract SoC version so that h6 and h616 can coexist. ++ * Version 1 AGM1968 + */ + + #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + + #include +@@ -17,41 +20,77 @@ + #include + #include + + #define MAX_NAME_LEN 7 + +-#define NVMEM_MASK 0x7 +-#define NVMEM_SHIFT 5 ++#define SUN50I_H616_NVMEM_MASK 0x22 ++#define SUN50I_H616_NVMEM_SHIFT 5 ++#define SUN50I_H6_NVMEM_MASK 0x7 ++#define SUN50I_H6_NVMEM_SHIFT 5 ++ ++struct sunxi_cpufreq_soc_data { ++ u32 (*efuse_xlate) (void *efuse); ++}; + + static struct platform_device *cpufreq_dt_pdev, *sun50i_cpufreq_pdev; + ++static u32 sun50i_h616_efuse_xlate(void *efuse) ++{ ++ u32 efuse_value = (*(u32 *)efuse >> SUN50I_H616_NVMEM_SHIFT) & ++ SUN50I_H616_NVMEM_MASK; ++ ++ /* Tested as V1 h616 soc. Expected efuse values are 1 - 3, ++ slowest to fastest */ ++ if (efuse_value >=1 && efuse_value <= 3) ++ return efuse_value - 1; ++ else ++ return 0; ++}; ++ ++static u32 sun50i_h6_efuse_xlate(void *efuse) ++{ ++ u32 efuse_value = (*(u32 *)efuse >> SUN50I_H6_NVMEM_SHIFT) & ++ SUN50I_H6_NVMEM_MASK; ++ ++ /* ++ * We treat unexpected efuse values as if the SoC was from ++ * the slowest bin. Expected efuse values are 1 - 3, slowest ++ * to fastest. ++ */ ++ if (efuse_value >= 1 && efuse_value <= 3) ++ return efuse_value - 1; ++ else ++ return 0; ++}; ++ ++ + /** + * sun50i_cpufreq_get_efuse() - Determine speed grade from efuse value ++ * @soc_data: pointer to sunxi_cpufreq_soc_data context + * @versions: Set to the value parsed from efuse + * + * Returns 0 if success. + */ +-static int sun50i_cpufreq_get_efuse(u32 *versions) ++static int sun50i_cpufreq_get_efuse(const struct sunxi_cpufreq_soc_data *soc_data, ++ u32 *versions) + { + struct nvmem_cell *speedbin_nvmem; + struct device_node *np; + struct device *cpu_dev; +- u32 *speedbin, efuse_value; ++ u32 *speedbin; + size_t len; +- int ret; + + cpu_dev = get_cpu_device(0); + if (!cpu_dev) + return -ENODEV; + + np = dev_pm_opp_of_get_opp_desc_node(cpu_dev); + if (!np) + return -ENOENT; +- +- ret = of_device_is_compatible(np, +- "allwinner,sun50i-h6-operating-points"); +- if (!ret) { ++ if (of_device_is_compatible(np, "allwinner,sun50i-h6-operating-points")) {} ++ else if (of_device_is_compatible(np, "allwinner,sun50i-h616-operating-points")) {} ++ else { + of_node_put(np); + return -ENOENT; + } + + speedbin_nvmem = of_nvmem_cell_get(np, NULL); +@@ -63,40 +102,35 @@ static int sun50i_cpufreq_get_efuse(u32 *versions) + speedbin = nvmem_cell_read(speedbin_nvmem, &len); + nvmem_cell_put(speedbin_nvmem); + if (IS_ERR(speedbin)) + return PTR_ERR(speedbin); + +- efuse_value = (*speedbin >> NVMEM_SHIFT) & NVMEM_MASK; +- +- /* +- * We treat unexpected efuse values as if the SoC was from +- * the slowest bin. Expected efuse values are 1-3, slowest +- * to fastest. +- */ +- if (efuse_value >= 1 && efuse_value <= 3) +- *versions = efuse_value - 1; +- else +- *versions = 0; ++ *versions = soc_data->efuse_xlate(speedbin); + + kfree(speedbin); + return 0; + }; + + static int sun50i_cpufreq_nvmem_probe(struct platform_device *pdev) + { ++ const struct of_device_id *match; + int *opp_tokens; + char name[MAX_NAME_LEN]; + unsigned int cpu; + u32 speed = 0; + int ret; + ++ match = dev_get_platdata(&pdev->dev); ++ if (!match) ++ return -EINVAL; ++ + opp_tokens = kcalloc(num_possible_cpus(), sizeof(*opp_tokens), + GFP_KERNEL); + if (!opp_tokens) + return -ENOMEM; + +- ret = sun50i_cpufreq_get_efuse(&speed); ++ ret = sun50i_cpufreq_get_efuse(match-> data, &speed); + if (ret) { + kfree(opp_tokens); + return ret; + } + +@@ -158,12 +192,21 @@ static struct platform_driver sun50i_cpufreq_driver = { + .driver = { + .name = "sun50i-cpufreq-nvmem", + }, + }; + ++static const struct sunxi_cpufreq_soc_data sun50i_h616_data = { ++ .efuse_xlate = sun50i_h616_efuse_xlate, ++}; ++ ++static const struct sunxi_cpufreq_soc_data sun50i_h6_data = { ++ .efuse_xlate = sun50i_h6_efuse_xlate, ++}; ++ + static const struct of_device_id sun50i_cpufreq_match_list[] = { +- { .compatible = "allwinner,sun50i-h6" }, ++ { .compatible = "allwinner,sun50i-h6", .data = &sun50i_h6_data }, ++ { .compatible = "allwinner,sun50i-h616", .data = &sun50i_h616_data }, + {} + }; + MODULE_DEVICE_TABLE(of, sun50i_cpufreq_match_list); + + static const struct of_device_id *sun50i_cpufreq_match_node(void) +@@ -195,12 +238,12 @@ static int __init sun50i_cpufreq_init(void) + ret = platform_driver_register(&sun50i_cpufreq_driver); + if (unlikely(ret < 0)) + return ret; + + sun50i_cpufreq_pdev = +- platform_device_register_simple("sun50i-cpufreq-nvmem", +- -1, NULL, 0); ++ platform_device_register_data(NULL, ++ "sun50i-cpufreq-nvmem", -1, match, sizeof(*match)); + ret = PTR_ERR_OR_ZERO(sun50i_cpufreq_pdev); + if (ret == 0) + return 0; + + platform_driver_unregister(&sun50i_cpufreq_driver); +-- +Created with Armbian build tools https://github.com/armbian/build diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-allwinner-h616-Add-thermal-sensor-and-thermal-zones.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-allwinner-h616-Add-thermal-sensor-and-thermal-zones.patch new file mode 100644 index 0000000000..a8ddcb08f1 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-allwinner-h616-Add-thermal-sensor-and-thermal-zones.patch @@ -0,0 +1,136 @@ +From 25511473332b2d43309b707be5c2970a5b9a4efd Mon Sep 17 00:00:00 2001 +From: Kali Prasad +Date: Sun, 19 Sep 2021 13:38:20 +0530 +Subject: [PATCH 083/153] arm64: dts: allwinner: h616: Add thermal sensor and + thermal zones + +There are four sensors, CPU, GPU, VE, and DDR. + +Signed-off-by: Kali Prasad +--- + .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 75 +++++++++++++++++++ + 1 file changed, 75 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +index 7ad1982fb..8628a9e3d 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +@@ -9,6 +9,7 @@ + #include + #include + #include ++#include + + / { + interrupt-parent = <&gic>; +@@ -25,6 +26,8 @@ cpu0: cpu@0 { + reg = <0>; + enable-method = "psci"; + clocks = <&ccu CLK_CPUX>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ #cooling-cells = <2>; + }; + + cpu1: cpu@1 { +@@ -33,6 +36,8 @@ cpu1: cpu@1 { + reg = <1>; + enable-method = "psci"; + clocks = <&ccu CLK_CPUX>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ #cooling-cells = <2>; + }; + + cpu2: cpu@2 { +@@ -41,6 +46,8 @@ cpu2: cpu@2 { + reg = <2>; + enable-method = "psci"; + clocks = <&ccu CLK_CPUX>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ #cooling-cells = <2>; + }; + + cpu3: cpu@3 { +@@ -49,6 +56,8 @@ cpu3: cpu@3 { + reg = <3>; + enable-method = "psci"; + clocks = <&ccu CLK_CPUX>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ #cooling-cells = <2>; + }; + }; + +@@ -833,5 +842,71 @@ r_rsb: rsb@7083000 { + #address-cells = <1>; + #size-cells = <0>; + }; ++ ++ ths: thermal-sensor@5070400 { ++ compatible = "allwinner,sun50i-h616-ths"; ++ reg = <0x05070400 0x400>; ++ interrupts = ; ++ clocks = <&ccu CLK_BUS_THS>; ++ clock-names = "bus"; ++ resets = <&ccu RST_BUS_THS>; ++ nvmem-cells = <&ths_calibration>; ++ nvmem-cell-names = "calibration"; ++ #thermal-sensor-cells = <1>; ++ }; ++ }; ++ ++ thermal-zones { ++ cpu-thermal { ++ polling-delay-passive = <500>; ++ polling-delay = <1000>; ++ thermal-sensors = <&ths 2>; ++ sustainable-power = <1000>; ++ k_po = <20>; ++ k_pu = <40>; ++ k_i = <0>; ++ ++ trips { ++ cpu_threshold: trip-point@0 { ++ temperature = <60000>; ++ type = "passive"; ++ hysteresis = <0>; ++ }; ++ cpu_target: trip-point@1 { ++ temperature = <70000>; ++ type = "passive"; ++ hysteresis = <0>; ++ }; ++ }; ++ ++ cooling-maps { ++ map0 { ++ trip = <&cpu_target>; ++ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ }; ++ }; ++ }; ++ ++ gpu-thermal { ++ polling-delay-passive = <500>; ++ polling-delay = <1000>; ++ thermal-sensors = <&ths 0>; ++ sustainable-power = <1100>; ++ }; ++ ++ ve-thermal { ++ polling-delay-passive = <0>; ++ polling-delay = <0>; ++ thermal-sensors = <&ths 1>; ++ }; ++ ++ ddr-thermal { ++ polling-delay-passive = <0>; ++ polling-delay = <0>; ++ thermal-sensors = <&ths 3>; ++ }; + }; + }; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-allwinner-h616-Fix-thermal-zones-missing-trips.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-allwinner-h616-Fix-thermal-zones-missing-trips.patch new file mode 100644 index 0000000000..67ac20e26e --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-allwinner-h616-Fix-thermal-zones-missing-trips.patch @@ -0,0 +1,82 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Micha=C5=82=20Dzieko=C5=84ski?= + +Date: Wed, 3 May 2023 12:17:28 +0000 +Subject: arm64: dts: allwinner: h616: Fix thermal zones (add missing trips) +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: MichaÅ‚ DziekoÅ„ski +--- + arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 29 ++++++++++ + 1 file changed, 29 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +index 8628a9e3d..17b13d319 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +@@ -875,10 +875,15 @@ cpu_threshold: trip-point@0 { + cpu_target: trip-point@1 { + temperature = <70000>; + type = "passive"; + hysteresis = <0>; + }; ++ cpu_temp_critical: trip-point@2 { ++ temperature = <110000>; ++ type = "critical"; ++ hysteresis = <0>; ++ }; + }; + + cooling-maps { + map0 { + trip = <&cpu_target>; +@@ -893,20 +898,44 @@ map0 { + gpu-thermal { + polling-delay-passive = <500>; + polling-delay = <1000>; + thermal-sensors = <&ths 0>; + sustainable-power = <1100>; ++ ++ trips { ++ gpu_temp_critical: trip-point@0 { ++ temperature = <110000>; ++ type = "critical"; ++ hysteresis = <0>; ++ }; ++ }; + }; + + ve-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths 1>; ++ ++ trips { ++ ve_temp_critical: trip-point@0 { ++ temperature = <110000>; ++ type = "critical"; ++ hysteresis = <0>; ++ }; ++ }; + }; + + ddr-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths 3>; ++ ++ trips { ++ ddr_temp_critical: trip-point@0 { ++ temperature = <110000>; ++ type = "critical"; ++ hysteresis = <0>; ++ }; ++ }; + }; + }; + }; +-- +Created with Armbian build tools https://github.com/armbian/build + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-allwinner-h616-LED-green_power_on-red_status_heartbeat.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-allwinner-h616-LED-green_power_on-red_status_heartbeat.patch new file mode 100644 index 0000000000..7ff61f15e7 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-allwinner-h616-LED-green_power_on-red_status_heartbeat.patch @@ -0,0 +1,39 @@ +From e88d105d8051a8f90e6103969858debf7a0946eb Mon Sep 17 00:00:00 2001 +From: AGM1968 +Date: Wed, 31 May 2023 08:12:00 +0000 +Subject: [PATCH] LED-green_power_on-red_status_heartbeat + arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts + +Signed-off-by: AGM1968 +--- + .../boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts | 7 ++++--- + 1 file changed, 4 insertions(+), 3 deletions(-) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts +index defb8b71f872..ddb5e387d1f4 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts +@@ -29,16 +29,17 @@ leds { + compatible = "gpio-leds"; + + led-0 { +- function = LED_FUNCTION_POWER; ++ function = LED_FUNCTION_STATUS; + color = ; + gpios = <&pio 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */ +- default-state = "on"; ++ linux,default-trigger = "heartbeat"; + }; + + led-1 { +- function = LED_FUNCTION_STATUS; ++ function = LED_FUNCTION_POWER; + color = ; + gpios = <&pio 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */ ++ default-state = "on"; + }; + }; + +-- +2.34.1 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-allwinner-h616-orangepi-zero2-Enable-expansion-board-USB-ports.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-allwinner-h616-orangepi-zero2-Enable-expansion-board-USB-ports.patch new file mode 100644 index 0000000000..a454fffa34 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-allwinner-h616-orangepi-zero2-Enable-expansion-board-USB-ports.patch @@ -0,0 +1,41 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Micha=C5=82=20Dzieko=C5=84ski?= + +Date: Sun, 28 May 2023 00:26:43 +0000 +Subject: arm64: dts: allwinner: h616 orangepi zero2: Enable expansion board + USB ports +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: MichaÅ‚ DziekoÅ„ski +--- + arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts +index b78941d29..565cd51e2 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts +@@ -64,10 +64,19 @@ reg_usb1_vbus: usb1-vbus { + + &ehci1 { + status = "okay"; + }; + ++ ++/* USB 2 & 3 are on headers used by expansion board */ ++&ehci2 { ++ status = "okay"; ++}; ++&ehci3 { ++ status = "okay"; ++}; ++ + &gpu { + mali-supply = <®_dcdcc>; + status = "okay"; + }; + +-- +Created with Armbian build tools https://github.com/armbian/build diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-allwinner-overlay-Add-Overlays-for-sunxi64.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-allwinner-overlay-Add-Overlays-for-sunxi64.patch new file mode 100644 index 0000000000..a908671811 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-allwinner-overlay-Add-Overlays-for-sunxi64.patch @@ -0,0 +1,2471 @@ +From 49f981f4c41e1057cbf1d37b3d36c2620d6ea2b2 Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Wed, 2 Feb 2022 13:02:10 +0300 +Subject: [PATCH 110/153] arm64:dts:allwinner:overlay: Add Overlays for sunxi64 + +--- + arch/arm64/boot/dts/allwinner/Makefile | 2 + + .../arm64/boot/dts/allwinner/overlay/Makefile | 58 ++++ + .../overlay/README.sun50i-a64-overlays | 196 ++++++++++++++ + .../overlay/README.sun50i-h5-overlays | 250 ++++++++++++++++++ + .../overlay/sun50i-a64-fixup.scr-cmd | 95 +++++++ + .../dts/allwinner/overlay/sun50i-a64-i2c0.dts | 32 +++ + .../dts/allwinner/overlay/sun50i-a64-i2c1.dts | 22 ++ + .../allwinner/overlay/sun50i-a64-pps-gpio.dts | 29 ++ + .../overlay/sun50i-a64-spi-add-cs1.dts | 41 +++ + .../overlay/sun50i-a64-spi-jedec-nor.dts | 34 +++ + .../overlay/sun50i-a64-spi-spidev.dts | 42 +++ + .../allwinner/overlay/sun50i-a64-uart1.dts | 22 ++ + .../allwinner/overlay/sun50i-a64-uart2.dts | 37 +++ + .../allwinner/overlay/sun50i-a64-uart3.dts | 32 +++ + .../allwinner/overlay/sun50i-a64-uart4.dts | 37 +++ + .../allwinner/overlay/sun50i-a64-w1-gpio.dts | 29 ++ + .../overlay/sun50i-h5-analog-codec.dts | 17 ++ + .../dts/allwinner/overlay/sun50i-h5-cir.dts | 15 ++ + .../allwinner/overlay/sun50i-h5-fixup.scr-cmd | 110 ++++++++ + .../dts/allwinner/overlay/sun50i-h5-i2c0.dts | 20 ++ + .../dts/allwinner/overlay/sun50i-h5-i2c1.dts | 20 ++ + .../dts/allwinner/overlay/sun50i-h5-i2c2.dts | 20 ++ + .../allwinner/overlay/sun50i-h5-pps-gpio.dts | 29 ++ + .../dts/allwinner/overlay/sun50i-h5-pwm.dts | 39 +++ + .../allwinner/overlay/sun50i-h5-spdif-out.dts | 38 +++ + .../overlay/sun50i-h5-spi-add-cs1.dts | 41 +++ + .../overlay/sun50i-h5-spi-jedec-nor.dts | 42 +++ + .../overlay/sun50i-h5-spi-spidev.dts | 42 +++ + .../dts/allwinner/overlay/sun50i-h5-uart1.dts | 22 ++ + .../dts/allwinner/overlay/sun50i-h5-uart2.dts | 32 +++ + .../dts/allwinner/overlay/sun50i-h5-uart3.dts | 32 +++ + .../allwinner/overlay/sun50i-h5-usbhost0.dts | 27 ++ + .../allwinner/overlay/sun50i-h5-usbhost1.dts | 27 ++ + .../allwinner/overlay/sun50i-h5-usbhost2.dts | 27 ++ + .../allwinner/overlay/sun50i-h5-usbhost3.dts | 27 ++ + .../allwinner/overlay/sun50i-h5-w1-gpio.dts | 29 ++ + .../allwinner/overlay/sun50i-h6-fixup.scr-cmd | 110 ++++++++ + .../dts/allwinner/overlay/sun50i-h6-i2c0.dts | 20 ++ + .../dts/allwinner/overlay/sun50i-h6-i2c1.dts | 20 ++ + .../dts/allwinner/overlay/sun50i-h6-i2c2.dts | 20 ++ + .../dts/allwinner/overlay/sun50i-h6-ruart.dts | 13 + + .../overlay/sun50i-h6-spi-add-cs1.dts | 41 +++ + .../overlay/sun50i-h6-spi-jedec-nor.dts | 42 +++ + .../overlay/sun50i-h6-spi-spidev.dts | 42 +++ + .../overlay/sun50i-h6-spi-spidev1.dts | 30 +++ + .../dts/allwinner/overlay/sun50i-h6-uart1.dts | 22 ++ + .../dts/allwinner/overlay/sun50i-h6-uart2.dts | 32 +++ + .../dts/allwinner/overlay/sun50i-h6-uart3.dts | 32 +++ + .../allwinner/overlay/sun50i-h6-w1-gpio.dts | 29 ++ + 49 files changed, 2067 insertions(+) + create mode 100644 arch/arm64/boot/dts/allwinner/overlay/Makefile + create mode 100644 arch/arm64/boot/dts/allwinner/overlay/README.sun50i-a64-overlays + create mode 100644 arch/arm64/boot/dts/allwinner/overlay/README.sun50i-h5-overlays + create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-fixup.scr-cmd + create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-i2c0.dts + create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-i2c1.dts + create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-pps-gpio.dts + create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-spi-add-cs1.dts + create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-spi-jedec-nor.dts + create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-spi-spidev.dts + create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-uart1.dts + create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-uart2.dts + create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-uart3.dts + create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-uart4.dts + create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-w1-gpio.dts + create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-analog-codec.dts + create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cir.dts + create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-fixup.scr-cmd + create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-i2c0.dts + create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-i2c1.dts + create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-i2c2.dts + create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-pps-gpio.dts + create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-pwm.dts + create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-spdif-out.dts + create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-spi-add-cs1.dts + create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-spi-jedec-nor.dts + create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-spi-spidev.dts + create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-uart1.dts + create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-uart2.dts + create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-uart3.dts + create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-usbhost0.dts + create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-usbhost1.dts + create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-usbhost2.dts + create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-usbhost3.dts + create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-w1-gpio.dts + create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-fixup.scr-cmd + create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-i2c0.dts + create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-i2c1.dts + create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-i2c2.dts + create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-ruart.dts + create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-add-cs1.dts + create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-jedec-nor.dts + create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-spidev.dts + create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-spidev1.dts + create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-uart1.dts + create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-uart2.dts + create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-uart3.dts + create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-w1-gpio.dts + +diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile +index 2fd4e07cb..43870e278 100644 +--- a/arch/arm64/boot/dts/allwinner/Makefile ++++ b/arch/arm64/boot/dts/allwinner/Makefile +@@ -45,3 +45,5 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6-mini.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-orangepi-zero2.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-x96-mate.dtb ++ ++subdir-y := $(dts-dirs) overlay +diff --git a/arch/arm64/boot/dts/allwinner/overlay/Makefile b/arch/arm64/boot/dts/allwinner/overlay/Makefile +new file mode 100644 +index 000000000..9b6528ec2 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/Makefile +@@ -0,0 +1,58 @@ ++# SPDX-License-Identifier: GPL-2.0 ++dtbo-$(CONFIG_ARCH_SUNXI) += \ ++ sun50i-a64-i2c0.dtbo \ ++ sun50i-a64-i2c1.dtbo \ ++ sun50i-a64-pps-gpio.dtbo \ ++ sun50i-a64-spi-add-cs1.dtbo \ ++ sun50i-a64-spi-jedec-nor.dtbo \ ++ sun50i-a64-spi-spidev.dtbo \ ++ sun50i-a64-uart1.dtbo \ ++ sun50i-a64-uart2.dtbo \ ++ sun50i-a64-uart3.dtbo \ ++ sun50i-a64-uart4.dtbo \ ++ sun50i-a64-w1-gpio.dtbo \ ++ sun50i-h5-analog-codec.dtbo \ ++ sun50i-h5-cir.dtbo \ ++ sun50i-h5-i2c0.dtbo \ ++ sun50i-h5-i2c1.dtbo \ ++ sun50i-h5-i2c2.dtbo \ ++ sun50i-h5-pps-gpio.dtbo \ ++ sun50i-h5-pwm.dtbo \ ++ sun50i-h5-spdif-out.dtbo \ ++ sun50i-h5-spi-add-cs1.dtbo \ ++ sun50i-h5-spi-jedec-nor.dtbo \ ++ sun50i-h5-spi-spidev.dtbo \ ++ sun50i-h5-uart1.dtbo \ ++ sun50i-h5-uart2.dtbo \ ++ sun50i-h5-uart3.dtbo \ ++ sun50i-h5-usbhost0.dtbo \ ++ sun50i-h5-usbhost1.dtbo \ ++ sun50i-h5-usbhost2.dtbo \ ++ sun50i-h5-usbhost3.dtbo \ ++ sun50i-h5-w1-gpio.dtbo \ ++ sun50i-h6-i2c0.dtbo \ ++ sun50i-h6-i2c1.dtbo \ ++ sun50i-h6-i2c2.dtbo \ ++ sun50i-h6-ruart.dtbo \ ++ sun50i-h6-spi-add-cs1.dtbo \ ++ sun50i-h6-spi-jedec-nor.dtbo \ ++ sun50i-h6-spi-spidev.dtbo \ ++ sun50i-h6-spi-spidev1.dtbo \ ++ sun50i-h6-uart1.dtbo \ ++ sun50i-h6-uart2.dtbo \ ++ sun50i-h6-uart3.dtbo \ ++ sun50i-h6-w1-gpio.dtbo ++ ++scr-$(CONFIG_ARCH_SUNXI) += \ ++ sun50i-a64-fixup.scr \ ++ sun50i-h5-fixup.scr \ ++ sun50i-h6-fixup.scr ++ ++dtbotxt-$(CONFIG_ARCH_SUNXI) += \ ++ README.sun50i-a64-overlays \ ++ README.sun50i-h5-overlays ++ ++targets += $(dtbo-y) $(scr-y) $(dtbotxt-y) ++ ++always := $(dtbo-y) $(scr-y) $(dtbotxt-y) ++clean-files := *.dtbo *.scr +diff --git a/arch/arm64/boot/dts/allwinner/overlay/README.sun50i-a64-overlays b/arch/arm64/boot/dts/allwinner/overlay/README.sun50i-a64-overlays +new file mode 100644 +index 000000000..cd9dbc686 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/README.sun50i-a64-overlays +@@ -0,0 +1,196 @@ ++This document describes overlays provided in the kernel packages ++For generic Armbian overlays documentation please see ++https://docs.armbian.com/Hardware_Allwinner_overlays/ ++ ++### Platform: ++ ++sun50i-a64 (Allwinner A64) ++ ++### Platform details: ++ ++Supported pin banks: PB, PC, PD, PH ++ ++Both SPI controllers have only one hardware CS pin exposed, ++adding fixed software (GPIO) chip selects is possible with a separate overlay ++ ++I2C controller 2 (PE14, PE15) pins are used for non-I2C CSI functions or are not available ++on supported boards, so this controller is not supported in provided overlays ++ ++### Provided overlays: ++ ++- i2c0 ++- i2c1 ++- pps-gpio ++- spi-add-cs1 ++- spi-jedec-nor ++- spi-spidev ++- uart1 ++- uart2 ++- uart3 ++- uart4 ++- w1-gpio ++ ++### Overlay details: ++ ++### i2c0 ++ ++Activates TWI/I2C bus 0 ++ ++I2C0 pins (SCL, SDA): PH0, PH1 ++ ++### i2c1 ++ ++Activates TWI/I2C bus 1 ++ ++I2C1 pins (SCL, SDA): PH2, PH3 ++ ++### pps-gpio ++ ++Activates pulse-per-second GPIO client ++ ++Parameters: ++ ++param_pps_pin (pin) ++ Pin PPS source is connected to ++ Optional ++ Default: PD4 ++ ++param_pps_falling_edge (bool) ++ Assert by falling edge ++ Optional ++ Default: 0 ++ When set (to 1), assert is indicated by a falling edge ++ (instead of by a rising edge) ++ ++### spi-add-cs1 ++ ++Adds support for using SPI chip select 1 with GPIO for both SPI controllers ++Respective GPIO will be claimed only if controller is enabled by another overlay ++This overlay is required for using chip select 1 with other SPI overlays ++ ++SPI 0 pins (CS1): PB6 ++SPI 1 pins (CS1): PD6 ++ ++### spi-jedec-nor ++ ++Activates MTD support for JEDEC compatible SPI NOR flash chips on SPI bus ++supported by the kernel SPI NOR driver ++ ++SPI 0 pins (MOSI, MISO, SCK, CS): PC0, PC1, PC2, PC3 ++SPI 1 pins (MOSI, MISO, SCK, CS): PD2, PD3, PD1, PD0 ++ ++Parameters: ++ ++param_spinor_spi_bus (int) ++ SPI bus to activate SPI NOR flash support on ++ Required ++ Supported values: 0, 1 ++ ++param_spinor_spi_cs (int) ++ SPI chip select number ++ Optional ++ Default: 0 ++ Supported values: 0, 1 ++ Using chip select 1 requires using "spi-add-cs1" overlay ++ ++param_spinor_max_freq (int) ++ Maximum SPI frequency ++ Optional ++ Default: 1000000 ++ Range: 3000 - 100000000 ++ ++### spi-spidev ++ ++Activates SPIdev device node (/dev/spidevX.Y) for userspace SPI access, ++where X is the bus number and Y is the CS number ++ ++SPI 0 pins (MOSI, MISO, SCK, CS): PC0, PC1, PC2, PC3 ++SPI 1 pins (MOSI, MISO, SCK, CS): PD2, PD3, PD1, PD0 ++ ++Parameters: ++ ++param_spidev_spi_bus (int) ++ SPI bus to activate SPIdev support on ++ Required ++ Supported values: 0, 1 ++ ++param_spidev_spi_cs (int) ++ SPI chip select number ++ Optional ++ Default: 0 ++ Supported values: 0, 1 ++ Using chip select 1 requires using "spi-add-cs1" overlay ++ ++param_spidev_max_freq (int) ++ Maximum SPIdev frequency ++ Optional ++ Default: 1000000 ++ Range: 3000 - 100000000 ++ ++### uart1 ++ ++Activates serial port 1 (/dev/ttyS1) ++ ++UART 1 pins (TX, RX, RTS, CTS): PG6, PG7, PG8, PG9 ++ ++Parameters: ++ ++param_uart1_rtscts (bool) ++ Enable RTS and CTS pins ++ Optional ++ Default: 0 ++ Set to 1 to enable ++ ++### uart2 ++ ++Activates serial port 2 (/dev/ttyS2) ++ ++UART 2 pins (TX, RX, RTS, CTS): PB0, PB1, PB2, PB3 ++ ++Parameters: ++ ++param_uart2_rtscts (bool) ++ Enable RTS and CTS pins ++ Optional ++ Default: 0 ++ Set to 1 to enable CTS and RTS pins ++ ++### uart3 ++ ++Activates serial port 3 (/dev/ttyS3) ++ ++UART 3 pins (TX, RX): PD0, PD1 ++ ++### uart4 ++ ++Activates serial port 4 (/dev/ttyS4) ++ ++UART 4 pins (TX, RX, RTS, CTS): PD2, PD3, PD4, PD5 ++ ++Parameters: ++ ++param_uart2_rtscts (bool) ++ Enable RTS and CTS pins ++ Optional ++ Default: 0 ++ Set to 1 to enable CTS and RTS pins ++ ++### w1-gpio ++ ++Activates 1-Wire GPIO master ++Requires external pull-up resistor on data pin ++ ++Parameters: ++ ++param_w1_pin (pin) ++ Data pin for 1-Wire master ++ Optional ++ Default: PD4 ++ ++param_w1_pin_int_pullup (bool) ++ Enable internal pull-up for the data pin ++ Optional ++ Default: 0 ++ Set to 1 to enable the pull-up ++ This option should not be used with multiple devices, parasite power setup ++ or long wires - please use external pull-up resistor instead +diff --git a/arch/arm64/boot/dts/allwinner/overlay/README.sun50i-h5-overlays b/arch/arm64/boot/dts/allwinner/overlay/README.sun50i-h5-overlays +new file mode 100644 +index 000000000..1ac7fbcf6 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/README.sun50i-h5-overlays +@@ -0,0 +1,250 @@ ++This document describes overlays provided in the kernel packages ++For generic Armbian overlays documentation please see ++https://docs.armbian.com/User-Guide_Allwinner_overlays/ ++ ++### Platform: ++ ++sun50i-h5 (Allwinner H5) ++ ++### Platform details: ++ ++Supported pin banks: PA, PC, PD, PG ++ ++Both SPI controllers have only one hardware CS pin exposed, ++adding fixed software (GPIO) chip selects is possible with a separate overlay ++ ++### Provided overlays: ++ ++- analog-codec ++- cir ++- i2c0 ++- i2c1 ++- i2c2 ++- pps-gpio ++- pwm ++- spdif-out ++- spi-add-cs1 ++- spi-jedec-nor ++- spi-spidev ++- uart1 ++- uart2 ++- uart3 ++- usbhost0 ++- usbhost1 ++- usbhost2 ++- usbhost3 ++- w1-gpio ++ ++### Overlay details: ++ ++### analog-codec ++ ++Activates SoC analog codec driver that provides Line Out and Mic In ++functionality ++ ++### cir ++ ++Activates CIR (Infrared remote) receiver ++ ++CIR pin: PL11 ++ ++### i2c0 ++ ++Activates TWI/I2C bus 0 ++ ++I2C0 pins (SCL, SDA): PA11, PA12 ++ ++### i2c1 ++ ++Activates TWI/I2C bus 1 ++ ++I2C1 pins (SCL, SDA): PA18, PA19 ++ ++### i2c2 ++ ++Activates TWI/I2C bus 2 ++ ++I2C2 pins (SCL, SDA): PE12, PE13 ++ ++On most board this bus is wired to Camera (CSI) socket ++ ++### pps-gpio ++ ++Activates pulse-per-second GPIO client ++ ++Parameters: ++ ++param_pps_pin (pin) ++ Pin PPS source is connected to ++ Optional ++ Default: PD14 ++ ++param_pps_falling_edge (bool) ++ Assert by falling edge ++ Optional ++ Default: 0 ++ When set (to 1), assert is indicated by a falling edge ++ (instead of by a rising edge) ++ ++### pwm ++ ++Activates hardware PWM controller ++ ++PWM pin: PA5 ++ ++Pin PA5 is used as UART0 RX by default, so if this overlay is activated, ++UART0 and kernel console on ttyS0 will be disabled ++ ++### spdif-out ++ ++Activates SPDIF/Toslink audio output ++ ++SPDIF pin: PA17 ++ ++### spi-add-cs1 ++ ++Adds support for using SPI chip select 1 with GPIO for both SPI controllers ++Respective GPIO will be claimed only if controller is enabled by another ++overlay ++This overlay is required for using chip select 1 with other SPI overlays ++Due to the u-boot limitations CS1 pin can't be customized by a parameter, but ++it can be changed by using an edited copy of this overlay ++A total of 4 chip selects can be used with custom overlays (1 HW + 3 GPIO) ++ ++SPI 0 pins (CS1): PA21 ++SPI 1 pins (CS1): PA10 ++ ++### spi-jedec-nor ++ ++Activates MTD support for JEDEC compatible SPI NOR flash chips on SPI bus ++supported by the kernel SPI NOR driver ++ ++SPI 0 pins (MOSI, MISO, SCK, CS): PC0, PC1, PC2, PC3 ++SPI 1 pins (MOSI, MISO, SCK, CS): PA15, PA16, PA14, PA13 ++ ++Parameters: ++ ++param_spinor_spi_bus (int) ++ SPI bus to activate SPI NOR flash support on ++ Required ++ Supported values: 0, 1 ++ ++param_spinor_spi_cs (int) ++ SPI chip select number ++ Optional ++ Default: 0 ++ Supported values: 0, 1 ++ Using chip select 1 requires using "spi-add-cs1" overlay ++ ++param_spinor_max_freq (int) ++ Maximum SPI frequency ++ Optional ++ Default: 1000000 ++ Range: 3000 - 100000000 ++ ++### spi-spidev ++ ++Activates SPIdev device node (/dev/spidevX.Y) for userspace SPI access, ++where X is the bus number and Y is the CS number ++ ++SPI 0 pins (MOSI, MISO, SCK, CS): PC0, PC1, PC2, PC3 ++SPI 1 pins (MOSI, MISO, SCK, CS): PA15, PA16, PA14, PA13 ++ ++Parameters: ++ ++param_spidev_spi_bus (int) ++ SPI bus to activate SPIdev support on ++ Required ++ Supported values: 0, 1 ++ ++param_spidev_spi_cs (int) ++ SPI chip select number ++ Optional ++ Default: 0 ++ Supported values: 0, 1 ++ Using chip select 1 requires using "spi-add-cs1" overlay ++ ++param_spidev_max_freq (int) ++ Maximum SPIdev frequency ++ Optional ++ Default: 1000000 ++ Range: 3000 - 100000000 ++ ++### uart1 ++ ++Activates serial port 1 (/dev/ttyS1) ++ ++UART 1 pins (TX, RX, RTS, CTS): PG6, PG7, PG8, PG9 ++ ++Parameters: ++ ++param_uart1_rtscts (bool) ++ Enable RTS and CTS pins ++ Optional ++ Default: 0 ++ Set to 1 to enable ++ ++### uart2 ++ ++Activates serial port 2 (/dev/ttyS2) ++ ++UART 2 pins (TX, RX, RTS, CTS): PA0, PA1, PA2, PA3 ++ ++Parameters: ++ ++param_uart2_rtscts (bool) ++ Enable RTS and CTS pins ++ Optional ++ Default: 0 ++ Set to 1 to enable CTS and RTS pins ++ ++### uart3 ++ ++Activates serial port 3 (/dev/ttyS3) ++ ++UART 3 pins (TX, RX, RTS, CTS): PA13, PA14, PA15, PA16 ++ ++Parameters: ++ ++param_uart3_rtscts (bool) ++ Enable RTS and CTS pins ++ Optional ++ Default: 0 ++ Set to 1 to enable CTS and RTS pins ++ ++### usbhost0 ++ ++Activates USB host controller 0 ++ ++### usbhost1 ++ ++Activates USB host controller 1 ++ ++### usbhost2 ++ ++Activates USB host controller 2 ++ ++### usbhost3 ++ ++Activates USB host controller 3 ++ ++### w1-gpio ++ ++Activates 1-Wire GPIO master ++Requires an external pull-up resistor on the data pin ++or enabling the internal pull-up ++ ++Parameters: ++ ++param_w1_pin (pin) ++ Data pin for 1-Wire master ++ Optional ++ Default: PD14 ++ ++param_w1_pin_int_pullup (bool) ++ Enable internal pull-up for the data pin ++ Optional ++ Default: 0 ++ Set to 1 to enable the pull-up ++ This option should not be used with multiple devices, parasite power setup ++ or long wires - please use external pull-up resistor instead +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-fixup.scr-cmd b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-fixup.scr-cmd +new file mode 100644 +index 000000000..9b34c05ec +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-fixup.scr-cmd +@@ -0,0 +1,95 @@ ++# overlays fixup script ++# implements (or rather substitutes) overlay arguments functionality ++# using u-boot scripting, environment variables and "fdt" command ++ ++# setexpr test_var ${tmp_bank} - A ++# works only for hex numbers (A-F) ++ ++setenv decompose_pin 'setexpr tmp_bank sub "P(B|C|D|H)\\d+" "\\1"; ++setexpr tmp_pin sub "P\\S(\\d+)" "\\1"; ++test "${tmp_bank}" = "B" && setenv tmp_bank 1; ++test "${tmp_bank}" = "C" && setenv tmp_bank 2; ++test "${tmp_bank}" = "D" && setenv tmp_bank 3; ++test "${tmp_bank}" = "H" && setenv tmp_bank 7' ++ ++if test -n "${param_spinor_spi_bus}"; then ++ test "${param_spinor_spi_bus}" = "0" && setenv tmp_spi_path "spi@1c68000" ++ test "${param_spinor_spi_bus}" = "1" && setenv tmp_spi_path "spi@1c69000" ++ fdt set /soc/${tmp_spi_path} status "okay" ++ fdt set /soc/${tmp_spi_path}/spiflash@0 status "okay" ++ if test -n "${param_spinor_max_freq}"; then ++ fdt set /soc/${tmp_spi_path}/spiflash@0 spi-max-frequency "<${param_spinor_max_freq}>" ++ fi ++ if test "${param_spinor_spi_cs}" = "1"; then ++ fdt set /soc/${tmp_spi_path}/spiflash@0 reg "<1>"; ++ fi ++ env delete tmp_spi_path ++fi ++ ++if test -n "${param_spidev_spi_bus}"; then ++ test "${param_spidev_spi_bus}" = "0" && setenv tmp_spi_path "spi@1c68000" ++ test "${param_spidev_spi_bus}" = "1" && setenv tmp_spi_path "spi@1c69000" ++ fdt set /soc/${tmp_spi_path} status "okay" ++ fdt set /soc/${tmp_spi_path}/spidev status "okay" ++ if test -n "${param_spidev_max_freq}"; then ++ fdt set /soc/${tmp_spi_path}/spidev spi-max-frequency "<${param_spidev_max_freq}>" ++ fi ++ if test "${param_spidev_spi_cs}" = "1"; then ++ fdt set /soc/${tmp_spi_path}/spidev reg "<1>"; ++ fi ++fi ++ ++if test -n "${param_pps_pin}"; then ++ setenv tmp_bank "${param_pps_pin}" ++ setenv tmp_pin "${param_pps_pin}" ++ run decompose_pin ++ fdt set /soc/pinctrl@1c20800/pps_pins pins "${param_pps_pin}" ++ fdt get value tmp_phandle /soc/pinctrl@1c20800 phandle ++ fdt set /pps@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>" ++ env delete tmp_pin tmp_bank tmp_phandle ++fi ++ ++if test "${param_pps_falling_edge}" = "1"; then ++ fdt set /pps@0 assert-falling-edge ++fi ++ ++if test -n "${param_w1_pin}"; then ++ setenv tmp_bank "${param_w1_pin}" ++ setenv tmp_pin "${param_w1_pin}" ++ run decompose_pin ++ fdt set /soc/pinctrl@1c20800/w1_pins pins "${param_w1_pin}" ++ fdt get value tmp_phandle /soc/pinctrl@1c20800 phandle ++ fdt set /onewire@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>" ++ env delete tmp_pin tmp_bank tmp_phandle ++fi ++ ++if test "${param_w1_pin_int_pullup}" = "1"; then ++ fdt set /soc/pinctrl@1c20800/w1_pins bias-pull-up ++fi ++ ++if test "${param_uart1_rtscts}" = "1"; then ++ fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart1-pins phandle ++ fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart1-rts-cts-pins phandle ++ fdt set /soc/serial@1c28400 pinctrl-names "default" "default" ++ fdt set /soc/serial@1c28400 pinctrl-0 "<${tmp_phandle1}>" ++ fdt set /soc/serial@1c28400 pinctrl-1 "<${tmp_phandle2}>" ++ env delete tmp_phandle1 tmp_phandle2 ++fi ++ ++if test "${param_uart2_rtscts}" = "1"; then ++ fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart2-pins phandle ++ fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart2-rts-cts-pins phandle ++ fdt set /soc/serial@1c28800 pinctrl-names "default" "default" ++ fdt set /soc/serial@1c28800 pinctrl-0 "<${tmp_phandle1}>" ++ fdt set /soc/serial@1c28800 pinctrl-1 "<${tmp_phandle2}>" ++ env delete tmp_phandle1 tmp_phandle2 ++fi ++ ++if test "${param_uart4_rtscts}" = "1"; then ++ fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart4-pins phandle ++ fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart4-rts-cts-pins phandle ++ fdt set /soc/serial@1c29000 pinctrl-names "default" "default" ++ fdt set /soc/serial@1c29000 pinctrl-0 "<${tmp_phandle1}>" ++ fdt set /soc/serial@1c29000 pinctrl-1 "<${tmp_phandle2}>" ++ env delete tmp_phandle1 tmp_phandle2 ++fi +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-i2c0.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-i2c0.dts +new file mode 100644 +index 000000000..37bdb2c2f +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-i2c0.dts +@@ -0,0 +1,32 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-a64"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ i2c0 = "/soc/i2c@1c2ac00"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&pio>; ++ __overlay__ { ++ i2c0_pins: i2c0_pins { ++ pins = "PH0", "PH1"; ++ function = "i2c0"; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&i2c0>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c0_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-i2c1.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-i2c1.dts +new file mode 100644 +index 000000000..b2483c9cd +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-i2c1.dts +@@ -0,0 +1,22 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-a64"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ i2c1 = "/soc/i2c@1c2b000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&i2c1>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c1_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-pps-gpio.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-pps-gpio.dts +new file mode 100644 +index 000000000..5fa161c47 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-pps-gpio.dts +@@ -0,0 +1,29 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-a64"; ++ ++ fragment@0 { ++ target = <&pio>; ++ __overlay__ { ++ pps_pins: pps_pins { ++ pins = "PD4"; ++ function = "gpio_in"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target-path = "/"; ++ __overlay__ { ++ pps@0 { ++ compatible = "pps-gpio"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pps_pins>; ++ gpios = <&pio 3 4 0>; /* PD4 */ ++ status = "okay"; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-spi-add-cs1.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-spi-add-cs1.dts +new file mode 100644 +index 000000000..4432aac51 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-spi-add-cs1.dts +@@ -0,0 +1,41 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-a64"; ++ ++ fragment@0 { ++ target = <&pio>; ++ __overlay__ { ++ spi0_cs1: spi0_cs1 { ++ pins = "PB6"; ++ function = "gpio_out"; ++ output-high; ++ }; ++ ++ spi1_cs1: spi1_cs1 { ++ pins = "PD6"; ++ function = "gpio_out"; ++ output-high; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&spi0>; ++ __overlay__ { ++ pinctrl-names = "default", "default"; ++ pinctrl-1 = <&spi0_cs1>; ++ cs-gpios = <0>, <&pio 1 6 0>; /* PB6 */ ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&spi1>; ++ __overlay__ { ++ pinctrl-names = "default", "default"; ++ pinctrl-1 = <&spi1_cs1>; ++ cs-gpios = <0>, <&pio 3 6 0>; /* PD6 */ ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-spi-jedec-nor.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-spi-jedec-nor.dts +new file mode 100644 +index 000000000..31d73e572 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-spi-jedec-nor.dts +@@ -0,0 +1,34 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-a64"; ++ ++ fragment@0 { ++ target = <&spi0>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spiflash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ status = "disabled"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&spi1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spiflash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ status = "disabled"; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-spi-spidev.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-spi-spidev.dts +new file mode 100644 +index 000000000..84a435b79 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-spi-spidev.dts +@@ -0,0 +1,42 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-a64"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ spi0 = "/soc/spi@1c68000"; ++ spi1 = "/soc/spi@1c69000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&spi0>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spidev@0 { ++ compatible = "armbian,spi-dev"; ++ status = "disabled"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&spi1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spidev@0 { ++ compatible = "armbian,spi-dev"; ++ status = "disabled"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-uart1.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-uart1.dts +new file mode 100644 +index 000000000..4d8dac1a5 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-uart1.dts +@@ -0,0 +1,22 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-a64"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ serial1 = "/soc/serial@1c28800"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&uart1>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-uart2.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-uart2.dts +new file mode 100644 +index 000000000..7286d7360 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-uart2.dts +@@ -0,0 +1,37 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-a64"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ serial2 = "/soc/serial@1c28800"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&pio>; ++ __overlay__ { ++ uart2_pins: uart2-pins { ++ pins = "PB0", "PB1"; ++ function = "uart2"; ++ }; ++ ++ uart2_rts_cts_pins: uart2-rts-cts-pins { ++ pins = "PB2", "PB3"; ++ function = "uart2"; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&uart2>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart2_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-uart3.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-uart3.dts +new file mode 100644 +index 000000000..c5729b9d2 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-uart3.dts +@@ -0,0 +1,32 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-a64"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ serial3 = "/soc/serial@1c28c00"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&pio>; ++ __overlay__ { ++ uart3_pins: uart3-pins { ++ pins = "PD0", "PD1"; ++ function = "uart3"; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&uart3>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart3_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-uart4.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-uart4.dts +new file mode 100644 +index 000000000..21c9b738a +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-uart4.dts +@@ -0,0 +1,37 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-a64"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ serial4 = "/soc/serial@1c29000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&pio>; ++ __overlay__ { ++ uart4_pins: uart4-pins { ++ pins = "PD2", "PD3"; ++ function = "uart4"; ++ }; ++ ++ uart4_rts_cts_pins: uart4-rts-cts-pins { ++ pins = "PD4", "PD5"; ++ function = "uart4"; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&uart4>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart4_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-w1-gpio.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-w1-gpio.dts +new file mode 100644 +index 000000000..d23046913 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-w1-gpio.dts +@@ -0,0 +1,29 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-a64"; ++ ++ fragment@0 { ++ target = <&pio>; ++ __overlay__ { ++ w1_pins: w1_pins { ++ pins = "PD4"; ++ function = "gpio_in"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target-path = "/"; ++ __overlay__ { ++ onewire@0 { ++ compatible = "w1-gpio"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&w1_pins>; ++ gpios = <&pio 3 4 0>; /* PD4 */ ++ status = "okay"; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-analog-codec.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-analog-codec.dts +new file mode 100644 +index 000000000..aaa66d5e7 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-analog-codec.dts +@@ -0,0 +1,17 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h5"; ++ ++ fragment@0 { ++ target = <&codec>; ++ __overlay__ { ++ allwinner,audio-routing = ++ "Line Out", "LINEOUT", ++ "MIC1", "Mic", ++ "Mic", "MBIAS"; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cir.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cir.dts +new file mode 100644 +index 000000000..90c264a0a +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cir.dts +@@ -0,0 +1,15 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h5"; ++ ++ fragment@0 { ++ target = <&ir>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&r_ir_rx_pin>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-fixup.scr-cmd b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-fixup.scr-cmd +new file mode 100644 +index 000000000..7abb64d84 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-fixup.scr-cmd +@@ -0,0 +1,110 @@ ++# overlays fixup script ++# implements (or rather substitutes) overlay arguments functionality ++# using u-boot scripting, environment variables and "fdt" command ++ ++# setexpr test_var ${tmp_bank} - A ++# works only for hex numbers (A-F) ++ ++setenv decompose_pin 'setexpr tmp_bank sub "P(A|C|D|G)\\d+" "\\1"; ++setexpr tmp_pin sub "P\\S(\\d+)" "\\1"; ++test "${tmp_bank}" = "A" && setenv tmp_bank 0; ++test "${tmp_bank}" = "C" && setenv tmp_bank 2; ++test "${tmp_bank}" = "D" && setenv tmp_bank 3; ++test "${tmp_bank}" = "G" && setenv tmp_bank 6' ++ ++if test -n "${param_spinor_spi_bus}"; then ++ test "${param_spinor_spi_bus}" = "0" && setenv tmp_spi_path "spi@1c68000" ++ test "${param_spinor_spi_bus}" = "1" && setenv tmp_spi_path "spi@1c69000" ++ fdt set /soc/${tmp_spi_path} status "okay" ++ fdt set /soc/${tmp_spi_path}/spiflash@0 status "okay" ++ if test -n "${param_spinor_max_freq}"; then ++ fdt set /soc/${tmp_spi_path}/spiflash@0 spi-max-frequency "<${param_spinor_max_freq}>" ++ fi ++ if test "${param_spinor_spi_cs}" = "1"; then ++ fdt set /soc/${tmp_spi_path}/spiflash@0 reg "<1>" ++ fi ++ env delete tmp_spi_path ++fi ++ ++if test -n "${param_spidev_spi_bus}"; then ++ test "${param_spidev_spi_bus}" = "0" && setenv tmp_spi_path "spi@1c68000" ++ test "${param_spidev_spi_bus}" = "1" && setenv tmp_spi_path "spi@1c69000" ++ fdt set /soc/${tmp_spi_path} status "okay" ++ fdt set /soc/${tmp_spi_path}/spidev status "okay" ++ if test -n "${param_spidev_max_freq}"; then ++ fdt set /soc/${tmp_spi_path}/spidev spi-max-frequency "<${param_spidev_max_freq}>" ++ fi ++ if test "${param_spidev_spi_cs}" = "1"; then ++ fdt set /soc/${tmp_spi_path}/spidev reg "<1>" ++ fi ++ env delete tmp_spi_path ++fi ++ ++if test -n "${param_pps_pin}"; then ++ setenv tmp_bank "${param_pps_pin}" ++ setenv tmp_pin "${param_pps_pin}" ++ run decompose_pin ++ fdt set /soc/pinctrl@1c20800/pps_pins pins "${param_pps_pin}" ++ fdt get value tmp_phandle /soc/pinctrl@1c20800 phandle ++ fdt set /pps@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>" ++ env delete tmp_pin tmp_bank tmp_phandle ++fi ++ ++if test "${param_pps_falling_edge}" = "1"; then ++ fdt set /pps@0 assert-falling-edge ++fi ++ ++for f in ${overlays}; do ++ if test "${f}" = "pwm"; then ++ setenv bootargs_new "" ++ for arg in ${bootargs}; do ++ if test "${arg}" = "console=ttyS0,115200"; then ++ echo "Warning: Disabling ttyS0 console due to enabled PWM overlay" ++ else ++ setenv bootargs_new "${bootargs_new} ${arg}" ++ fi ++ done ++ setenv bootargs "${bootargs_new}" ++ fi ++done ++ ++if test -n "${param_w1_pin}"; then ++ setenv tmp_bank "${param_w1_pin}" ++ setenv tmp_pin "${param_w1_pin}" ++ run decompose_pin ++ fdt set /soc/pinctrl@1c20800/w1_pins pins "${param_w1_pin}" ++ fdt get value tmp_phandle /soc/pinctrl@1c20800 phandle ++ fdt set /onewire@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>" ++ env delete tmp_pin tmp_bank tmp_phandle ++fi ++ ++if test "${param_w1_pin_int_pullup}" = "1"; then ++ fdt set /soc/pinctrl@1c20800/w1_pins bias-pull-up ++fi ++ ++if test "${param_uart1_rtscts}" = "1"; then ++ fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart1-pins phandle ++ fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart1-rts-cts-pins phandle ++ fdt set /soc/serial@1c28400 pinctrl-names "default" "default" ++ fdt set /soc/serial@1c28400 pinctrl-0 "<${tmp_phandle1}>" ++ fdt set /soc/serial@1c28400 pinctrl-1 "<${tmp_phandle2}>" ++ env delete tmp_phandle1 tmp_phandle2 ++fi ++ ++if test "${param_uart2_rtscts}" = "1"; then ++ fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart2-pins phandle ++ fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart2-rts-cts-pins phandle ++ fdt set /soc/serial@1c28800 pinctrl-names "default" "default" ++ fdt set /soc/serial@1c28800 pinctrl-0 "<${tmp_phandle1}>" ++ fdt set /soc/serial@1c28800 pinctrl-1 "<${tmp_phandle2}>" ++ env delete tmp_phandle1 tmp_phandle2 ++fi ++ ++if test "${param_uart3_rtscts}" = "1"; then ++ fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart3-pins phandle ++ fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart3-rts-cts-pins phandle ++ fdt set /soc/serial@1c28c00 pinctrl-names "default" "default" ++ fdt set /soc/serial@1c28c00 pinctrl-0 "<${tmp_phandle1}>" ++ fdt set /soc/serial@1c28c00 pinctrl-1 "<${tmp_phandle2}>" ++ env delete tmp_phandle1 tmp_phandle2 ++fi +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-i2c0.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-i2c0.dts +new file mode 100644 +index 000000000..87fbd7e51 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-i2c0.dts +@@ -0,0 +1,20 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h5"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ i2c0 = "/soc/i2c@1c2ac00"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&i2c0>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-i2c1.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-i2c1.dts +new file mode 100644 +index 000000000..6008b9a08 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-i2c1.dts +@@ -0,0 +1,20 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h5"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ i2c1 = "/soc/i2c@1c2b000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&i2c1>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-i2c2.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-i2c2.dts +new file mode 100644 +index 000000000..2980dbf34 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-i2c2.dts +@@ -0,0 +1,20 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h5"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ i2c2 = "/soc/i2c@1c2b400"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&i2c2>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-pps-gpio.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-pps-gpio.dts +new file mode 100644 +index 000000000..46e067562 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-pps-gpio.dts +@@ -0,0 +1,29 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h5"; ++ ++ fragment@0 { ++ target = <&pio>; ++ __overlay__ { ++ pps_pins: pps_pins { ++ pins = "PD14"; ++ function = "gpio_in"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target-path = "/"; ++ __overlay__ { ++ pps@0 { ++ compatible = "pps-gpio"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pps_pins>; ++ gpios = <&pio 3 14 0>; /* PD14 */ ++ status = "okay"; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-pwm.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-pwm.dts +new file mode 100644 +index 000000000..6d12e8420 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-pwm.dts +@@ -0,0 +1,39 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h5"; ++ ++ fragment@0 { ++ target-path = "/chosen"; ++ __overlay__ { ++ /delete-property/ stdout-path; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&uart0>; ++ __overlay__ { ++ status = "disabled"; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&pio>; ++ __overlay__ { ++ pwm0_pin: pwm0 { ++ pins = "PA5"; ++ function = "pwm0"; ++ }; ++ }; ++ }; ++ ++ fragment@3 { ++ target = <&pwm>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm0_pin>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-spdif-out.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-spdif-out.dts +new file mode 100644 +index 000000000..65bc51b02 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-spdif-out.dts +@@ -0,0 +1,38 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h5"; ++ ++ fragment@0 { ++ target = <&spdif>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spdif_tx_pin>; ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target-path = "/"; ++ __overlay__ { ++ sound { ++ compatible = "simple-audio-card"; ++ simple-audio-card,name = "On-board SPDIF"; ++ ++ simple-audio-card,cpu { ++ sound-dai = <&spdif>; ++ }; ++ ++ simple-audio-card,codec { ++ sound-dai = <&spdif_out>; ++ }; ++ }; ++ ++ spdif_out: spdif-out { ++ #sound-dai-cells = <0>; ++ compatible = "linux,spdif-dit"; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-spi-add-cs1.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-spi-add-cs1.dts +new file mode 100644 +index 000000000..8e3eab295 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-spi-add-cs1.dts +@@ -0,0 +1,41 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h5"; ++ ++ fragment@0 { ++ target = <&pio>; ++ __overlay__ { ++ spi0_cs1: spi0_cs1 { ++ pins = "PA21"; ++ function = "gpio_out"; ++ output-high; ++ }; ++ ++ spi1_cs1: spi1_cs1 { ++ pins = "PA10"; ++ function = "gpio_out"; ++ output-high; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&spi0>; ++ __overlay__ { ++ pinctrl-names = "default", "default"; ++ pinctrl-1 = <&spi0_cs1>; ++ cs-gpios = <0>, <&pio 0 21 0>; /* PA21 */ ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&spi1>; ++ __overlay__ { ++ pinctrl-names = "default", "default"; ++ pinctrl-1 = <&spi1_cs1>; ++ cs-gpios = <0>, <&pio 0 10 0>; /* PA10 */ ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-spi-jedec-nor.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-spi-jedec-nor.dts +new file mode 100644 +index 000000000..5a45808c1 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-spi-jedec-nor.dts +@@ -0,0 +1,42 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h5"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ spi0 = "/soc/spi@1c68000"; ++ spi1 = "/soc/spi@1c69000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&spi0>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spiflash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ status = "disabled"; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&spi1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spiflash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ status = "disabled"; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-spi-spidev.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-spi-spidev.dts +new file mode 100644 +index 000000000..69a14b2c6 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-spi-spidev.dts +@@ -0,0 +1,42 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h5"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ spi0 = "/soc/spi@1c68000"; ++ spi1 = "/soc/spi@1c69000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&spi0>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spidev@0 { ++ compatible = "armbian,spi-dev"; ++ status = "disabled"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&spi1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spidev@0 { ++ compatible = "armbian,spi-dev"; ++ status = "disabled"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-uart1.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-uart1.dts +new file mode 100644 +index 000000000..92e3eb4d9 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-uart1.dts +@@ -0,0 +1,22 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h5"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ serial1 = "/soc/serial@1c28400"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&uart1>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-uart2.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-uart2.dts +new file mode 100644 +index 000000000..92bee1a96 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-uart2.dts +@@ -0,0 +1,32 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h5"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ serial2 = "/soc/serial@1c28800"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&pio>; ++ __overlay__ { ++ uart2_rts_cts: uart2-rts-cts-pins { ++ pins = "PA2", "PA3"; ++ function = "uart2"; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&uart2>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart2_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-uart3.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-uart3.dts +new file mode 100644 +index 000000000..a2197f166 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-uart3.dts +@@ -0,0 +1,32 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h5"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ serial3 = "/soc/serial@1c28c00"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&pio>; ++ __overlay__ { ++ uart3_rts_cts: uart3-rts-cts-pins { ++ pins = "PA15", "PA16"; ++ function = "uart3"; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&uart3>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart3_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-usbhost0.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-usbhost0.dts +new file mode 100644 +index 000000000..c1d79c232 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-usbhost0.dts +@@ -0,0 +1,27 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h5"; ++ ++ fragment@0 { ++ target = <&ehci0>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&ohci0>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&usbphy>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-usbhost1.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-usbhost1.dts +new file mode 100644 +index 000000000..2b4f245bf +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-usbhost1.dts +@@ -0,0 +1,27 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h5"; ++ ++ fragment@0 { ++ target = <&ehci1>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&ohci1>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&usbphy>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-usbhost2.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-usbhost2.dts +new file mode 100644 +index 000000000..54800e729 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-usbhost2.dts +@@ -0,0 +1,27 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h5"; ++ ++ fragment@0 { ++ target = <&ehci2>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&ohci2>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&usbphy>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-usbhost3.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-usbhost3.dts +new file mode 100644 +index 000000000..a99524ea3 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-usbhost3.dts +@@ -0,0 +1,27 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h5"; ++ ++ fragment@0 { ++ target = <&ehci3>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&ohci3>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&usbphy>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-w1-gpio.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-w1-gpio.dts +new file mode 100644 +index 000000000..6e99626ac +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-w1-gpio.dts +@@ -0,0 +1,29 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h5"; ++ ++ fragment@0 { ++ target = <&pio>; ++ __overlay__ { ++ w1_pins: w1_pins { ++ pins = "PD14"; ++ function = "gpio_in"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target-path = "/"; ++ __overlay__ { ++ onewire@0 { ++ compatible = "w1-gpio"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&w1_pins>; ++ gpios = <&pio 3 14 0>; /* PD14 */ ++ status = "okay"; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-fixup.scr-cmd b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-fixup.scr-cmd +new file mode 100644 +index 000000000..d8e79ba45 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-fixup.scr-cmd +@@ -0,0 +1,110 @@ ++# overlays fixup script ++# implements (or rather substitutes) overlay arguments functionality ++# using u-boot scripting, environment variables and "fdt" command ++ ++# setexpr test_var ${tmp_bank} - A ++# works only for hex numbers (A-F) ++ ++setenv decompose_pin 'setexpr tmp_bank sub "P(A|C|D|G)\\d+" "\\1"; ++setexpr tmp_pin sub "P\\S(\\d+)" "\\1"; ++test "${tmp_bank}" = "A" && setenv tmp_bank 0; ++test "${tmp_bank}" = "C" && setenv tmp_bank 2; ++test "${tmp_bank}" = "D" && setenv tmp_bank 3; ++test "${tmp_bank}" = "G" && setenv tmp_bank 6' ++ ++if test -n "${param_spinor_spi_bus}"; then ++ test "${param_spinor_spi_bus}" = "0" && setenv tmp_spi_path "spi@5010000" ++ test "${param_spinor_spi_bus}" = "1" && setenv tmp_spi_path "spi@5011000" ++ fdt set /soc/${tmp_spi_path} status "okay" ++ fdt set /soc/${tmp_spi_path}/spiflash@0 status "okay" ++ if test -n "${param_spinor_max_freq}"; then ++ fdt set /soc/${tmp_spi_path}/spiflash@0 spi-max-frequency "<${param_spinor_max_freq}>" ++ fi ++ if test "${param_spinor_spi_cs}" = "1"; then ++ fdt set /soc/${tmp_spi_path}/spiflash@0 reg "<1>" ++ fi ++ env delete tmp_spi_path ++fi ++ ++if test -n "${param_spidev_spi_bus}"; then ++ test "${param_spidev_spi_bus}" = "0" && setenv tmp_spi_path "spi@5010000" ++ test "${param_spidev_spi_bus}" = "1" && setenv tmp_spi_path "spi@5011000" ++ fdt set /soc/${tmp_spi_path} status "okay" ++ fdt set /soc/${tmp_spi_path}/spidev status "okay" ++ if test -n "${param_spidev_max_freq}"; then ++ fdt set /soc/${tmp_spi_path}/spidev spi-max-frequency "<${param_spidev_max_freq}>" ++ fi ++ if test "${param_spidev_spi_cs}" = "1"; then ++ fdt set /soc/${tmp_spi_path}/spidev reg "<1>" ++ fi ++ env delete tmp_spi_path ++fi ++ ++if test -n "${param_pps_pin}"; then ++ setenv tmp_bank "${param_pps_pin}" ++ setenv tmp_pin "${param_pps_pin}" ++ run decompose_pin ++ fdt set /soc/pinctrl@300b000/pps_pins pins "${param_pps_pin}" ++ fdt get value tmp_phandle /soc/pinctrl@300b000 phandle ++ fdt set /pps@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>" ++ env delete tmp_pin tmp_bank tmp_phandle ++fi ++ ++if test "${param_pps_falling_edge}" = "1"; then ++ fdt set /pps@0 assert-falling-edge ++fi ++ ++for f in ${overlays}; do ++ if test "${f}" = "pwm"; then ++ setenv bootargs_new "" ++ for arg in ${bootargs}; do ++ if test "${arg}" = "console=ttyS0,115200"; then ++ echo "Warning: Disabling ttyS0 console due to enabled PWM overlay" ++ else ++ setenv bootargs_new "${bootargs_new} ${arg}" ++ fi ++ done ++ setenv bootargs "${bootargs_new}" ++ fi ++done ++ ++if test -n "${param_w1_pin}"; then ++ setenv tmp_bank "${param_w1_pin}" ++ setenv tmp_pin "${param_w1_pin}" ++ run decompose_pin ++ fdt set /soc/pinctrl@300b000/w1_pins pins "${param_w1_pin}" ++ fdt get value tmp_phandle /soc/pinctrl@300b000 phandle ++ fdt set /onewire@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>" ++ env delete tmp_pin tmp_bank tmp_phandle ++fi ++ ++if test "${param_w1_pin_int_pullup}" = "1"; then ++ fdt set /soc/pinctrl@300b000/w1_pins bias-pull-up ++fi ++ ++if test "${param_uart1_rtscts}" = "1"; then ++ fdt get value tmp_phandle1 /soc/pinctrl@300b000/uart1-pins phandle ++ fdt get value tmp_phandle2 /soc/pinctrl@300b000/uart1-rts-cts-pins phandle ++ fdt set /soc/serial@5000400 pinctrl-names "default" "default" ++ fdt set /soc/serial@5000400 pinctrl-0 "<${tmp_phandle1}>" ++ fdt set /soc/serial@5000400 pinctrl-1 "<${tmp_phandle2}>" ++ env delete tmp_phandle1 tmp_phandle2 ++fi ++ ++if test "${param_uart2_rtscts}" = "1"; then ++ fdt get value tmp_phandle1 /soc/pinctrl@300b000/uart2-pins phandle ++ fdt get value tmp_phandle2 /soc/pinctrl@300b000/uart2-rts-cts-pins phandle ++ fdt set /soc/serial@5000800 pinctrl-names "default" "default" ++ fdt set /soc/serial@5000800 pinctrl-0 "<${tmp_phandle1}>" ++ fdt set /soc/serial@5000800 pinctrl-1 "<${tmp_phandle2}>" ++ env delete tmp_phandle1 tmp_phandle2 ++fi ++ ++if test "${param_uart3_rtscts}" = "1"; then ++ fdt get value tmp_phandle1 /soc/pinctrl@300b000/uart3-pins phandle ++ fdt get value tmp_phandle2 /soc/pinctrl@300b000/uart3-rts-cts-pins phandle ++ fdt set /soc/serial@5000c00 pinctrl-names "default" "default" ++ fdt set /soc/serial@5000c00 pinctrl-0 "<${tmp_phandle1}>" ++ fdt set /soc/serial@5000c00 pinctrl-1 "<${tmp_phandle2}>" ++ env delete tmp_phandle1 tmp_phandle2 ++fi +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-i2c0.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-i2c0.dts +new file mode 100644 +index 000000000..7e7ee8c46 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-i2c0.dts +@@ -0,0 +1,20 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h6"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ i2c0 = "/soc/i2c@5002000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&i2c0>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-i2c1.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-i2c1.dts +new file mode 100644 +index 000000000..111769821 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-i2c1.dts +@@ -0,0 +1,20 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h6"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ i2c1 = "/soc/i2c@5002400"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&i2c1>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-i2c2.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-i2c2.dts +new file mode 100644 +index 000000000..b627529c2 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-i2c2.dts +@@ -0,0 +1,20 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h6"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ i2c2 = "/soc/i2c@5002800"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&i2c2>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-ruart.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-ruart.dts +new file mode 100644 +index 000000000..6430cb083 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-ruart.dts +@@ -0,0 +1,13 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h6"; ++ ++ fragment@0 { ++ target = <&r_uart>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-add-cs1.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-add-cs1.dts +new file mode 100644 +index 000000000..0fa060fa1 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-add-cs1.dts +@@ -0,0 +1,41 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h6"; ++ ++ fragment@0 { ++ target = <&pio>; ++ __overlay__ { ++ spi0_cs1: spi0_cs1 { ++ pins = "PA10"; ++ function = "gpio_out"; ++ output-high; ++ }; ++ ++ spi1_cs1: spi1_cs1 { ++ pins = "PA21"; ++ function = "gpio_out"; ++ output-high; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&spi0>; ++ __overlay__ { ++ pinctrl-names = "default", "default"; ++ pinctrl-1 = <&spi0_cs1>; ++ cs-gpios = <0>, <&pio 0 10 0>; /* PA10 */ ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&spi1>; ++ __overlay__ { ++ pinctrl-names = "default", "default"; ++ pinctrl-1 = <&spi1_cs1>; ++ cs-gpios = <0>, <&pio 0 21 0>; /* PA21 */ ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-jedec-nor.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-jedec-nor.dts +new file mode 100644 +index 000000000..4f81dbb99 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-jedec-nor.dts +@@ -0,0 +1,42 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h6"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ spi0 = "/soc/spi@5010000"; ++ spi1 = "/soc/spi@5011000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&spi0>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spiflash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ status = "disabled"; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&spi1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spiflash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ status = "disabled"; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-spidev.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-spidev.dts +new file mode 100644 +index 000000000..1f077ea80 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-spidev.dts +@@ -0,0 +1,42 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun8i-h3-spi"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ spi0 = "/soc/spi@5010000"; ++ spi1 = "/soc/spi@5011000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&spi0>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spidev@0 { ++ compatible = "armbian,spi-dev"; ++ status = "disabled"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&spi1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spidev@0 { ++ compatible = "armbian,spi-dev"; ++ status = "disabled"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-spidev1.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-spidev1.dts +new file mode 100644 +index 000000000..5e6b70530 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-spidev1.dts +@@ -0,0 +1,30 @@ ++// Enable the spidev interface ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun8i-h3-spi"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ /* Path to the SPI controller nodes */ ++ spi1 = "/soc/spi@5011000"; ++ }; ++ }; ++ fragment@1 { ++ target = <&spi1>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi1_pins>; ++ status = "okay"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spidev@0 { ++ compatible = "armbian,spi-dev"; ++ reg = <0x0>; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-uart1.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-uart1.dts +new file mode 100644 +index 000000000..44aa94efd +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-uart1.dts +@@ -0,0 +1,22 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h6"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ serial1 = "/soc/serial@5000400"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&uart1>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-uart2.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-uart2.dts +new file mode 100644 +index 000000000..bf9174bcd +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-uart2.dts +@@ -0,0 +1,32 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h6"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ serial2 = "/soc/serial@5000800"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&pio>; ++ __overlay__ { ++ uart2_rts_cts: uart2-rts-cts-pins { ++ pins = "PD21", "PD22"; ++ function = "uart2"; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&uart2>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart2_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-uart3.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-uart3.dts +new file mode 100644 +index 000000000..418edc14a +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-uart3.dts +@@ -0,0 +1,32 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h6"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ serial3 = "/soc/serial@5000c00"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&pio>; ++ __overlay__ { ++ uart3_rts_cts: uart3-rts-cts-pins { ++ pins = "PD25", "PD26"; ++ function = "uart3"; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&uart3>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart3_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-w1-gpio.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-w1-gpio.dts +new file mode 100644 +index 000000000..3043c8778 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-w1-gpio.dts +@@ -0,0 +1,29 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h6"; ++ ++ fragment@0 { ++ target = <&pio>; ++ __overlay__ { ++ w1_pins: w1_pins { ++ pins = "PC9"; ++ function = "gpio_in"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target-path = "/"; ++ __overlay__ { ++ onewire@0 { ++ compatible = "w1-gpio"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&w1_pins>; ++ gpios = <&pio 2 9 0>; /* PC9 */ ++ status = "okay"; ++ }; ++ }; ++ }; ++}; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-allwinner-sun50i-h6-Fix-H6-emmc.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-allwinner-sun50i-h6-Fix-H6-emmc.patch new file mode 100644 index 0000000000..5c683b9a4c --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-allwinner-sun50i-h6-Fix-H6-emmc.patch @@ -0,0 +1,26 @@ +From 5687615bc7367de46448b94afa29c4590fc009ce Mon Sep 17 00:00:00 2001 +From: Ukhellfire +Date: Fri, 25 Mar 2022 07:10:57 +0000 +Subject: [PATCH 148/153] arm64: dts/allwinner/sun50i-h6: Fix H6 emmc + +--- + arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +index ed54c2c11..6d09fa021 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +@@ -612,8 +612,7 @@ mmc1: mmc@4021000 { + }; + + mmc2: mmc@4022000 { +- compatible = "allwinner,sun50i-h6-emmc", +- "allwinner,sun50i-a64-emmc"; ++ compatible = "allwinner,sun50i-h6-emmc"; + reg = <0x04022000 0x1000>; + clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; + clock-names = "ahb", "mmc"; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-allwinner-sun50i-h616-Add-GPU-node.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-allwinner-sun50i-h616-Add-GPU-node.patch new file mode 100644 index 0000000000..9b7f00b1a4 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-allwinner-sun50i-h616-Add-GPU-node.patch @@ -0,0 +1,38 @@ +From 47783d3af85fbbd13bc02c3d830ced631e4a9d75 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Fri, 15 Oct 2021 21:07:46 +0200 +Subject: [PATCH 077/153] arm64:dts: allwinner: sun50i-h616 Add GPU node + +Signed-off-by: Jernej Skrabec +--- + arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 14 ++++++++++++++ + 1 file changed, 14 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +index 44f8ae11c..26ef79c5d 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +@@ -108,6 +108,20 @@ soc { + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x40000000>; + ++ gpu: gpu@1800000 { ++ compatible = "allwinner,sun50i-h616-mali", ++ "arm,mali-bifrost"; ++ reg = <0x1800000 0x40000>; ++ interrupts = , ++ , ++ ; ++ interrupt-names = "job", "mmu", "gpu"; ++ clocks = <&ccu CLK_GPU0>, <&ccu CLK_BUS_GPU>; ++ clock-names = "core", "bus"; ++ resets = <&ccu RST_BUS_GPU>; ++ status = "disabled"; ++ }; ++ + syscon: syscon@3000000 { + compatible = "allwinner,sun50i-h616-system-control"; + reg = <0x03000000 0x1000>; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-allwinner-sun50i-h616-Add-VPU-node.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-allwinner-sun50i-h616-Add-VPU-node.patch new file mode 100644 index 0000000000..ee490183f6 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-allwinner-sun50i-h616-Add-VPU-node.patch @@ -0,0 +1,55 @@ +From 45ab614d69593ab4cbcbca83ccefd16102749e49 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Fri, 15 Oct 2021 21:14:55 +0200 +Subject: [PATCH 079/153] arm64:dts:allwinner: sun50i-h616 Add VPU node + +Signed-off-by: Jernej Skrabec +--- + .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 24 +++++++++++++++++++ + 1 file changed, 24 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +index 26ef79c5d..944ff2747 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +@@ -122,6 +122,17 @@ gpu: gpu@1800000 { + status = "disabled"; + }; + ++ video-codec@1c0e000 { ++ compatible = "allwinner,sun50i-h616-video-engine"; ++ reg = <0x01c0e000 0x2000>; ++ clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, ++ <&ccu CLK_MBUS_VE>; ++ clock-names = "ahb", "mod", "ram"; ++ resets = <&ccu RST_BUS_VE>; ++ interrupts = ; ++ allwinner,sram = <&ve_sram 1>; ++ }; ++ + syscon: syscon@3000000 { + compatible = "allwinner,sun50i-h616-system-control"; + reg = <0x03000000 0x1000>; +@@ -136,6 +147,19 @@ sram_c: sram@28000 { + #size-cells = <1>; + ranges = <0 0x00028000 0x30000>; + }; ++ ++ sram_c1: sram@1a00000 { ++ compatible = "mmio-sram"; ++ reg = <0x01a00000 0x200000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0 0x01a00000 0x200000>; ++ ++ ve_sram: sram-section@0 { ++ compatible = "allwinner,sun50i-h616-sram-c1"; ++ reg = <0x000000 0x200000>; ++ }; ++ }; + }; + + ccu: clock@3001000 { +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-nanopi-a64-set-right-phy-mode-to-rgmii-id.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-nanopi-a64-set-right-phy-mode-to-rgmii-id.patch new file mode 100644 index 0000000000..8ffcfa6dff --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-nanopi-a64-set-right-phy-mode-to-rgmii-id.patch @@ -0,0 +1,29 @@ +From 275620c5565c5e4d692440aaca8b85483aae8127 Mon Sep 17 00:00:00 2001 +From: root +Date: Tue, 26 Jan 2021 18:17:33 +0300 +Subject: [PATCH 086/153] arm64:dts: nanopi-a64 set right phy-mode to rgmii-id + +set right phy-mode for NPI A64 to rgmii-id for working +onboard-ethernet + +Signed-off-by: root +--- + arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts +index 6239d2c43..2d65dad79 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts +@@ -80,7 +80,7 @@ &ehci1 { + &emac { + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; +- phy-mode = "rgmii"; ++ phy-mode = "rgmii-id"; + phy-handle = <&ext_rgmii_phy>; + phy-supply = <®_dcdc1>; + status = "okay"; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-overlay-sun50i-a64-pine64-7inch-lcd.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-overlay-sun50i-a64-pine64-7inch-lcd.patch new file mode 100644 index 0000000000..0711e88cc0 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-overlay-sun50i-a64-pine64-7inch-lcd.patch @@ -0,0 +1,144 @@ +From 39cdc18896fa2d819e1e825ad255adf7a47e175a Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Wed, 2 Feb 2022 20:27:02 +0300 +Subject: [PATCH 113/153] arm64:dts:overlay: sun50i-a64-pine64-7inch-lcd + +Added to orange-pi-5.9 2020-11-30 +--- + .../arm64/boot/dts/allwinner/overlay/Makefile | 1 + + .../overlay/README.sun50i-a64-overlays | 5 ++ + .../overlay/sun50i-a64-pine64-7inch-lcd.dts | 87 +++++++++++++++++++ + 3 files changed, 93 insertions(+) + create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-pine64-7inch-lcd.dts + +diff --git a/arch/arm64/boot/dts/allwinner/overlay/Makefile b/arch/arm64/boot/dts/allwinner/overlay/Makefile +index 9b6528ec2..591eef672 100644 +--- a/arch/arm64/boot/dts/allwinner/overlay/Makefile ++++ b/arch/arm64/boot/dts/allwinner/overlay/Makefile +@@ -2,6 +2,7 @@ + dtbo-$(CONFIG_ARCH_SUNXI) += \ + sun50i-a64-i2c0.dtbo \ + sun50i-a64-i2c1.dtbo \ ++ sun50i-a64-pine64-7inch-lcd.dtbo \ + sun50i-a64-pps-gpio.dtbo \ + sun50i-a64-spi-add-cs1.dtbo \ + sun50i-a64-spi-jedec-nor.dtbo \ +diff --git a/arch/arm64/boot/dts/allwinner/overlay/README.sun50i-a64-overlays b/arch/arm64/boot/dts/allwinner/overlay/README.sun50i-a64-overlays +index cd9dbc686..b684c2e3a 100644 +--- a/arch/arm64/boot/dts/allwinner/overlay/README.sun50i-a64-overlays ++++ b/arch/arm64/boot/dts/allwinner/overlay/README.sun50i-a64-overlays +@@ -20,6 +20,7 @@ on supported boards, so this controller is not supported in provided overlays + + - i2c0 + - i2c1 ++- pine64-7inch-lcd + - pps-gpio + - spi-add-cs1 + - spi-jedec-nor +@@ -44,6 +45,10 @@ Activates TWI/I2C bus 1 + + I2C1 pins (SCL, SDA): PH2, PH3 + ++### pine64-7inch-lcd ++ ++Activates the Pine64 7" LCD on pine64/pine64so boards ++ + ### pps-gpio + + Activates pulse-per-second GPIO client +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-pine64-7inch-lcd.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-pine64-7inch-lcd.dts +new file mode 100644 +index 000000000..34708103f +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-pine64-7inch-lcd.dts +@@ -0,0 +1,87 @@ ++/dts-v1/; ++/plugin/; ++ ++#include ++#include ++#include ++ ++/ { ++ compatible = "allwinner,sun50i-a64"; ++ ++ fragment@0 { ++ target = <®_ldo_io0>; ++ ++ __overlay__ { ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-ctp"; ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&i2c0>; ++ ++ __overlay__ { ++ status = "okay"; ++ ++ gt911: touchscreen@5d { ++ compatible = "goodix,gt911"; ++ reg = <0x5d>; ++ ++ interrupt-parent = <&pio>; ++ interrupts = <7 4 IRQ_TYPE_EDGE_RISING>; /* PH4 */ ++ reset-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */ ++ AVDD28-supply = <®_ldo_io0>; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&r_pwm>; ++ ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@3 { ++ target-path = "/"; ++ ++ __overlay__ { ++ backlight: backlight { ++ compatible = "pwm-backlight"; ++ pwms = <&r_pwm 0 50000 PWM_POLARITY_INVERTED>; ++ brightness-levels = <1 2 4 8 16 32 64 128 512>; ++ default-brightness-level = <8>; ++ enable-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */ ++ }; ++ }; ++ }; ++ ++ fragment@4 { ++ target = <&dsi>; ++ ++ __overlay__ { ++ vcc-dsi-supply = <®_dldo1>; ++ status = "okay"; ++ ++ panel@0 { ++ compatible = "feiyang,fy07024di26a30d"; ++ reg = <0>; ++ avdd-supply = <®_dc1sw>; ++ dvdd-supply = <®_dldo2>; ++ reset-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */ ++ backlight = <&backlight>; ++ }; ++ }; ++ }; ++ ++ fragment@5 { ++ target = <&dphy>; ++ ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++}; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-overlay-sun50i-h5-add-gpio-regulator-overclock.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-overlay-sun50i-h5-add-gpio-regulator-overclock.patch new file mode 100644 index 0000000000..c8e27aeb82 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-overlay-sun50i-h5-add-gpio-regulator-overclock.patch @@ -0,0 +1,221 @@ +From b68f17bb2badece9592e560458aaaf66138d20a8 Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Wed, 2 Feb 2022 21:01:10 +0300 +Subject: [PATCH 114/153] arm64:dts:overlay sun50i-h5 add gpio regulator + overclock + +--- + .../arm64/boot/dts/allwinner/overlay/Makefile | 4 ++ + .../sun50i-h5-cpu-clock-1.0GHz-1.1v.dts | 31 ++++++++++ + .../sun50i-h5-cpu-clock-1.2GHz-1.3v.dts | 31 ++++++++++ + .../sun50i-h5-cpu-clock-1.3GHz-1.3v.dts | 61 +++++++++++++++++++ + .../overlay/sun50i-h5-gpio-regulator-1.3v.dts | 38 ++++++++++++ + 5 files changed, 165 insertions(+) + create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cpu-clock-1.0GHz-1.1v.dts + create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cpu-clock-1.2GHz-1.3v.dts + create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cpu-clock-1.3GHz-1.3v.dts + create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-gpio-regulator-1.3v.dts + +diff --git a/arch/arm64/boot/dts/allwinner/overlay/Makefile b/arch/arm64/boot/dts/allwinner/overlay/Makefile +index 591eef672..87f5addec 100644 +--- a/arch/arm64/boot/dts/allwinner/overlay/Makefile ++++ b/arch/arm64/boot/dts/allwinner/overlay/Makefile +@@ -14,6 +14,10 @@ dtbo-$(CONFIG_ARCH_SUNXI) += \ + sun50i-a64-w1-gpio.dtbo \ + sun50i-h5-analog-codec.dtbo \ + sun50i-h5-cir.dtbo \ ++ sun50i-h5-cpu-clock-1.0GHz-1.1v.dtbo \ ++ sun50i-h5-cpu-clock-1.2GHz-1.3v.dtbo \ ++ sun50i-h5-cpu-clock-1.3GHz-1.3v.dtbo \ ++ sun50i-h5-gpio-regulator-1.3v.dtbo \ + sun50i-h5-i2c0.dtbo \ + sun50i-h5-i2c1.dtbo \ + sun50i-h5-i2c2.dtbo \ +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cpu-clock-1.0GHz-1.1v.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cpu-clock-1.0GHz-1.1v.dts +new file mode 100644 +index 000000000..674ec1dcb +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cpu-clock-1.0GHz-1.1v.dts +@@ -0,0 +1,31 @@ ++// DT overlay for CPU frequency operating points to up to 1.0GHz at a maximum CPU voltage of 1.1v ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ fragment@0 { ++ target = <&cpu_opp_table>; ++ ++ __overlay__ { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ ++ // in order to match the H5 DT cooling-maps, update the existing OP table in-place ++ // with the new voltages ++ ++ opp-960000000 { ++ opp-hz = /bits/ 64 <960000000>; ++ opp-microvolt = <1100000 1100000 1300000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ ++ opp-1008000000 { ++ opp-hz = /bits/ 64 <1008000000>; ++ opp-microvolt = <1100000 1100000 1300000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ }; ++ }; ++}; ++ +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cpu-clock-1.2GHz-1.3v.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cpu-clock-1.2GHz-1.3v.dts +new file mode 100644 +index 000000000..4fb5c81d3 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cpu-clock-1.2GHz-1.3v.dts +@@ -0,0 +1,31 @@ ++// DT overlay for CPU frequency operating points to up to 1.2GHz at a maximum CPU voltage of 1.3v ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ fragment@0 { ++ target = <&cpu_opp_table>; ++ ++ __overlay__ { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ ++ // in order to match the H5 DT cooling-maps, update the existing OP table in-place ++ // with the new voltages ++ ++ opp-1104000000 { ++ opp-hz = /bits/ 64 <1104000000>; ++ opp-microvolt = <1300000 1300000 1300000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ ++ opp-1200000000 { ++ opp-hz = /bits/ 64 <1200000000>; ++ opp-microvolt = <1300000 1300000 1300000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ }; ++ }; ++}; ++ +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cpu-clock-1.3GHz-1.3v.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cpu-clock-1.3GHz-1.3v.dts +new file mode 100644 +index 000000000..9c633973d +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cpu-clock-1.3GHz-1.3v.dts +@@ -0,0 +1,61 @@ ++// DT overlay for CPU frequency operating points to 1.3GHz at a maximum CPU voltage of 1.3v ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ fragment@0 { ++ target = <&cpu_opp_table>; ++ ++ __overlay__ { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ ++ // in order to match the H5 DT cooling-maps, update the existing OP table in-place ++ // with the new voltages ++ ++ opp-1056000000 { ++ opp-hz = /bits/ 64 <1056000000>; ++ opp-microvolt = <1300000 1300000 1300000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ ++ opp-1104000000 { ++ opp-hz = /bits/ 64 <1104000000>; ++ opp-microvolt = <1300000 1300000 1300000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ ++ opp-1152000000 { ++ opp-hz = /bits/ 64 <1152000000>; ++ opp-microvolt = <1300000 1300000 1300000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ ++ opp-1200000000 { ++ opp-hz = /bits/ 64 <1200000000>; ++ opp-microvolt = <1300000 1300000 1300000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ ++ opp-1224000000 { ++ opp-hz = /bits/ 64 <1224000000>; ++ opp-microvolt = <1300000 1300000 1300000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ ++ opp-1248000000 { ++ opp-hz = /bits/ 64 <1248000000>; ++ opp-microvolt = <1300000 1300000 1300000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ ++ opp-1296000000 { ++ opp-hz = /bits/ 64 <1296000000>; ++ opp-microvolt = <1300000 1300000 1300000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ }; ++ }; ++}; ++ +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-gpio-regulator-1.3v.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-gpio-regulator-1.3v.dts +new file mode 100644 +index 000000000..8d2755c3d +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-gpio-regulator-1.3v.dts +@@ -0,0 +1,38 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h5"; ++ ++ fragment@0 { ++ target-path = "/"; ++ ++ __overlay__ { ++ reg_vdd_cpux: gpio-regulator { ++ compatible = "regulator-gpio"; ++ regulator-name = "vdd-cpux"; ++ regulator-type = "voltage"; ++ regulator-boot-on; ++ regulator-always-on; ++ regulator-min-microvolt = <1100000>; ++ regulator-max-microvolt = <1300000>; ++ regulator-ramp-delay = <50>; /* 4ms */ ++ ++ gpios = <&r_pio 0 6 0>; /* PL6 */ ++ enable-active-high; ++ gpios-states = <0x1>; ++ states = <1100000 0x0 ++ 1300000 0x1>; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&cpu0>; ++ ++ __overlay__ { ++ cpu-supply = <®_vdd_cpux>; ++ }; ++ }; ++}; ++ +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-overlay-sun50i-h616-bigtreetech-cb1.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-overlay-sun50i-h616-bigtreetech-cb1.patch new file mode 100644 index 0000000000..11b2ce10cb --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-overlay-sun50i-h616-bigtreetech-cb1.patch @@ -0,0 +1,497 @@ +From 0480784b475fe2af7f06ce980583b8c875d2bc5a Mon Sep 17 00:00:00 2001 +From: Your Name +Date: Tue, 30 May 2023 12:04:55 +0800 +Subject: [PATCH] cb1-overlay + +--- + arch/arm64/boot/dts/allwinner/overlay/Makefile | 15 +++++++++++++-- + .../overlay/sun50i-h616-fixup.scr-cmd | 110 ++++++++++++++++++ + .../dts/allwinner/overlay/sun50i-h616-ir.dts | 13 +++ + .../allwinner/overlay/sun50i-h616-light.dts | 27 +++++ + .../allwinner/overlay/sun50i-h616-mcp2515.dts | 18 +++ + .../overlay/sun50i-h616-spi-spidev.dts | 42 +++++++ + .../overlay/sun50i-h616-spidev0_0.dts | 28 +++++ + .../overlay/sun50i-h616-spidev1_0.dts | 28 +++++ + .../overlay/sun50i-h616-spidev1_1.dts | 28 +++++ + .../overlay/sun50i-h616-spidev1_2.dts | 28 +++++ + .../overlay/sun50i-h616-tft35_spi.dts | 33 ++++++ + .../allwinner/overlay/sun50i-h616-ws2812.dts | 13 +++ + 12 files changed, 383 insertions(+), 2 deletions(-) + create mode 100755 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-fixup.scr-cmd + create mode 100755 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-ir.dts + create mode 100755 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-light.dts + create mode 100755 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-mcp2515.dts + create mode 100755 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spi-spidev.dts + create mode 100755 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spidev0_0.dts + create mode 100755 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spidev1_0.dts + create mode 100755 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spidev1_1.dts + create mode 100755 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spidev1_2.dts + create mode 100755 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-tft35_spi.dts + create mode 100755 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-ws2812.dts + +diff --git a/arch/arm64/boot/dts/allwinner/overlay/Makefile b/arch/arm64/boot/dts/allwinner/overlay/Makefile +index 7cabe8f42c5a..e19b987e3b03 100644 +--- a/arch/arm64/boot/dts/allwinner/overlay/Makefile ++++ b/arch/arm64/boot/dts/allwinner/overlay/Makefile +@@ -47,12 +47,23 @@ dtbo-$(CONFIG_ARCH_SUNXI) += \ + sun50i-h6-uart1.dtbo \ + sun50i-h6-uart2.dtbo \ + sun50i-h6-uart3.dtbo \ +- sun50i-h6-w1-gpio.dtbo ++ sun50i-h6-w1-gpio.dtbo \ ++ sun50i-h616-spi-spidev.dtbo \ ++ sun50i-h616-spidev0_0.dtbo \ ++ sun50i-h616-spidev1_0.dtbo \ ++ sun50i-h616-spidev1_1.dtbo \ ++ sun50i-h616-spidev1_2.dtbo \ ++ sun50i-h616-ir.dtbo \ ++ sun50i-h616-tft35_spi.dtbo \ ++ sun50i-h616-mcp2515.dtbo \ ++ sun50i-h616-ws2812.dtbo \ ++ sun50i-h616-light.dtbo + + scr-$(CONFIG_ARCH_SUNXI) += \ + sun50i-a64-fixup.scr \ + sun50i-h5-fixup.scr \ +- sun50i-h6-fixup.scr ++ sun50i-h6-fixup.scr \ ++ sun50i-h616-fixup.scr + + dtbotxt-$(CONFIG_ARCH_SUNXI) += \ + README.sun50i-a64-overlays \ +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-fixup.scr-cmd b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-fixup.scr-cmd +new file mode 100755 +index 000000000000..2bde77cb082d +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-fixup.scr-cmd +@@ -0,0 +1,110 @@ ++# overlays fixup script ++# implements (or rather substitutes) overlay arguments functionality ++# using u-boot scripting, environment variables and "fdt" command ++ ++# setexpr test_var ${tmp_bank} - A ++# works only for hex numbers (A-F) ++ ++setenv decompose_pin 'setexpr tmp_bank sub "P(C|G|H|I)\\d+" "\\1"; ++setexpr tmp_pin sub "P\\S(\\d+)" "\\1"; ++test "${tmp_bank}" = "C" && setenv tmp_bank 2; ++test "${tmp_bank}" = "G" && setenv tmp_bank 6' ++test "${tmp_bank}" = "H" && setenv tmp_bank 7; ++test "${tmp_bank}" = "I" && setenv tmp_bank 8; ++ ++if test -n "${param_spinor_spi_bus}"; then ++ test "${param_spinor_spi_bus}" = "0" && setenv tmp_spi_path "spi@5010000" ++ test "${param_spinor_spi_bus}" = "1" && setenv tmp_spi_path "spi@5011000" ++ fdt set /soc/${tmp_spi_path} status "okay" ++ fdt set /soc/${tmp_spi_path}/spiflash@0 status "okay" ++ if test -n "${param_spinor_max_freq}"; then ++ fdt set /soc/${tmp_spi_path}/spiflash@0 spi-max-frequency "<${param_spinor_max_freq}>" ++ fi ++ if test "${param_spinor_spi_cs}" = "1"; then ++ fdt set /soc/${tmp_spi_path}/spiflash@0 reg "<1>" ++ fi ++ env delete tmp_spi_path ++fi ++ ++if test -n "${param_spidev_spi_bus}"; then ++ test "${param_spidev_spi_bus}" = "0" && setenv tmp_spi_path "spi@5010000" ++ test "${param_spidev_spi_bus}" = "1" && setenv tmp_spi_path "spi@5011000" ++ fdt set /soc/${tmp_spi_path} status "okay" ++ fdt set /soc/${tmp_spi_path}/spidev status "okay" ++ if test -n "${param_spidev_max_freq}"; then ++ fdt set /soc/${tmp_spi_path}/spidev spi-max-frequency "<${param_spidev_max_freq}>" ++ fi ++ if test "${param_spidev_spi_cs}" = "1"; then ++ fdt set /soc/${tmp_spi_path}/spidev reg "<1>" ++ fi ++ env delete tmp_spi_path ++fi ++ ++if test -n "${param_pps_pin}"; then ++ setenv tmp_bank "${param_pps_pin}" ++ setenv tmp_pin "${param_pps_pin}" ++ run decompose_pin ++ fdt set /soc/pinctrl@300b000/pps_pins pins "${param_pps_pin}" ++ fdt get value tmp_phandle /soc/pinctrl@300b000 phandle ++ fdt set /pps@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>" ++ env delete tmp_pin tmp_bank tmp_phandle ++fi ++ ++if test "${param_pps_falling_edge}" = "1"; then ++ fdt set /pps@0 assert-falling-edge ++fi ++ ++for f in ${overlays}; do ++ if test "${f}" = "pwm34"; then ++ setenv bootargs_new "" ++ for arg in ${bootargs}; do ++ if test "${arg}" = "console=ttyS0,115200"; then ++ echo "Warning: Disabling ttyS0 console due to enabled PWM3 and PWM4 overlay" ++ else ++ setenv bootargs_new "${bootargs_new} ${arg}" ++ fi ++ done ++ setenv bootargs "${bootargs_new}" ++ fi ++done ++ ++if test -n "${param_w1_pin}"; then ++ setenv tmp_bank "${param_w1_pin}" ++ setenv tmp_pin "${param_w1_pin}" ++ run decompose_pin ++ fdt set /soc/pinctrl@300b000/w1_pins pins "${param_w1_pin}" ++ fdt get value tmp_phandle /soc/pinctrl@300b000 phandle ++ fdt set /onewire@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>" ++ env delete tmp_pin tmp_bank tmp_phandle ++fi ++ ++if test "${param_w1_pin_int_pullup}" = "1"; then ++ fdt set /soc/pinctrl@300b000/w1_pins bias-pull-up ++fi ++ ++if test "${param_uart1_rtscts}" = "1"; then ++ fdt get value tmp_phandle1 /soc/pinctrl@300b000/uart1-pins phandle ++ fdt get value tmp_phandle2 /soc/pinctrl@300b000/uart1-rts-cts-pins phandle ++ fdt set /soc/serial@5000400 pinctrl-names "default" "default" ++ fdt set /soc/serial@5000400 pinctrl-0 "<${tmp_phandle1}>" ++ fdt set /soc/serial@5000400 pinctrl-1 "<${tmp_phandle2}>" ++ env delete tmp_phandle1 tmp_phandle2 ++fi ++ ++if test "${param_uart2_rtscts}" = "1"; then ++ fdt get value tmp_phandle1 /soc/pinctrl@300b000/uart2-pins phandle ++ fdt get value tmp_phandle2 /soc/pinctrl@300b000/uart2-rts-cts-pins phandle ++ fdt set /soc/serial@5000800 pinctrl-names "default" "default" ++ fdt set /soc/serial@5000800 pinctrl-0 "<${tmp_phandle1}>" ++ fdt set /soc/serial@5000800 pinctrl-1 "<${tmp_phandle2}>" ++ env delete tmp_phandle1 tmp_phandle2 ++fi ++ ++if test "${param_uart3_rtscts}" = "1"; then ++ fdt get value tmp_phandle1 /soc/pinctrl@300b000/uart3-pins phandle ++ fdt get value tmp_phandle2 /soc/pinctrl@300b000/uart3-rts-cts-pins phandle ++ fdt set /soc/serial@5000c00 pinctrl-names "default" "default" ++ fdt set /soc/serial@5000c00 pinctrl-0 "<${tmp_phandle1}>" ++ fdt set /soc/serial@5000c00 pinctrl-1 "<${tmp_phandle2}>" ++ env delete tmp_phandle1 tmp_phandle2 ++fi +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-ir.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-ir.dts +new file mode 100755 +index 000000000000..825433add1c3 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-ir.dts +@@ -0,0 +1,13 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h616"; ++ ++ fragment@0 { ++ target = <&ir>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-light.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-light.dts +new file mode 100755 +index 000000000000..5010ea6a57b5 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-light.dts +@@ -0,0 +1,27 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h616"; ++ ++ fragment@0 { ++ target = <&i2c_gpio>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&uart0>; ++ __overlay__ { ++ status = "disabled"; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&pwm>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-mcp2515.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-mcp2515.dts +new file mode 100755 +index 000000000000..64841956e568 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-mcp2515.dts +@@ -0,0 +1,18 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ fragment@0 { ++ target = <&spi1>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&can>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spi-spidev.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spi-spidev.dts +new file mode 100755 +index 000000000000..e0ceed71965f +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spi-spidev.dts +@@ -0,0 +1,42 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h616"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ spi0 = "/soc/spi@5010000"; ++ spi1 = "/soc/spi@5011000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&spi0>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spidev@0 { ++ compatible = "rohm,dh2228fv"; ++ status = "disabled"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&spi1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spidev@0 { ++ compatible = "rohm,dh2228fv"; ++ status = "disabled"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spidev0_0.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spidev0_0.dts +new file mode 100755 +index 000000000000..a5a89707c3dd +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spidev0_0.dts +@@ -0,0 +1,28 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h616"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ spi0 = "/soc/spi@5010000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&spi0>; ++ __overlay__ { ++ status = "okay"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spidev0_0: spidev@0 { ++ compatible = "rohm,dh2228fv"; ++ status = "okay"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spidev1_0.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spidev1_0.dts +new file mode 100755 +index 000000000000..20a0486442cc +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spidev1_0.dts +@@ -0,0 +1,28 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h616"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ spi1 = "/soc/spi@5011000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&spi1>; ++ __overlay__ { ++ status = "okay"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spidev1_0: spidev@0 { ++ compatible = "rohm,dh2228fv"; ++ status = "okay"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spidev1_1.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spidev1_1.dts +new file mode 100755 +index 000000000000..a9ae45e84063 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spidev1_1.dts +@@ -0,0 +1,28 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h616"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ spi1 = "/soc/spi@5011000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&spi1>; ++ __overlay__ { ++ status = "okay"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spidev1_1: spidev@1 { ++ compatible = "rohm,dh2228fv"; ++ status = "okay"; ++ reg = <1>; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spidev1_2.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spidev1_2.dts +new file mode 100755 +index 000000000000..efe5a8949b3a +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spidev1_2.dts +@@ -0,0 +1,28 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h616"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ spi1 = "/soc/spi@5011000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&spi1>; ++ __overlay__ { ++ status = "okay"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spidev1_2: spidev@2 { ++ compatible = "rohm,dh2228fv"; ++ status = "okay"; ++ reg = <2>; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-tft35_spi.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-tft35_spi.dts +new file mode 100755 +index 000000000000..e96582bcbed5 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-tft35_spi.dts +@@ -0,0 +1,33 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ fragment@0 { ++ target = <&i2c_gpio>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&spi1>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&tft_35>; ++ __overlay__ { ++ status = "okay"; ++ spi-max-frequency = <12500000>; ++ }; ++ }; ++ ++ fragment@3 { ++ target = <&tft_tp>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-ws2812.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-ws2812.dts +new file mode 100755 +index 000000000000..4e43907cb0ce +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-ws2812.dts +@@ -0,0 +1,13 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h616"; ++ ++ fragment@0 { ++ target = <&ws2812>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++}; +-- +2.34.1 diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-a64-force-mmc0-bus-width.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-a64-force-mmc0-bus-width.patch new file mode 100644 index 0000000000..331d080a67 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-a64-force-mmc0-bus-width.patch @@ -0,0 +1,24 @@ +From 3d1dd7fa07b3e07802bc5785304f78ba444e1145 Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Fri, 28 Jan 2022 15:52:48 +0300 +Subject: [PATCH 105/153] arm64:dts: sun50i-a64 force mmc0 bus-width + +--- + arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +index 416532006..6cd8e04ab 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +@@ -568,6 +568,7 @@ mmc0: mmc@1c0f000 { + interrupts = ; + max-frequency = <150000000>; + status = "disabled"; ++ bus-width = <0x4>; + #address-cells = <1>; + #size-cells = <0>; + }; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-a64-olinuxino-1Ge16GW-Disable-clock-phase-and-.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-a64-olinuxino-1Ge16GW-Disable-clock-phase-and-.patch new file mode 100644 index 0000000000..d3fa0076ce --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-a64-olinuxino-1Ge16GW-Disable-clock-phase-and-.patch @@ -0,0 +1,28 @@ +From dc5e67efd08e5419c3e9c9d30c1cccc7b58aac85 Mon Sep 17 00:00:00 2001 +From: hehopmajieh +Date: Wed, 20 May 2020 09:25:56 +0300 +Subject: [PATCH 129/153] arm64:dts:sun50i-a64-olinuxino-1Ge16GW Disable clock + phase and hs just for test + +--- + .../arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1Ge16GW.dts | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1Ge16GW.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1Ge16GW.dts +index 100a7ce49..41c7a4ed4 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1Ge16GW.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1Ge16GW.dts +@@ -15,8 +15,8 @@ / { + + &mmc2 { + vqmmc-supply = <®_eldo1>; +- mmc-hs200-1_8v; +- allwinner,drive-data-phase = <180>; ++/* mmc-hs200-1_8v; ++ allwinner,drive-data-phase = <180>;*/ + }; + + &pio { +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-a64-olinuxino-1Ge16GW-enable-bluetooth.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-a64-olinuxino-1Ge16GW-enable-bluetooth.patch new file mode 100644 index 0000000000..83c7aae01b --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-a64-olinuxino-1Ge16GW-enable-bluetooth.patch @@ -0,0 +1,42 @@ +From 3f0f108f4d09beaa1cea05717ee012e5e02419d1 Mon Sep 17 00:00:00 2001 +From: Stefan Saraev +Date: Fri, 20 Mar 2020 17:31:49 +0200 +Subject: [PATCH 127/153] arm64:dts: sun50i-a64-olinuxino-1Ge16GW: enable + bluetooth + +--- + .../sun50i-a64-olinuxino-1Ge16GW.dts | 21 +++++++++++++++++++ + 1 file changed, 21 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1Ge16GW.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1Ge16GW.dts +index a508d77d2..100a7ce49 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1Ge16GW.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1Ge16GW.dts +@@ -18,3 +18,24 @@ &mmc2 { + mmc-hs200-1_8v; + allwinner,drive-data-phase = <180>; + }; ++ ++&pio { ++ vcc-pc-supply = <®_eldo1>; ++ uart1_cts_pins: uart1_cts_pins { ++ pins = "PG8"; ++ function = "uart1"; ++ }; ++}; ++ ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1_pins>, <&uart1_cts_pins>; ++ status = "okay"; ++ bluetooth { ++ compatible = "realtek,rtl8723bs-bt"; ++ reset-gpios = <&r_pio 0 4 GPIO_ACTIVE_LOW>; /* PL4 */ ++ device-wake-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */ ++ host-wake-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ ++ firmware-postfix = "olinuxino"; ++ }; ++}; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-a64-olinuxino-add-boards.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-a64-olinuxino-add-boards.patch new file mode 100644 index 0000000000..1c9b380368 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-a64-olinuxino-add-boards.patch @@ -0,0 +1,603 @@ +From 0687ea1c6ac23b44ce9c6faf1968c9d1537fbb28 Mon Sep 17 00:00:00 2001 +From: Mitko Gamishev +Date: Wed, 5 Feb 2020 15:03:08 +0200 +Subject: [PATCH 125/153] arm64:dts:sun50i-a64-olinuxino add boards + +--- + arch/arm64/boot/dts/allwinner/Makefile | 5 + + .../dts/allwinner/sun50i-a64-olinuxino-1G.dts | 362 ++++++++++++++++++ + .../sun50i-a64-olinuxino-1Ge16GW.dts | 20 + + .../allwinner/sun50i-a64-olinuxino-1Ge4GW.dts | 97 +++++ + .../allwinner/sun50i-a64-olinuxino-1Gs16M.dts | 31 ++ + .../allwinner/sun50i-a64-olinuxino-2Ge8G.dts | 25 ++ + 6 files changed, 540 insertions(+) + create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1G.dts + create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1Ge16GW.dts + create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1Ge4GW.dts + create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1Gs16M.dts + create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-2Ge8G.dts + +diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile +index 43870e278..ea455f120 100644 +--- a/arch/arm64/boot/dts/allwinner/Makefile ++++ b/arch/arm64/boot/dts/allwinner/Makefile +@@ -5,6 +5,11 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-nanopi-a64.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-oceanic-5205-5inmfd.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-olinuxino.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-olinuxino-emmc.dtb ++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-olinuxino-1G.dtb ++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-olinuxino-1Ge4GW.dtb ++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-olinuxino-1Ge16GW.dtb ++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-olinuxino-1Gs16M.dtb ++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-olinuxino-2Ge8G.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-orangepi-win.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-lts.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-plus.dtb sun50i-a64-pine64.dtb +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1G.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1G.dts +new file mode 100644 +index 000000000..54af704d2 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1G.dts +@@ -0,0 +1,362 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (C) 2019 OLIMEX Ltd. ++ * ++ */ ++ ++/dts-v1/; ++ ++#include "sun50i-a64.dtsi" ++ ++#include ++ ++/ { ++ model = "Olimex A64-Olinuxino-1G"; ++ compatible = "olimex,a64-olinuxino-1g", "allwinner,sun50i-a64"; ++ ++ aliases { ++ ethernet0 = &emac; ++ serial0 = &uart0; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ hdmi-connector { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi_con_in: endpoint { ++ remote-endpoint = <&hdmi_out_con>; ++ }; ++ }; ++ }; ++ ++ hdmi-sound { ++ compatible = "simple-audio-card"; ++ simple-audio-card,format = "i2s"; ++ simple-audio-card,name = "allwinner,hdmi"; ++ simple-audio-card,mclk-fs = <256>; ++ status = "okay"; ++ ++ simple-audio-card,codec { ++ sound-dai = <&hdmi>; ++ }; ++ ++ simple-audio-card,cpu { ++ sound-dai = <&i2s2>; ++ }; ++ }; ++ ++ reg_vcc_sys: vcc-sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc-sys"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ status = "okay"; ++ }; ++ ++ reg_usb1_vbus: usb1-vbus { ++ compatible = "regulator-fixed"; ++ regulator-name = "usb1-vbus"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ enable-active-high; ++ gpio = <&pio 6 9 GPIO_ACTIVE_HIGH>; /* PG9 */ ++ status = "okay"; ++ }; ++}; ++ ++&codec { ++ status = "okay"; ++}; ++ ++&codec_analog { ++ hpvcc-supply = <®_eldo1>; ++ status = "okay"; ++}; ++ ++&dai { ++ status = "okay"; ++}; ++ ++&de { ++ status = "okay"; ++}; ++ ++&ehci0 { ++ status = "okay"; ++}; ++ ++&ehci1 { ++ status = "okay"; ++}; ++ ++&emac { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&rgmii_pins>; ++ phy-mode = "rgmii"; ++ phy-handle = <&ext_rgmii_phy>; ++ phy-supply = <®_dcdc1>; ++ allwinner,tx-delay-ps = <600>; ++ status = "okay"; ++}; ++ ++&hdmi { ++ hvcc-supply = <®_dldo1>; ++ status = "okay"; ++}; ++ ++&hdmi_out { ++ hdmi_out_con: endpoint { ++ remote-endpoint = <&hdmi_con_in>; ++ }; ++}; ++ ++/* Exposed to UEXT connector */ ++&i2c1 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c1_pins>; ++ status = "disabled"; ++}; ++ ++&i2s2 { ++ status = "okay"; ++}; ++ ++&mdio { ++ ext_rgmii_phy: ethernet-phy@1 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <1>; ++ }; ++}; ++ ++&mmc0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc0_pins>; ++ vmmc-supply = <®_dcdc1>; ++ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; ++ disable-wp; ++ bus-width = <4>; ++ status = "okay"; ++}; ++ ++&ohci0 { ++ status = "okay"; ++}; ++ ++&ohci1 { ++ status = "okay"; ++}; ++ ++&r_rsb { ++ status = "okay"; ++ ++ axp803: pmic@3a3 { ++ compatible = "x-powers,axp803"; ++ reg = <0x3a3>; ++ interrupt-parent = <&r_intc>; ++ interrupts = ; ++ x-powers,drive-vbus-en; /* set N_VBUSEN as output pin */ ++ }; ++}; ++ ++#include "axp803.dtsi" ++ ++&ac_power_supply { ++ status = "okay"; ++}; ++ ++&axp_led { ++ label = "axp20x:yellow:chgled"; ++ status = "okay"; ++ x-powers,charger-mode = <0>; ++}; ++ ++&battery_power_supply { ++ status = "okay"; ++}; ++ ++®_aldo1 { ++ regulator-always-on; ++ regulator-min-microvolt = <2800000>; ++ regulator-max-microvolt = <2800000>; ++ regulator-name = "vcc-pe"; ++}; ++ ++®_aldo2 { ++ regulator-always-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-pl"; ++}; ++ ++®_aldo3 { ++ regulator-always-on; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-name = "vcc-pll-avcc"; ++}; ++ ++®_dcdc1 { ++ regulator-always-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-3v3"; ++}; ++ ++®_dcdc2 { ++ regulator-always-on; ++ regulator-min-microvolt = <1040000>; ++ regulator-max-microvolt = <1300000>; ++ regulator-name = "vdd-cpux"; ++}; ++ ++/* DCDC3 is polyphased with DCDC2 */ ++ ++/* ++ * The board uses DDR3L DRAM chips. 1.36V is the closest to the nominal ++ * 1.35V that the PMIC can drive. ++ */ ++®_dcdc5 { ++ regulator-always-on; ++ regulator-min-microvolt = <1360000>; ++ regulator-max-microvolt = <1360000>; ++ regulator-name = "vcc-ddr3"; ++}; ++ ++®_dcdc6 { ++ regulator-always-on; ++ regulator-min-microvolt = <1100000>; ++ regulator-max-microvolt = <1100000>; ++ regulator-name = "vdd-sys"; ++}; ++ ++®_dldo1 { ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-hdmi"; ++}; ++ ++®_dldo2 { ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-mipi"; ++}; ++ ++®_dldo3 { ++ regulator-min-microvolt = <2800000>; ++ regulator-max-microvolt = <2800000>; ++ regulator-name = "vcc-avdd-csi"; ++}; ++ ++®_dldo4 { ++ regulator-always-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-wifi-io"; ++}; ++ ++®_drivevbus { ++ regulator-name = "usb0-vbus"; ++ status = "okay"; ++}; ++ ++®_eldo1 { ++ regulator-always-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc-emmc"; ++}; ++ ++®_eldo2 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc-dvdd-csi"; ++}; ++ ++®_fldo1 { ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1200000>; ++ regulator-name = "vcc-1v2-hsic"; ++}; ++ ++/* ++ * The A64 chip cannot work without this regulator off, although ++ * it seems to be only driving the AR100 core. ++ * Maybe we don't still know well about CPUs domain. ++ */ ++®_fldo2 { ++ regulator-always-on; ++ regulator-min-microvolt = <1100000>; ++ regulator-max-microvolt = <1100000>; ++ regulator-name = "vdd-cpus"; ++}; ++ ++®_rtc_ldo { ++ regulator-name = "vcc-rtc"; ++}; ++ ++&simplefb_hdmi { ++ vcc-hdmi-supply = <®_dldo1>; ++}; ++ ++&sound { ++ simple-audio-card,aux-devs = <&codec_analog>; ++ simple-audio-card,widgets = "Microphone", "Microphone Jack Left", ++ "Microphone", "Microphone Jack Right", ++ "Headphone", "Headphone Jack"; ++ simple-audio-card,routing = "Left DAC", "AIF1 Slot 0 Left", ++ "Right DAC", "AIF1 Slot 0 Right", ++ "Headphone Jack", "HP", ++ "AIF1 Slot 0 Left ADC", "Left ADC", ++ "AIF1 Slot 0 Right ADC", "Right ADC", ++ "Microphone Jack Left", "MBIAS", ++ "MIC1", "Microphone Jack Left", ++ "Microphone Jack Left", "HBIAS", ++ "MIC2", "Microphone Jack Right"; ++ status = "okay"; ++}; ++ ++&spdif { ++ status = "disabled"; ++}; ++ ++/* Exposed on UEXT */ ++&spi0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi0_pins>; ++ status = "disabled"; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pb_pins>; ++ status = "okay"; ++}; ++ ++/* Exposed on UEXT */ ++&uart3 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart3_pins>; ++ status = "disabled"; ++}; ++ ++&usb_otg { ++ dr_mode = "otg"; ++ status = "okay"; ++}; ++ ++&usbphy { ++ status = "okay"; ++ usb0_id_det-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */ ++ usb0_vbus_det-gpios = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */ ++ usb0_vbus-supply = <®_drivevbus>; ++ usb1_vbus-supply = <®_usb1_vbus>; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1Ge16GW.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1Ge16GW.dts +new file mode 100644 +index 000000000..a508d77d2 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1Ge16GW.dts +@@ -0,0 +1,20 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (C) 2019 OLIMEX Ltd. ++ * ++ */ ++ ++/dts-v1/; ++ ++#include "sun50i-a64-olinuxino-1Ge4GW.dts" ++ ++/ { ++ model = "Olimex A64-Olinuxino-1Ge16GW"; ++ compatible = "olimex,a64-olinuxino-1ge16gw", "allwinner,sun50i-a64"; ++}; ++ ++&mmc2 { ++ vqmmc-supply = <®_eldo1>; ++ mmc-hs200-1_8v; ++ allwinner,drive-data-phase = <180>; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1Ge4GW.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1Ge4GW.dts +new file mode 100644 +index 000000000..c87ecc6e1 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1Ge4GW.dts +@@ -0,0 +1,97 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (C) 2019 OLIMEX Ltd. ++ * ++ */ ++ ++/dts-v1/; ++ ++#include "sun50i-a64-olinuxino-1G.dts" ++ ++/ { ++ model = "Olimex A64-Olinuxino-1Ge4GW"; ++ compatible = "olimex,a64-olinuxino-1ge4gw", "allwinner,sun50i-a64"; ++ ++ aliases { ++ ethernet1 = &rtl8723bs; ++ mmc1 = &mmc2; ++ }; ++ ++ bt-sound { ++ compatible = "simple-audio-card"; ++ simple-audio-card,format = "i2s"; ++ simple-audio-card,bitclock-inversion = <1>; ++ simple-audio-card,mclk-fs = <256>; ++ simple-audio-card,name = "RTL8723BS"; ++ simple-audio-card,cpu { ++ sound-dai = <&i2s1>; ++ }; ++ simple-audio-card,codec { ++ sound-dai = <&bt_sco>; ++ }; ++ }; ++ ++ bt_sco: bt-sco { ++ compatible = "linux,bt-sco"; ++ #sound-dai-cells = <0>; ++ status = "okay"; ++ }; ++ ++ wifi_pwrseq: wifi_pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ ++ }; ++}; ++ ++&i2s1 { ++ status = "okay"; ++}; ++ ++&mmc1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc1_pins>; ++ vmmc-supply = <®_aldo2>; ++ vqmmc-supply = <®_dldo4>; ++ mmc-pwrseq = <&wifi_pwrseq>; ++ bus-width = <4>; ++ non-removable; ++ status = "okay"; ++ ++ rtl8723bs: wifi@1 { ++ reg = <1>; ++ interrupt-parent = <&r_pio>; ++ interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* PL3 */ ++ interrupt-names = "host-wake"; ++ }; ++}; ++ ++&mmc2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc2_pins>; ++ vmmc-supply = <®_dcdc1>; ++ vqmmc-supply = <®_dcdc1>; ++ bus-width = <8>; ++ non-removable; ++ cap-mmc-hw-reset; ++ status = "okay"; ++}; ++ ++&pio { ++ uart1_cts_pins: uart1_cts_pins { ++ pins = "PG8"; ++ function = "uart1"; ++ }; ++}; ++ ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1_pins>, <&uart1_cts_pins>; ++ status = "okay"; ++ bluetooth { ++ compatible = "realtek,rtl8723bs-bt"; ++ reset-gpios = <&r_pio 0 4 GPIO_ACTIVE_LOW>; /* PL4 */ ++ device-wake-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */ ++ host-wake-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ ++ firmware-postfix = "olinuxino"; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1Gs16M.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1Gs16M.dts +new file mode 100644 +index 000000000..5b85f4d2b +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1Gs16M.dts +@@ -0,0 +1,31 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (C) 2019 OLIMEX Ltd. ++ * ++ */ ++ ++/dts-v1/; ++ ++#include "sun50i-a64-olinuxino-1G.dts" ++ ++/ { ++ model = "Olimex A64-Olinuxino-1Gs16M"; ++ compatible = "olimex,a64-olinuxino-1gs16m", "allwinner,sun50i-a64"; ++ ++ aliases { ++ spi0 = &spi0; ++ }; ++}; ++ ++&spi0 { ++ status = "okay"; ++ ++ spi-nor@0 { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ compatible = "winbond,w25q128", "jedec,spi-nor", "spi-flash"; ++ reg = <0>; ++ spi-max-frequency = <10000000>; ++ status = "okay"; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-2Ge8G.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-2Ge8G.dts +new file mode 100644 +index 000000000..3583c37d3 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-2Ge8G.dts +@@ -0,0 +1,25 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (C) 2019 OLIMEX Ltd. ++ * ++ */ ++ ++/dts-v1/; ++ ++#include "sun50i-a64-olinuxino-1G.dts" ++ ++/ { ++ model = "Olimex A64-Olinuxino-2Ge8G-IND"; ++ compatible = "olimex,a64-olinuxino-2ge8g", "allwinner,sun50i-a64"; ++}; ++ ++&mmc2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc2_pins>; ++ vmmc-supply = <®_dcdc1>; ++ vqmmc-supply = <®_dcdc1>; ++ bus-width = <8>; ++ non-removable; ++ cap-mmc-hw-reset; ++ status = "okay"; ++}; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-a64-olinuxino-emmc-enable-bluetooth.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-a64-olinuxino-emmc-enable-bluetooth.patch new file mode 100644 index 0000000000..3ef8689ffb --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-a64-olinuxino-emmc-enable-bluetooth.patch @@ -0,0 +1,39 @@ +From f4640ed124a9b8b72e1019e2f98da5b731d7dd54 Mon Sep 17 00:00:00 2001 +From: Stefan Saraev +Date: Fri, 20 Mar 2020 13:53:44 +0200 +Subject: [PATCH 126/153] arm64:dts: sun50i-a64-olinuxino-emmc: enable + bluetooth + +--- + .../dts/allwinner/sun50i-a64-olinuxino-emmc.dts | 17 +++++++++++++++++ + 1 file changed, 17 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-emmc.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-emmc.dts +index efb20846d..963b8b207 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-emmc.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-emmc.dts +@@ -22,4 +22,21 @@ &mmc2 { + + &pio { + vcc-pc-supply = <®_eldo1>; ++ uart1_cts_pins: uart1_cts_pins { ++ pins = "PG8"; ++ function = "uart1"; ++ }; ++}; ++ ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1_pins>, <&uart1_cts_pins>; ++ status = "okay"; ++ bluetooth { ++ compatible = "realtek,rtl8723bs-bt"; ++ reset-gpios = <&r_pio 0 4 GPIO_ACTIVE_LOW>; /* PL4 */ ++ device-wake-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */ ++ host-wake-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ ++ firmware-postfix = "olinuxino"; ++ }; + }; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-a64-orangepi-win-add-aliase-ethernet1.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-a64-orangepi-win-add-aliase-ethernet1.patch new file mode 100644 index 0000000000..77fd4434ed --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-a64-orangepi-win-add-aliase-ethernet1.patch @@ -0,0 +1,25 @@ +From 50fe379ded06f778d171a602775c234c5c993aa7 Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Fri, 28 Jan 2022 15:48:25 +0300 +Subject: [PATCH 104/153] arm64:dts: sun50i-a64-orangepi-win add aliase + ethernet1 + +--- + arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts +index 306ce4acf..fff7fe6dd 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts +@@ -15,6 +15,7 @@ / { + + aliases { + ethernet0 = &emac; ++ ethernet1 = &brcmf; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-a64-pine64-add-spi0.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-a64-pine64-add-spi0.patch new file mode 100644 index 0000000000..f6aa9bb7ba --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-a64-pine64-add-spi0.patch @@ -0,0 +1,49 @@ +From c2660d24a4fc09776908b689e0e550afbbf44c7e Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Tue, 25 Jan 2022 19:10:06 +0300 +Subject: [PATCH 102/153] arm64:dts: sun50i-a64-pine64 add spi0 + +--- + .../boot/dts/allwinner/sun50i-a64-pine64.dts | 29 +++++++++++++++++++ + 1 file changed, 29 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts +index cba8ae875..fc0f7975c 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts +@@ -350,3 +350,32 @@ &usb_otg { + &usbphy { + status = "okay"; + }; ++ ++&spi0 { ++ status = "okay"; ++ spi-flash@0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "jedec,spi-nor"; ++ reg = <0>; /* Chip select 0 */ ++ spi-max-frequency = <10000000>; ++ status = "disabled"; ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ partition@0 { ++ label = "uboot"; ++ reg = <0x0 0x100000>; ++ }; ++ partition@100000 { ++ label = "env"; ++ reg = <0x100000 0x100000>; ++ }; ++ partition@200000 { ++ label = "data"; ++ reg = <0x200000 0x200000>; ++ }; ++ }; ++ }; ++}; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-a64-pine64-enable-Bluetooth.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-a64-pine64-enable-Bluetooth.patch new file mode 100644 index 0000000000..76fa36ce6e --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-a64-pine64-enable-Bluetooth.patch @@ -0,0 +1,40 @@ +From 0ffec9e46c33be6ab3d4cc12a43410dad53fc0ad Mon Sep 17 00:00:00 2001 +From: Vasily Khoruzhick +Date: Wed, 31 Oct 2018 20:45:16 -0700 +Subject: [PATCH 084/153] arm64:dts: sun50i-a64-pine64 enable Bluetooth + +Pine64 has optional RTL8723BS WiFi + BT module, BT is connected to UART1 +and uses PL4 as BT reset, PL5 as device wake GPIO, PL6 as host wake GPIO +the I2C controlling signals are connected to R_I2C bus. + +Enable it in the device tree. + +Signed-off-by: Vasily Khoruzhick +--- + arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 10 +++++++++- + 1 file changed, 9 insertions(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts +index a08c97f23..cba8ae875 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts +@@ -310,7 +310,15 @@ &uart0 { + &uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; +- status = "disabled"; ++ status = "okay"; ++ ++ bluetooth { ++ compatible = "realtek,rtl8723bs-bt"; ++ reset-gpios = <&r_pio 0 4 GPIO_ACTIVE_LOW>; /* PL4 */ ++ device-wake-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */ ++ host-wake-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ ++ firmware-postfix = "pine64"; ++ }; + }; + + /* On Pi-2 connector */ +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-a64-pine64-enable-wifi-mmc1.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-a64-pine64-enable-wifi-mmc1.patch new file mode 100644 index 0000000000..fcfe9453b8 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-a64-pine64-enable-wifi-mmc1.patch @@ -0,0 +1,52 @@ +From 1be928ed96e5d396bb96c1f3cb0d56470ae0c58a Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Thu, 9 Feb 2017 00:18:56 +0800 +Subject: [PATCH 071/153] arm64:dts: sun50i-a64-pine64 enable wifi mmc1 + +The Wi-Fi modules of Pine64 is powered via DLDO4 and ELDO1 (the latter +one provides I/O voltage). + +Add device node for it. + +Signed-off-by: Icenowy Zheng +--- + .../boot/dts/allwinner/sun50i-a64-pine64.dts | 16 ++++++++++++++++ + 1 file changed, 16 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts +index 17886709b..a08c97f23 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts +@@ -35,6 +35,11 @@ hdmi_con_in: endpoint { + }; + }; + }; ++ ++ wifi_pwrseq: wifi_pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ ++ }; + }; + + &codec { +@@ -128,6 +133,17 @@ &mmc0 { + status = "okay"; + }; + ++&mmc1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc1_pins>; ++ vmmc-supply = <®_dldo4>; ++ vqmmc-supply = <®_eldo1>; ++ mmc-pwrseq = <&wifi_pwrseq>; ++ non-removable; ++ bus-width = <4>; ++ status = "okay"; ++}; ++ + &ohci0 { + status = "okay"; + }; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-a64-pinephone-wowlan.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-a64-pinephone-wowlan.patch new file mode 100644 index 0000000000..4c2cf5772d --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-a64-pinephone-wowlan.patch @@ -0,0 +1,53 @@ +From 49ebdb69e5aa1f581bec7c5752de72b19fa8ccb6 Mon Sep 17 00:00:00 2001 +From: AGM1968 +Date: Mon, 26 Jun 2023 14:29:56 +0000 +Subject: [PATCH] Temp_fix mailbox + arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi + +Signed-off-by: AGM1968 +--- + arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 7 ++++--- + 1 file changed, 4 insertions(+), 3 deletions(-) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi +index 2f73f937aaf0..c7940fd3623a 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi +@@ -42,7 +42,7 @@ bat: battery { + resistance-temp-table = <20 150>; + ocv-capacity-celsius = <20>; + ocv-capacity-table-0 = +- <4334000 100>, ++ <4334000 100>, + <4319700 99>, + <4304300 98>, + <4292200 97>, +@@ -144,7 +144,7 @@ bat: battery { + <3393500 1>, + <3256000 0>; + x-powers,ocv-capacity-table = +- <0xc0 0>, ++ <0xc0 0>, + <0xc1 1>, + <0xc2 1>, + <0xc3 2>, +@@ -191,7 +191,7 @@ ppkb_battery: keyboard-battery { + factory-internal-resistance-micro-ohms = <120000>; + ocv-capacity-celsius = <20>; + ocv-capacity-table-0 = +- <4147328 100>, ++ <4147328 100>, + <4132636 99>, + <4121720 98>, + <4110905 97>, +@@ -748,6 +748,7 @@ &mmc1 { + non-removable; + post-power-on-delay-ms = <1>; /* wifi power is always on */ + status = "okay"; ++ keep-power-in-suspend; + + rtl8723cs: wifi@1 { + reg = <1>; +-- +2.34.1 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-a64-sopine-baseboard-Add-i2s2-mmc1.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-a64-sopine-baseboard-Add-i2s2-mmc1.patch new file mode 100644 index 0000000000..c74c690ff1 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-a64-sopine-baseboard-Add-i2s2-mmc1.patch @@ -0,0 +1,44 @@ +From db200162a3596d3b38b12c46dd1c6d512b01bc34 Mon Sep 17 00:00:00 2001 +From: Vasily Khoruzhick +Date: Sun, 3 Dec 2017 11:43:08 -0800 +Subject: [PATCH 073/153] arm64:dts: sun50i-a64-sopine-baseboard Add i2s2 mmc1 + +--- + .../dts/allwinner/sun50i-a64-sopine-baseboard.dts | 14 ++++++++++++++ + 1 file changed, 14 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts +index 970d52837..ee4fd195e 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts +@@ -100,6 +100,10 @@ &i2s2 { + status = "okay"; + }; + ++&i2s2 { ++ status = "okay"; ++}; ++ + &mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; +@@ -107,6 +111,16 @@ ext_rgmii_phy: ethernet-phy@1 { + }; + }; + ++&mmc1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc1_pins>; ++ vmmc-supply = <®_dldo4>; ++ vqmmc-supply = <®_eldo1>; ++ non-removable; ++ bus-width = <4>; ++ status = "okay"; ++}; ++ + &mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-a64-sopine-baseboard-enable-Bluetooth.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-a64-sopine-baseboard-enable-Bluetooth.patch new file mode 100644 index 0000000000..f10382d39c --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-a64-sopine-baseboard-enable-Bluetooth.patch @@ -0,0 +1,45 @@ +From a2d72298960a239df7cc284ae347f1758a07c3c7 Mon Sep 17 00:00:00 2001 +From: Vasily Khoruzhick +Date: Wed, 31 Oct 2018 20:50:09 -0700 +Subject: [PATCH 085/153] arm64:dts: sun50i-a64-sopine-baseboard enable + Bluetooth + +SoPine has optional RTL8723BS WiFi + BT module, BT is connected to UART1 +and uses PL4 as BT reset, PL5 as device wake GPIO, PL6 as host wake GPIO +the I2C controlling signals are connected to R_I2C bus. + +Enable it in the device tree. + +Signed-off-by: Vasily Khoruzhick +--- + .../dts/allwinner/sun50i-a64-sopine-baseboard.dts | 14 ++++++++++++++ + 1 file changed, 14 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts +index ee4fd195e..56714cc3f 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts +@@ -197,6 +197,20 @@ &uart0 { + status = "okay"; + }; + ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; ++ status = "okay"; ++ ++ bluetooth { ++ compatible = "realtek,rtl8723bs-bt"; ++ reset-gpios = <&r_pio 0 4 GPIO_ACTIVE_LOW>; /* PL4 */ ++ device-wake-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */ ++ host-wake-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ ++ firmware-postfix = "pine64"; ++ }; ++}; ++ + /* On Pi-2 connector */ + &uart2 { + pinctrl-names = "default"; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-a64.dtsi-adjust-thermal-trip-points.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-a64.dtsi-adjust-thermal-trip-points.patch new file mode 100644 index 0000000000..4236f266f3 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-a64.dtsi-adjust-thermal-trip-points.patch @@ -0,0 +1,42 @@ +From cbf6d09b1bd690775f6c24a9742055e58be7f9bb Mon Sep 17 00:00:00 2001 +From: Stefan Saraev +Date: Mon, 6 Apr 2020 15:26:10 +0300 +Subject: [PATCH 128/153] arm64:dts:sun50i-a64.dtsi adjust thermal trip points + +default values for alert1/crit are way too high. +--- + arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +index 6cd8e04ab..e7095e514 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +@@ -244,21 +244,21 @@ map1 { + trips { + cpu_alert0: cpu_alert0 { + /* milliCelsius */ +- temperature = <75000>; ++ temperature = <70000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_alert1: cpu_alert1 { + /* milliCelsius */ +- temperature = <90000>; ++ temperature = <80000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpu_crit: cpu_crit { + /* milliCelsius */ +- temperature = <110000>; ++ temperature = <90000>; + hysteresis = <2000>; + type = "critical"; + }; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h5-add-cpu-opp-refs.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h5-add-cpu-opp-refs.patch new file mode 100644 index 0000000000..892d32e7e8 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h5-add-cpu-opp-refs.patch @@ -0,0 +1,122 @@ +From e51c780cc9461af2d2ea82449a8c5a427674e9ba Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Wed, 2 Feb 2022 20:40:02 +0300 +Subject: [PATCH 131/153] arm64:dts:sun50i-h5 add cpu opp refs + +--- + arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus.dts | 1 + + arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-k1-plus.dts | 3 ++- + arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-m1-plus2.dts | 1 + + arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-core2.dts | 1 + + arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts | 1 + + arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2-v1.1.dts | 1 + + arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts | 1 + + arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts | 1 + + 8 files changed, 9 insertions(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus.dts +index 77661006d..fa1f4e706 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus.dts +@@ -3,6 +3,7 @@ + + /dts-v1/; + #include "sun50i-h5.dtsi" ++#include "sun50i-h5-cpu-opp.dtsi" + #include + + / { +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-k1-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-k1-plus.dts +index b7045a9ef..4980076da 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-k1-plus.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-k1-plus.dts +@@ -42,6 +42,7 @@ + + /dts-v1/; + #include "sun50i-h5.dtsi" ++#include "sun50i-h5-cpu-opp.dtsi" + + #include + #include +@@ -393,4 +394,4 @@ &usbphy { + &i2s0 { + sound-dai = <&pcm5102a>; + status = "disabled"; +-}; +\ No newline at end of file ++}; +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-m1-plus2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-m1-plus2.dts +index d051382cc..2c742e0e8 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-m1-plus2.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-m1-plus2.dts +@@ -43,6 +43,7 @@ + + /dts-v1/; + #include "sun50i-h5.dtsi" ++#include "sun50i-h5-cpu-opp.dtsi" + + #include + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-core2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-core2.dts +index 57283cc16..8d1958cd5 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-core2.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-core2.dts +@@ -43,6 +43,7 @@ + + /dts-v1/; + #include "sun50i-h5.dtsi" ++#include "sun50i-h5-cpu-opp.dtsi" + + #include + #include +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts +index 4c3921ac2..49e28ed6d 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts +@@ -4,6 +4,7 @@ + + /dts-v1/; + #include "sun50i-h5.dtsi" ++#include "sun50i-h5-cpu-opp.dtsi" + + #include + #include +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2-v1.1.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2-v1.1.dts +index 06ffbbd29..be48938ee 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2-v1.1.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2-v1.1.dts +@@ -42,6 +42,7 @@ + + /dts-v1/; + #include "sun50i-h5.dtsi" ++#include "sun50i-h5-cpu-opp.dtsi" + + #include + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts +index 39331229c..ba597c9d3 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts +@@ -3,6 +3,7 @@ + + /dts-v1/; + #include "sun50i-h5.dtsi" ++#include "sun50i-h5-cpu-opp.dtsi" + + #include + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts +index 375572d2f..8b92d5e77 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts +@@ -5,6 +5,7 @@ + + /dts-v1/; + #include "sun50i-h5.dtsi" ++#include "sun50i-h5-cpu-opp.dtsi" + + #include + #include +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h5-add-termal-zones.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h5-add-termal-zones.patch new file mode 100644 index 0000000000..1097f09d44 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h5-add-termal-zones.patch @@ -0,0 +1,102 @@ +From 263bb996828c94d6dcc6bf5ef41ead641fc909d8 Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Wed, 2 Feb 2022 21:12:46 +0300 +Subject: [PATCH 132/153] arm64:dts:sun50i-h5 add termal zones + +--- + arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 66 ++++++++++++++++---- + 1 file changed, 54 insertions(+), 12 deletions(-) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi +index 62952660b..f6d970d9b 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi +@@ -207,31 +207,73 @@ ths: thermal-sensor@1c25000 { + + thermal-zones { + cpu_thermal: cpu-thermal { +- polling-delay-passive = <0>; +- polling-delay = <0>; ++ /* milliseconds */ ++ polling-delay-passive = <250>; ++ polling-delay = <1000>; + thermal-sensors = <&ths 0>; + + trips { +- cpu_hot_trip: cpu-hot { ++ cpu_warm: cpu_warm { ++ temperature = <75000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ ++ cpu_hot_pre: cpu_hot_pre { + temperature = <80000>; + hysteresis = <2000>; + type = "passive"; + }; + +- cpu_very_hot_trip: cpu-very-hot { +- temperature = <100000>; +- hysteresis = <0>; ++ cpu_hot: cpu_hot { ++ temperature = <85000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ ++ cpu_very_hot_pre: cpu_very_hot_pre { ++ temperature = <90000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ ++ cpu_very_hot: cpu_very_hot { ++ temperature = <95000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ ++ cpu_crit: cpu_crit { ++ temperature = <105000>; ++ hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { +- cpu-hot-limit { +- trip = <&cpu_hot_trip>; +- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ cpu_warm_limit_cpu { ++ trip = <&cpu_warm>; ++ cooling-device = <&cpu0 THERMAL_NO_LIMIT 2>; ++ }; ++ ++ cpu_hot_pre_limit_cpu { ++ trip = <&cpu_hot_pre>; ++ cooling-device = <&cpu0 2 3>; ++ }; ++ ++ cpu_hot_limit_cpu { ++ trip = <&cpu_hot>; ++ cooling-device = <&cpu0 3 4>; ++ }; ++ ++ cpu_very_hot_pre_limit_cpu { ++ trip = <&cpu_very_hot_pre>; ++ cooling-device = <&cpu0 5 6>; ++ }; ++ ++ cpu_very_hot_limit_cpu { ++ trip = <&cpu_very_hot>; ++ cooling-device = <&cpu0 7 THERMAL_NO_LIMIT>; + }; + }; + }; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h5-nanopi-neo2-add-regulator-led-triger.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h5-nanopi-neo2-add-regulator-led-triger.patch new file mode 100644 index 0000000000..ad02cb2a1a --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h5-nanopi-neo2-add-regulator-led-triger.patch @@ -0,0 +1,66 @@ +From 9229f14cbdfed251f4bca5647fdba69c6f61b42b Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Mon, 24 Jan 2022 19:24:24 +0300 +Subject: [PATCH 092/153] arm64:dts: sun50i-h5-nanopi-neo2 add regulator, led + triger + +--- + .../dts/allwinner/sun50i-h5-nanopi-neo2.dts | 23 ++++++++++++++++++- + 1 file changed, 22 insertions(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts +index 05486ccce..39331229c 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts +@@ -25,12 +25,13 @@ leds { + led-0 { + label = "nanopi:green:pwr"; + gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; +- default-state = "on"; ++ linux,default-trigger = "default-on"; + }; + + led-1 { + label = "nanopi:blue:status"; + gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "heartbeat"; + }; + }; + +@@ -51,6 +52,22 @@ reg_vcc3v3: vcc3v3 { + regulator-max-microvolt = <3300000>; + }; + ++ vdd_cpux: gpio-regulator { ++ compatible = "regulator-gpio"; ++ pinctrl-names = "default"; ++ regulator-name = "vdd-cpux"; ++ regulator-type = "voltage"; ++ regulator-boot-on; ++ regulator-always-on; ++ regulator-min-microvolt = <1100000>; ++ regulator-max-microvolt = <1100000>; ++ regulator-ramp-delay = <50>; /* 4ms */ ++ gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ ++ gpios-states = <0x1>; ++ states = <1100000 0x0 ++ 1100000 0x1>; ++ }; ++ + reg_usb0_vbus: usb0-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb0-vbus"; +@@ -62,6 +79,10 @@ reg_usb0_vbus: usb0-vbus { + }; + }; + ++&cpu0 { ++ cpu-supply = <&vdd_cpux>; ++}; ++ + &ehci0 { + status = "okay"; + }; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h5-nanopi-r1s-h5-add-rtl8153-suppor.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h5-nanopi-r1s-h5-add-rtl8153-suppor.patch new file mode 100644 index 0000000000..47204753b4 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h5-nanopi-r1s-h5-add-rtl8153-suppor.patch @@ -0,0 +1,41 @@ +From e7484ea6673338b10e5ebe3b28fafc782301e153 Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Tue, 27 Sep 2022 15:28:08 +0300 +Subject: [PATCH 150/153] arm64: dts: sun50i-h5-nanopi-r1s-h5: add rtl8153 + support + +--- + .../boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts | 10 +++++++++- + 1 file changed, 9 insertions(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts +index a3e040da3..78c568cab 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts +@@ -21,7 +21,8 @@ / { + + aliases { + ethernet0 = &emac; +- ethernet1 = &rtl8189etv; ++ ethernet1 = &rtl8153; ++ ethernet2 = &rtl8189etv; + serial0 = &uart0; + }; + +@@ -116,6 +117,13 @@ &cpu0 { + + &ehci1 { + status = "okay"; ++ ++ rtl8153: device@1 { ++ compatible = "usbbda,8153"; ++ reg = <1>; ++ realtek,led-data = <0x87>; ++ local-mac-address = [00 00 00 00 00 00]; ++ }; + }; + + &ehci2 { +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h5-orangepi-pc2-add-spi-flash.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h5-orangepi-pc2-add-spi-flash.patch new file mode 100644 index 0000000000..cce84e578a --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h5-orangepi-pc2-add-spi-flash.patch @@ -0,0 +1,51 @@ +From e660f69add6fa460f9b824915cb5fd980997a33c Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Mon, 24 Jan 2022 19:27:52 +0300 +Subject: [PATCH 093/153] arm64:dts: sun50i-h5-orangepi-pc2 add spi flash + +--- + .../dts/allwinner/sun50i-h5-orangepi-pc2.dts | 25 ++++++++++++++----- + 1 file changed, 19 insertions(+), 6 deletions(-) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts +index 20bcbe707..a6dc8696a 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts +@@ -182,15 +182,28 @@ &sound_hdmi { + status = "okay"; + }; + +-&spi0 { ++&spi0 { + status = "okay"; +- +- flash@0 { ++ spi-flash@0 { + #address-cells = <1>; +- #size-cells = <1>; ++ #size-cells = <0>; + compatible = "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <40000000>; ++ reg = <0>; /* Chip select 0 */ ++ spi-max-frequency = <10000000>; ++ status = "okay"; ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ partition@0 { ++ label = "uboot"; ++ reg = <0x0 0x100000>; ++ }; ++ partition@100000 { ++ label = "env"; ++ reg = <0x100000 0x100000>; ++ }; ++ }; + }; + }; + +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h5-orangepi-prime-add-regulator.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h5-orangepi-prime-add-regulator.patch new file mode 100644 index 0000000000..8209196bb7 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h5-orangepi-prime-add-regulator.patch @@ -0,0 +1,92 @@ +From 97c2daed24e3317b3dbc4f1c8fc647d42d268c85 Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Mon, 24 Jan 2022 19:34:31 +0300 +Subject: [PATCH 094/153] arm64:dts: sun50i-h5-orangepi-prime add regulator + +--- + .../allwinner/sun50i-h5-orangepi-prime.dts | 43 ++++++++++++++++--- + 1 file changed, 36 insertions(+), 7 deletions(-) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts +index 6e44f86a8..375572d2f 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts +@@ -8,11 +8,19 @@ + + #include + #include ++#include + + / { + model = "Xunlong Orange Pi Prime"; + compatible = "xunlong,orangepi-prime", "allwinner,sun50i-h5"; + ++ reg_vcc3v3: vcc3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ }; ++ + aliases { + ethernet0 = &emac; + serial0 = &uart0; +@@ -68,13 +76,6 @@ reg_gmac_3v3: gmac-3v3 { + gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; + }; + +- reg_vcc3v3: vcc3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- + reg_usb0_vbus: usb0-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb0-vbus"; +@@ -91,6 +92,10 @@ wifi_pwrseq: wifi_pwrseq { + }; + }; + ++&cpu0 { ++ cpu-supply = <®_vdd_cpux>; ++}; ++ + &codec { + allwinner,audio-routing = + "Line Out", "LINEOUT", +@@ -189,6 +194,30 @@ &ohci3 { + &sound_hdmi { + status = "okay"; + }; ++&r_i2c { ++ status = "okay"; ++ ++ reg_vdd_cpux: regulator@65 { ++ compatible = "silergy,sy8106a"; ++ reg = <0x65>; ++ regulator-name = "vdd-cpux"; ++ silergy,fixed-microvolt = <1200000>; ++ /* ++ * The datasheet uses 1.1V as the minimum value of VDD-CPUX, ++ * however both the Armbian DVFS table and the official one ++ * have operating points with voltage under 1.1V, and both ++ * DVFS table are known to work properly at the lowest ++ * operating point. ++ * ++ * Use 1.0V as the minimum voltage instead. ++ */ ++ regulator-min-microvolt = <1000000>; ++ regulator-max-microvolt = <1400000>; ++ regulator-ramp-delay = <200>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++}; + + &uart0 { + pinctrl-names = "default"; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h5-orangepi-prime-add-rtl8723cs.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h5-orangepi-prime-add-rtl8723cs.patch new file mode 100644 index 0000000000..6e13277d3e --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h5-orangepi-prime-add-rtl8723cs.patch @@ -0,0 +1,35 @@ +From 9e9848bb89025a104dd9b2faad1c5931f3adead4 Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Mon, 7 Feb 2022 19:11:07 +0300 +Subject: [PATCH 138/153] arm64:dts: sun50i-h5-orangepi-prime add rtl8723cs + +--- + arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts +index 8b92d5e77..f430acd85 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts +@@ -25,6 +25,7 @@ reg_vcc3v3: vcc3v3 { + aliases { + ethernet0 = &emac; + serial0 = &uart0; ++ ethernet1 = &rtl8723cs; + }; + + chosen { +@@ -174,6 +175,10 @@ &mmc1 { + bus-width = <4>; + non-removable; + status = "okay"; ++ ++ rtl8723cs: sdio_wifi@1 { ++ reg = <1>; ++ }; + }; + + &ohci0 { +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h5-orangepi-zero-plus-add-regulator.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h5-orangepi-zero-plus-add-regulator.patch new file mode 100644 index 0000000000..95ab70ff23 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h5-orangepi-zero-plus-add-regulator.patch @@ -0,0 +1,67 @@ +From 0ddff3861766b1b8433872b6f607ee0ffb6ef5c8 Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Mon, 24 Jan 2022 19:49:11 +0300 +Subject: [PATCH 095/153] arm64:dts: sun50i-h5-orangepi-zero-plus add regulator + +--- + .../sun50i-h5-orangepi-zero-plus.dts | 25 ++++++++++++++++++- + 1 file changed, 24 insertions(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts +index 7ec5ac850..dfa5fd2a7 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts +@@ -4,6 +4,7 @@ + + /dts-v1/; + #include "sun50i-h5.dtsi" ++#include "sun50i-h5-cpu-opp.dtsi" + + #include + #include +@@ -36,12 +37,13 @@ leds { + led-0 { + label = "orangepi:green:pwr"; + gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PA10 */ +- default-state = "on"; ++ linux,default-trigger = "default-on"; + }; + + led-1 { + label = "orangepi:red:status"; + gpios = <&pio 0 17 GPIO_ACTIVE_HIGH>; /* PA17 */ ++ linux,default-trigger = "heartbeat"; + }; + }; + +@@ -54,6 +56,27 @@ reg_gmac_3v3: gmac-3v3 { + enable-active-high; + gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */ + }; ++ ++ reg_sy8113b: gpio-regulator { ++ compatible = "regulator-gpio"; ++ regulator-name = "vdd-cpux"; ++ regulator-type = "voltage"; ++ regulator-boot-on; ++ regulator-always-on; ++ regulator-min-microvolt = <1100000>; ++ regulator-max-microvolt = <1300000>; ++ regulator-ramp-delay = <50>; /* 4ms */ ++ ++ gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ ++ enable-active-high; ++ gpios-states = <0x1>; ++ states = <1100000 0x0 ++ 1300000 0x1>; ++ }; ++}; ++ ++&cpu0 { ++ cpu-supply = <®_sy8113b>; + }; + + &ehci0 { +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h5-orangepi-zero-plus2-regulator-gpio-fix.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h5-orangepi-zero-plus2-regulator-gpio-fix.patch new file mode 100644 index 0000000000..88015c1c31 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h5-orangepi-zero-plus2-regulator-gpio-fix.patch @@ -0,0 +1,107 @@ +From 609e1ded7fdb0f4bb7c5a46ac841fb92d2f13620 Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Mon, 24 Jan 2022 19:54:04 +0300 +Subject: [PATCH 096/153] arm64:dts: sun50i-h5-orangepi-zero-plus2 + regulator-gpio fix + +--- + .../sun50i-h5-orangepi-zero-plus2.dts | 58 ++++++++++++++----- + 1 file changed, 45 insertions(+), 13 deletions(-) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts +index 3e69ebde5..999fdcd96 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts +@@ -4,6 +4,7 @@ + /dts-v1/; + + #include "sun50i-h5.dtsi" ++#include "sun50i-h5-cpu-opp.dtsi" + + #include + +@@ -30,33 +31,55 @@ hdmi_con_in: endpoint { + }; + }; + ++ reg_vcc3v3: vcc3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ }; ++ ++ wifi_pwrseq: wifi_pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ reset-gpios = <&pio 0 9 GPIO_ACTIVE_LOW>; /* PA9 */ ++ post-power-on-delay-ms = <200>; ++ }; ++ + leds { + compatible = "gpio-leds"; + + led-0 { + label = "orangepi:green:pwr"; +- gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; +- default-state = "on"; ++ gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ ++ linux,default-trigger = "default-on"; + }; + + led-1 { + label = "orangepi:red:status"; +- gpios = <&pio 0 17 GPIO_ACTIVE_HIGH>; ++ gpios = <&pio 0 17 GPIO_ACTIVE_HIGH>; /* PA17 */ ++ linux,default-trigger = "heartbeat"; + }; + }; + +- reg_vcc3v3: vcc3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; ++ reg_vdd_cpux: gpio-regulator { ++ compatible = "regulator-gpio"; ++ regulator-name = "vdd-cpux"; ++ regulator-type = "voltage"; ++ regulator-boot-on; ++ regulator-always-on; ++ regulator-min-microvolt = <1108475>; ++ regulator-max-microvolt = <1307810>; ++ regulator-ramp-delay = <50>; /* 4ms */ ++// enable-gpios = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */ ++ gpios = <&r_pio 0 6 0>; /* PL6 */ ++ enable-active-high; ++ gpios-states = <0x1>; ++ states = <1108475 0x0 ++ 1307810 0x1>; + }; ++}; + +- wifi_pwrseq: wifi_pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&pio 0 9 GPIO_ACTIVE_LOW>; /* PA9 */ +- post-power-on-delay-ms = <200>; +- }; ++&cpu0 { ++ cpu-supply = <®_vdd_cpux>; + }; + + &de { +@@ -149,3 +172,12 @@ &usb_otg { + &usbphy { + status = "okay"; + }; ++ ++&usb_otg { ++ dr_mode = "otg"; ++ status = "okay"; ++}; ++ ++&usbphy { ++ status = "okay"; ++}; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h6-Add-AC200-EPHY-related-nodes.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h6-Add-AC200-EPHY-related-nodes.patch new file mode 100644 index 0000000000..a085081bef --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h6-Add-AC200-EPHY-related-nodes.patch @@ -0,0 +1,122 @@ +From fbb61f5656e716e63aba5b04f42966656790cd4b Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sun, 12 Jan 2020 12:09:12 +0100 +Subject: [PATCH 072/153] arm64:dts: sun50i-h6: Add AC200 EPHY related nodes + +Signed-off-by: Jernej Skrabec +--- + arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 63 ++++++++++++++++++++ + 1 file changed, 63 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +index fcabca590..8118a3465 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +@@ -23,6 +23,16 @@ aliases { + mmc2 = &mmc2; + }; + ++ ac200_pwm_clk: ac200_clk { ++ compatible = "pwm-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <24000000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm1_pin>; ++ pwms = <&pwm 1 42 0>; ++ status = "disabled"; ++ }; ++ + cpus { + #address-cells = <1>; + #size-cells = <0>; +@@ -320,6 +330,10 @@ ths_calibration: thermal-sensor-calibration@14 { + reg = <0x14 0x8>; + }; + ++ ephy_calibration: ephy-calibration@2c { ++ reg = <0x2c 0x2>; ++ }; ++ + cpu_speed_grade: cpu-speed-grade@1c { + reg = <0x1c 0x4>; + }; +@@ -377,6 +391,14 @@ ext_rgmii_pins: rgmii-pins { + drive-strength = <40>; + }; + ++ /omit-if-no-ref/ ++ ext_rmii_pins: rmii_pins { ++ pins = "PA0", "PA1", "PA2", "PA3", "PA4", ++ "PA5", "PA6", "PA7", "PA8", "PA9"; ++ function = "emac"; ++ drive-strength = <40>; ++ }; ++ + hdmi_pins: hdmi-pins { + pins = "PH8", "PH9", "PH10"; + function = "hdmi"; +@@ -397,6 +419,11 @@ i2c2_pins: i2c2-pins { + function = "i2c2"; + }; + ++ i2c3_pins: i2c3-pins { ++ pins = "PB17", "PB18"; ++ function = "i2c3"; ++ }; ++ + mmc0_pins: mmc0-pins { + pins = "PF0", "PF1", "PF2", "PF3", + "PF4", "PF5"; +@@ -414,6 +441,11 @@ mmc1_pins: mmc1-pins { + bias-pull-up; + }; + ++ pwm1_pin: pwm1-pin { ++ pins = "PB19"; ++ function = "pwm1"; ++ }; ++ + mmc2_pins: mmc2-pins { + pins = "PC1", "PC4", "PC5", "PC6", + "PC7", "PC8", "PC9", "PC10", +@@ -656,6 +688,37 @@ spi1: spi@5011000 { + #size-cells = <0>; + }; + ++ i2c3: i2c@5002c00 { ++ compatible = "allwinner,sun50i-h6-i2c", ++ "allwinner,sun6i-a31-i2c"; ++ reg = <0x05002c00 0x400>; ++ interrupts = ; ++ clocks = <&ccu CLK_BUS_I2C3>; ++ resets = <&ccu RST_BUS_I2C3>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c3_pins>; ++ status = "disabled"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ ac200: mfd@10 { ++ compatible = "x-powers,ac200"; ++ reg = <0x10>; ++ interrupt-parent = <&pio>; ++ interrupts = <1 20 IRQ_TYPE_LEVEL_LOW>; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ ++ ac200_ephy: phy { ++ compatible = "x-powers,ac200-ephy"; ++ clocks = <&ac200_pwm_clk>; ++ nvmem-cells = <&ephy_calibration>; ++ nvmem-cell-names = "calibration"; ++ status = "disabled"; ++ }; ++ }; ++ }; ++ + emac: ethernet@5020000 { + compatible = "allwinner,sun50i-h6-emac", + "allwinner,sun50i-a64-emac"; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h6-Add-r_uart-uart2-3-pins.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h6-Add-r_uart-uart2-3-pins.patch new file mode 100644 index 0000000000..41909d6033 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h6-Add-r_uart-uart2-3-pins.patch @@ -0,0 +1,119 @@ +From 2330659335bd12f215a6d08a8642c3f92243bd6c Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Sun, 23 Jan 2022 20:49:27 +0300 +Subject: [PATCH 074/153] arm64:dts: sun50i-h6 Add r_uart uart2-3 pins + +--- + arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 60 ++++++++++++++++---- + 1 file changed, 50 insertions(+), 10 deletions(-) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +index 8118a3465..2c6204845 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +@@ -320,6 +320,17 @@ msgbox: mailbox@3003000 { + #mbox-cells = <1>; + }; + ++ gic: interrupt-controller@3021000 { ++ compatible = "arm,gic-400"; ++ reg = <0x03021000 0x1000>, ++ <0x03022000 0x2000>, ++ <0x03024000 0x2000>, ++ <0x03026000 0x2000>; ++ interrupts = ; ++ interrupt-controller; ++ #interrupt-cells = <3>; ++ }; ++ + sid: efuse@3006000 { + compatible = "allwinner,sun50i-h6-sid"; + reg = <0x03006000 0x400>; +@@ -383,6 +394,7 @@ pio: pinctrl@300b000 { + interrupt-controller; + #interrupt-cells = <3>; + ++ /omit-if-no-ref/ + ext_rgmii_pins: rgmii-pins { + pins = "PD0", "PD1", "PD2", "PD3", "PD4", + "PD5", "PD7", "PD8", "PD9", "PD10", +@@ -446,6 +458,7 @@ pwm1_pin: pwm1-pin { + function = "pwm1"; + }; + ++ /omit-if-no-ref/ + mmc2_pins: mmc2-pins { + pins = "PC1", "PC4", "PC5", "PC6", + "PC7", "PC8", "PC9", "PC10", +@@ -499,17 +512,26 @@ uart1_rts_cts_pins: uart1-rts-cts-pins { + pins = "PG8", "PG9"; + function = "uart1"; + }; +- }; + +- gic: interrupt-controller@3021000 { +- compatible = "arm,gic-400"; +- reg = <0x03021000 0x1000>, +- <0x03022000 0x2000>, +- <0x03024000 0x2000>, +- <0x03026000 0x2000>; +- interrupts = ; +- interrupt-controller; +- #interrupt-cells = <3>; ++ uart2_pins: uart2-pins { ++ pins = "PD19", "PD20"; ++ function = "uart2"; ++ }; ++ ++ uart2_rts_cts_pins: uart2-rts-cts-pins { ++ pins = "PD21", "PD22"; ++ function = "uart2"; ++ }; ++ ++ uart3_pins: uart3-pins { ++ pins = "PD23", "PD24"; ++ function = "uart3"; ++ }; ++ ++ uart3_rts_cts_pins: uart3-rts-cts-pins { ++ pins = "PD25", "PD26"; ++ function = "uart3"; ++ }; + }; + + iommu: iommu@30f0000 { +@@ -1027,6 +1049,19 @@ tcon_tv_out_tcon_top: endpoint@1 { + }; + }; + ++ r_uart: serial@7080000 { ++ compatible = "snps,dw-apb-uart"; ++ reg = <0x07080000 0x400>; ++ interrupts = ; ++ reg-shift = <2>; ++ reg-io-width = <4>; ++ clocks = <&r_ccu CLK_R_APB2_UART>; ++ resets = <&r_ccu RST_R_APB2_UART>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&r_uart_pins>; ++ status = "disabled"; ++ }; ++ + rtc: rtc@7000000 { + compatible = "allwinner,sun50i-h6-rtc"; + reg = <0x07000000 0x400>; +@@ -1092,6 +1127,11 @@ r_rsb_pins: r-rsb-pins { + pins = "PL0", "PL1"; + function = "s_rsb"; + }; ++ ++ r_uart_pins: r-uart-pins { ++ pins = "PL2", "PL3"; ++ function = "s_uart"; ++ }; + }; + + r_ir: ir@7040000 { +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h6-orangepi-3-add-r_uart-aliase.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h6-orangepi-3-add-r_uart-aliase.patch new file mode 100644 index 0000000000..397dbaa019 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h6-orangepi-3-add-r_uart-aliase.patch @@ -0,0 +1,24 @@ +From 26999073bbe90f85d65cbc273b0e64496618bd45 Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Wed, 2 Feb 2022 20:12:37 +0300 +Subject: [PATCH 130/153] arm64:dts: sun50i-h6-orangepi-3 add r_uart aliase + +--- + arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts +index 52b733c7e..59e9095d7 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts +@@ -15,6 +15,7 @@ / { + aliases { + serial0 = &uart0; + serial1 = &uart1; ++ serial9 = &r_uart; + ethernet0 = &emac; + }; + +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h6-orangepi-3-delete-node-spi0.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h6-orangepi-3-delete-node-spi0.patch new file mode 100644 index 0000000000..be560956e8 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h6-orangepi-3-delete-node-spi0.patch @@ -0,0 +1,25 @@ +From 7e57e8a636d2e300860752c3bab526fb0002ff5e Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Tue, 25 Jan 2022 17:06:21 +0300 +Subject: [PATCH 098/153] arm64:dts: sun50i-h6-orangepi-3 delete-node &spi0 + +--- + arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts +index ead12d861..52b733c7e 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts +@@ -347,6 +347,8 @@ &sound_hdmi { + status = "okay"; + }; + ++/delete-node/ &spi0; ++ + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ph_pins>; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h6-orangepi-add-cpu-opp-refs.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h6-orangepi-add-cpu-opp-refs.patch new file mode 100644 index 0000000000..ecd350ffe5 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h6-orangepi-add-cpu-opp-refs.patch @@ -0,0 +1,35 @@ +From 73f520243a73122d115367e115afdc29ac4c8a5e Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Wed, 2 Feb 2022 21:18:05 +0300 +Subject: [PATCH 133/153] arm64:dts: sun50i-h6-orangepi add cpu opp refs + +--- + arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi +index b019bbaae..a494b3bbf 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi +@@ -5,6 +5,7 @@ + /dts-v1/; + + #include "sun50i-h6.dtsi" ++#include "sun50i-h6-cpu-opp.dtsi" + + #include + +@@ -64,6 +65,10 @@ reg_vcc5v: vcc5v { + }; + }; + ++&cpu0 { ++ cpu-supply = <®_dcdca>; ++}; ++ + &de { + status = "okay"; + }; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h6-orangepi-enable-higher-clock-regulator-max-.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h6-orangepi-enable-higher-clock-regulator-max-.patch new file mode 100644 index 0000000000..fb30bc98e3 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h6-orangepi-enable-higher-clock-regulator-max-.patch @@ -0,0 +1,26 @@ +From 99aa5c20eeea53e0e51ccb0a453f9ca7a385bd49 Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Wed, 2 Feb 2022 21:22:57 +0300 +Subject: [PATCH 134/153] arm64:dts: sun50i-h6-orangepi enable higher clock + regulator-max-microvolt + +--- + arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi +index a494b3bbf..ee1919b80 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi +@@ -217,7 +217,7 @@ reg_cldo3: cldo3 { + reg_dcdca: dcdca { + regulator-always-on; + regulator-min-microvolt = <810000>; +- regulator-max-microvolt = <1080000>; ++ regulator-max-microvolt = <1160000>; + regulator-name = "vdd-cpu"; + }; + +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h6-orangepi-lite2-spi0-usb3phy-dwc3-enable.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h6-orangepi-lite2-spi0-usb3phy-dwc3-enable.patch new file mode 100644 index 0000000000..4c80343a0b --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h6-orangepi-lite2-spi0-usb3phy-dwc3-enable.patch @@ -0,0 +1,61 @@ +From 31caa82a78ff7546dad5c27372a499ff85b7fa78 Mon Sep 17 00:00:00 2001 +From: Igor Pecovnik +Date: Thu, 22 Jul 2021 08:56:39 +0200 +Subject: [PATCH 099/153] arm64:dts: sun50i-h6-orangepi-lite2 spi0, usb3phy, + dwc3 enable + +Signed-off-by: Igor Pecovnik +--- + .../allwinner/sun50i-h6-orangepi-lite2.dts | 26 +++++++++++++++++++ + 1 file changed, 26 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts +index fb31dcb1c..d16ef4cc0 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts +@@ -1,5 +1,6 @@ + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) + // Copyright (C) 2018 Jagan Teki ++// Copyright (C) 2021 Igor Pecovnik + + #include "sun50i-h6-orangepi.dtsi" + +@@ -11,6 +12,16 @@ aliases { + serial1 = &uart1; /* BT-UART */ + }; + ++ reg_usb_vbus: vbus { ++ compatible = "regulator-fixed"; ++ regulator-name = "usb-vbus"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ startup-delay-us = <100000>; ++ gpio = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 USB0-DRVVBUS */ ++ enable-active-high; ++ }; ++ + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rtc CLK_OSC32K_FANOUT>; +@@ -72,3 +83,18 @@ bluetooth { + max-speed = <1500000>; + }; + }; ++ ++&spi0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi0_pins>; ++ status = "disabled"; ++}; ++ ++&usb3phy { ++ phy-supply = <®_usb_vbus>; ++ status = "okay"; ++}; ++ ++&dwc3 { ++ status = "okay"; ++}; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h6-orangepi.dtsi-Rollback-r_rsb-to-r_i2c.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h6-orangepi.dtsi-Rollback-r_rsb-to-r_i2c.patch new file mode 100644 index 0000000000..4f47a17a5f --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h6-orangepi.dtsi-Rollback-r_rsb-to-r_i2c.patch @@ -0,0 +1,41 @@ +From bf74a867f2c0f63ad7c7051fb5052391b6444cf7 Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Sun, 24 Jul 2022 13:56:50 +0300 +Subject: [PATCH 152/153] arm64: dts: sun50i-h6-orangepi.dtsi: Rollback r_rsb + to r_i2c + +This fix affects two boards: +sun50i-h6-orangepi-lite2.dts +sun50i-h6-orangepi-one-plus.dts + +It also depends on the revision of the board. +If your board fails when working with this fix, just disable +it by adding (-) minus to the first position of the line +in which the patch is written in the series.conf file. +--- + arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi +index ee1919b80..15f4d7de9 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi +@@ -129,12 +129,12 @@ &r_pio { + vcc-pm-supply = <®_bldo3>; + }; + +-&r_rsb { ++&r_i2c { + status = "okay"; + +- axp805: pmic@745 { ++ axp805: pmic@36 { + compatible = "x-powers,axp805", "x-powers,axp806"; +- reg = <0x745>; ++ reg = <0x36>; + interrupt-parent = <&r_intc>; + interrupts = ; + interrupt-controller; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h6-pine-h64-add-dwc3-usb3phy.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h6-pine-h64-add-dwc3-usb3phy.patch new file mode 100644 index 0000000000..4232f58ccc --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h6-pine-h64-add-dwc3-usb3phy.patch @@ -0,0 +1,36 @@ +From 44d50a796b4611b646f18bf5a25792d4febf50b4 Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Tue, 25 Jan 2022 19:05:25 +0300 +Subject: [PATCH 101/153] arm64:dts: sun50i-h6-pine-h64 add dwc3 usb3phy + +--- + arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts +index 41d3b5d21..454d2a297 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts +@@ -89,6 +89,10 @@ reg_usb_vbus: vbus { + }; + }; + ++&dwc3 { ++ status = "okay"; ++}; ++ + &cpu0 { + cpu-supply = <®_dcdca>; + }; +@@ -378,3 +382,8 @@ &usb2phy { + usb3_vbus-supply = <®_usb_vbus>; + status = "okay"; + }; ++ ++&usb3phy { ++ phy-supply = <®_usb_vbus>; ++ status = "okay"; ++}; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h6-pine-h64-add-wifi-rtl8723cs.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h6-pine-h64-add-wifi-rtl8723cs.patch new file mode 100644 index 0000000000..fa0472552e --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h6-pine-h64-add-wifi-rtl8723cs.patch @@ -0,0 +1,81 @@ +From 7e74d4487fe647f97fa665603bd369a0e5dab361 Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Tue, 25 Jan 2022 18:41:47 +0300 +Subject: [PATCH 100/153] arm64:dts: sun50i-h6-pine-h64 add wifi rtl8723cs + +--- + .../boot/dts/allwinner/sun50i-h6-pine-h64.dts | 38 +++++++++++++++++++ + 1 file changed, 38 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts +index 341f42ae0..41d3b5d21 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts +@@ -41,6 +41,14 @@ hdmi_con_in: endpoint { + }; + }; + ++ wifi_pwrseq: wifi_pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ clocks = <&rtc 1>; ++ clock-names = "ext_clock"; ++ reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */ ++ post-power-on-delay-ms = <200>; ++ }; ++ + leds { + compatible = "gpio-leds"; + +@@ -141,6 +149,24 @@ &mmc0 { + status = "okay"; + }; + ++&mmc1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc1_pins>; ++ vmmc-supply = <®_cldo2>; ++ vqmmc-supply = <®_bldo2>; ++ mmc-pwrseq = <&wifi_pwrseq>; ++ bus-width = <4>; ++ non-removable; ++ status = "okay"; ++ ++ rtl8723cs: sdio_wifi@1 { ++ reg = <1>; ++ interrupt-parent = <&r_pio>; ++ interrupts = <1 0 IRQ_TYPE_LEVEL_LOW>; /* PM0 */ ++ interrupt-names = "host-wake"; ++ }; ++}; ++ + &mmc2 { + vmmc-supply = <®_cldo1>; + vqmmc-supply = <®_bldo2>; +@@ -234,12 +260,24 @@ reg_cldo1: cldo1 { + }; + + reg_cldo2: cldo2 { ++ /* ++ * This regulator is connected with CLDO3. ++ * Before the kernel can support synchronized ++ * enable of coupled regulators, keep them ++ * both always on as a ugly hack. ++ */ ++ regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi-1"; + }; + + reg_cldo3: cldo3 { ++ /* ++ * This regulator is connected with CLDO2. ++ * See the comments for CLDO2. ++ */ ++ regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi-2"; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h6.dtsi-add-pinctrl-pins-for-spi.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h6.dtsi-add-pinctrl-pins-for-spi.patch new file mode 100644 index 0000000000..f721889523 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h6.dtsi-add-pinctrl-pins-for-spi.patch @@ -0,0 +1,34 @@ +From 3d26d49b828b3da506e582ee26c6c0b2c5b16124 Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Fri, 28 Jan 2022 15:19:32 +0300 +Subject: [PATCH 103/153] arm64:dts: sun50i-h6.dtsi add pinctrl pins for spi + +--- + arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +index 699c8dee7..e6fd95b6f 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +@@ -690,6 +690,8 @@ spi0: spi@5010000 { + clock-names = "ahb", "mod"; + dmas = <&dma 22>, <&dma 22>; + dma-names = "rx", "tx"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi0_pins>, <&spi0_cs_pin>; + resets = <&ccu RST_BUS_SPI0>; + status = "disabled"; + #address-cells = <1>; +@@ -705,6 +707,8 @@ spi1: spi@5011000 { + clock-names = "ahb", "mod"; + dmas = <&dma 23>, <&dma 23>; + dma-names = "rx", "tx"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi1_pins>, <&spi1_cs_pin>; + resets = <&ccu RST_BUS_SPI1>; + status = "disabled"; + #address-cells = <1>; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h6.dtsi-improve-thermals.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h6.dtsi-improve-thermals.patch new file mode 100644 index 0000000000..5b645c83bd --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h6.dtsi-improve-thermals.patch @@ -0,0 +1,111 @@ +From 6c442e503238ffff25a260ca9d988a0a1682e579 Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Tue, 25 Jan 2022 17:02:30 +0300 +Subject: [PATCH 097/153] arm64:dts: sun50i-h6.dtsi improve thermals + +--- + arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 68 ++++++++++++++++---- + 1 file changed, 55 insertions(+), 13 deletions(-) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +index 2c6204845..699c8dee7 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +@@ -1,5 +1,6 @@ + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) + // Copyright (C) 2017 Icenowy Zheng ++// Copyright (C) 2020 Igor Pecovnik + + #include + #include +@@ -1191,33 +1192,74 @@ ths: thermal-sensor@5070400 { + + thermal-zones { + cpu-thermal { +- polling-delay-passive = <0>; +- polling-delay = <0>; ++ polling-delay-passive = <250>; ++ polling-delay = <1000>; + thermal-sensors = <&ths 0>; + + trips { +- cpu_alert: cpu-alert { ++ cpu_warm: cpu_warm { ++ temperature = <75000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ ++ cpu_hot_pre: cpu_hot_pre { ++ temperature = <80000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ ++ cpu_hot: cpu_hot { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + +- cpu-crit { +- temperature = <100000>; +- hysteresis = <0>; ++ cpu_very_hot_pre: cpu_very_hot_pre { ++ temperature = <90000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ ++ cpu_very_hot: cpu_very_hot { ++ temperature = <95000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ ++ cpu_crit: cpu_crit { ++ temperature = <105000>; ++ hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { +- map0 { +- trip = <&cpu_alert>; +- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ cpu_warm_limit_cpu { ++ trip = <&cpu_warm>; ++ cooling-device = <&cpu0 THERMAL_NO_LIMIT 2>; + }; +- }; ++ ++ cpu_hot_pre_limit_cpu { ++ trip = <&cpu_hot_pre>; ++ cooling-device = <&cpu0 2 3>; ++ }; ++ ++ cpu_hot_limit_cpu { ++ trip = <&cpu_hot>; ++ cooling-device = <&cpu0 3 4>; ++ }; ++ ++ cpu_very_hot_pre_limit_cpu { ++ trip = <&cpu_very_hot_pre>; ++ cooling-device = <&cpu0 5 6>; ++ }; ++ ++ cpu_very_hot_limit_cpu { ++ trip = <&cpu_very_hot>; ++ cooling-device = <&cpu0 7 THERMAL_NO_LIMIT>; ++ }; ++ }; + }; + + gpu-thermal { +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h616-bigtreetech-cb1.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h616-bigtreetech-cb1.patch new file mode 100644 index 0000000000..bfa34e26f6 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h616-bigtreetech-cb1.patch @@ -0,0 +1,453 @@ +From 7251864d480d2d59779f7eed72d5b87175727914 Mon Sep 17 00:00:00 2001 +From: Your Name +Date: Tue, 30 May 2023 10:18:55 +0800 +Subject: [PATCH] add bigtreetech-cb1 dts + +--- + arch/arm64/boot/dts/allwinner/Makefile | 2 + + .../sun50i-h616-bigtreetech-cb1-emmc.dts | 44 +++ + .../sun50i-h616-bigtreetech-cb1-sd.dts | 35 ++ + .../sun50i-h616-bigtreetech-cb1.dtsi | 327 ++++++++++++++++++ + 4 files changed, 408 insertions(+) + create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1-emmc.dts + create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1-sd.dts + create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi + +diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile +index 92a30f72fb47..8a07fb03e884 100644 +--- a/arch/arm64/boot/dts/allwinner/Makefile ++++ b/arch/arm64/boot/dts/allwinner/Makefile +@@ -51,5 +51,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6-mini.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-orangepi-zero2.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-x96-mate.dtb ++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-bigtreetech-cb1-sd.dtb ++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-bigtreetech-cb1-emmc.dtb + + subdir-y := $(dts-dirs) overlay +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1-emmc.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1-emmc.dts +new file mode 100644 +index 000000000000..f878c23f1d90 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1-emmc.dts +@@ -0,0 +1,44 @@ ++// SPDX-License-Identifier: (GPL-2.0+ or MIT) ++/* ++ * Copyright (C) 2023 Alan.Ma . ++ */ ++ ++/dts-v1/; ++ ++#include "sun50i-h616-bigtreetech-cb1.dtsi" ++ ++&mmc2 { ++ vmmc-supply = <®_dldo1>; ++ ++ no-1-8-v; ++ bus-width = <8>; ++ non-removable; ++ status = "okay"; ++}; ++ ++&ws2812 { ++ gpios = <&pio 8 15 GPIO_ACTIVE_LOW>; /* PI15 */ ++}; ++ ++&i2c_gpio { ++ gpios = <&pio 8 6 GPIO_ACTIVE_HIGH>, /* SDA PI6 */ ++ <&pio 8 4 GPIO_ACTIVE_HIGH>; /* SCL PI4 */ ++}; ++ ++&can0_pin_irq { ++ pins = "PI3"; ++}; ++ ++&can { ++ interrupts = <8 3 0x08>; /* PI3 IRQ_TYPE_LEVEL_LOW */ ++}; ++ ++&tft_35 { ++ dc-gpios = <&pio 8 15 GPIO_ACTIVE_HIGH>; /* PI15 */ ++}; ++ ++&spi1 { ++ cs-gpios = <&pio 8 5 GPIO_ACTIVE_HIGH>, /* PI5 */ ++ <&pio 8 14 GPIO_ACTIVE_HIGH>, /* PI14 */ ++ <&pio 8 7 GPIO_ACTIVE_HIGH>; /* PI7 */ ++}; +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1-sd.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1-sd.dts +new file mode 100644 +index 000000000000..e18dd854d74b +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1-sd.dts +@@ -0,0 +1,35 @@ ++// SPDX-License-Identifier: (GPL-2.0+ or MIT) ++/* ++ * Copyright (C) 2023 Alan.Ma . ++ */ ++ ++/dts-v1/; ++ ++#include "sun50i-h616-bigtreetech-cb1.dtsi" ++ ++&ws2812 { ++ gpios = <&pio 2 14 GPIO_ACTIVE_LOW>; /* PC14 */ ++}; ++ ++&i2c_gpio { ++ gpios = <&pio 2 12 GPIO_ACTIVE_HIGH>, /* SDA PC12 */ ++ <&pio 2 10 GPIO_ACTIVE_HIGH>; /* SCL PC10 */ ++}; ++ ++&can0_pin_irq { ++ pins = "PC9"; ++}; ++ ++&can { ++ interrupts = <2 9 0x08>; /* PC9 IRQ_TYPE_LEVEL_LOW */ ++}; ++ ++&tft_35 { ++ dc-gpios = <&pio 2 14 GPIO_ACTIVE_HIGH>; /* PC14 */ ++}; ++ ++&spi1 { ++ cs-gpios = <&pio 2 11 GPIO_ACTIVE_HIGH>, /* PC11 */ ++ <&pio 2 7 GPIO_ACTIVE_HIGH>, /* PC7 */ ++ <&pio 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */ ++}; +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi +new file mode 100644 +index 000000000000..c80cc830c321 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi +@@ -0,0 +1,327 @@ ++// SPDX-License-Identifier: (GPL-2.0+ or MIT) ++/* ++ * Copyright (C) 2023 Alan.Ma . ++ */ ++ ++/dts-v1/; ++ ++#include "sun50i-h616.dtsi" ++#include "sun50i-h616-cpu-opp.dtsi" ++ ++#include ++#include ++#include ++ ++/ { ++ model = "BigTreeTech CB1"; ++ compatible = "bigtreetech,cb1", "allwinner,sun50i-h616"; ++ ++ aliases { ++ ethernet0 = &emac1; ++ serial0 = &uart0; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ act_led: led-0 { ++ gpios = <&pio 7 5 GPIO_ACTIVE_LOW>; /* PH5 */ ++ linux,default-trigger = "heartbeat"; ++ }; ++ ++ gpio_1 { ++ function = "wifi_power"; ++ gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ ++ default-state = "on"; ++ }; ++ ++ gpio_2 { ++ function = "wifi_wake"; ++ gpios = <&pio 6 15 GPIO_ACTIVE_HIGH>; /* PG15 */ ++ default-state = "on"; ++ }; ++ }; ++ ++ reg_vcc5v: regulator-vcc5v { ++ /* board wide 5V supply directly from the USB-C socket */ ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc-5v"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ }; ++ ++ reg_usb1_vbus: regulator-usb1-vbus { ++ compatible = "regulator-fixed"; ++ regulator-name = "usb1-vbus"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <®_vcc5v>; ++ enable-active-high; ++ }; ++ ++ reg_vcc33_wifi: vcc33-wifi { ++ /* Always on 3.3V regulator for WiFi and BT */ ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc33-wifi"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ vin-supply = <®_vcc5v>; ++ }; ++ ++ reg_vcc_wifi_io: vcc-wifi-io { ++ /* Always on 1.8V/300mA regulator for WiFi and BT IO */ ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc-wifi-io"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ vin-supply = <®_vcc33_wifi>; ++ }; ++ ++ wifi_pwrseq: wifi-pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ clocks = <&rtc 1>; ++ clock-names = "osc32k-out"; ++ reset-gpios = <&pio 6 18 GPIO_ACTIVE_LOW>; /* PG18 */ ++ post-power-on-delay-ms = <200>; ++ }; ++ ++ ws2812: ws2812 { ++ compatible = "rgb-ws2812"; ++ pinctrl-names = "default"; ++ rgb_cnt = <2>; ++ rgb_value = <0x010000 0x010000>; ++ status = "disabled"; ++ }; ++ ++ i2c_gpio: i2c-gpio { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "i2c-gpio"; ++ status = "disabled"; ++ ++ i2c-gpio,delay-us = <3>; /* 100 kHz */ ++ ++ tft_tp: ns2009@48 { ++ compatible = "ti,tsc2007"; ++ reg = <0x48>; ++ status = "disabled"; ++ ti,x-plate-ohms = <660>; ++ ti,rt-thr = <3000>; ++ ti,fuzzx = <32>; ++ ti,fuzzy = <16>; ++ i2c,ignore-nak = <1>; ++ }; ++ ++ light: bh1750@5c { ++ compatible = "rohm,bh1750"; ++ reg = <0x5c>; ++ status = "disabled"; ++ }; ++ }; ++ ++ mcp2515_clock: mcp2515_clock { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <12000000>; ++ }; ++}; ++ ++&mmc0 { ++ vmmc-supply = <®_dldo1>; ++ broken-cd; ++ bus-width = <4>; ++ max-frequency = <50000000>; ++ status = "okay"; ++}; ++ ++&mmc1 { ++ vmmc-supply = <®_vcc33_wifi>; ++ vqmmc-supply = <®_vcc_wifi_io>; ++ mmc-pwrseq = <&wifi_pwrseq>; ++ bus-width = <4>; ++ max-frequency = <25000000>; ++ non-removable; ++ mmc-ddr-1_8v; ++ status = "okay"; ++}; ++ ++&pio { ++ can0_pin_irq: can0_pin_irq { ++ function = "irq"; ++ bias-pull-up; ++ }; ++}; ++ ++&spi1 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi1_pins>; ++ ++ can: mcp2515@0 { ++ status = "disabled"; ++ compatible = "microchip,mcp2515"; ++ reg = <0x0>; ++ clocks = <&mcp2515_clock>; ++ spi-max-frequency = <12500000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&can0_pin_irq>; ++ interrupt-parent = <&pio>; ++ vdd-supply = <®_vcc33_wifi>; ++ xceiver-supply = <®_vcc33_wifi>; ++ }; ++ ++ tft_35: st7789v@1 { ++ status = "disabled"; ++ compatible = "sitronix,st7796s"; ++ reg = <1>; ++ spi-max-frequency =<12500000>; ++ fps =<60>; ++ buswidth = <8>; ++ rotate =<0>; ++ width = <480>; ++ height = <320>; ++ bpp = <24>; ++ bgr; ++ regwidth = <8>; ++ debug = <0x00>; //0x20 show fps ++ txbuflen = <307200>; ++ spi-cpol; ++ spi-cpha; ++ }; ++}; ++ ++&r_i2c { ++ status = "okay"; ++ ++ axp313a: pmic@36 { ++ compatible = "x-powers,axp313a"; ++ reg = <0x36>; ++ wakeup-source; ++ ++ regulators{ ++ reg_dcdc1: dcdc1 { ++ regulator-name = "axp313a-dcdc1"; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ regulator-step-delay-us = <25>; ++ regulator-final-delay-us = <50>; ++ regulator-always-on; ++ }; ++ ++ reg_dcdc2: dcdc2 { ++ regulator-name = "axp313a-dcdc2"; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1540000>; ++ regulator-step-delay-us = <25>; ++ regulator-final-delay-us = <50>; ++ regulator-ramp-delay = <200>; ++ regulator-always-on; ++ }; ++ ++ reg_dcdc3: dcdc3 { ++ regulator-name = "axp313a-dcdc3"; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1840000>; ++ regulator-step-delay-us = <25>; ++ regulator-final-delay-us = <50>; ++ regulator-always-on; ++ }; ++ ++ reg_aldo1: ldo1 { ++ regulator-name = "axp313a-aldo1"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-step-delay-us = <25>; ++ regulator-final-delay-us = <50>; ++ regulator-always-on; ++ }; ++ ++ reg_dldo1: ldo2 { ++ regulator-name = "axp313a-dldo1"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-step-delay-us = <25>; ++ regulator-final-delay-us = <50>; ++ regulator-always-on; ++ }; ++ }; ++ }; ++}; ++ ++&cpu0 { ++ cpu-supply = <®_dcdc2>; ++ status = "okay"; ++}; ++ ++&gpu { ++ mali-supply = <®_dcdc3>; ++ status = "okay"; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_ph_pins>; ++ status = "okay"; ++}; ++ ++&usbphy { ++ usb1_vbus-supply = <®_usb1_vbus>; ++ status = "okay"; ++}; ++ ++&ehci0 { ++ status = "okay"; ++}; ++ ++&ohci0 { ++ status = "okay"; ++}; ++ ++&ehci1 { ++ status = "okay"; ++}; ++ ++&ohci1 { ++ status = "okay"; ++}; ++ ++&ehci2 { ++ status = "okay"; ++}; ++ ++&ohci2 { ++ status = "okay"; ++}; ++ ++&ehci3 { ++ status = "okay"; ++}; ++ ++&ohci3 { ++ status = "okay"; ++}; ++ ++&usbotg { ++ /* ++ * PHY0 pins are connected to a USB-C socket, but a role switch ++ * is not implemented: both CC pins are pulled to GND. ++ * The VBUS pins power the device, so a fixed peripheral mode ++ * is the best choice. ++ * The board can be powered via GPIOs, in this case port0 *can* ++ * act as a host (with a cable/adapter ignoring CC), as VBUS is ++ * then provided by the GPIOs. Any user of this setup would ++ * need to adjust the DT accordingly: dr_mode set to "host", ++ * enabling OHCI0 and EHCI0. ++ */ ++ dr_mode = "peripheral"; ++ status = "okay"; ++}; +-- +2.34.1 diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h616-orangepi-zero2-Enable-GPU-mali.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h616-orangepi-zero2-Enable-GPU-mali.patch new file mode 100644 index 0000000000..47dbf4bd7e --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h616-orangepi-zero2-Enable-GPU-mali.patch @@ -0,0 +1,29 @@ +From 93bc8c9c2c8bbff21471c06b6420e6e0793dd7da Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Fri, 15 Oct 2021 21:09:42 +0200 +Subject: [PATCH 078/153] arm64:dts: sun50i-h616-orangepi-zero2 Enable GPU mali + +Signed-off-by: Jernej Skrabec +--- + arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts +index f3847aea2..0a24b8571 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts +@@ -66,6 +66,11 @@ &ehci1 { + status = "okay"; + }; + ++&gpu { ++ mali-supply = <®_dcdcc>; ++ status = "okay"; ++}; ++ + /* USB 2 & 3 are on headers only. */ + + &emac0 { +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h616-orangepi-zero2-reg_usb1_vbus-status-ok.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h616-orangepi-zero2-reg_usb1_vbus-status-ok.patch new file mode 100644 index 0000000000..db228e57c7 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h616-orangepi-zero2-reg_usb1_vbus-status-ok.patch @@ -0,0 +1,25 @@ +From 143e6e22f5186f6762e29a43023e0bcae8f1ea9e Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Wed, 14 Dec 2022 20:15:41 +0300 +Subject: [PATCH 076/153] arm64: dts: sun50i-h616-orangepi-zero2: reg_usb1_vbus + status ok + +--- + arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts +index cb8600d0e..f3847aea2 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts +@@ -58,6 +58,7 @@ reg_usb1_vbus: regulator-usb1-vbus { + vin-supply = <®_vcc5v>; + enable-active-high; + gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */ ++ status = "okay"; + }; + }; + +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h616-x96-mate-T95-eth-sd-card-hack.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h616-x96-mate-T95-eth-sd-card-hack.patch new file mode 100644 index 0000000000..0d4fbc81ff --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h616-x96-mate-T95-eth-sd-card-hack.patch @@ -0,0 +1,104 @@ +From 668d61ecb2ec13cc6a5583fa47047012fdbefd47 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Mon, 14 Jun 2021 20:48:15 +0200 +Subject: [PATCH 080/153] arm64:dts: sun50i-h616-x96-mate T95 eth & sd card + hack + +Signed-off-by: Jernej Skrabec +--- + .../dts/allwinner/sun50i-h616-x96-mate.dts | 21 ++++++++++++++- + .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 26 +++++++++++++++++++ + 2 files changed, 46 insertions(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts +index 07424c28b..31c8bf0e1 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts +@@ -15,6 +15,7 @@ / { + compatible = "hechuang,x96-mate", "allwinner,sun50i-h616"; + + aliases { ++ ethernet0 = &emac1; + serial0 = &uart0; + }; + +@@ -40,13 +41,31 @@ &ehci2 { + status = "okay"; + }; + ++&emac1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&rmii_pins>; ++ phy-mode = "rmii"; ++ phy-handle = <&rmii_phy>; ++ phy-supply = <®_aldo1>; ++ allwinner,rx-delay-ps = <3100>; ++ allwinner,tx-delay-ps = <700>; ++ status = "okay"; ++}; ++ + &ir { + status = "okay"; + }; + ++&mdio1 { ++ rmii_phy: ethernet-phy@1 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <1>; ++ }; ++}; ++ + &mmc0 { + vmmc-supply = <®_dcdce>; +- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ ++ broken-cd; + bus-width = <4>; + status = "okay"; + }; +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +index 944ff2747..45359b0d3 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +@@ -247,6 +247,13 @@ mmc2_pins: mmc2-pins { + bias-pull-up; + }; + ++ rmii_pins: rmii-pins { ++ pins = "PA0", "PA1", "PA2", "PA3", "PA4", ++ "PA5", "PA6", "PA7", "PA8", "PA9"; ++ function = "emac1"; ++ drive-strength = <40>; ++ }; ++ + /omit-if-no-ref/ + spi0_pins: spi0-pins { + pins = "PC0", "PC2", "PC4"; +@@ -546,6 +553,25 @@ mdio0: mdio { + }; + }; + ++ emac1: ethernet@5030000 { ++ compatible = "allwinner,sun50i-h616-emac"; ++ syscon = <&syscon 1>; ++ reg = <0x05030000 0x10000>; ++ interrupts = ; ++ interrupt-names = "macirq"; ++ resets = <&ccu RST_BUS_EMAC1>; ++ reset-names = "stmmaceth"; ++ clocks = <&ccu CLK_BUS_EMAC1>; ++ clock-names = "stmmaceth"; ++ status = "disabled"; ++ ++ mdio1: mdio { ++ compatible = "snps,dwmac-mdio"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ }; ++ + usbotg: usb@5100000 { + compatible = "allwinner,sun50i-h616-musb", + "allwinner,sun8i-h3-musb"; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h616-x96-mate-add-hdmi.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h616-x96-mate-add-hdmi.patch new file mode 100644 index 0000000000..0432f654b4 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/arm64-dts-sun50i-h616-x96-mate-add-hdmi.patch @@ -0,0 +1,64 @@ +From e0c20e44cf3b26ebb5646f3a69f3a6774780d851 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Mon, 14 Jun 2021 22:39:58 +0200 +Subject: [PATCH 081/153] arm64:dts: sun50i-h616-x96-mate add hdmi + +Signed-off-by: Jernej Skrabec +--- + .../dts/allwinner/sun50i-h616-x96-mate.dts | 26 +++++++++++++++++++ + 1 file changed, 26 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts +index 31c8bf0e1..f4a8241db 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts +@@ -23,6 +23,17 @@ chosen { + stdout-path = "serial0:115200n8"; + }; + ++ connector { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi_con_in: endpoint { ++ remote-endpoint = <&hdmi_out_con>; ++ }; ++ }; ++ }; ++ + reg_vcc5v: vcc5v { + /* board wide 5V supply directly from the DC input */ + compatible = "regulator-fixed"; +@@ -33,6 +44,10 @@ reg_vcc5v: vcc5v { + }; + }; + ++&de { ++ status = "okay"; ++}; ++ + &ehci0 { + status = "okay"; + }; +@@ -52,6 +67,17 @@ &emac1 { + status = "okay"; + }; + ++&hdmi { ++ hvcc-supply = <®_bldo1>; ++ status = "okay"; ++}; ++ ++&hdmi_out { ++ hdmi_out_con: endpoint { ++ remote-endpoint = <&hdmi_con_in>; ++ }; ++}; ++ + &ir { + status = "okay"; + }; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-bluetooth-btrtl-Add-rtl8822cs-hci-ver-0008.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-bluetooth-btrtl-Add-rtl8822cs-hci-ver-0008.patch new file mode 100644 index 0000000000..6d048f1dfe --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-bluetooth-btrtl-Add-rtl8822cs-hci-ver-0008.patch @@ -0,0 +1,31 @@ +From cde82da6f17d7807e95cb1b5ed429f0ff04f3cd0 Mon Sep 17 00:00:00 2001 +From: chbgdn +Date: Fri, 15 Oct 2021 23:08:52 +0300 +Subject: [PATCH 001/153] drv:bluetooth: btrtl: Add rtl8822cs (hci ver 0008) + +Signed-off-by: chbgdn +--- + drivers/bluetooth/btrtl.c | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/drivers/bluetooth/btrtl.c b/drivers/bluetooth/btrtl.c +index ce0af60db..251acd0e6 100644 +--- a/drivers/bluetooth/btrtl.c ++++ b/drivers/bluetooth/btrtl.c +@@ -206,6 +206,13 @@ static const struct id_table ic_id_table[] = { + .fw_name = "rtl_bt/rtl8822cs_fw.bin", + .cfg_name = "rtl_bt/rtl8822cs_config" }, + ++ /* 8822C with UART interface */ ++ { IC_INFO(RTL_ROM_LMP_8822B, 0xc, 0x8, HCI_UART), ++ .config_needed = true, ++ .has_rom_version = true, ++ .fw_name = "rtl_bt/rtl8822cs_fw.bin", ++ .cfg_name = "rtl_bt/rtl8822cs_config" }, ++ + /* 8822C with USB interface */ + { IC_INFO(RTL_ROM_LMP_8822B, 0xc, 0xa, HCI_USB), + .config_needed = false, +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-clk-sunxi-ng-ccu-add-min-max-rate-sun50i-a64.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-clk-sunxi-ng-ccu-add-min-max-rate-sun50i-a64.patch new file mode 100644 index 0000000000..2dc7583eea --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-clk-sunxi-ng-ccu-add-min-max-rate-sun50i-a64.patch @@ -0,0 +1,57 @@ +From 0c9e2f71295e75f4c9cbce6749d118628ede121e Mon Sep 17 00:00:00 2001 +From: Vasily Khoruzhick +Date: Tue, 24 Jul 2018 10:17:55 -0700 +Subject: [PATCH 029/153] drv:clk:sunxi-ng: ccu: add min/max rate sun50i-a64 + +--- + drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 2 ++ + drivers/clk/sunxi-ng/ccu_nkm.c | 5 +++++ + drivers/clk/sunxi-ng/ccu_nkm.h | 3 +++ + 3 files changed, 10 insertions(+) + +diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c +index 761d50597..9833ab1a1 100644 +--- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c ++++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c +@@ -196,6 +196,8 @@ static struct ccu_nkm pll_mipi_clk = { + .n = _SUNXI_CCU_MULT(8, 4), + .k = _SUNXI_CCU_MULT_MIN(4, 2, 2), + .m = _SUNXI_CCU_DIV(0, 4), ++ .min_rate = 300000000, ++ .max_rate = 1400000000, + .common = { + .reg = 0x040, + .hw.init = CLK_HW_INIT("pll-mipi", "pll-video0", +diff --git a/drivers/clk/sunxi-ng/ccu_nkm.c b/drivers/clk/sunxi-ng/ccu_nkm.c +index 67da2c189..83d969db0 100644 +--- a/drivers/clk/sunxi-ng/ccu_nkm.c ++++ b/drivers/clk/sunxi-ng/ccu_nkm.c +@@ -119,6 +119,11 @@ static unsigned long ccu_nkm_round_rate(struct ccu_mux_internal *mux, + _nkm.min_m = 1; + _nkm.max_m = nkm->m.max ?: 1 << nkm->m.width; + ++ if (rate < nkm->min_rate) ++ rate = nkm->min_rate; ++ if (nkm->max_rate && (rate > nkm->max_rate)) ++ rate = nkm->max_rate; ++ + if (nkm->common.features & CCU_FEATURE_FIXED_POSTDIV) + rate *= nkm->fixed_post_div; + +diff --git a/drivers/clk/sunxi-ng/ccu_nkm.h b/drivers/clk/sunxi-ng/ccu_nkm.h +index 6601defb3..57aa8087c 100644 +--- a/drivers/clk/sunxi-ng/ccu_nkm.h ++++ b/drivers/clk/sunxi-ng/ccu_nkm.h +@@ -28,6 +28,9 @@ struct ccu_nkm { + + unsigned int fixed_post_div; + ++ unsigned int min_rate; ++ unsigned int max_rate; ++ + struct ccu_common common; + }; + +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-clk-sunxi-ng-ccu-sun50i-a64-revert-ccu-Pinebook-A64.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-clk-sunxi-ng-ccu-sun50i-a64-revert-ccu-Pinebook-A64.patch new file mode 100644 index 0000000000..f0ec8761a4 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-clk-sunxi-ng-ccu-sun50i-a64-revert-ccu-Pinebook-A64.patch @@ -0,0 +1,64 @@ +From 5a11d6ca74867d866a14bd6f6e987f47df1d2630 Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Fri, 28 Jan 2022 14:10:52 +0300 +Subject: [PATCH 030/153] drv:clk:sunxi-ng:ccu-sun50i-a64: revert ccu + Pinebook-A64 + +--- + drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 18 +++++++++--------- + 1 file changed, 9 insertions(+), 9 deletions(-) + +diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c +index 9833ab1a1..9e5de9521 100644 +--- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c ++++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c +@@ -560,8 +560,8 @@ static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents, + * is required to restore the rate of TCON0 when the rate of PLL-Video0 + * changed. + */ +-static const char * const tcon0_parents[] = { "pll-mipi", /* "pll-video0-2x" */ }; +-static const u8 tcon0_table[] = { 0, /* 2, */ }; ++static const char * const tcon0_parents[] = { "pll-mipi", "pll-video0-2x" }; ++static const u8 tcon0_table[] = { 0, 2, }; + static SUNXI_CCU_MUX_TABLE_WITH_GATE(tcon0_clk, "tcon0", tcon0_parents, + tcon0_table, 0x118, 24, 3, BIT(31), + CLK_SET_RATE_PARENT); +@@ -968,9 +968,9 @@ static struct ccu_mux_nb sun50i_a64_cpu_nb = { + .bypass_index = 1, /* index of 24 MHz oscillator */ + }; + +-static struct ccu_rate_reset_nb sun50i_a64_pll_video0_reset_tcon0_nb = { ++/*static struct ccu_rate_reset_nb sun50i_a64_pll_video0_reset_tcon0_nb = { + .common = &pll_video0_clk.common, +-}; ++};*/ + + #define CCU_MIPI_DSI_CLK 0x168 + +@@ -1004,9 +1004,9 @@ static int sun50i_a64_ccu_probe(struct platform_device *pdev) + } + + /* Force the parent of TCON0 to PLL-MIPI */ +- val = readl(reg + SUN50I_A64_TCON0_REG); +- val &= ~GENMASK(26, 24); +- writel(val | (0 << 24), reg + SUN50I_A64_TCON0_REG); ++// val = readl(reg + SUN50I_A64_TCON0_REG); ++// val &= ~GENMASK(26, 24); ++// writel(val | (0 << 24), reg + SUN50I_A64_TCON0_REG); + + ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun50i_a64_ccu_desc); + if (ret) +@@ -1020,8 +1020,8 @@ static int sun50i_a64_ccu_probe(struct platform_device *pdev) + &sun50i_a64_cpu_nb); + + /* Reset the rate of TCON0 clock when PLL-VIDEO0 is changed */ +- sun50i_a64_pll_video0_reset_tcon0_nb.target_clk = tcon0_clk.common.hw.clk; +- ccu_rate_reset_notifier_register(&sun50i_a64_pll_video0_reset_tcon0_nb); ++// sun50i_a64_pll_video0_reset_tcon0_nb.target_clk = tcon0_clk.common.hw.clk; ++// ccu_rate_reset_notifier_register(&sun50i_a64_pll_video0_reset_tcon0_nb); + + return 0; + } +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-clocksource-arm_arch_timer-fix-a64-timejump.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-clocksource-arm_arch_timer-fix-a64-timejump.patch new file mode 100644 index 0000000000..bfff51e70a --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-clocksource-arm_arch_timer-fix-a64-timejump.patch @@ -0,0 +1,48 @@ +From 10428d15972d1940646470645cd278ab8d157fb9 Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Fri, 28 Jan 2022 14:18:17 +0300 +Subject: [PATCH 031/153] drv:clocksource:arm_arch_timer fix a64 timejump + +--- + drivers/clocksource/arm_arch_timer.c | 25 ++++++++++++++----------- + 1 file changed, 14 insertions(+), 11 deletions(-) + +diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c +index e09d4427f..44ea9e2ad 100644 +--- a/drivers/clocksource/arm_arch_timer.c ++++ b/drivers/clocksource/arm_arch_timer.c +@@ -365,17 +365,20 @@ static u64 notrace arm64_858921_read_cntvct_el0(void) + * with all ones or all zeros in the low bits. Bound the loop by the maximum + * number of CPU cycles in 3 consecutive 24 MHz counter periods. + */ +-#define __sun50i_a64_read_reg(reg) ({ \ +- u64 _val; \ +- int _retries = 150; \ +- \ +- do { \ +- _val = read_sysreg(reg); \ +- _retries--; \ +- } while (((_val + 1) & GENMASK(8, 0)) <= 1 && _retries); \ +- \ +- WARN_ON_ONCE(!_retries); \ +- _val; \ ++#define __sun50i_a64_read_reg(reg) ({ \ ++ register u64 _tries = 5, _old, _new; \ ++ \ ++ do { \ ++ if (unlikely(_tries < 3)) \ ++ isb(); \ ++ _old = read_sysreg(reg); \ ++ _new = read_sysreg(reg); \ ++ } while (unlikely((_new - _old) >> 4) && --_tries); \ ++ \ ++ if (unlikely(!_tries)) \ ++ pr_err("(cpu %d) returning possibly incorrect counter value %llx (%llx)\n", \ ++ smp_processor_id() + 1, _new, _old); \ ++ _new; \ + }) + + static u64 notrace sun50i_a64_read_cntpct_el0(void) +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-gpu-drm-gem-dma-Export-with-handle-allocator.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-gpu-drm-gem-dma-Export-with-handle-allocator.patch new file mode 100644 index 0000000000..5121118286 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-gpu-drm-gem-dma-Export-with-handle-allocator.patch @@ -0,0 +1,51 @@ +From 5da5beb55d8d49df5d4b4a42a007629a5e685c77 Mon Sep 17 00:00:00 2001 +From: Maxime Ripard +Date: Mon, 7 Dec 2015 09:33:28 +0100 +Subject: [PATCH 008/153] drv:gpu:drm: gem: dma: Export with handle allocator + +Signed-off-by: Maxime Ripard +Signed-off-by: The-going <48602507+The-going@users.noreply.github.com> +--- + drivers/gpu/drm/drm_gem_dma_helper.c | 3 ++- + include/drm/drm_gem_dma_helper.h | 4 ++++ + 2 files changed, 6 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/drm_gem_dma_helper.c b/drivers/gpu/drm/drm_gem_dma_helper.c +index 1e658c448..65baeef1f 100644 +--- a/drivers/gpu/drm/drm_gem_dma_helper.c ++++ b/drivers/gpu/drm/drm_gem_dma_helper.c +@@ -187,7 +187,7 @@ EXPORT_SYMBOL_GPL(drm_gem_dma_create); + * A struct drm_gem_dma_object * on success or an ERR_PTR()-encoded negative + * error code on failure. + */ +-static struct drm_gem_dma_object * ++struct drm_gem_dma_object * + drm_gem_dma_create_with_handle(struct drm_file *file_priv, + struct drm_device *drm, size_t size, + uint32_t *handle) +@@ -214,6 +214,7 @@ drm_gem_dma_create_with_handle(struct drm_file *file_priv, + + return dma_obj; + } ++EXPORT_SYMBOL_GPL(drm_gem_dma_create_with_handle); + + /** + * drm_gem_dma_free - free resources associated with a DMA GEM object +diff --git a/include/drm/drm_gem_dma_helper.h b/include/drm/drm_gem_dma_helper.h +index 8a043235d..7b3025b7b 100644 +--- a/include/drm/drm_gem_dma_helper.h ++++ b/include/drm/drm_gem_dma_helper.h +@@ -34,6 +34,10 @@ struct drm_gem_dma_object { + + struct drm_gem_dma_object *drm_gem_dma_create(struct drm_device *drm, + size_t size); ++struct drm_gem_dma_object * ++drm_gem_dma_create_with_handle(struct drm_file *file_priv, ++ struct drm_device *drm, size_t size, ++ uint32_t *handle); + void drm_gem_dma_free(struct drm_gem_dma_object *dma_obj); + void drm_gem_dma_print_info(const struct drm_gem_dma_object *dma_obj, + struct drm_printer *p, unsigned int indent); +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-gpu-drm-panel-simple-Add-compability-olinuxino-lcd.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-gpu-drm-panel-simple-Add-compability-olinuxino-lcd.patch new file mode 100644 index 0000000000..85d2e4bf7f --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-gpu-drm-panel-simple-Add-compability-olinuxino-lcd.patch @@ -0,0 +1,171 @@ +From f3fda59ef91be1d316134695ab2c511a86a03d99 Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Wed, 2 Feb 2022 19:34:55 +0300 +Subject: [PATCH 047/153] drv:gpu:drm: panel-simple Add compability olinuxino + lcd + +--- + drivers/gpu/drm/panel/panel-simple.c | 126 ++++++++++++++++++++++++++- + 1 file changed, 122 insertions(+), 4 deletions(-) + +diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c +index 8a3b685c2..fbdeb6251 100644 +--- a/drivers/gpu/drm/panel/panel-simple.c ++++ b/drivers/gpu/drm/panel/panel-simple.c +@@ -2944,6 +2944,44 @@ static const struct panel_desc okaya_rs800480t_7x0gp = { + .bus_format = MEDIA_BUS_FMT_RGB666_1X18, + }; + ++static const struct drm_display_mode olimex_vga_olinuxino_800_mode = { ++ .clock = 40000, ++ .hdisplay = 800, ++ .hsync_start = 800 + 40, ++ .hsync_end = 800 + 40 + 128, ++ .htotal = 800 + 40 + 128 + 88, ++ .vdisplay = 600, ++ .vsync_start = 600 + 5, ++ .vsync_end = 600 + 5 + 4, ++ .vtotal = 600 + 5 + 4 + 19, ++}; ++ ++static const struct drm_display_mode olimex_vga_olinuxino_1024_mode = { ++ .clock = 45000, ++ .hdisplay = 1024, ++ .hsync_start = 1024 + 16, ++ .hsync_end = 1024 + 16 + 10, ++ .htotal = 1024 + 16 + 10 + 150, ++ .vdisplay = 600, ++ .vsync_start = 600 + 2, ++ .vsync_end = 600 + 2 + 21, ++ .vtotal = 600 + 2 + 21 + 2, ++}; ++ ++ ++static const struct drm_display_mode olimex_lcd_olinuxino_43_mode = { ++ .clock = 12000, ++ .hdisplay = 480, ++ .hsync_start = 480 + 8, ++ .hsync_end = 480 + 8 + 20, ++ .htotal = 480 + 8 + 20 + 23, ++ .vdisplay = 272, ++ .vsync_start = 272 + 4, ++ .vsync_end = 272 + 4 + 10, ++ .vtotal = 272 + 4 + 10 + 13, ++}; ++ ++ + static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { + .clock = 9000, + .hdisplay = 480, +@@ -2956,8 +2994,8 @@ static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { + .vtotal = 272 + 8 + 5 + 3, + }; + +-static const struct panel_desc olimex_lcd_olinuxino_43ts = { +- .modes = &olimex_lcd_olinuxino_43ts_mode, ++static const struct panel_desc olimex_lcd_olinuxino_43 = { ++ .modes = &olimex_lcd_olinuxino_43_mode, + .num_modes = 1, + .size = { + .width = 95, +@@ -2966,6 +3004,71 @@ static const struct panel_desc olimex_lcd_olinuxino_43ts = { + .bus_format = MEDIA_BUS_FMT_RGB888_1X24, + }; + ++static const struct drm_display_mode olimex_lcd_olinuxino_5_mode = { ++ .clock = 33300, ++ .hdisplay = 800, ++ .hsync_start = 800 + 210, ++ .hsync_end = 800 + 210 + 20, ++ .htotal = 800 + 210 + 20 + 26, ++ .vdisplay = 480, ++ .vsync_start = 480 + 22, ++ .vsync_end = 480 + 22 + 10, ++ .vtotal = 480 + 22 + 10 + 13, ++}; ++ ++static const struct panel_desc olimex_lcd_olinuxino_5 = { ++ .modes = &olimex_lcd_olinuxino_5_mode, ++ .num_modes = 1, ++ .size = { ++ .width = 154, ++ .height = 86, ++ }, ++ .bus_format = MEDIA_BUS_FMT_RGB888_1X24, ++}; ++static const struct drm_display_mode olimex_lcd_olinuxino_7_mode = { ++ .clock = 33300, ++ .hdisplay = 800, ++ .hsync_start = 800 + 210, ++ .hsync_end = 800 + 210 + 20, ++ .htotal = 800 + 210 + 20 + 26, ++ .vdisplay = 480, ++ .vsync_start = 480 + 22, ++ .vsync_end = 480 + 22 + 10, ++ .vtotal = 480 + 22 + 10 + 13, ++}; ++ ++static const struct panel_desc olimex_lcd_olinuxino_7 = { ++ .modes = &olimex_lcd_olinuxino_7_mode, ++ .num_modes = 1, ++ .size = { ++ .width = 154, ++ .height = 86, ++ }, ++ .bus_format = MEDIA_BUS_FMT_RGB888_1X24, ++}; ++ ++static const struct drm_display_mode olimex_lcd_olinuxino_10_mode = { ++ .clock = 45000, ++ .hdisplay = 1024, ++ .hsync_start = 1024 + 16, ++ .hsync_end = 1024 + 16 + 1, ++ .htotal = 1024 + 10 + 6 + 160, ++ .vdisplay = 600, ++ .vsync_start = 600 + 1, ++ .vsync_end = 600 + 1 + 1, ++ .vtotal = 600 + 1 + 1 + 22, ++}; ++ ++static const struct panel_desc olimex_lcd_olinuxino_10 = { ++ .modes = &olimex_lcd_olinuxino_10_mode, ++ .num_modes = 1, ++ .size = { ++ .width = 222, ++ .height = 143, ++ }, ++ .bus_format = MEDIA_BUS_FMT_RGB888_1X24, ++}; ++ + /* + * 800x480 CVT. The panel appears to be quite accepting, at least as far as + * pixel clocks, but this is the timing that was being used in the Adafruit +@@ -4189,8 +4292,23 @@ static const struct of_device_id platform_of_match[] = { + .compatible = "okaya,rs800480t-7x0gp", + .data = &okaya_rs800480t_7x0gp, + }, { +- .compatible = "olimex,lcd-olinuxino-43-ts", +- .data = &olimex_lcd_olinuxino_43ts, ++ .compatible = "olimex,olinuxino-vga-800x600", ++ .data = &olimex_vga_olinuxino_800_mode, ++ }, { ++ .compatible = "olimex,olinuxino-vga-1024x768", ++ .data = &olimex_vga_olinuxino_1024_mode, ++ }, { ++ .compatible = "olimex,lcd-olinuxino-4.3", ++ .data = &olimex_lcd_olinuxino_43, ++ }, { ++ .compatible = "olimex,lcd-olinuxino-5", ++ .data = &olimex_lcd_olinuxino_5, ++ }, { ++ .compatible = "olimex,lcd-olinuxino-7", ++ .data = &olimex_lcd_olinuxino_7, ++ }, { ++ .compatible = "olimex,lcd-olinuxino-10", ++ .data = &olimex_lcd_olinuxino_10, + }, { + .compatible = "ontat,yx700wv03", + .data = &ontat_yx700wv03, +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-gpu-drm-sun4i-Add-GEM-allocator.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-gpu-drm-sun4i-Add-GEM-allocator.patch new file mode 100644 index 0000000000..75e6ac421d --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-gpu-drm-sun4i-Add-GEM-allocator.patch @@ -0,0 +1,103 @@ +From 8f70b58d5ff984b505958c19eeefb7a0b5b9b50f Mon Sep 17 00:00:00 2001 +From: Maxime Ripard +Date: Mon, 7 Dec 2015 09:47:34 +0100 +Subject: [PATCH 009/153] drv:gpu:drm:sun4i: Add GEM allocator + +Signed-off-by: Maxime Ripard +Signed-off-by: The-going <48602507+The-going@users.noreply.github.com> +--- + drivers/gpu/drm/sun4i/sun4i_drv.c | 27 +++++++++++++++++++++++++++ + include/uapi/drm/sun4i_drm.h | 29 +++++++++++++++++++++++++++++ + 2 files changed, 56 insertions(+) + create mode 100644 include/uapi/drm/sun4i_drm.h + +diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c b/drivers/gpu/drm/sun4i/sun4i_drv.c +index cc94efbbf..af861d2db 100644 +--- a/drivers/gpu/drm/sun4i/sun4i_drv.c ++++ b/drivers/gpu/drm/sun4i/sun4i_drv.c +@@ -24,6 +24,8 @@ + #include + #include + ++#include ++ + #include "sun4i_drv.h" + #include "sun4i_frontend.h" + #include "sun4i_framebuffer.h" +@@ -42,6 +44,27 @@ static int drm_sun4i_gem_dumb_create(struct drm_file *file_priv, + + DEFINE_DRM_GEM_DMA_FOPS(sun4i_drv_fops); + ++static int sun4i_gem_create_ioctl(struct drm_device *drm, void *data, ++ struct drm_file *file_priv) ++{ ++ struct drm_sun4i_gem_create *args = data; ++ struct drm_gem_dma_object *dma_obj; ++ size_t size; ++ ++ /* The Mali requires a 64 bytes alignment */ ++ size = ALIGN(args->size, 64); ++ ++ dma_obj = drm_gem_dma_create_with_handle(file_priv, drm, size, ++ &args->handle); ++ ++ return PTR_ERR_OR_ZERO(dma_obj); ++} ++ ++static const struct drm_ioctl_desc sun4i_drv_ioctls[] = { ++ DRM_IOCTL_DEF_DRV(SUN4I_GEM_CREATE, sun4i_gem_create_ioctl, ++ DRM_UNLOCKED | DRM_AUTH), ++}; ++ + static const struct drm_driver sun4i_drv_driver = { + .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC, + +@@ -53,6 +76,10 @@ static const struct drm_driver sun4i_drv_driver = { + .major = 1, + .minor = 0, + ++ /* Custom ioctls */ ++ .ioctls = sun4i_drv_ioctls, ++ .num_ioctls = ARRAY_SIZE(sun4i_drv_ioctls), ++ + /* GEM Operations */ + DRM_GEM_DMA_DRIVER_OPS_WITH_DUMB_CREATE(drm_sun4i_gem_dumb_create), + }; +diff --git a/include/uapi/drm/sun4i_drm.h b/include/uapi/drm/sun4i_drm.h +new file mode 100644 +index 000000000..67b9dd4ee +--- /dev/null ++++ b/include/uapi/drm/sun4i_drm.h +@@ -0,0 +1,29 @@ ++/* ++ * Copyright (C) 2015 Free Electrons ++ * Copyright (C) 2015 NextThing Co ++ * ++ * Maxime Ripard ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ */ ++ ++#ifndef _UAPI_SUN4I_DRM_H_ ++#define _UAPI_SUN4I_DRM_H_ ++ ++#include ++ ++struct drm_sun4i_gem_create { ++ __u64 size; ++ __u32 flags; ++ __u32 handle; ++}; ++ ++#define DRM_SUN4I_GEM_CREATE 0x00 ++ ++#define DRM_IOCTL_SUN4I_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_SUN4I_GEM_CREATE, \ ++ struct drm_sun4i_gem_create) ++ ++#endif +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-gpu-drm-sun4i-Add-HDMI-audio-sun4i-hdmi-encoder.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-gpu-drm-sun4i-Add-HDMI-audio-sun4i-hdmi-encoder.patch new file mode 100644 index 0000000000..21074c8c15 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-gpu-drm-sun4i-Add-HDMI-audio-sun4i-hdmi-encoder.patch @@ -0,0 +1,633 @@ +From bc0dd4de2cb5318819b7d9c8b15aabcf75fce3ff Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Mon, 24 Jan 2022 13:07:16 +0300 +Subject: [PATCH 010/153] drv:gpu:drm:sun4i: Add HDMI audio sun4i-hdmi encoder + +Add HDMI audio support for the sun4i-hdmi encoder, used on +the older Allwinner chips - A10, A20, A31. + +Most of the code is based on the BSP implementation. In it +dditional formats are supported (S20_3LE and S24_LE), however +there where some problems with them and only S16_LE is left. + +Signed-off-by: Stefan Mavrodiev +--- + drivers/gpu/drm/sun4i/Kconfig | 11 + + drivers/gpu/drm/sun4i/Makefile | 3 + + drivers/gpu/drm/sun4i/sun4i_hdmi.h | 36 ++ + drivers/gpu/drm/sun4i/sun4i_hdmi_audio.c | 450 +++++++++++++++++++++++ + drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c | 16 + + 5 files changed, 516 insertions(+) + create mode 100644 drivers/gpu/drm/sun4i/sun4i_hdmi_audio.c + +diff --git a/drivers/gpu/drm/sun4i/Kconfig b/drivers/gpu/drm/sun4i/Kconfig +index 4741d9f65..733381869 100644 +--- a/drivers/gpu/drm/sun4i/Kconfig ++++ b/drivers/gpu/drm/sun4i/Kconfig +@@ -23,6 +23,17 @@ config DRM_SUN4I_HDMI + Choose this option if you have an Allwinner A10/A10s/A20/A31 + SoC with an HDMI controller. + ++config DRM_SUN4I_HDMI_AUDIO ++ bool "Allwinner A10 HDMI Audio Support" ++ default y ++ depends on DRM_SUN4I_HDMI ++ depends on SND_SOC=y || SND_SOC=DRM_SUN4I_HDMI ++ select SND_PCM_ELD ++ select SND_SOC_GENERIC_DMAENGINE_PCM ++ help ++ Choose this option if you have an Allwinner SoC with an HDMI ++ controller and want to use audio. ++ + config DRM_SUN4I_HDMI_CEC + bool "Allwinner A10/A10s/A20/A31 HDMI CEC Support" + depends on DRM_SUN4I_HDMI +diff --git a/drivers/gpu/drm/sun4i/Makefile b/drivers/gpu/drm/sun4i/Makefile +index 0d04f2447..492bfd28a 100644 +--- a/drivers/gpu/drm/sun4i/Makefile ++++ b/drivers/gpu/drm/sun4i/Makefile +@@ -5,6 +5,9 @@ sun4i-frontend-y += sun4i_frontend.o + sun4i-drm-y += sun4i_drv.o + sun4i-drm-y += sun4i_framebuffer.o + ++ifdef CONFIG_DRM_SUN4I_HDMI_AUDIO ++sun4i-drm-hdmi-y += sun4i_hdmi_audio.o ++endif + sun4i-drm-hdmi-y += sun4i_hdmi_ddc_clk.o + sun4i-drm-hdmi-y += sun4i_hdmi_enc.o + sun4i-drm-hdmi-y += sun4i_hdmi_i2c.o +diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi.h b/drivers/gpu/drm/sun4i/sun4i_hdmi.h +index 65c801cd6..2edced4eb 100644 +--- a/drivers/gpu/drm/sun4i/sun4i_hdmi.h ++++ b/drivers/gpu/drm/sun4i/sun4i_hdmi.h +@@ -42,7 +42,32 @@ + #define SUN4I_HDMI_VID_TIMING_POL_VSYNC BIT(1) + #define SUN4I_HDMI_VID_TIMING_POL_HSYNC BIT(0) + ++#define SUN4I_HDMI_AUDIO_CTRL_REG 0x040 ++#define SUN4I_HDMI_AUDIO_CTRL_ENABLE BIT(31) ++#define SUN4I_HDMI_AUDIO_CTRL_RESET BIT(30) ++ ++#define SUN4I_HDMI_AUDIO_FMT_REG 0x048 ++#define SUN4I_HDMI_AUDIO_FMT_SRC BIT(31) ++#define SUN4I_HDMI_AUDIO_FMT_LAYOUT BIT(3) ++#define SUN4I_HDMI_AUDIO_FMT_CH_CFG(n) ((n) - 1) ++#define SUN4I_HDMI_AUDIO_FMT_CH_CFG_MASK GENMASK(2, 0) ++ ++#define SUN4I_HDMI_AUDIO_PCM_REG 0x4c ++#define SUN4I_HDMI_AUDIO_PCM_CH_MAP(n, m) (((m) - 1) << ((n) * 4)) ++#define SUN4I_HDMI_AUDIO_PCM_CH_MAP_MASK(n) (GENMASK(2, 0) << ((n) * 4)) ++ ++#define SUN4I_HDMI_AUDIO_CTS_REG 0x050 ++#define SUN4I_HDMI_AUDIO_CTS(n) ((n) & GENMASK(19, 0)) ++ ++#define SUN4I_HDMI_AUDIO_N_REG 0x054 ++#define SUN4I_HDMI_AUDIO_N(n) ((n) & GENMASK(19, 0)) ++ ++#define SUN4I_HDMI_AUDIO_STAT0_REG 0x58 ++#define SUN4I_HDMI_AUDIO_STAT0_FREQ(n) ((n) << 24) ++#define SUN4I_HDMI_AUDIO_STAT0_FREQ_MASK GENMASK(27, 24) ++ + #define SUN4I_HDMI_AVI_INFOFRAME_REG(n) (0x080 + (n)) ++#define SUN4I_HDMI_AUDIO_INFOFRAME_REG(n) (0x0a0 + (n)) + + #define SUN4I_HDMI_PAD_CTRL0_REG 0x200 + #define SUN4I_HDMI_PAD_CTRL0_BIASEN BIT(31) +@@ -242,6 +267,11 @@ struct sun4i_hdmi_variant { + bool ddc_fifo_has_dir; + }; + ++struct sun4i_hdmi_audio { ++ struct snd_soc_card *card; ++ u8 channels; ++}; ++ + struct sun4i_hdmi { + struct drm_connector connector; + struct drm_encoder encoder; +@@ -285,6 +315,10 @@ struct sun4i_hdmi { + + struct sun4i_drv *drv; + ++ bool hdmi_audio; ++ ++ struct sun4i_hdmi_audio audio; ++ + struct cec_adapter *cec_adap; + + const struct sun4i_hdmi_variant *variant; +@@ -293,5 +327,7 @@ struct sun4i_hdmi { + int sun4i_ddc_create(struct sun4i_hdmi *hdmi, struct clk *clk); + int sun4i_tmds_create(struct sun4i_hdmi *hdmi); + int sun4i_hdmi_i2c_create(struct device *dev, struct sun4i_hdmi *hdmi); ++int sun4i_hdmi_audio_create(struct sun4i_hdmi *hdmi); ++void sun4i_hdmi_audio_destroy(struct sun4i_hdmi *hdmi); + + #endif /* _SUN4I_HDMI_H_ */ +diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi_audio.c b/drivers/gpu/drm/sun4i/sun4i_hdmi_audio.c +new file mode 100644 +index 000000000..2ac967bfd +--- /dev/null ++++ b/drivers/gpu/drm/sun4i/sun4i_hdmi_audio.c +@@ -0,0 +1,450 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later ++/* ++ * Copyright (C) 2020 Olimex Ltd. ++ * Author: Stefan Mavrodiev ++ */ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include "sun4i_hdmi.h" ++ ++static int sun4i_hdmi_audio_ctl_eld_info(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_info *uinfo) ++{ ++ uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; ++ uinfo->count = MAX_ELD_BYTES; ++ return 0; ++} ++ ++static int sun4i_hdmi_audio_ctl_eld_get(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); ++ struct snd_soc_card *card = snd_soc_component_get_drvdata(component); ++ struct sun4i_hdmi *hdmi = snd_soc_card_get_drvdata(card); ++ ++ memcpy(ucontrol->value.bytes.data, ++ hdmi->connector.eld, ++ MAX_ELD_BYTES); ++ ++ return 0; ++} ++ ++static const struct snd_kcontrol_new sun4i_hdmi_audio_controls[] = { ++ { ++ .access = SNDRV_CTL_ELEM_ACCESS_READ | ++ SNDRV_CTL_ELEM_ACCESS_VOLATILE, ++ .iface = SNDRV_CTL_ELEM_IFACE_PCM, ++ .name = "ELD", ++ .info = sun4i_hdmi_audio_ctl_eld_info, ++ .get = sun4i_hdmi_audio_ctl_eld_get, ++ }, ++}; ++ ++static const struct snd_soc_dapm_widget sun4i_hdmi_audio_widgets[] = { ++ SND_SOC_DAPM_OUTPUT("TX"), ++}; ++ ++static const struct snd_soc_dapm_route sun4i_hdmi_audio_routes[] = { ++ { "TX", NULL, "Playback" }, ++}; ++ ++static const struct snd_soc_component_driver sun4i_hdmi_audio_component = { ++ .controls = sun4i_hdmi_audio_controls, ++ .num_controls = ARRAY_SIZE(sun4i_hdmi_audio_controls), ++ .dapm_widgets = sun4i_hdmi_audio_widgets, ++ .num_dapm_widgets = ARRAY_SIZE(sun4i_hdmi_audio_widgets), ++ .dapm_routes = sun4i_hdmi_audio_routes, ++ .num_dapm_routes = ARRAY_SIZE(sun4i_hdmi_audio_routes), ++}; ++ ++static int sun4i_hdmi_audio_startup(struct snd_pcm_substream *substream, ++ struct snd_soc_dai *dai) ++{ ++ struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai); ++ struct sun4i_hdmi *hdmi = snd_soc_card_get_drvdata(card); ++ u32 reg; ++ int ret; ++ ++ regmap_write(hdmi->regmap, SUN4I_HDMI_AUDIO_CTRL_REG, 0); ++ regmap_write(hdmi->regmap, ++ SUN4I_HDMI_AUDIO_CTRL_REG, ++ SUN4I_HDMI_AUDIO_CTRL_RESET); ++ ret = regmap_read_poll_timeout(hdmi->regmap, ++ SUN4I_HDMI_AUDIO_CTRL_REG, ++ reg, !reg, 100, 50000); ++ if (ret < 0) { ++ DRM_ERROR("Failed to reset HDMI Audio\n"); ++ return ret; ++ } ++ ++ regmap_write(hdmi->regmap, ++ SUN4I_HDMI_AUDIO_CTRL_REG, ++ SUN4I_HDMI_AUDIO_CTRL_ENABLE); ++ ++ return snd_pcm_hw_constraint_eld(substream->runtime, ++ hdmi->connector.eld); ++} ++ ++static void sun4i_hdmi_audio_shutdown(struct snd_pcm_substream *substream, ++ struct snd_soc_dai *dai) ++{ ++ struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai); ++ struct sun4i_hdmi *hdmi = snd_soc_card_get_drvdata(card); ++ ++ regmap_write(hdmi->regmap, SUN4I_HDMI_AUDIO_CTRL_REG, 0); ++} ++ ++static int sun4i_hdmi_setup_audio_infoframes(struct sun4i_hdmi *hdmi) ++{ ++ union hdmi_infoframe frame; ++ u8 buffer[14]; ++ int i, ret; ++ ++ ret = hdmi_audio_infoframe_init(&frame.audio); ++ if (ret < 0) { ++ DRM_ERROR("Failed to init HDMI audio infoframe\n"); ++ return ret; ++ } ++ ++ frame.audio.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM; ++ frame.audio.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM; ++ frame.audio.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM; ++ frame.audio.channels = hdmi->audio.channels; ++ ++ ret = hdmi_infoframe_pack(&frame, buffer, sizeof(buffer)); ++ if (ret < 0) { ++ DRM_ERROR("Failed to pack HDMI audio infoframe\n"); ++ return ret; ++ } ++ ++ for (i = 0; i < sizeof(buffer); i++) ++ writeb(buffer[i], ++ hdmi->base + SUN4I_HDMI_AUDIO_INFOFRAME_REG(i)); ++ ++ return 0; ++} ++ ++static void sun4i_hdmi_audio_set_cts_n(struct sun4i_hdmi *hdmi, ++ struct snd_pcm_hw_params *params) ++{ ++ struct drm_encoder *encoder = &hdmi->encoder; ++ struct drm_crtc *crtc = encoder->crtc; ++ const struct drm_display_mode *mode = &crtc->state->adjusted_mode; ++ u32 rate = params_rate(params); ++ u32 n, cts; ++ u64 tmp; ++ ++ /** ++ * Calculate Cycle Time Stamp (CTS) and Numerator (N): ++ * ++ * N = 128 * Samplerate / 1000 ++ * CTS = (Ftdms * N) / (128 * Samplerate) ++ */ ++ ++ n = 128 * rate / 1000; ++ tmp = (u64)(mode->clock * 1000) * n; ++ do_div(tmp, 128 * rate); ++ cts = tmp; ++ ++ regmap_write(hdmi->regmap, ++ SUN4I_HDMI_AUDIO_CTS_REG, ++ SUN4I_HDMI_AUDIO_CTS(cts)); ++ ++ regmap_write(hdmi->regmap, ++ SUN4I_HDMI_AUDIO_N_REG, ++ SUN4I_HDMI_AUDIO_N(n)); ++} ++ ++static int sun4i_hdmi_audio_set_hw_rate(struct sun4i_hdmi *hdmi, ++ struct snd_pcm_hw_params *params) ++{ ++ u32 rate = params_rate(params); ++ u32 val; ++ ++ switch (rate) { ++ case 44100: ++ val = 0x0; ++ break; ++ case 48000: ++ val = 0x2; ++ break; ++ case 32000: ++ val = 0x3; ++ break; ++ case 88200: ++ val = 0x8; ++ break; ++ case 96000: ++ val = 0x9; ++ break; ++ case 176400: ++ val = 0xc; ++ break; ++ case 192000: ++ val = 0xe; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ regmap_update_bits(hdmi->regmap, ++ SUN4I_HDMI_AUDIO_STAT0_REG, ++ SUN4I_HDMI_AUDIO_STAT0_FREQ_MASK, ++ SUN4I_HDMI_AUDIO_STAT0_FREQ(val)); ++ ++ return 0; ++} ++ ++static int sun4i_hdmi_audio_set_hw_channels(struct sun4i_hdmi *hdmi, ++ struct snd_pcm_hw_params *params) ++{ ++ u32 channels = params_channels(params); ++ ++ if (channels > 8) ++ return -EINVAL; ++ ++ hdmi->audio.channels = channels; ++ ++ regmap_update_bits(hdmi->regmap, ++ SUN4I_HDMI_AUDIO_FMT_REG, ++ SUN4I_HDMI_AUDIO_FMT_LAYOUT, ++ (channels > 2) ? SUN4I_HDMI_AUDIO_FMT_LAYOUT : 0); ++ ++ regmap_update_bits(hdmi->regmap, ++ SUN4I_HDMI_AUDIO_FMT_REG, ++ SUN4I_HDMI_AUDIO_FMT_CH_CFG_MASK, ++ SUN4I_HDMI_AUDIO_FMT_CH_CFG(channels)); ++ ++ regmap_write(hdmi->regmap, SUN4I_HDMI_AUDIO_PCM_REG, 0x76543210); ++ ++ /** ++ * If only one channel is required, send the same sample ++ * to the sink device as a left and right channel. ++ */ ++ if (channels == 1) ++ regmap_update_bits(hdmi->regmap, ++ SUN4I_HDMI_AUDIO_PCM_REG, ++ SUN4I_HDMI_AUDIO_PCM_CH_MAP_MASK(1), ++ SUN4I_HDMI_AUDIO_PCM_CH_MAP(1, 1)); ++ ++ return 0; ++} ++ ++static int sun4i_hdmi_audio_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params, ++ struct snd_soc_dai *dai) ++{ ++ struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai); ++ struct sun4i_hdmi *hdmi = snd_soc_card_get_drvdata(card); ++ int ret; ++ ++ ret = sun4i_hdmi_audio_set_hw_rate(hdmi, params); ++ if (ret < 0) ++ return ret; ++ ++ ret = sun4i_hdmi_audio_set_hw_channels(hdmi, params); ++ if (ret < 0) ++ return ret; ++ ++ sun4i_hdmi_audio_set_cts_n(hdmi, params); ++ ++ return 0; ++} ++ ++static int sun4i_hdmi_audio_trigger(struct snd_pcm_substream *substream, ++ int cmd, ++ struct snd_soc_dai *dai) ++{ ++ struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai); ++ struct sun4i_hdmi *hdmi = snd_soc_card_get_drvdata(card); ++ int ret = 0; ++ ++ switch (cmd) { ++ case SNDRV_PCM_TRIGGER_START: ++ ret = sun4i_hdmi_setup_audio_infoframes(hdmi); ++ break; ++ default: ++ break; ++ } ++ ++ return ret; ++} ++ ++static const struct snd_soc_dai_ops sun4i_hdmi_audio_dai_ops = { ++ .startup = sun4i_hdmi_audio_startup, ++ .shutdown = sun4i_hdmi_audio_shutdown, ++ .hw_params = sun4i_hdmi_audio_hw_params, ++ .trigger = sun4i_hdmi_audio_trigger, ++}; ++ ++static int sun4i_hdmi_audio_dai_probe(struct snd_soc_dai *dai) ++{ ++ struct snd_dmaengine_dai_dma_data *dma_data; ++ ++ dma_data = devm_kzalloc(dai->dev, sizeof(*dma_data), GFP_KERNEL); ++ if (!dma_data) ++ return -ENOMEM; ++ ++ dma_data->addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; ++ dma_data->maxburst = 8; ++ ++ snd_soc_dai_init_dma_data(dai, dma_data, NULL); ++ ++ return 0; ++} ++ ++static struct snd_soc_dai_driver sun4i_hdmi_audio_dai = { ++ .name = "HDMI", ++ .ops = &sun4i_hdmi_audio_dai_ops, ++ .probe = sun4i_hdmi_audio_dai_probe, ++ .playback = { ++ .stream_name = "Playback", ++ .channels_min = 1, ++ .channels_max = 8, ++ .formats = SNDRV_PCM_FMTBIT_S16_LE, ++ .rates = SNDRV_PCM_RATE_8000_192000, ++ }, ++}; ++ ++static const struct snd_pcm_hardware sun4i_hdmi_audio_pcm_hardware = { ++ .info = SNDRV_PCM_INFO_INTERLEAVED | ++ SNDRV_PCM_INFO_BLOCK_TRANSFER | ++ SNDRV_PCM_INFO_MMAP | ++ SNDRV_PCM_INFO_MMAP_VALID | ++ SNDRV_PCM_INFO_PAUSE | ++ SNDRV_PCM_INFO_RESUME, ++ .formats = SNDRV_PCM_FMTBIT_S16_LE, ++ .rates = SNDRV_PCM_RATE_8000_192000, ++ .rate_min = 8000, ++ .rate_max = 192000, ++ .channels_min = 1, ++ .channels_max = 8, ++ .buffer_bytes_max = 128 * 1024, ++ .period_bytes_min = 4 * 1024, ++ .period_bytes_max = 32 * 1024, ++ .periods_min = 2, ++ .periods_max = 8, ++ .fifo_size = 128, ++}; ++ ++static const struct snd_dmaengine_pcm_config sun4i_hdmi_audio_pcm_config = { ++ .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-tx", ++ .pcm_hardware = &sun4i_hdmi_audio_pcm_hardware, ++ .prealloc_buffer_size = 128 * 1024, ++ .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, ++}; ++ ++struct snd_soc_card sun4i_hdmi_audio_card = { ++ .name = "sun4i-hdmi", ++}; ++ ++int sun4i_hdmi_audio_create(struct sun4i_hdmi *hdmi) ++{ ++ struct snd_soc_card *card = &sun4i_hdmi_audio_card; ++ struct snd_soc_dai_link_component *comp; ++ struct snd_soc_dai_link *link; ++ int ret; ++ ++ ret = snd_dmaengine_pcm_register(hdmi->dev, ++ &sun4i_hdmi_audio_pcm_config, 0); ++ if (ret < 0) { ++ DRM_ERROR("Could not register PCM\n"); ++ return ret; ++ } ++ ++ ret = snd_soc_register_component(hdmi->dev, ++ &sun4i_hdmi_audio_component, ++ &sun4i_hdmi_audio_dai, 1); ++ if (ret < 0) { ++ DRM_ERROR("Could not register DAI\n"); ++ goto unregister_pcm; ++ } ++ ++ link = devm_kzalloc(hdmi->dev, sizeof(*link), GFP_KERNEL); ++ if (!link) { ++ ret = -ENOMEM; ++ goto unregister_component; ++ } ++ ++ comp = devm_kzalloc(hdmi->dev, sizeof(*comp) * 3, GFP_KERNEL); ++ if (!comp) { ++ ret = -ENOMEM; ++ goto unregister_component; ++ } ++ ++ link->cpus = &comp[0]; ++ link->codecs = &comp[1]; ++ link->platforms = &comp[2]; ++ ++ link->num_cpus = 1; ++ link->num_codecs = 1; ++ link->num_platforms = 1; ++ ++ link->playback_only = 1; ++ ++ link->name = "SUN4I-HDMI"; ++ link->stream_name = "SUN4I-HDMI PCM"; ++ ++ link->codecs->name = dev_name(hdmi->dev); ++ link->codecs->dai_name = sun4i_hdmi_audio_dai.name; ++ ++ link->cpus->dai_name = dev_name(hdmi->dev); ++ ++ link->platforms->name = dev_name(hdmi->dev); ++ ++ link->dai_fmt = SND_SOC_DAIFMT_I2S; ++ ++ card->dai_link = link; ++ card->num_links = 1; ++ card->dev = hdmi->dev; ++ ++ hdmi->audio.card = card; ++ ++ /** ++ * snd_soc_register_card() will overwrite the driver_data pointer. ++ * So before registering the card, store the original pointer in ++ * card->drvdata. ++ */ ++ snd_soc_card_set_drvdata(card, hdmi); ++ ret = snd_soc_register_card(card); ++ if (ret) ++ goto unregister_component; ++ ++ return 0; ++ ++unregister_component: ++ snd_soc_unregister_component(hdmi->dev); ++unregister_pcm: ++ snd_dmaengine_pcm_unregister(hdmi->dev); ++ return ret; ++} ++ ++void sun4i_hdmi_audio_destroy(struct sun4i_hdmi *hdmi) ++{ ++ struct snd_soc_card *card = hdmi->audio.card; ++ void *data; ++ ++ /** ++ * Before removing the card, restore the previously stored driver_data. ++ * This will ensure proper removal of the sun4i-hdmi module, since it ++ * uses dev_get_drvdata() in the unbind function. ++ */ ++ data = snd_soc_card_get_drvdata(card); ++ ++ snd_soc_unregister_card(card); ++ snd_soc_unregister_component(hdmi->dev); ++ snd_dmaengine_pcm_unregister(hdmi->dev); ++ ++ dev_set_drvdata(hdmi->dev, data); ++} +diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c b/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c +index c0df5e892..739b2120a 100644 +--- a/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c ++++ b/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c +@@ -25,6 +25,8 @@ + #include + #include + ++#include ++ + #include "sun4i_backend.h" + #include "sun4i_crtc.h" + #include "sun4i_drv.h" +@@ -89,6 +91,11 @@ static void sun4i_hdmi_disable(struct drm_encoder *encoder) + + DRM_DEBUG_DRIVER("Disabling the HDMI Output\n"); + ++#ifdef CONFIG_DRM_SUN4I_HDMI_AUDIO ++ if (hdmi->hdmi_audio) ++ sun4i_hdmi_audio_destroy(hdmi); ++#endif ++ + val = readl(hdmi->base + SUN4I_HDMI_VID_CTRL_REG); + val &= ~SUN4I_HDMI_VID_CTRL_ENABLE; + writel(val, hdmi->base + SUN4I_HDMI_VID_CTRL_REG); +@@ -117,6 +124,11 @@ static void sun4i_hdmi_enable(struct drm_encoder *encoder) + val |= SUN4I_HDMI_VID_CTRL_HDMI_MODE; + + writel(val, hdmi->base + SUN4I_HDMI_VID_CTRL_REG); ++ ++#ifdef CONFIG_DRM_SUN4I_HDMI_AUDIO ++ if (hdmi->hdmi_audio && sun4i_hdmi_audio_create(hdmi)) ++ DRM_ERROR("Couldn't create the HDMI audio adapter\n"); ++#endif + } + + static void sun4i_hdmi_mode_set(struct drm_encoder *encoder, +@@ -217,6 +229,10 @@ static int sun4i_hdmi_get_modes(struct drm_connector *connector) + if (!edid) + return 0; + ++#ifdef CONFIG_DRM_SUN4I_HDMI_AUDIO ++ hdmi->hdmi_audio = drm_detect_monitor_audio(edid); ++#endif ++ + DRM_DEBUG_DRIVER("Monitor is %s monitor\n", + connector->display_info.is_hdmi ? "an HDMI" : "a DVI"); + +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-gpu-drm-sun4i-sun8i_mixer.c-add-h3-mixer1.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-gpu-drm-sun4i-sun8i_mixer.c-add-h3-mixer1.patch new file mode 100644 index 0000000000..a04000c328 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-gpu-drm-sun4i-sun8i_mixer.c-add-h3-mixer1.patch @@ -0,0 +1,42 @@ +From f25b4a7fc51d89650795752f4271c9844fdc4172 Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Tue, 1 Feb 2022 19:37:03 +0300 +Subject: [PATCH 038/153] drv:gpu:drm:sun4i:sun8i_mixer.c add h3 mixer1 + +--- + drivers/gpu/drm/sun4i/sun8i_mixer.c | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c +index 8dbc5d00f..9c17bb410 100644 +--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c ++++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c +@@ -718,6 +718,14 @@ static const struct sun8i_mixer_cfg sun8i_h3_mixer0_cfg = { + .vi_num = 1, + }; + ++static const struct sun8i_mixer_cfg sun8i_h3_mixer1_cfg = { ++ .ccsc = CCSC_MIXER1_LAYOUT, ++ .mod_rate = 432000000, ++ .scaler_mask = 0xf, ++ .ui_num = 3, ++ .vi_num = 1, ++}; ++ + static const struct sun8i_mixer_cfg sun8i_r40_mixer0_cfg = { + .ccsc = CCSC_MIXER0_LAYOUT, + .mod_rate = 297000000, +@@ -804,6 +812,10 @@ static const struct of_device_id sun8i_mixer_of_table[] = { + .compatible = "allwinner,sun8i-h3-de2-mixer-0", + .data = &sun8i_h3_mixer0_cfg, + }, ++ { ++ .compatible = "allwinner,sun8i-h3-de2-mixer-1", ++ .data = &sun8i_h3_mixer1_cfg, ++ }, + { + .compatible = "allwinner,sun8i-r40-de2-mixer-0", + .data = &sun8i_r40_mixer0_cfg, +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-iio-adc-Kconfig-enable-A80-A64-H5-for-THS.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-iio-adc-Kconfig-enable-A80-A64-H5-for-THS.patch new file mode 100644 index 0000000000..b66215d929 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-iio-adc-Kconfig-enable-A80-A64-H5-for-THS.patch @@ -0,0 +1,26 @@ +From 51b179b340ec62fa14bbd45dc486600f67b56967 Mon Sep 17 00:00:00 2001 +From: Philipp Rossak +Date: Wed, 24 Jan 2018 22:35:13 +0100 +Subject: [PATCH 021/153] drv:iio:adc: Kconfig: enable A80,A64,H5 for THS + +Signed-off-by: Philipp Rossak +--- + drivers/iio/adc/Kconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig +index 63f80d747..0502391eb 100644 +--- a/drivers/iio/adc/Kconfig ++++ b/drivers/iio/adc/Kconfig +@@ -1096,7 +1096,7 @@ config STMPE_ADC + config SUN4I_GPADC + tristate "Support for the Allwinner SoCs GPADC" + depends on IIO +- depends on MFD_SUN4I_GPADC || MACH_SUN8I ++ depends on MFD_SUN4I_GPADC || MACH_SUN8I || MACH_SUN50I || MACH_SUN9I + depends on THERMAL || !THERMAL_OF + select REGMAP_IRQ + help +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-iio-adc-axp20x_adc-arm64-dts-axp803-hwmon-enable-thermal.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-iio-adc-axp20x_adc-arm64-dts-axp803-hwmon-enable-thermal.patch new file mode 100644 index 0000000000..11c7463660 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-iio-adc-axp20x_adc-arm64-dts-axp803-hwmon-enable-thermal.patch @@ -0,0 +1,168 @@ +From 58e3cfe59cfac833d482abd901b8333cdcff06b5 Mon Sep 17 00:00:00 2001 +From: Mitko Gamishev +Date: Wed, 5 Feb 2020 14:57:10 +0200 +Subject: [PATCH] drv:iio:adc:axp20x_adc arm64:dts:axp803 hwmon enable thermal + +--- + arch/arm64/boot/dts/allwinner/axp803.dtsi | 1 + + drivers/iio/adc/axp20x_adc.c | 88 +++++++++++++++++++++++ + 2 files changed, 89 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/axp803.dtsi b/arch/arm64/boot/dts/allwinner/axp803.dtsi +index a6b4b87f185d..422be59f5d88 100644 +--- a/arch/arm64/boot/dts/allwinner/axp803.dtsi ++++ b/arch/arm64/boot/dts/allwinner/axp803.dtsi +@@ -19,6 +19,7 @@ ac_power_supply: ac-power { + axp_adc: adc { + compatible = "x-powers,axp803-adc", "x-powers,axp813-adc"; + #io-channel-cells = <1>; ++ #thermal-sensor-cells = <0>; + }; + + axp_gpio: gpio { +diff --git a/drivers/iio/adc/axp20x_adc.c b/drivers/iio/adc/axp20x_adc.c +index 83e228980ad5..1c6978037513 100644 +--- a/drivers/iio/adc/axp20x_adc.c ++++ b/drivers/iio/adc/axp20x_adc.c +@@ -7,6 +7,7 @@ + + #include + #include ++#include + #include + #include + #include +@@ -619,6 +620,74 @@ static int axp813_adc_rate(struct axp20x_adc_iio *info, int rate) + AXP813_ADC_RATE_HZ(rate)); + } + ++ ++static umode_t axp813_adc_hwmon_is_visible(const void *data, ++ enum hwmon_sensor_types type, ++ u32 attr, int channel) ++{ ++ return (type == hwmon_temp && attr == hwmon_temp_input) ? 0444 : 0; ++} ++ ++static int axp813_adc_hwmon_read(struct device *dev, ++ enum hwmon_sensor_types type, ++ u32 attr, int channel, long *temp) ++{ ++ struct axp20x_adc_iio *info = dev_get_drvdata(dev); ++ int ret; ++ int raw; ++ ++ switch (attr) { ++ case hwmon_temp_input: ++ raw = axp20x_read_variable_width(info->regmap, AXP22X_PMIC_TEMP_H, 12); ++ *temp = (raw - 2667) * 100; ++ ret = 0; ++ break; ++ default: ++ ret = -EOPNOTSUPP; ++ break; ++ } ++ ++ return ret; ++} ++ ++static u32 axp813_adc_hwmon_chip_config[] = { ++ HWMON_C_REGISTER_TZ, ++ 0 ++}; ++ ++static const struct hwmon_channel_info axp813_adc_hwmon_chip = { ++ .type = hwmon_chip, ++ .config = axp813_adc_hwmon_chip_config, ++}; ++ ++static u32 axp813_adc_hwmon_temp_config[] = { ++ HWMON_T_INPUT, ++ 0 ++}; ++ ++ ++static const struct hwmon_channel_info axp813_adc_hwmon_temp = { ++ .type = hwmon_temp, ++ .config = axp813_adc_hwmon_temp_config, ++}; ++ ++ ++static const struct hwmon_channel_info *axp813_adc_hwmon_info[] = { ++ &axp813_adc_hwmon_chip, ++ &axp813_adc_hwmon_temp, ++ NULL ++}; ++ ++static const struct hwmon_ops axp813_adc_hwmon_hwmon_ops = { ++ .is_visible = axp813_adc_hwmon_is_visible, ++ .read = axp813_adc_hwmon_read, ++}; ++ ++static const struct hwmon_chip_info axp813_adc_hwmon_chip_info = { ++ .ops = &axp813_adc_hwmon_hwmon_ops, ++ .info = axp813_adc_hwmon_info, ++}; ++ + struct axp_data { + const struct iio_info *iio_info; + int num_channels; +@@ -627,6 +696,7 @@ struct axp_data { + unsigned long adc_en2_mask; + int (*adc_rate)(struct axp20x_adc_iio *info, + int rate); ++ bool hwmon_en; + struct iio_map *maps; + }; + +@@ -637,6 +707,7 @@ static const struct axp_data axp20x_data = { + .adc_en1_mask = AXP20X_ADC_EN1_MASK, + .adc_en2_mask = AXP20X_ADC_EN2_MASK, + .adc_rate = axp20x_adc_rate, ++ .hwmon_en = false, + .maps = axp20x_maps, + }; + +@@ -646,6 +717,7 @@ static const struct axp_data axp22x_data = { + .channels = axp22x_adc_channels, + .adc_en1_mask = AXP22X_ADC_EN1_MASK, + .adc_rate = axp22x_adc_rate, ++ .hwmon_en = false, + .maps = axp22x_maps, + }; + +@@ -655,6 +727,7 @@ static const struct axp_data axp813_data = { + .channels = axp813_adc_channels, + .adc_en1_mask = AXP22X_ADC_EN1_MASK, + .adc_rate = axp813_adc_rate, ++ .hwmon_en = true, + .maps = axp22x_maps, + }; + +@@ -737,8 +810,23 @@ static int axp20x_probe(struct platform_device *pdev) + goto fail_register; + } + ++ if (info->data->hwmon_en) { ++ /* Register hwmon device */ ++ struct device *hwmon_dev; ++ ++ hwmon_dev = devm_hwmon_device_register_with_info(&pdev->dev, "axp813_adc", info, &axp813_adc_hwmon_chip_info, NULL); ++ if (IS_ERR(hwmon_dev)) { ++ ret = PTR_ERR(hwmon_dev); ++ dev_err(&pdev->dev, "unable to register hwmon device %d\n", ret); ++ goto fail_hwmon; ++ } ++ } ++ + return 0; + ++fail_hwmon: ++ iio_device_unregister(indio_dev); ++ + fail_register: + iio_map_array_unregister(indio_dev); + +-- +2.34.1 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-iio-adc-sun4i-gpadc-iio-add-A64-thermal-sensor.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-iio-adc-sun4i-gpadc-iio-add-A64-thermal-sensor.patch new file mode 100644 index 0000000000..efacdac3eb --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-iio-adc-sun4i-gpadc-iio-add-A64-thermal-sensor.patch @@ -0,0 +1,86 @@ +From 4f1fe30625c077c4e9e2f79f81def3bc376baeba Mon Sep 17 00:00:00 2001 +From: Philipp Rossak +Date: Wed, 24 Jan 2018 17:41:45 +0100 +Subject: [PATCH 023/153] drv:iio: adc: sun4i-gpadc-iio: add A64 thermal sensor + +This patch adds support for the A64 ths sensor. + +The A64 supports interrupts. The interrupt is configured to update +the sensor values every second. + +Signed-off-by: Philipp Rossak +--- + drivers/iio/adc/sun4i-gpadc-iio.c | 50 +++++++++++++++++++++++++++++++ + 1 file changed, 50 insertions(+) + +diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c b/drivers/iio/adc/sun4i-gpadc-iio.c +index cc1547116..2889a7078 100644 +--- a/drivers/iio/adc/sun4i-gpadc-iio.c ++++ b/drivers/iio/adc/sun4i-gpadc-iio.c +@@ -243,6 +243,52 @@ static const struct gpadc_data sun9i_a80_ths_data = { + SUNXI_THS_TEMP_PERIOD(0x3a), + }; + ++static const struct gpadc_data sun50i_a64_ths_data = { ++ .temp_offset = -2170, ++ .temp_scale = -117, ++ .temp_data = {SUNXI_THS_TDATA0, ++ SUNXI_THS_TDATA1, ++ SUNXI_THS_TDATA2, ++ 0}, ++ .sample_start = sunxi_ths_sample_start, ++ .sample_end = sunxi_ths_sample_end, ++ .has_bus_clk = true, ++ .has_bus_rst = true, ++ .has_mod_clk = true, ++ .sensor_count = 3, ++ .supports_nvmem = false, ++ .support_irq = true, ++ ++ /* The final sample period is calculated as follows: ++ * (THERMAL_PER + 1) * 4096 / 24MHz * 2^(FILTER_TYPE + 1) ++ * ++ * This results to about 1Hz with these settings. ++ */ ++ .ctrl0_map = SUNXI_THS_ACQ0(0xff), ++ .ctrl2_map = SUNXI_THS_TEMP_SENSE_EN0 | ++ SUNXI_THS_TEMP_SENSE_EN1 | ++ SUNXI_THS_TEMP_SENSE_EN2 | ++ SUNXI_THS_ACQ1(0x3f), ++ .filter_map = SUNXI_THS_FILTER_EN | ++ SUNXI_THS_FILTER_TYPE(0x1), ++ .irq_clear_map = SUNXI_THS_INTS_ALARM_INT_0 | ++ SUNXI_THS_INTS_ALARM_INT_1 | ++ SUNXI_THS_INTS_ALARM_INT_2 | ++ SUNXI_THS_INTS_SHUT_INT_0 | ++ SUNXI_THS_INTS_SHUT_INT_1 | ++ SUNXI_THS_INTS_SHUT_INT_2 | ++ SUNXI_THS_INTS_TDATA_IRQ_0 | ++ SUNXI_THS_INTS_TDATA_IRQ_1 | ++ SUNXI_THS_INTS_TDATA_IRQ_2 | ++ SUNXI_THS_INTS_ALARM_OFF_0 | ++ SUNXI_THS_INTS_ALARM_OFF_1 | ++ SUNXI_THS_INTS_ALARM_OFF_2, ++ .irq_control_map = SUNXI_THS_INTC_TDATA_IRQ_EN0 | ++ SUNXI_THS_INTC_TDATA_IRQ_EN1 | ++ SUNXI_THS_INTC_TDATA_IRQ_EN2 | ++ SUNXI_THS_TEMP_PERIOD(0x7), ++}; ++ + struct sun4i_gpadc_iio { + struct iio_dev *indio_dev; + struct completion completion; +@@ -751,6 +797,10 @@ static const struct of_device_id sun4i_gpadc_of_id[] = { + .compatible = "allwinner,sun9i-a80-ths", + .data = &sun9i_a80_ths_data, + }, ++ { ++ .compatible = "allwinner,sun50i-a64-ths", ++ .data = &sun50i_a64_ths_data, ++ }, + { /* sentinel */ } + }; + +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-iio-adc-sun4i-gpadc-iio-add-A80-thermal-sensor.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-iio-adc-sun4i-gpadc-iio-add-A80-thermal-sensor.patch new file mode 100644 index 0000000000..941b6c7b4a --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-iio-adc-sun4i-gpadc-iio-add-A80-thermal-sensor.patch @@ -0,0 +1,85 @@ +From 3ecaf8cb5dff95072c3d6be273500b7205bd59e3 Mon Sep 17 00:00:00 2001 +From: Philipp Rossak +Date: Wed, 24 Jan 2018 17:28:02 +0100 +Subject: [PATCH 022/153] drv:iio:adc:sun4i-gpadc-iio: add A80 thermal sensor + +This patch adds support for the A80 ths sensor. + +The A80 has 4 sensors and supports interrupts. The interrupt is configured to update +the sensor values every second. The A80 shares some registers with the +integrated GPADC. ACQ0 must be set in the GPADC register with the offset +0x00. In fact the GPADC and the THS use the same register base and also +the same clocks and resets. + +Signed-off-by: Philipp Rossak +--- + drivers/iio/adc/sun4i-gpadc-iio.c | 46 +++++++++++++++++++++++++++++++ + 1 file changed, 46 insertions(+) + +diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c b/drivers/iio/adc/sun4i-gpadc-iio.c +index 775df17da..cc1547116 100644 +--- a/drivers/iio/adc/sun4i-gpadc-iio.c ++++ b/drivers/iio/adc/sun4i-gpadc-iio.c +@@ -201,6 +201,48 @@ static const struct gpadc_data sun8i_a83t_ths_data = { + SUNXI_THS_TEMP_PERIOD(0x257), + }; + ++static const struct gpadc_data sun9i_a80_ths_data = { ++ .temp_offset = -2794, ++ .temp_scale = -67, ++ .temp_data = {SUNXI_THS_TDATA0, ++ SUNXI_THS_TDATA1, ++ SUNXI_THS_TDATA2, ++ SUNXI_THS_TDATA3}, ++ .sample_start = sunxi_ths_sample_start, ++ .sample_end = sunxi_ths_sample_end, ++ .has_bus_clk = true, ++ .has_bus_rst = true, ++ .has_mod_clk = true, ++ .sensor_count = 4, ++ .supports_nvmem = false, ++ .support_irq = true, ++ .ctrl0_map = SUNXI_THS_ACQ0(0x1f3), ++ .ctrl2_map = SUNXI_THS_TEMP_SENSE_EN0 | ++ SUNXI_THS_TEMP_SENSE_EN1 | ++ SUNXI_THS_TEMP_SENSE_EN2 | ++ SUNXI_THS_TEMP_SENSE_EN3 | ++ SUNXI_THS_ACQ1(0x1f3), ++ .filter_map = SUNXI_THS_FILTER_EN | ++ SUNXI_THS_FILTER_TYPE(0x2), ++ .irq_clear_map = SUNXI_THS_INTS_ALARM_INT_0 | ++ SUNXI_THS_INTS_ALARM_INT_1 | ++ SUNXI_THS_INTS_ALARM_INT_2 | ++ SUNXI_THS_INTS_ALARM_INT_3 | ++ SUNXI_THS_INTS_SHUT_INT_0 | ++ SUNXI_THS_INTS_SHUT_INT_1 | ++ SUNXI_THS_INTS_SHUT_INT_2 | ++ SUNXI_THS_INTS_SHUT_INT_3 | ++ SUNXI_THS_INTS_TDATA_IRQ_0 | ++ SUNXI_THS_INTS_TDATA_IRQ_1 | ++ SUNXI_THS_INTS_TDATA_IRQ_2 | ++ SUNXI_THS_INTS_TDATA_IRQ_3, ++ .irq_control_map = SUNXI_THS_INTC_TDATA_IRQ_EN0 | ++ SUNXI_THS_INTC_TDATA_IRQ_EN1 | ++ SUNXI_THS_INTC_TDATA_IRQ_EN2 | ++ SUNXI_THS_INTC_TDATA_IRQ_EN3 | ++ SUNXI_THS_TEMP_PERIOD(0x3a), ++}; ++ + struct sun4i_gpadc_iio { + struct iio_dev *indio_dev; + struct completion completion; +@@ -705,6 +747,10 @@ static const struct of_device_id sun4i_gpadc_of_id[] = { + .compatible = "allwinner,sun8i-a83t-ths", + .data = &sun8i_a83t_ths_data, + }, ++ { ++ .compatible = "allwinner,sun9i-a80-ths", ++ .data = &sun9i_a80_ths_data, ++ }, + { /* sentinel */ } + }; + +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-iio-adc-sun4i-gpadc-iio-add-A83T-thermal-sensor.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-iio-adc-sun4i-gpadc-iio-add-A83T-thermal-sensor.patch new file mode 100644 index 0000000000..ce2d8b3c97 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-iio-adc-sun4i-gpadc-iio-add-A83T-thermal-sensor.patch @@ -0,0 +1,74 @@ +From 220d035797389f188a93a5cf231e67ed0915acda Mon Sep 17 00:00:00 2001 +From: Philipp Rossak +Date: Sun, 21 Jan 2018 18:50:11 +0100 +Subject: [PATCH 020/153] drv:iio:adc:sun4i-gpadc-iio: add A83T thermal sensor + +This patch adds support for the A83T ths sensor. + +The A83T does not support interrupts. This seems to be broken. +The calibration data is writen at the begin of the init process. + +Signed-off-by: Philipp Rossak +--- + drivers/iio/adc/sun4i-gpadc-iio.c | 38 +++++++++++++++++++++++++++++++ + 1 file changed, 38 insertions(+) + +diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c b/drivers/iio/adc/sun4i-gpadc-iio.c +index af0283369..775df17da 100644 +--- a/drivers/iio/adc/sun4i-gpadc-iio.c ++++ b/drivers/iio/adc/sun4i-gpadc-iio.c +@@ -167,6 +167,40 @@ static const struct gpadc_data sun8i_h3_ths_data = { + SUNXI_THS_TEMP_PERIOD(0x7), + }; + ++static const struct gpadc_data sun8i_a83t_ths_data = { ++ .temp_offset = -2724, ++ .temp_scale = -70, ++ .temp_data = {SUNXI_THS_TDATA0, ++ SUNXI_THS_TDATA1, ++ SUNXI_THS_TDATA2, ++ 0}, ++ .sample_start = sunxi_ths_sample_start, ++ .sample_end = sunxi_ths_sample_end, ++ .sensor_count = 3, ++ .supports_nvmem = false, ++ .support_irq = true, ++ .ctrl0_map = SUNXI_THS_ACQ0(0x1f3), ++ .ctrl2_map = SUNXI_THS_ACQ1(0x1f3), ++ .sensor_en_map = SUNXI_THS_TEMP_SENSE_EN0 | ++ SUNXI_THS_TEMP_SENSE_EN1 | ++ SUNXI_THS_TEMP_SENSE_EN2, ++ .filter_map = SUNXI_THS_FILTER_EN | ++ SUNXI_THS_FILTER_TYPE(0x2), ++ .irq_clear_map = SUNXI_THS_INTS_ALARM_INT_0 | ++ SUNXI_THS_INTS_ALARM_INT_1 | ++ SUNXI_THS_INTS_ALARM_INT_2 | ++ SUNXI_THS_INTS_SHUT_INT_0 | ++ SUNXI_THS_INTS_SHUT_INT_1 | ++ SUNXI_THS_INTS_SHUT_INT_2 | ++ SUNXI_THS_INTS_TDATA_IRQ_0 | ++ SUNXI_THS_INTS_TDATA_IRQ_1 | ++ SUNXI_THS_INTS_TDATA_IRQ_2, ++ .irq_control_map = SUNXI_THS_INTC_TDATA_IRQ_EN0 | ++ SUNXI_THS_INTC_TDATA_IRQ_EN1 | ++ SUNXI_THS_INTC_TDATA_IRQ_EN2 | ++ SUNXI_THS_TEMP_PERIOD(0x257), ++}; ++ + struct sun4i_gpadc_iio { + struct iio_dev *indio_dev; + struct completion completion; +@@ -667,6 +701,10 @@ static const struct of_device_id sun4i_gpadc_of_id[] = { + .compatible = "allwinner,sun8i-h3-ths", + .data = &sun8i_h3_ths_data, + }, ++ { ++ .compatible = "allwinner,sun8i-a83t-ths", ++ .data = &sun8i_a83t_ths_data, ++ }, + { /* sentinel */ } + }; + +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-iio-adc-sun4i-gpadc-iio-add-H3-thermal-sensor.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-iio-adc-sun4i-gpadc-iio-add-H3-thermal-sensor.patch new file mode 100644 index 0000000000..e2f0834fa7 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-iio-adc-sun4i-gpadc-iio-add-H3-thermal-sensor.patch @@ -0,0 +1,66 @@ +From ad5242c87933118bba5f661815b95688e7820b1c Mon Sep 17 00:00:00 2001 +From: Philipp Rossak +Date: Sun, 21 Jan 2018 23:14:09 +0100 +Subject: [PATCH 019/153] drv:iio:adc: sun4i-gpadc-iio: add H3 thermal sensor + +This patch adds support for the H3 ths sensor. + +The H3 supports interrupts. The interrupt is configured to update the +the sensor values every second. The calibration data is writen at the +begin of the init process. + +Signed-off-by: Philipp Rossak +--- + drivers/iio/adc/sun4i-gpadc-iio.c | 29 +++++++++++++++++++++++++++++ + 1 file changed, 29 insertions(+) + +diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c b/drivers/iio/adc/sun4i-gpadc-iio.c +index fd1f3a497..af0283369 100644 +--- a/drivers/iio/adc/sun4i-gpadc-iio.c ++++ b/drivers/iio/adc/sun4i-gpadc-iio.c +@@ -142,6 +142,31 @@ static const struct gpadc_data sun8i_a33_gpadc_data = { + .support_irq = false, + }; + ++static const struct gpadc_data sun8i_h3_ths_data = { ++ .temp_offset = -1791, ++ .temp_scale = -121, ++ .temp_data = {SUNXI_THS_TDATA0, 0, 0, 0}, ++ .sample_start = sunxi_ths_sample_start, ++ .sample_end = sunxi_ths_sample_end, ++ .has_bus_clk = true, ++ .has_bus_rst = true, ++ .has_mod_clk = true, ++ .sensor_count = 1, ++ .supports_nvmem = true, ++ .support_irq = true, ++ .ctrl0_map = SUNXI_THS_ACQ0(0xff), ++ .ctrl2_map = SUNXI_THS_ACQ1(0x3f), ++ .sensor_en_map = SUNXI_THS_TEMP_SENSE_EN0, ++ .filter_map = SUNXI_THS_FILTER_EN | ++ SUNXI_THS_FILTER_TYPE(0x2), ++ .irq_clear_map = SUNXI_THS_INTS_ALARM_INT_0 | ++ SUNXI_THS_INTS_SHUT_INT_0 | ++ SUNXI_THS_INTS_TDATA_IRQ_0 | ++ SUNXI_THS_INTS_ALARM_OFF_0, ++ .irq_control_map = SUNXI_THS_INTC_TDATA_IRQ_EN0 | ++ SUNXI_THS_TEMP_PERIOD(0x7), ++}; ++ + struct sun4i_gpadc_iio { + struct iio_dev *indio_dev; + struct completion completion; +@@ -638,6 +663,10 @@ static const struct of_device_id sun4i_gpadc_of_id[] = { + .compatible = "allwinner,sun8i-a33-ths", + .data = &sun8i_a33_gpadc_data, + }, ++ { ++ .compatible = "allwinner,sun8i-h3-ths", ++ .data = &sun8i_h3_ths_data, ++ }, + { /* sentinel */ } + }; + +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-iio-adc-sun4i-gpadc-iio-add-interrupt-support.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-iio-adc-sun4i-gpadc-iio-add-interrupt-support.patch new file mode 100644 index 0000000000..242062b3f3 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-iio-adc-sun4i-gpadc-iio-add-interrupt-support.patch @@ -0,0 +1,252 @@ +From 05cfa62b5c8748537a34181abcf6d73d7e8d8c7d Mon Sep 17 00:00:00 2001 +From: Philipp Rossak +Date: Sun, 21 Jan 2018 11:20:55 +0100 +Subject: [PATCH 018/153] drv:iio:adc:sun4i-gpadc-iio: add interrupt support + +This patch rewors the driver to support interrupts for the thermal part +of the sensor. + +This is only available for the newer sensor (currently H3 and A83T). +The interrupt will be trigerd on data available and triggers the update +for the thermal sensors. All newer sensors have different amount of +sensors and different interrupts for each device the reset of the +interrupts need to be done different + +For the newer sensors is the autosuspend disabled. + +Signed-off-by: Philipp Rossak +--- + drivers/iio/adc/sun4i-gpadc-iio.c | 68 ++++++++++++++++++++++++++++--- + include/linux/mfd/sun4i-gpadc.h | 33 +++++++++++++++ + 2 files changed, 95 insertions(+), 6 deletions(-) + +diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c b/drivers/iio/adc/sun4i-gpadc-iio.c +index b6723afca..fd1f3a497 100644 +--- a/drivers/iio/adc/sun4i-gpadc-iio.c ++++ b/drivers/iio/adc/sun4i-gpadc-iio.c +@@ -75,11 +75,14 @@ struct gpadc_data { + u32 ctrl2_map; + u32 sensor_en_map; + u32 filter_map; ++ u32 irq_clear_map; ++ u32 irq_control_map; + bool has_bus_clk; + bool has_bus_rst; + bool has_mod_clk; + int sensor_count; + bool supports_nvmem; ++ bool support_irq; + }; + + static const struct gpadc_data sun4i_gpadc_data = { +@@ -94,6 +97,7 @@ static const struct gpadc_data sun4i_gpadc_data = { + .sample_end = sun4i_gpadc_sample_end, + .sensor_count = 1, + .supports_nvmem = false, ++ .support_irq = false, + }; + + static const struct gpadc_data sun5i_gpadc_data = { +@@ -108,6 +112,7 @@ static const struct gpadc_data sun5i_gpadc_data = { + .sample_end = sun4i_gpadc_sample_end, + .sensor_count = 1, + .supports_nvmem = false, ++ .support_irq = false, + }; + + static const struct gpadc_data sun6i_gpadc_data = { +@@ -122,6 +127,7 @@ static const struct gpadc_data sun6i_gpadc_data = { + .sample_end = sun4i_gpadc_sample_end, + .sensor_count = 1, + .supports_nvmem = false, ++ .support_irq = false, + }; + + static const struct gpadc_data sun8i_a33_gpadc_data = { +@@ -133,6 +139,7 @@ static const struct gpadc_data sun8i_a33_gpadc_data = { + .sample_end = sun4i_gpadc_sample_end, + .sensor_count = 1, + .supports_nvmem = false, ++ .support_irq = false, + }; + + struct sun4i_gpadc_iio { +@@ -336,6 +343,11 @@ static int sun4i_gpadc_temp_read(struct iio_dev *indio_dev, int *val, + return 0; + } + ++ if (info->data->support_irq) { ++ regmap_read(info->regmap, info->data->temp_data[sensor], val); ++ return 0; ++ } ++ + return sun4i_gpadc_read(indio_dev, 0, val, info->temp_data_irq); + } + +@@ -433,6 +445,17 @@ static irqreturn_t sun4i_gpadc_fifo_data_irq_handler(int irq, void *dev_id) + return IRQ_HANDLED; + } + ++static irqreturn_t sunxi_irq_thread(int irq, void *data) ++{ ++ struct sun4i_gpadc_iio *info = data; ++ ++ regmap_write(info->regmap, SUNXI_THS_STAT, info->data->irq_clear_map); ++ ++ thermal_zone_device_update(info->tzd, THERMAL_EVENT_TEMP_SAMPLE); ++ ++ return IRQ_HANDLED; ++} ++ + static int sun4i_gpadc_sample_end(struct sun4i_gpadc_iio *info) + { + /* Disable the ADC on IP */ +@@ -445,6 +468,8 @@ static int sun4i_gpadc_sample_end(struct sun4i_gpadc_iio *info) + + static int sunxi_ths_sample_end(struct sun4i_gpadc_iio *info) + { ++ /* Disable ths interrupt*/ ++ regmap_write(info->regmap, SUNXI_THS_INTC, 0x0); + /* Disable temperature sensor */ + regmap_write(info->regmap, SUNXI_THS_CTRL2, 0x0); + +@@ -506,9 +531,15 @@ static int sunxi_ths_sample_start(struct sun4i_gpadc_iio *info) + regmap_write(info->regmap, SUNXI_THS_CTRL2, + info->data->ctrl2_map); + ++ regmap_write(info->regmap, SUNXI_THS_STAT, ++ info->data->irq_clear_map); ++ + regmap_write(info->regmap, SUNXI_THS_FILTER, + info->data->filter_map); + ++ regmap_write(info->regmap, SUNXI_THS_INTC, ++ info->data->irq_control_map); ++ + regmap_read(info->regmap, SUNXI_THS_CTRL2, &value); + + regmap_write(info->regmap, SUNXI_THS_CTRL2, +@@ -619,12 +650,29 @@ static int sun4i_gpadc_probe_dt(struct platform_device *pdev, + struct nvmem_cell *cell; + ssize_t cell_size; + u64 *cell_data; ++ int irq; + + info->data = of_device_get_match_data(&pdev->dev); + if (!info->data) + return -ENODEV; + +- info->no_irq = true; ++ if (info->data->support_irq) { ++ /* only the new versions of ths support right now irqs */ ++ irq = platform_get_irq(pdev, 0); ++ if (irq < 0) { ++ dev_err(&pdev->dev, "failed to get IRQ: %d\n", irq); ++ return irq; ++ } ++ ++ ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, ++ sunxi_irq_thread, IRQF_ONESHOT, ++ dev_name(&pdev->dev), info); ++ if (ret) ++ return ret; ++ ++ } else ++ info->no_irq = true; ++ + indio_dev->num_channels = ARRAY_SIZE(sun8i_a33_gpadc_channels); + indio_dev->channels = sun8i_a33_gpadc_channels; + +@@ -832,11 +880,13 @@ static int sun4i_gpadc_probe(struct platform_device *pdev) + if (ret) + return ret; + +- pm_runtime_set_autosuspend_delay(&pdev->dev, +- SUN4I_GPADC_AUTOSUSPEND_DELAY); +- pm_runtime_use_autosuspend(&pdev->dev); +- pm_runtime_set_suspended(&pdev->dev); +- pm_runtime_enable(&pdev->dev); ++ if (!info->data->support_irq) { ++ pm_runtime_set_autosuspend_delay(&pdev->dev, ++ SUN4I_GPADC_AUTOSUSPEND_DELAY); ++ pm_runtime_use_autosuspend(&pdev->dev); ++ pm_runtime_set_suspended(&pdev->dev); ++ pm_runtime_enable(&pdev->dev); ++ } + + if (IS_ENABLED(CONFIG_THERMAL_OF)) { + info->tzd = devm_thermal_of_zone_register(info->sensor_device, +@@ -860,6 +910,9 @@ static int sun4i_gpadc_probe(struct platform_device *pdev) + } + } + ++ if (info->data->support_irq) ++ info->data->sample_start(info); ++ + ret = devm_iio_device_register(&pdev->dev, indio_dev); + if (ret < 0) { + dev_err(&pdev->dev, "could not register the device\n"); +@@ -889,6 +942,9 @@ static int sun4i_gpadc_remove(struct platform_device *pdev) + if (!IS_ENABLED(CONFIG_THERMAL_OF)) + return 0; + ++ if (info->data->support_irq) ++ info->data->sample_end(info); ++ + if (!info->no_irq) + iio_map_array_unregister(indio_dev); + +diff --git a/include/linux/mfd/sun4i-gpadc.h b/include/linux/mfd/sun4i-gpadc.h +index 1439422b0..5c196e4a5 100644 +--- a/include/linux/mfd/sun4i-gpadc.h ++++ b/include/linux/mfd/sun4i-gpadc.h +@@ -86,6 +86,8 @@ + /* SUNXI_THS COMMON REGISTERS + DEFINES */ + #define SUNXI_THS_CTRL0 0x00 + #define SUNXI_THS_CTRL2 0x40 ++#define SUNXI_THS_INTC 0x44 ++#define SUNXI_THS_STAT 0x48 + #define SUNXI_THS_FILTER 0x70 + #define SUNXI_THS_CDATA_0_1 0x74 + #define SUNXI_THS_CDATA_2_3 0x78 +@@ -104,6 +106,37 @@ + #define SUNXI_THS_TEMP_SENSE_EN2 BIT(2) + #define SUNXI_THS_TEMP_SENSE_EN3 BIT(3) + ++#define SUNXI_THS_TEMP_PERIOD(x) (GENMASK(31, 12) & ((x) << 12)) ++ ++#define SUNXI_THS_INTS_ALARM_OFF_2 BIT(14) ++#define SUNXI_THS_INTS_ALARM_OFF_1 BIT(13) ++#define SUNXI_THS_INTS_ALARM_OFF_0 BIT(12) ++#define SUNXI_THS_INTS_TDATA_IRQ_3 BIT(11) ++#define SUNXI_THS_INTS_TDATA_IRQ_2 BIT(10) ++#define SUNXI_THS_INTS_TDATA_IRQ_1 BIT(9) ++#define SUNXI_THS_INTS_TDATA_IRQ_0 BIT(8) ++#define SUNXI_THS_INTS_SHUT_INT_3 BIT(7) ++#define SUNXI_THS_INTS_SHUT_INT_2 BIT(6) ++#define SUNXI_THS_INTS_SHUT_INT_1 BIT(5) ++#define SUNXI_THS_INTS_SHUT_INT_0 BIT(4) ++#define SUNXI_THS_INTS_ALARM_INT_3 BIT(3) ++#define SUNXI_THS_INTS_ALARM_INT_2 BIT(2) ++#define SUNXI_THS_INTS_ALARM_INT_1 BIT(1) ++#define SUNXI_THS_INTS_ALARM_INT_0 BIT(0) ++ ++#define SUNXI_THS_INTC_TDATA_IRQ_EN3 BIT(11) ++#define SUNXI_THS_INTC_TDATA_IRQ_EN2 BIT(10) ++#define SUNXI_THS_INTC_TDATA_IRQ_EN1 BIT(9) ++#define SUNXI_THS_INTC_TDATA_IRQ_EN0 BIT(8) ++#define SUNXI_THS_INTC_SHUT_INT_EN3 BIT(7) ++#define SUNXI_THS_INTC_SHUT_INT_EN2 BIT(6) ++#define SUNXI_THS_INTC_SHUT_INT_EN1 BIT(5) ++#define SUNXI_THS_INTC_SHUT_INT_EN0 BIT(4) ++#define SUNXI_THS_INTC_ALARM_INT_EN3 BIT(3) ++#define SUNXI_THS_INTC_ALARM_INT_EN2 BIT(2) ++#define SUNXI_THS_INTC_ALARM_INT_EN1 BIT(1) ++#define SUNXI_THS_INTC_ALARM_INT_EN0 BIT(0) ++ + #define MAX_SENSOR_COUNT 4 + + struct sun4i_gpadc_dev { +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-iio-adc-sun4i-gpadc-iio-multible-sensors-support.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-iio-adc-sun4i-gpadc-iio-multible-sensors-support.patch new file mode 100644 index 0000000000..8f2e0938eb --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-iio-adc-sun4i-gpadc-iio-multible-sensors-support.patch @@ -0,0 +1,182 @@ +From 34ac46e89ae9031cf99f998983c1889495de6eac Mon Sep 17 00:00:00 2001 +From: Philipp Rossak +Date: Sun, 21 Jan 2018 22:26:50 +0100 +Subject: [PATCH 016/153] drv:iio:adc:sun4i-gpadc-iio: multible sensors support + +For adding newer sensor some basic rework of the code is necessary. + +This patch reworks the driver to be able to handle more than one +thermal sensor. Newer SoC like the A80 have 4 thermal sensors. +Because of this the maximal sensor count value was set to 4. + +The sensor_id value is set during sensor registration and is for each +registered sensor indiviual. This makes it able to differntiate the +sensors when the value is read from the register. + +Signed-off-by: Philipp Rossak +--- + drivers/iio/adc/sun4i-gpadc-iio.c | 33 +++++++++++++++++++++---------- + include/linux/mfd/sun4i-gpadc.h | 6 ++++++ + 2 files changed, 29 insertions(+), 10 deletions(-) + +diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c b/drivers/iio/adc/sun4i-gpadc-iio.c +index ec0e1ced5..e42b357e5 100644 +--- a/drivers/iio/adc/sun4i-gpadc-iio.c ++++ b/drivers/iio/adc/sun4i-gpadc-iio.c +@@ -67,7 +67,7 @@ struct gpadc_data { + unsigned int tp_adc_select; + unsigned int (*adc_chan_select)(unsigned int chan); + unsigned int adc_chan_mask; +- unsigned int temp_data; ++ unsigned int temp_data[MAX_SENSOR_COUNT]; + int (*sample_start)(struct sun4i_gpadc_iio *info); + int (*sample_end)(struct sun4i_gpadc_iio *info); + u32 ctrl0_map; +@@ -77,6 +77,7 @@ struct gpadc_data { + bool has_bus_clk; + bool has_bus_rst; + bool has_mod_clk; ++ int sensor_count; + }; + + static const struct gpadc_data sun4i_gpadc_data = { +@@ -86,9 +87,10 @@ static const struct gpadc_data sun4i_gpadc_data = { + .tp_adc_select = SUN4I_GPADC_CTRL1_TP_ADC_SELECT, + .adc_chan_select = &sun4i_gpadc_chan_select, + .adc_chan_mask = SUN4I_GPADC_CTRL1_ADC_CHAN_MASK, +- .temp_data = SUN4I_GPADC_TEMP_DATA, ++ .temp_data = {SUN4I_GPADC_TEMP_DATA, 0, 0, 0}, + .sample_start = sun4i_gpadc_sample_start, + .sample_end = sun4i_gpadc_sample_end, ++ .sensor_count = 1, + }; + + static const struct gpadc_data sun5i_gpadc_data = { +@@ -98,9 +100,10 @@ static const struct gpadc_data sun5i_gpadc_data = { + .tp_adc_select = SUN4I_GPADC_CTRL1_TP_ADC_SELECT, + .adc_chan_select = &sun4i_gpadc_chan_select, + .adc_chan_mask = SUN4I_GPADC_CTRL1_ADC_CHAN_MASK, +- .temp_data = SUN4I_GPADC_TEMP_DATA, ++ .temp_data = {SUN4I_GPADC_TEMP_DATA, 0, 0, 0}, + .sample_start = sun4i_gpadc_sample_start, + .sample_end = sun4i_gpadc_sample_end, ++ .sensor_count = 1, + }; + + static const struct gpadc_data sun6i_gpadc_data = { +@@ -110,18 +113,20 @@ static const struct gpadc_data sun6i_gpadc_data = { + .tp_adc_select = SUN6I_GPADC_CTRL1_TP_ADC_SELECT, + .adc_chan_select = &sun6i_gpadc_chan_select, + .adc_chan_mask = SUN6I_GPADC_CTRL1_ADC_CHAN_MASK, +- .temp_data = SUN4I_GPADC_TEMP_DATA, ++ .temp_data = {SUN4I_GPADC_TEMP_DATA, 0, 0, 0}, + .sample_start = sun4i_gpadc_sample_start, + .sample_end = sun4i_gpadc_sample_end, ++ .sensor_count = 1, + }; + + static const struct gpadc_data sun8i_a33_gpadc_data = { + .temp_offset = -1662, + .temp_scale = 162, + .tp_mode_en = SUN8I_A33_GPADC_CTRL1_CHOP_TEMP_EN, +- .temp_data = SUN4I_GPADC_TEMP_DATA, ++ .temp_data = {SUN4I_GPADC_TEMP_DATA, 0, 0, 0}, + .sample_start = sun4i_gpadc_sample_start, + .sample_end = sun4i_gpadc_sample_end, ++ .sensor_count = 1, + }; + + struct sun4i_gpadc_iio { +@@ -139,6 +144,7 @@ struct sun4i_gpadc_iio { + struct clk *bus_clk; + struct clk *mod_clk; + struct reset_control *reset; ++ int sensor_id; + /* prevents concurrent reads of temperature and ADC */ + struct mutex mutex; + struct thermal_zone_device *tzd; +@@ -306,14 +312,15 @@ static int sun4i_gpadc_adc_read(struct iio_dev *indio_dev, int channel, + return sun4i_gpadc_read(indio_dev, channel, val, info->fifo_data_irq); + } + +-static int sun4i_gpadc_temp_read(struct iio_dev *indio_dev, int *val) ++static int sun4i_gpadc_temp_read(struct iio_dev *indio_dev, int *val, ++ int sensor) + { + struct sun4i_gpadc_iio *info = iio_priv(indio_dev); + + if (info->no_irq) { + pm_runtime_get_sync(indio_dev->dev.parent); + +- regmap_read(info->regmap, info->data->temp_data, val); ++ regmap_read(info->regmap, info->data->temp_data[sensor], val); + + pm_runtime_mark_last_busy(indio_dev->dev.parent); + pm_runtime_put_autosuspend(indio_dev->dev.parent); +@@ -360,7 +367,7 @@ static int sun4i_gpadc_read_raw(struct iio_dev *indio_dev, + ret = sun4i_gpadc_adc_read(indio_dev, chan->channel, + val); + else +- ret = sun4i_gpadc_temp_read(indio_dev, val); ++ ret = sun4i_gpadc_temp_read(indio_dev, val, 0); + + if (ret) + return ret; +@@ -508,7 +515,7 @@ static int sun4i_gpadc_get_temp(struct thermal_zone_device *tz, int *temp) + struct sun4i_gpadc_iio *info = tz->devdata; + int val, scale, offset; + +- if (sun4i_gpadc_temp_read(info->indio_dev, &val)) ++ if (sun4i_gpadc_temp_read(info->indio_dev, &val, info->sensor_id)) + return -ETIMEDOUT; + + sun4i_gpadc_temp_scale(info->indio_dev, &scale); +@@ -748,7 +755,7 @@ static int sun4i_gpadc_probe(struct platform_device *pdev) + { + struct sun4i_gpadc_iio *info; + struct iio_dev *indio_dev; +- int ret; ++ int ret, i; + + indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*info)); + if (!indio_dev) +@@ -783,6 +790,12 @@ static int sun4i_gpadc_probe(struct platform_device *pdev) + info->tzd = devm_thermal_of_zone_register(info->sensor_device, + 0, info, + &sun4i_ts_tz_ops); ++ for (i = 0; i < info->data->sensor_count; i++) { ++ info->sensor_id = i; ++ info->tzd = devm_thermal_of_zone_register( ++ info->sensor_device, ++ i, info, &sun4i_ts_tz_ops); ++ } + /* + * Do not fail driver probing when failing to register in + * thermal because no thermal DT node is found. +diff --git a/include/linux/mfd/sun4i-gpadc.h b/include/linux/mfd/sun4i-gpadc.h +index a7cd4c644..4b4415bf4 100644 +--- a/include/linux/mfd/sun4i-gpadc.h ++++ b/include/linux/mfd/sun4i-gpadc.h +@@ -87,6 +87,10 @@ + #define SUNXI_THS_CTRL0 0x00 + #define SUNXI_THS_CTRL2 0x40 + #define SUNXI_THS_FILTER 0x70 ++#define SUNXI_THS_TDATA0 0x80 ++#define SUNXI_THS_TDATA1 0x84 ++#define SUNXI_THS_TDATA2 0x88 ++#define SUNXI_THS_TDATA3 0x8c + + #define SUNXI_THS_FILTER_EN BIT(2) + #define SUNXI_THS_FILTER_TYPE(x) (GENMASK(1, 0) & (x)) +@@ -98,6 +102,8 @@ + #define SUNXI_THS_TEMP_SENSE_EN2 BIT(2) + #define SUNXI_THS_TEMP_SENSE_EN3 BIT(3) + ++#define MAX_SENSOR_COUNT 4 ++ + struct sun4i_gpadc_dev { + struct device *dev; + struct regmap *regmap; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-iio-adc-sun4i-gpadc-iio-rename-A33-specified-registers-to-c.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-iio-adc-sun4i-gpadc-iio-rename-A33-specified-registers-to-c.patch new file mode 100644 index 0000000000..58a9e9144e --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-iio-adc-sun4i-gpadc-iio-rename-A33-specified-registers-to-c.patch @@ -0,0 +1,56 @@ +From 8347d5b5405ab85f920da9338c64dec90a630aa8 Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Thu, 14 Sep 2017 22:52:47 +0800 +Subject: [PATCH 013/153] drv:iio:adc: sun4i-gpadc-iio: rename A33-specified + registers to contain A33 + +As the H3 SoC, which is also in sun8i line, has totally different +register map for the thermal sensor (a cut down version of GPADC), we +should rename A23/A33-specified registers to contain A33, in order to +prevent obfuscation with H3 registers. Currently these registers are +only prefixed "SUN8I", not "SUN8I_A33". + +Add "_A33" after "SUN8I" on the register names. + +Signed-off-by: Icenowy Zheng +Reviewed-by: Chen-Yu Tsai +Acked-by: Maxime Ripard +Acked-by: Lee Jones +--- + drivers/iio/adc/sun4i-gpadc-iio.c | 2 +- + include/linux/mfd/sun4i-gpadc.h | 6 +++--- + 2 files changed, 4 insertions(+), 4 deletions(-) + +diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c b/drivers/iio/adc/sun4i-gpadc-iio.c +index 60584a6ab..fc421a162 100644 +--- a/drivers/iio/adc/sun4i-gpadc-iio.c ++++ b/drivers/iio/adc/sun4i-gpadc-iio.c +@@ -85,7 +85,7 @@ static const struct gpadc_data sun6i_gpadc_data = { + static const struct gpadc_data sun8i_a33_gpadc_data = { + .temp_offset = -1662, + .temp_scale = 162, +- .tp_mode_en = SUN8I_GPADC_CTRL1_CHOP_TEMP_EN, ++ .tp_mode_en = SUN8I_A33_GPADC_CTRL1_CHOP_TEMP_EN, + }; + + struct sun4i_gpadc_iio { +diff --git a/include/linux/mfd/sun4i-gpadc.h b/include/linux/mfd/sun4i-gpadc.h +index 021f820f9..af79cfd9a 100644 +--- a/include/linux/mfd/sun4i-gpadc.h ++++ b/include/linux/mfd/sun4i-gpadc.h +@@ -35,9 +35,9 @@ + #define SUN6I_GPADC_CTRL1_ADC_CHAN_SELECT(x) (GENMASK(3, 0) & BIT(x)) + #define SUN6I_GPADC_CTRL1_ADC_CHAN_MASK GENMASK(3, 0) + +-/* TP_CTRL1 bits for sun8i SoCs */ +-#define SUN8I_GPADC_CTRL1_CHOP_TEMP_EN BIT(8) +-#define SUN8I_GPADC_CTRL1_GPADC_CALI_EN BIT(7) ++/* TP_CTRL1 bits for A33 */ ++#define SUN8I_A33_GPADC_CTRL1_CHOP_TEMP_EN BIT(8) ++#define SUN8I_A33_GPADC_CTRL1_GPADC_CALI_EN BIT(7) + + #define SUN4I_GPADC_CTRL2 0x08 + +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-iio-adc-sun4i-gpadc-iio-sampling-start-end-code-readout-reg.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-iio-adc-sun4i-gpadc-iio-sampling-start-end-code-readout-reg.patch new file mode 100644 index 0000000000..ad83f7bb8f --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-iio-adc-sun4i-gpadc-iio-sampling-start-end-code-readout-reg.patch @@ -0,0 +1,237 @@ +From 4184e4b8eb87b31c3f97ff9267006bbb43a64fa2 Mon Sep 17 00:00:00 2001 +From: Philipp Rossak +Date: Sat, 20 Jan 2018 14:03:10 +0100 +Subject: [PATCH 014/153] drv:iio:adc: sun4i-gpadc-iio: sampling start/end code + readout reg rework + +For adding newer sensor some basic rework of the code is necessary. + +This commit reworks the code and allows the sampling start/end code and +the position of value readout register to be altered. Later the start/end +functions will be used to configure the ths and start/stop the +sampling. + +Signed-off-by: Icenowy Zheng +Signed-off-by: Philipp Rossak +--- + drivers/iio/adc/sun4i-gpadc-iio.c | 87 ++++++++++++++++++++++++++++--- + include/linux/mfd/sun4i-gpadc.h | 19 +++++-- + 2 files changed, 94 insertions(+), 12 deletions(-) + +diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c b/drivers/iio/adc/sun4i-gpadc-iio.c +index fc421a162..e9bce34bf 100644 +--- a/drivers/iio/adc/sun4i-gpadc-iio.c ++++ b/drivers/iio/adc/sun4i-gpadc-iio.c +@@ -46,6 +46,18 @@ static unsigned int sun6i_gpadc_chan_select(unsigned int chan) + return SUN6I_GPADC_CTRL1_ADC_CHAN_SELECT(chan); + } + ++struct sun4i_gpadc_iio; ++ ++/* ++ * Prototypes for these functions, which enable these functions to be ++ * referenced in gpadc_data structures. ++ */ ++static int sun4i_gpadc_sample_start(struct sun4i_gpadc_iio *info); ++static int sun4i_gpadc_sample_end(struct sun4i_gpadc_iio *info); ++ ++static int sunxi_ths_sample_start(struct sun4i_gpadc_iio *info); ++static int sunxi_ths_sample_end(struct sun4i_gpadc_iio *info); ++ + struct gpadc_data { + int temp_offset; + int temp_scale; +@@ -53,6 +65,13 @@ struct gpadc_data { + unsigned int tp_adc_select; + unsigned int (*adc_chan_select)(unsigned int chan); + unsigned int adc_chan_mask; ++ unsigned int temp_data; ++ int (*sample_start)(struct sun4i_gpadc_iio *info); ++ int (*sample_end)(struct sun4i_gpadc_iio *info); ++ u32 ctrl0_map; ++ u32 ctrl2_map; ++ u32 sensor_en_map; ++ u32 filter_map; + }; + + static const struct gpadc_data sun4i_gpadc_data = { +@@ -62,6 +81,9 @@ static const struct gpadc_data sun4i_gpadc_data = { + .tp_adc_select = SUN4I_GPADC_CTRL1_TP_ADC_SELECT, + .adc_chan_select = &sun4i_gpadc_chan_select, + .adc_chan_mask = SUN4I_GPADC_CTRL1_ADC_CHAN_MASK, ++ .temp_data = SUN4I_GPADC_TEMP_DATA, ++ .sample_start = sun4i_gpadc_sample_start, ++ .sample_end = sun4i_gpadc_sample_end, + }; + + static const struct gpadc_data sun5i_gpadc_data = { +@@ -71,6 +93,9 @@ static const struct gpadc_data sun5i_gpadc_data = { + .tp_adc_select = SUN4I_GPADC_CTRL1_TP_ADC_SELECT, + .adc_chan_select = &sun4i_gpadc_chan_select, + .adc_chan_mask = SUN4I_GPADC_CTRL1_ADC_CHAN_MASK, ++ .temp_data = SUN4I_GPADC_TEMP_DATA, ++ .sample_start = sun4i_gpadc_sample_start, ++ .sample_end = sun4i_gpadc_sample_end, + }; + + static const struct gpadc_data sun6i_gpadc_data = { +@@ -80,12 +105,18 @@ static const struct gpadc_data sun6i_gpadc_data = { + .tp_adc_select = SUN6I_GPADC_CTRL1_TP_ADC_SELECT, + .adc_chan_select = &sun6i_gpadc_chan_select, + .adc_chan_mask = SUN6I_GPADC_CTRL1_ADC_CHAN_MASK, ++ .temp_data = SUN4I_GPADC_TEMP_DATA, ++ .sample_start = sun4i_gpadc_sample_start, ++ .sample_end = sun4i_gpadc_sample_end, + }; + + static const struct gpadc_data sun8i_a33_gpadc_data = { + .temp_offset = -1662, + .temp_scale = 162, + .tp_mode_en = SUN8I_A33_GPADC_CTRL1_CHOP_TEMP_EN, ++ .temp_data = SUN4I_GPADC_TEMP_DATA, ++ .sample_start = sun4i_gpadc_sample_start, ++ .sample_end = sun4i_gpadc_sample_end, + }; + + struct sun4i_gpadc_iio { +@@ -274,7 +305,7 @@ static int sun4i_gpadc_temp_read(struct iio_dev *indio_dev, int *val) + if (info->no_irq) { + pm_runtime_get_sync(indio_dev->dev.parent); + +- regmap_read(info->regmap, SUN4I_GPADC_TEMP_DATA, val); ++ regmap_read(info->regmap, info->data->temp_data, val); + + pm_runtime_mark_last_busy(indio_dev->dev.parent); + pm_runtime_put_autosuspend(indio_dev->dev.parent); +@@ -379,10 +410,8 @@ static irqreturn_t sun4i_gpadc_fifo_data_irq_handler(int irq, void *dev_id) + return IRQ_HANDLED; + } + +-static int sun4i_gpadc_runtime_suspend(struct device *dev) ++static int sun4i_gpadc_sample_end(struct sun4i_gpadc_iio *info) + { +- struct sun4i_gpadc_iio *info = iio_priv(dev_get_drvdata(dev)); +- + /* Disable the ADC on IP */ + regmap_write(info->regmap, SUN4I_GPADC_CTRL1, 0); + /* Disable temperature sensor on IP */ +@@ -391,19 +420,32 @@ static int sun4i_gpadc_runtime_suspend(struct device *dev) + return 0; + } + +-static int sun4i_gpadc_runtime_resume(struct device *dev) ++static int sunxi_ths_sample_end(struct sun4i_gpadc_iio *info) ++{ ++ /* Disable temperature sensor */ ++ regmap_write(info->regmap, SUNXI_THS_CTRL2, 0x0); ++ ++ return 0; ++} ++ ++static int sun4i_gpadc_runtime_suspend(struct device *dev) + { + struct sun4i_gpadc_iio *info = iio_priv(dev_get_drvdata(dev)); + ++ return info->data->sample_end(info); ++} ++ ++static int sun4i_gpadc_sample_start(struct sun4i_gpadc_iio *info) ++{ + /* clkin = 6MHz */ + regmap_write(info->regmap, SUN4I_GPADC_CTRL0, + SUN4I_GPADC_CTRL0_ADC_CLK_DIVIDER(2) | + SUN4I_GPADC_CTRL0_FS_DIV(7) | +- SUN4I_GPADC_CTRL0_T_ACQ(63)); ++ SUNXI_THS_ACQ0(63)); + regmap_write(info->regmap, SUN4I_GPADC_CTRL1, info->data->tp_mode_en); + regmap_write(info->regmap, SUN4I_GPADC_CTRL3, +- SUN4I_GPADC_CTRL3_FILTER_EN | +- SUN4I_GPADC_CTRL3_FILTER_TYPE(1)); ++ SUNXI_THS_FILTER_EN | ++ SUNXI_THS_FILTER_TYPE(1)); + /* period = SUN4I_GPADC_TPR_TEMP_PERIOD * 256 * 16 / clkin; ~0.6s */ + regmap_write(info->regmap, SUN4I_GPADC_TPR, + SUN4I_GPADC_TPR_TEMP_ENABLE | +@@ -412,6 +454,35 @@ static int sun4i_gpadc_runtime_resume(struct device *dev) + return 0; + } + ++static int sunxi_ths_sample_start(struct sun4i_gpadc_iio *info) ++{ ++ u32 value; ++ ++ if (info->data->ctrl0_map) ++ regmap_write(info->regmap, SUNXI_THS_CTRL0, ++ info->data->ctrl0_map); ++ ++ regmap_write(info->regmap, SUNXI_THS_CTRL2, ++ info->data->ctrl2_map); ++ ++ regmap_write(info->regmap, SUNXI_THS_FILTER, ++ info->data->filter_map); ++ ++ regmap_read(info->regmap, SUNXI_THS_CTRL2, &value); ++ ++ regmap_write(info->regmap, SUNXI_THS_CTRL2, ++ info->data->sensor_en_map | value); ++ ++ return 0; ++} ++ ++static int sun4i_gpadc_runtime_resume(struct device *dev) ++{ ++ struct sun4i_gpadc_iio *info = iio_priv(dev_get_drvdata(dev)); ++ ++ return info->data->sample_start(info); ++} ++ + static int sun4i_gpadc_get_temp(struct thermal_zone_device *tz, int *temp) + { + struct sun4i_gpadc_iio *info = tz->devdata; +diff --git a/include/linux/mfd/sun4i-gpadc.h b/include/linux/mfd/sun4i-gpadc.h +index af79cfd9a..a7cd4c644 100644 +--- a/include/linux/mfd/sun4i-gpadc.h ++++ b/include/linux/mfd/sun4i-gpadc.h +@@ -14,7 +14,6 @@ + #define SUN4I_GPADC_CTRL0_ADC_CLK_SELECT BIT(22) + #define SUN4I_GPADC_CTRL0_ADC_CLK_DIVIDER(x) ((GENMASK(1, 0) & (x)) << 20) + #define SUN4I_GPADC_CTRL0_FS_DIV(x) ((GENMASK(3, 0) & (x)) << 16) +-#define SUN4I_GPADC_CTRL0_T_ACQ(x) (GENMASK(15, 0) & (x)) + + #define SUN4I_GPADC_CTRL1 0x04 + +@@ -48,9 +47,6 @@ + + #define SUN4I_GPADC_CTRL3 0x0c + +-#define SUN4I_GPADC_CTRL3_FILTER_EN BIT(2) +-#define SUN4I_GPADC_CTRL3_FILTER_TYPE(x) (GENMASK(1, 0) & (x)) +- + #define SUN4I_GPADC_TPR 0x18 + + #define SUN4I_GPADC_TPR_TEMP_ENABLE BIT(16) +@@ -87,6 +83,21 @@ + /* 10s delay before suspending the IP */ + #define SUN4I_GPADC_AUTOSUSPEND_DELAY 10000 + ++/* SUNXI_THS COMMON REGISTERS + DEFINES */ ++#define SUNXI_THS_CTRL0 0x00 ++#define SUNXI_THS_CTRL2 0x40 ++#define SUNXI_THS_FILTER 0x70 ++ ++#define SUNXI_THS_FILTER_EN BIT(2) ++#define SUNXI_THS_FILTER_TYPE(x) (GENMASK(1, 0) & (x)) ++#define SUNXI_THS_ACQ0(x) (GENMASK(15, 0) & (x)) ++#define SUNXI_THS_ACQ1(x) (GENMASK(31, 16) & ((x) << 16)) ++ ++#define SUNXI_THS_TEMP_SENSE_EN0 BIT(0) ++#define SUNXI_THS_TEMP_SENSE_EN1 BIT(1) ++#define SUNXI_THS_TEMP_SENSE_EN2 BIT(2) ++#define SUNXI_THS_TEMP_SENSE_EN3 BIT(3) ++ + struct sun4i_gpadc_dev { + struct device *dev; + struct regmap *regmap; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-iio-adc-sun4i-gpadc-iio-support-clocks-and-reset.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-iio-adc-sun4i-gpadc-iio-support-clocks-and-reset.patch new file mode 100644 index 0000000000..d7039f91ff --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-iio-adc-sun4i-gpadc-iio-support-clocks-and-reset.patch @@ -0,0 +1,168 @@ +From 75d075a0a986637b253533e27145694aab8d71cd Mon Sep 17 00:00:00 2001 +From: Philipp Rossak +Date: Sun, 21 Jan 2018 22:23:00 +0100 +Subject: [PATCH 015/153] drv:iio:adc: sun4i-gpadc-iio: support clocks and + reset + +For adding newer sensor some basic rework of the code is necessary. + +The SoCs after H3 has newer thermal sensor ADCs, which have two clock +inputs (bus clock and sampling clock) and a reset. The registers are +also re-arranged. + +This commit reworks the code, adds the process of the clocks and +resets. + +Signed-off-by: Philipp Rossak +Signed-off-by: Icenowy Zheng +--- + drivers/iio/adc/sun4i-gpadc-iio.c | 80 +++++++++++++++++++++++++++++++ + 1 file changed, 80 insertions(+) + +diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c b/drivers/iio/adc/sun4i-gpadc-iio.c +index e9bce34bf..ec0e1ced5 100644 +--- a/drivers/iio/adc/sun4i-gpadc-iio.c ++++ b/drivers/iio/adc/sun4i-gpadc-iio.c +@@ -19,6 +19,7 @@ + * shutdown for not being used. + */ + ++#include + #include + #include + #include +@@ -28,6 +29,7 @@ + #include + #include + #include ++#include + #include + #include + +@@ -72,6 +74,9 @@ struct gpadc_data { + u32 ctrl2_map; + u32 sensor_en_map; + u32 filter_map; ++ bool has_bus_clk; ++ bool has_bus_rst; ++ bool has_mod_clk; + }; + + static const struct gpadc_data sun4i_gpadc_data = { +@@ -131,6 +136,9 @@ struct sun4i_gpadc_iio { + atomic_t ignore_temp_data_irq; + const struct gpadc_data *data; + bool no_irq; ++ struct clk *bus_clk; ++ struct clk *mod_clk; ++ struct reset_control *reset; + /* prevents concurrent reads of temperature and ADC */ + struct mutex mutex; + struct thermal_zone_device *tzd; +@@ -432,6 +440,12 @@ static int sun4i_gpadc_runtime_suspend(struct device *dev) + { + struct sun4i_gpadc_iio *info = iio_priv(dev_get_drvdata(dev)); + ++ if (info->data->has_mod_clk) ++ clk_disable(info->mod_clk); ++ ++ if (info->data->has_bus_clk) ++ clk_disable(info->bus_clk); ++ + return info->data->sample_end(info); + } + +@@ -480,6 +494,12 @@ static int sun4i_gpadc_runtime_resume(struct device *dev) + { + struct sun4i_gpadc_iio *info = iio_priv(dev_get_drvdata(dev)); + ++ if (info->data->has_mod_clk) ++ clk_enable(info->mod_clk); ++ ++ if (info->data->has_bus_clk) ++ clk_enable(info->bus_clk); ++ + return info->data->sample_start(info); + } + +@@ -590,10 +610,61 @@ static int sun4i_gpadc_probe_dt(struct platform_device *pdev, + return ret; + } + ++ if (info->data->has_bus_rst) { ++ info->reset = devm_reset_control_get(&pdev->dev, NULL); ++ if (IS_ERR(info->reset)) { ++ ret = PTR_ERR(info->reset); ++ return ret; ++ } ++ ++ ret = reset_control_deassert(info->reset); ++ if (ret) ++ return ret; ++ } ++ ++ if (info->data->has_bus_clk) { ++ info->bus_clk = devm_clk_get(&pdev->dev, "bus"); ++ if (IS_ERR(info->bus_clk)) { ++ ret = PTR_ERR(info->bus_clk); ++ goto assert_reset; ++ } ++ ++ ret = clk_prepare_enable(info->bus_clk); ++ if (ret) ++ goto assert_reset; ++ } ++ ++ if (info->data->has_mod_clk) { ++ info->mod_clk = devm_clk_get(&pdev->dev, "mod"); ++ if (IS_ERR(info->mod_clk)) { ++ ret = PTR_ERR(info->mod_clk); ++ goto disable_bus_clk; ++ } ++ ++ /* Running at 6MHz */ ++ ret = clk_set_rate(info->mod_clk, 4000000); ++ if (ret) ++ goto disable_bus_clk; ++ ++ ret = clk_prepare_enable(info->mod_clk); ++ if (ret) ++ goto disable_bus_clk; ++ } ++ + if (IS_ENABLED(CONFIG_THERMAL_OF)) + info->sensor_device = &pdev->dev; + + return 0; ++ ++disable_bus_clk: ++ if (info->data->has_bus_clk) ++ clk_disable_unprepare(info->bus_clk); ++ ++assert_reset: ++ if (info->data->has_bus_rst) ++ reset_control_assert(info->reset); ++ ++ return ret; + } + + static int sun4i_gpadc_probe_mfd(struct platform_device *pdev, +@@ -756,6 +827,15 @@ static int sun4i_gpadc_remove(struct platform_device *pdev) + if (!info->no_irq) + iio_map_array_unregister(indio_dev); + ++ if (info->data->has_mod_clk) ++ clk_disable_unprepare(info->mod_clk); ++ ++ if (info->data->has_bus_clk) ++ clk_disable_unprepare(info->bus_clk); ++ ++ if (info->data->has_bus_rst) ++ reset_control_assert(info->reset); ++ + return 0; + } + +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-iio-adc-sun4i-gpadc-iio-support-nvmem-calibration-data.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-iio-adc-sun4i-gpadc-iio-support-nvmem-calibration-data.patch new file mode 100644 index 0000000000..71f5f582d4 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-iio-adc-sun4i-gpadc-iio-support-nvmem-calibration-data.patch @@ -0,0 +1,166 @@ +From 10e3aadc5c25cae9f7d8ea86faa3082f78307fb2 Mon Sep 17 00:00:00 2001 +From: Philipp Rossak +Date: Sun, 21 Jan 2018 22:29:55 +0100 +Subject: [PATCH 017/153] drv:iio:adc:sun4i-gpadc-iio: support nvmem + calibration data + +This patch reworks the driver to support nvmem calibration cells. +The driver checks if the nvmem calibration is supported and reads out +the nvmem. At the beginning of the startup process the calibration data +is written to the related registers. + +Signed-off-by: Philipp Rossak +--- + drivers/iio/adc/sun4i-gpadc-iio.c | 52 +++++++++++++++++++++++++++++++ + include/linux/mfd/sun4i-gpadc.h | 2 ++ + 2 files changed, 54 insertions(+) + +diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c b/drivers/iio/adc/sun4i-gpadc-iio.c +index e42b357e5..b6723afca 100644 +--- a/drivers/iio/adc/sun4i-gpadc-iio.c ++++ b/drivers/iio/adc/sun4i-gpadc-iio.c +@@ -24,6 +24,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -78,6 +79,7 @@ struct gpadc_data { + bool has_bus_rst; + bool has_mod_clk; + int sensor_count; ++ bool supports_nvmem; + }; + + static const struct gpadc_data sun4i_gpadc_data = { +@@ -91,6 +93,7 @@ static const struct gpadc_data sun4i_gpadc_data = { + .sample_start = sun4i_gpadc_sample_start, + .sample_end = sun4i_gpadc_sample_end, + .sensor_count = 1, ++ .supports_nvmem = false, + }; + + static const struct gpadc_data sun5i_gpadc_data = { +@@ -104,6 +107,7 @@ static const struct gpadc_data sun5i_gpadc_data = { + .sample_start = sun4i_gpadc_sample_start, + .sample_end = sun4i_gpadc_sample_end, + .sensor_count = 1, ++ .supports_nvmem = false, + }; + + static const struct gpadc_data sun6i_gpadc_data = { +@@ -117,6 +121,7 @@ static const struct gpadc_data sun6i_gpadc_data = { + .sample_start = sun4i_gpadc_sample_start, + .sample_end = sun4i_gpadc_sample_end, + .sensor_count = 1, ++ .supports_nvmem = false, + }; + + static const struct gpadc_data sun8i_a33_gpadc_data = { +@@ -127,6 +132,7 @@ static const struct gpadc_data sun8i_a33_gpadc_data = { + .sample_start = sun4i_gpadc_sample_start, + .sample_end = sun4i_gpadc_sample_end, + .sensor_count = 1, ++ .supports_nvmem = false, + }; + + struct sun4i_gpadc_iio { +@@ -145,6 +151,8 @@ struct sun4i_gpadc_iio { + struct clk *mod_clk; + struct reset_control *reset; + int sensor_id; ++ u32 calibration_data[2]; ++ bool has_calibration_data[2]; + /* prevents concurrent reads of temperature and ADC */ + struct mutex mutex; + struct thermal_zone_device *tzd; +@@ -456,6 +464,17 @@ static int sun4i_gpadc_runtime_suspend(struct device *dev) + return info->data->sample_end(info); + } + ++static void sunxi_calibrate(struct sun4i_gpadc_iio *info) ++{ ++ if (info->has_calibration_data[0]) ++ regmap_write(info->regmap, SUNXI_THS_CDATA_0_1, ++ info->calibration_data[0]); ++ ++ if (info->has_calibration_data[1]) ++ regmap_write(info->regmap, SUNXI_THS_CDATA_2_3, ++ info->calibration_data[1]); ++} ++ + static int sun4i_gpadc_sample_start(struct sun4i_gpadc_iio *info) + { + /* clkin = 6MHz */ +@@ -478,6 +497,7 @@ static int sun4i_gpadc_sample_start(struct sun4i_gpadc_iio *info) + static int sunxi_ths_sample_start(struct sun4i_gpadc_iio *info) + { + u32 value; ++ sunxi_calibrate(info); + + if (info->data->ctrl0_map) + regmap_write(info->regmap, SUNXI_THS_CTRL0, +@@ -596,6 +616,9 @@ static int sun4i_gpadc_probe_dt(struct platform_device *pdev, + struct sun4i_gpadc_iio *info = iio_priv(indio_dev); + void __iomem *base; + int ret; ++ struct nvmem_cell *cell; ++ ssize_t cell_size; ++ u64 *cell_data; + + info->data = of_device_get_match_data(&pdev->dev); + if (!info->data) +@@ -609,6 +632,35 @@ static int sun4i_gpadc_probe_dt(struct platform_device *pdev, + if (IS_ERR(base)) + return PTR_ERR(base); + ++ info->has_calibration_data[0] = false; ++ info->has_calibration_data[1] = false; ++ ++ if (!info->data->supports_nvmem) ++ goto no_nvmem; ++ ++ cell = devm_nvmem_cell_get(&pdev->dev, "calibration"); ++ if (IS_ERR(cell)) { ++ if (PTR_ERR(cell) == -EPROBE_DEFER) ++ return PTR_ERR(cell); ++ } else { ++ cell_data = (u64 *)nvmem_cell_read(cell, &cell_size); ++ devm_nvmem_cell_put(&pdev->dev, cell); ++ if (cell_size <= 4) { ++ info->has_calibration_data[0] = true; ++ info->calibration_data[0] = be32_to_cpu(cell_data[0] & ++ GENMASK(31, 0)); ++ } else if (cell_size <= 8) { ++ info->has_calibration_data[0] = true; ++ info->calibration_data[0] = be32_to_cpu(cell_data[0] & ++ GENMASK(31, 0)); ++ info->has_calibration_data[1] = true; ++ info->calibration_data[1] = be32_to_cpu( ++ (cell_data[0] >> 32) & GENMASK(31, 0)); ++ } ++ } ++ ++no_nvmem: ++ + info->regmap = devm_regmap_init_mmio(&pdev->dev, base, + &sun4i_gpadc_regmap_config); + if (IS_ERR(info->regmap)) { +diff --git a/include/linux/mfd/sun4i-gpadc.h b/include/linux/mfd/sun4i-gpadc.h +index 4b4415bf4..1439422b0 100644 +--- a/include/linux/mfd/sun4i-gpadc.h ++++ b/include/linux/mfd/sun4i-gpadc.h +@@ -87,6 +87,8 @@ + #define SUNXI_THS_CTRL0 0x00 + #define SUNXI_THS_CTRL2 0x40 + #define SUNXI_THS_FILTER 0x70 ++#define SUNXI_THS_CDATA_0_1 0x74 ++#define SUNXI_THS_CDATA_2_3 0x78 + #define SUNXI_THS_TDATA0 0x80 + #define SUNXI_THS_TDATA1 0x84 + #define SUNXI_THS_TDATA2 0x88 +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-iio-sun4i-gpadc-iio-don-t-force-poweroff.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-iio-sun4i-gpadc-iio-don-t-force-poweroff.patch new file mode 100644 index 0000000000..71e6ad7b1b --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-iio-sun4i-gpadc-iio-don-t-force-poweroff.patch @@ -0,0 +1,32 @@ +From 0d1d6858945e92f61409039ea7f6dd88b562e9ef Mon Sep 17 00:00:00 2001 +From: Vasily Khoruzhick +Date: Tue, 24 Apr 2018 22:21:10 -0700 +Subject: [PATCH 024/153] drv:iio:sun4i-gpadc-iio: don`t force poweroff + +ignore zero samples to avoid force poweroff when reading first sample + +Signed-off-by: Vasily Khoruzhick +--- + drivers/iio/adc/sun4i-gpadc-iio.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c b/drivers/iio/adc/sun4i-gpadc-iio.c +index 2889a7078..ead5d9f4d 100644 +--- a/drivers/iio/adc/sun4i-gpadc-iio.c ++++ b/drivers/iio/adc/sun4i-gpadc-iio.c +@@ -716,6 +716,12 @@ static int sun4i_gpadc_get_temp(struct thermal_zone_device *tz, int *temp) + if (sun4i_gpadc_temp_read(info->indio_dev, &val, info->sensor_id)) + return -ETIMEDOUT; + ++ /* Ignore first sample which is always zero. 0 is either too ++ * cold or too hot, so we can safely ignore it ++ */ ++ if (val == 0) ++ return -ETIMEDOUT; ++ + sun4i_gpadc_temp_scale(info->indio_dev, &scale); + sun4i_gpadc_temp_offset(info->indio_dev, &offset); + +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-input-touchscreen-sun4i-ts-Enable-parsing.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-input-touchscreen-sun4i-ts-Enable-parsing.patch new file mode 100644 index 0000000000..00b0ff0567 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-input-touchscreen-sun4i-ts-Enable-parsing.patch @@ -0,0 +1,63 @@ +From aa082564f745db2876d0530b81f0ff0e54c3ad54 Mon Sep 17 00:00:00 2001 +From: Mitko Gamishev +Date: Wed, 5 Feb 2020 15:18:04 +0200 +Subject: [PATCH 048/153] drv:input:touchscreen:sun4i-ts Enable parsing + +--- + drivers/input/touchscreen/sun4i-ts.c | 19 +++++++++++++++---- + 1 file changed, 15 insertions(+), 4 deletions(-) + +diff --git a/drivers/input/touchscreen/sun4i-ts.c b/drivers/input/touchscreen/sun4i-ts.c +index 73eb8f80b..da29f38bb 100644 +--- a/drivers/input/touchscreen/sun4i-ts.c ++++ b/drivers/input/touchscreen/sun4i-ts.c +@@ -32,6 +32,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -106,6 +107,7 @@ + struct sun4i_ts_data { + struct device *dev; + struct input_dev *input; ++ struct touchscreen_properties prop; + void __iomem *base; + unsigned int irq; + bool ignore_fifo_data; +@@ -123,8 +125,8 @@ static void sun4i_ts_irq_handle_input(struct sun4i_ts_data *ts, u32 reg_val) + y = readl(ts->base + TP_DATA); + /* The 1st location reported after an up event is unreliable */ + if (!ts->ignore_fifo_data) { +- input_report_abs(ts->input, ABS_X, x); +- input_report_abs(ts->input, ABS_Y, y); ++ touchscreen_report_pos(ts->input, &ts->prop, x, y, false); ++ + /* + * The hardware has a separate down status bit, but + * that gets set before we get the first location, +@@ -296,8 +298,17 @@ static int sun4i_ts_probe(struct platform_device *pdev) + ts->input->id.version = 0x0100; + ts->input->evbit[0] = BIT(EV_SYN) | BIT(EV_KEY) | BIT(EV_ABS); + __set_bit(BTN_TOUCH, ts->input->keybit); +- input_set_abs_params(ts->input, ABS_X, 0, 4095, 0, 0); +- input_set_abs_params(ts->input, ABS_Y, 0, 4095, 0, 0); ++ ++ touchscreen_parse_properties(ts->input, false, &ts->prop); ++ ++ if (!ts->prop.max_x || !ts->prop.max_y) { ++ dev_info(&pdev->dev, "Invalid configuration, using defaults\n"); ++ ts->prop.max_x = 4095; ++ ts->prop.max_y = 4095; ++ } ++ ++ input_set_abs_params(ts->input, ABS_X, 0, ts->prop.max_x, 0, 0); ++ input_set_abs_params(ts->input, ABS_Y, 0, ts->prop.max_y, 0, 0); + input_set_drvdata(ts->input, ts); + } + +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-media-cedrus-10-bit-HEVC-support.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-media-cedrus-10-bit-HEVC-support.patch new file mode 100644 index 0000000000..c6163cfe04 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-media-cedrus-10-bit-HEVC-support.patch @@ -0,0 +1,170 @@ +From ab73d1a2cb44c65cc5547dcef7a286c108c05ec1 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sun, 15 Mar 2020 21:35:39 +0100 +Subject: [PATCH 039/170] drv:media:cedrus: 10-bit HEVC support + +WIp: 10-bit HEVC support + +Signed-off-by: Jernej Skrabec +--- + drivers/staging/media/sunxi/cedrus/cedrus.c | 4 +-- + .../staging/media/sunxi/cedrus/cedrus_h265.c | 12 ++++++++ + .../staging/media/sunxi/cedrus/cedrus_regs.h | 4 +++ + .../staging/media/sunxi/cedrus/cedrus_video.c | 30 +++++++++++++++---- + .../staging/media/sunxi/cedrus/cedrus_video.h | 2 +- + 5 files changed, 44 insertions(+), 8 deletions(-) + +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.c b/drivers/staging/media/sunxi/cedrus/cedrus.c +index 0c67e1ee3..98487d8fe 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus.c ++++ b/drivers/staging/media/sunxi/cedrus/cedrus.c +@@ -336,7 +336,7 @@ static int cedrus_open(struct file *file) + goto err_ctrls; + } + ctx->dst_fmt.pixelformat = V4L2_PIX_FMT_NV12_32L32; +- cedrus_prepare_format(&ctx->dst_fmt); ++ cedrus_prepare_format(&ctx->dst_fmt, 0); + ctx->src_fmt.pixelformat = V4L2_PIX_FMT_MPEG2_SLICE; + /* + * TILED_NV12 has more strict requirements, so copy the width and +@@ -344,7 +344,7 @@ static int cedrus_open(struct file *file) + */ + ctx->src_fmt.width = ctx->dst_fmt.width; + ctx->src_fmt.height = ctx->dst_fmt.height; +- cedrus_prepare_format(&ctx->src_fmt); ++ cedrus_prepare_format(&ctx->src_fmt, 0); + + v4l2_fh_add(&ctx->fh); + +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c +index 908bccde2..422046a6a 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c +@@ -562,6 +562,18 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, + + cedrus_write(dev, VE_DEC_H265_DEC_PCM_CTRL, reg); + ++ if (sps->bit_depth_luma_minus8 == 2) { ++ unsigned int size; ++ ++ size = ALIGN(ctx->src_fmt.width, 16) * ALIGN(ctx->src_fmt.height, 16); ++ ++ reg = (size * 3) / 2; ++ cedrus_write(dev, VE_DEC_H265_OFFSET_ADDR_FIRST_OUT, reg); ++ ++ reg = DIV_ROUND_UP(ctx->src_fmt.width, 4); ++ cedrus_write(dev, VE_DEC_H265_10BIT_CONFIGURE, ALIGN(reg, 32)); ++ } ++ + /* PPS. */ + + reg = VE_DEC_H265_DEC_PPS_CTRL0_PPS_CR_QP_OFFSET(pps->pps_cr_qp_offset) | +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h +index bdb062ad8..7ab3a2b0a 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h +@@ -498,6 +498,10 @@ + + #define VE_DEC_H265_LOW_ADDR (VE_ENGINE_DEC_H265 + 0x80) + ++#define VE_DEC_H265_OFFSET_ADDR_FIRST_OUT (VE_ENGINE_DEC_H265 + 0x84) ++#define VE_DEC_H265_OFFSET_ADDR_SECOND_OUT (VE_ENGINE_DEC_H265 + 0x88) ++#define VE_DEC_H265_10BIT_CONFIGURE (VE_ENGINE_DEC_H265 + 0x8c) ++ + #define VE_DEC_H265_LOW_ADDR_PRIMARY_CHROMA(a) \ + SHIFT_AND_MASK_BITS(a, 31, 24) + #define VE_DEC_H265_LOW_ADDR_SECONDARY_CHROMA(a) \ +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_video.c b/drivers/staging/media/sunxi/cedrus/cedrus_video.c +index 9bb82c8e0..2a4fcc9c9 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus_video.c ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_video.c +@@ -100,7 +100,7 @@ static struct cedrus_format *cedrus_find_format(u32 pixelformat, u32 directions, + return &cedrus_formats[i]; + } + +-void cedrus_prepare_format(struct v4l2_pix_format *pix_fmt) ++void cedrus_prepare_format(struct v4l2_pix_format *pix_fmt, int extended) + { + unsigned int width = pix_fmt->width; + unsigned int height = pix_fmt->height; +@@ -155,6 +155,17 @@ void cedrus_prepare_format(struct v4l2_pix_format *pix_fmt) + break; + } + ++ if (extended) { ++ unsigned int extra_size; ++ ++ extra_size = DIV_ROUND_UP(pix_fmt->width, 4); ++ extra_size = ALIGN(extra_size, 32); ++ extra_size *= ALIGN(pix_fmt->height, 16) * 3; ++ extra_size /= 2; ++ ++ sizeimage += extra_size; ++ } ++ + pix_fmt->width = width; + pix_fmt->height = height; + +@@ -247,17 +258,27 @@ static int cedrus_try_fmt_vid_cap(struct file *file, void *priv, + struct cedrus_ctx *ctx = cedrus_file2ctx(file); + struct cedrus_dev *dev = ctx->dev; + struct v4l2_pix_format *pix_fmt = &f->fmt.pix; ++ const struct v4l2_ctrl_hevc_sps *sps; + struct cedrus_format *fmt = + cedrus_find_format(pix_fmt->pixelformat, CEDRUS_DECODE_DST, + dev->capabilities); ++ int extended; + + if (!fmt) + return -EINVAL; + ++ sps = cedrus_find_control_data(ctx, V4L2_CID_MPEG_VIDEO_HEVC_SPS); ++ ++ /* The 10-bitHEVC decoder needs extra size on the output buffer. */ ++ extended = ctx->src_fmt.pixelformat == V4L2_PIX_FMT_HEVC_SLICE && ++ sps->bit_depth_luma_minus8 == 2; ++ + pix_fmt->pixelformat = fmt->pixelformat; + pix_fmt->width = ctx->src_fmt.width; + pix_fmt->height = ctx->src_fmt.height; +- cedrus_prepare_format(pix_fmt); ++ ++ pix_fmt->pixelformat = fmt->pixelformat; ++ cedrus_prepare_format(pix_fmt, extended); + + return 0; + } +@@ -275,8 +296,7 @@ static int cedrus_try_fmt_vid_out(struct file *file, void *priv, + if (!fmt) + return -EINVAL; + +- pix_fmt->pixelformat = fmt->pixelformat; +- cedrus_prepare_format(pix_fmt); ++ cedrus_prepare_format(pix_fmt, 0); + + return 0; + } +@@ -357,7 +377,7 @@ static int cedrus_s_fmt_vid_out(struct file *file, void *priv, + ctx->dst_fmt.quantization = f->fmt.pix.quantization; + ctx->dst_fmt.width = ctx->src_fmt.width; + ctx->dst_fmt.height = ctx->src_fmt.height; +- cedrus_prepare_format(&ctx->dst_fmt); ++ cedrus_prepare_format(&ctx->dst_fmt, 0); + + return 0; + } +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_video.h b/drivers/staging/media/sunxi/cedrus/cedrus_video.h +index 05050c0a0..d42e4ebf6 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus_video.h ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_video.h +@@ -26,6 +26,6 @@ extern const struct v4l2_ioctl_ops cedrus_ioctl_ops; + + int cedrus_queue_init(void *priv, struct vb2_queue *src_vq, + struct vb2_queue *dst_vq); +-void cedrus_prepare_format(struct v4l2_pix_format *pix_fmt); ++void cedrus_prepare_format(struct v4l2_pix_format *pix_fmt, int extended); + + #endif +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-media-cedrus-Add-callback-for-buffer-cleanup.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-media-cedrus-Add-callback-for-buffer-cleanup.patch new file mode 100644 index 0000000000..1d57306816 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-media-cedrus-Add-callback-for-buffer-cleanup.patch @@ -0,0 +1,57 @@ +From 5ea9d06c14e2c254e90a36cc97e6e8cdd86a9b66 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sat, 9 Nov 2019 13:06:15 +0100 +Subject: [PATCH 034/170] drv:media: cedrus: Add callback for buffer cleanup + +Signed-off-by: Jernej Skrabec +--- + drivers/staging/media/sunxi/cedrus/cedrus.h | 1 + + drivers/staging/media/sunxi/cedrus/cedrus_video.c | 13 +++++++++++++ + 2 files changed, 14 insertions(+) + +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.h b/drivers/staging/media/sunxi/cedrus/cedrus.h +index 9d34e5785..0a17ed0dc 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus.h ++++ b/drivers/staging/media/sunxi/cedrus/cedrus.h +@@ -168,6 +168,7 @@ struct cedrus_dec_ops { + int (*start)(struct cedrus_ctx *ctx); + void (*stop)(struct cedrus_ctx *ctx); + void (*trigger)(struct cedrus_ctx *ctx); ++ void (*buf_cleanup)(struct cedrus_ctx *ctx, struct cedrus_buffer *buf); + }; + + struct cedrus_variant { +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_video.c b/drivers/staging/media/sunxi/cedrus/cedrus_video.c +index 33726175d..9bb82c8e0 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus_video.c ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_video.c +@@ -469,6 +469,18 @@ static int cedrus_buf_prepare(struct vb2_buffer *vb) + return 0; + } + ++static void cedrus_buf_cleanup(struct vb2_buffer *vb) ++{ ++ struct vb2_queue *vq = vb->vb2_queue; ++ struct cedrus_ctx *ctx = vb2_get_drv_priv(vq); ++ struct cedrus_dev *dev = ctx->dev; ++ struct cedrus_dec_ops *ops = dev->dec_ops[ctx->current_codec]; ++ ++ if (!V4L2_TYPE_IS_OUTPUT(vq->type) && ops->buf_cleanup) ++ ops->buf_cleanup(ctx, ++ vb2_to_cedrus_buffer(vq->bufs[vb->index])); ++} ++ + static int cedrus_start_streaming(struct vb2_queue *vq, unsigned int count) + { + struct cedrus_ctx *ctx = vb2_get_drv_priv(vq); +@@ -551,6 +563,7 @@ static void cedrus_buf_request_complete(struct vb2_buffer *vb) + static struct vb2_ops cedrus_qops = { + .queue_setup = cedrus_queue_setup, + .buf_prepare = cedrus_buf_prepare, ++ .buf_cleanup = cedrus_buf_cleanup, + .buf_queue = cedrus_buf_queue, + .buf_out_validate = cedrus_buf_out_validate, + .buf_request_complete = cedrus_buf_request_complete, +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-media-cedrus-h264-Improve-buffer-management.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-media-cedrus-h264-Improve-buffer-management.patch new file mode 100644 index 0000000000..d9c5046c9b --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-media-cedrus-h264-Improve-buffer-management.patch @@ -0,0 +1,207 @@ +From b867585f3054ab77f6dc2205ae322ed2ccb99832 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sat, 9 Nov 2019 14:12:42 +0100 +Subject: [PATCH 036/170] drv:media: cedrus: h264: Improve buffer management + +Signed-off-by: Jernej Skrabec +--- + drivers/staging/media/sunxi/cedrus/cedrus.h | 3 + + .../staging/media/sunxi/cedrus/cedrus_h264.c | 95 ++++++++----------- + 2 files changed, 44 insertions(+), 54 deletions(-) + +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.h b/drivers/staging/media/sunxi/cedrus/cedrus.h +index 1b20e23ee..ef9f1d9c8 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus.h ++++ b/drivers/staging/media/sunxi/cedrus/cedrus.h +@@ -106,6 +106,9 @@ struct cedrus_buffer { + struct { + unsigned int position; + enum cedrus_h264_pic_type pic_type; ++ void *mv_col_buf; ++ dma_addr_t mv_col_buf_dma; ++ ssize_t mv_col_buf_size; + } h264; + struct { + void *mv_col_buf; +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h264.c b/drivers/staging/media/sunxi/cedrus/cedrus_h264.c +index d8fb93035..281909c57 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus_h264.c ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_h264.c +@@ -55,16 +55,14 @@ static void cedrus_h264_write_sram(struct cedrus_dev *dev, + } + + static dma_addr_t cedrus_h264_mv_col_buf_addr(struct cedrus_ctx *ctx, +- unsigned int position, ++ struct cedrus_buffer *buf, + unsigned int field) + { +- dma_addr_t addr = ctx->codec.h264.mv_col_buf_dma; +- +- /* Adjust for the position */ +- addr += position * ctx->codec.h264.mv_col_buf_field_size * 2; ++ dma_addr_t addr = buf->codec.h264.mv_col_buf_dma; + + /* Adjust for the field */ +- addr += field * ctx->codec.h264.mv_col_buf_field_size; ++ if (field) ++ addr += buf->codec.h264.mv_col_buf_size / 2; + + return addr; + } +@@ -76,7 +74,6 @@ static void cedrus_fill_ref_pic(struct cedrus_ctx *ctx, + struct cedrus_h264_sram_ref_pic *pic) + { + struct vb2_buffer *vbuf = &buf->m2m_buf.vb.vb2_buf; +- unsigned int position = buf->codec.h264.position; + + pic->top_field_order_cnt = cpu_to_le32(top_field_order_cnt); + pic->bottom_field_order_cnt = cpu_to_le32(bottom_field_order_cnt); +@@ -85,9 +82,9 @@ static void cedrus_fill_ref_pic(struct cedrus_ctx *ctx, + pic->luma_ptr = cpu_to_le32(cedrus_buf_addr(vbuf, &ctx->dst_fmt, 0)); + pic->chroma_ptr = cpu_to_le32(cedrus_buf_addr(vbuf, &ctx->dst_fmt, 1)); + pic->mv_col_top_ptr = +- cpu_to_le32(cedrus_h264_mv_col_buf_addr(ctx, position, 0)); ++ cpu_to_le32(cedrus_h264_mv_col_buf_addr(ctx, buf, 0)); + pic->mv_col_bot_ptr = +- cpu_to_le32(cedrus_h264_mv_col_buf_addr(ctx, position, 1)); ++ cpu_to_le32(cedrus_h264_mv_col_buf_addr(ctx, buf, 1)); + } + + static void cedrus_write_frame_list(struct cedrus_ctx *ctx, +@@ -146,6 +143,28 @@ static void cedrus_write_frame_list(struct cedrus_ctx *ctx, + output_buf = vb2_to_cedrus_buffer(&run->dst->vb2_buf); + output_buf->codec.h264.position = position; + ++ if (!output_buf->codec.h264.mv_col_buf_size) { ++ const struct v4l2_ctrl_h264_sps *sps = run->h264.sps; ++ unsigned int field_size; ++ ++ field_size = DIV_ROUND_UP(ctx->src_fmt.width, 16) * ++ DIV_ROUND_UP(ctx->src_fmt.height, 16) * 16; ++ if (!(sps->flags & V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE)) ++ field_size = field_size * 2; ++ if (!(sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY)) ++ field_size = field_size * 2; ++ ++ output_buf->codec.h264.mv_col_buf_size = field_size * 2; ++ output_buf->codec.h264.mv_col_buf = ++ dma_alloc_attrs(dev->dev, ++ output_buf->codec.h264.mv_col_buf_size, ++ &output_buf->codec.h264.mv_col_buf_dma, ++ GFP_KERNEL, DMA_ATTR_NO_KERNEL_MAPPING); ++ ++ if (!output_buf->codec.h264.mv_col_buf) ++ output_buf->codec.h264.mv_col_buf_size = 0; ++ } ++ + if (decode->flags & V4L2_H264_DECODE_PARAM_FLAG_FIELD_PIC) + output_buf->codec.h264.pic_type = CEDRUS_H264_PIC_TYPE_FIELD; + else if (sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD) +@@ -516,8 +535,6 @@ static int cedrus_h264_start(struct cedrus_ctx *ctx) + { + struct cedrus_dev *dev = ctx->dev; + unsigned int pic_info_size; +- unsigned int field_size; +- unsigned int mv_col_size; + int ret; + + /* +@@ -565,38 +582,6 @@ static int cedrus_h264_start(struct cedrus_ctx *ctx) + goto err_pic_buf; + } + +- field_size = DIV_ROUND_UP(ctx->src_fmt.width, 16) * +- DIV_ROUND_UP(ctx->src_fmt.height, 16) * 16; +- +- /* +- * FIXME: This is actually conditional to +- * V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE not being set, we +- * might have to rework this if memory efficiency ever is +- * something we need to work on. +- */ +- field_size = field_size * 2; +- +- /* +- * FIXME: This is actually conditional to +- * V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY not being set, we might +- * have to rework this if memory efficiency ever is something +- * we need to work on. +- */ +- field_size = field_size * 2; +- ctx->codec.h264.mv_col_buf_field_size = field_size; +- +- mv_col_size = field_size * 2 * CEDRUS_H264_FRAME_NUM; +- ctx->codec.h264.mv_col_buf_size = mv_col_size; +- ctx->codec.h264.mv_col_buf = +- dma_alloc_attrs(dev->dev, +- ctx->codec.h264.mv_col_buf_size, +- &ctx->codec.h264.mv_col_buf_dma, +- GFP_KERNEL, DMA_ATTR_NO_KERNEL_MAPPING); +- if (!ctx->codec.h264.mv_col_buf) { +- ret = -ENOMEM; +- goto err_neighbor_buf; +- } +- + if (ctx->src_fmt.width > 2048) { + /* + * Formulas for deblock and intra prediction buffer sizes +@@ -612,7 +597,7 @@ static int cedrus_h264_start(struct cedrus_ctx *ctx) + GFP_KERNEL, DMA_ATTR_NO_KERNEL_MAPPING); + if (!ctx->codec.h264.deblk_buf) { + ret = -ENOMEM; +- goto err_mv_col_buf; ++ goto err_neighbor_buf; + } + + /* +@@ -640,12 +625,6 @@ static int cedrus_h264_start(struct cedrus_ctx *ctx) + ctx->codec.h264.deblk_buf_dma, + DMA_ATTR_NO_KERNEL_MAPPING); + +-err_mv_col_buf: +- dma_free_attrs(dev->dev, ctx->codec.h264.mv_col_buf_size, +- ctx->codec.h264.mv_col_buf, +- ctx->codec.h264.mv_col_buf_dma, +- DMA_ATTR_NO_KERNEL_MAPPING); +- + err_neighbor_buf: + dma_free_attrs(dev->dev, CEDRUS_NEIGHBOR_INFO_BUF_SIZE, + ctx->codec.h264.neighbor_info_buf, +@@ -664,10 +643,6 @@ static void cedrus_h264_stop(struct cedrus_ctx *ctx) + { + struct cedrus_dev *dev = ctx->dev; + +- dma_free_attrs(dev->dev, ctx->codec.h264.mv_col_buf_size, +- ctx->codec.h264.mv_col_buf, +- ctx->codec.h264.mv_col_buf_dma, +- DMA_ATTR_NO_KERNEL_MAPPING); + dma_free_attrs(dev->dev, CEDRUS_NEIGHBOR_INFO_BUF_SIZE, + ctx->codec.h264.neighbor_info_buf, + ctx->codec.h264.neighbor_info_buf_dma, +@@ -696,6 +671,17 @@ static void cedrus_h264_trigger(struct cedrus_ctx *ctx) + VE_H264_TRIGGER_TYPE_AVC_SLICE_DECODE); + } + ++static void cedrus_h264_buf_cleanup(struct cedrus_ctx *ctx, ++ struct cedrus_buffer *buf) ++{ ++ if (buf->codec.h264.mv_col_buf_size) ++ dma_free_attrs(ctx->dev->dev, ++ buf->codec.h264.mv_col_buf_size, ++ buf->codec.h264.mv_col_buf, ++ buf->codec.h264.mv_col_buf_dma, ++ DMA_ATTR_NO_KERNEL_MAPPING); ++} ++ + struct cedrus_dec_ops cedrus_dec_ops_h264 = { + .irq_clear = cedrus_h264_irq_clear, + .irq_disable = cedrus_h264_irq_disable, +@@ -704,4 +690,5 @@ struct cedrus_dec_ops cedrus_dec_ops_h264 = { + .start = cedrus_h264_start, + .stop = cedrus_h264_stop, + .trigger = cedrus_h264_trigger, ++ .buf_cleanup = cedrus_h264_buf_cleanup, + }; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-media-cedrus-hevc-Improve-buffer-management.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-media-cedrus-hevc-Improve-buffer-management.patch new file mode 100644 index 0000000000..c43c0f5eab --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-media-cedrus-hevc-Improve-buffer-management.patch @@ -0,0 +1,245 @@ +From 432246948309396204697a010342ba6a5a94f387 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sat, 9 Nov 2019 13:22:05 +0100 +Subject: [PATCH 035/170] drv:media:cedrus: hevc: Improve buffer management + +Signed-off-by: Jernej Skrabec +--- + drivers/staging/media/sunxi/cedrus/cedrus.h | 9 +- + .../staging/media/sunxi/cedrus/cedrus_h265.c | 120 ++++++++++-------- + 2 files changed, 70 insertions(+), 59 deletions(-) + +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.h b/drivers/staging/media/sunxi/cedrus/cedrus.h +index 0a17ed0dc..1b20e23ee 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus.h ++++ b/drivers/staging/media/sunxi/cedrus/cedrus.h +@@ -107,6 +107,11 @@ struct cedrus_buffer { + unsigned int position; + enum cedrus_h264_pic_type pic_type; + } h264; ++ struct { ++ void *mv_col_buf; ++ dma_addr_t mv_col_buf_dma; ++ ssize_t mv_col_buf_size; ++ } h265; + } codec; + }; + +@@ -140,10 +145,6 @@ struct cedrus_ctx { + ssize_t intra_pred_buf_size; + } h264; + struct { +- void *mv_col_buf; +- dma_addr_t mv_col_buf_addr; +- ssize_t mv_col_buf_size; +- ssize_t mv_col_buf_unit_size; + void *neighbor_info_buf; + dma_addr_t neighbor_info_buf_addr; + void *entry_points_buf; +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c +index 685cb00de..55a1874c8 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c +@@ -91,26 +91,66 @@ static void cedrus_h265_sram_write_data(struct cedrus_dev *dev, void *data, + + static inline dma_addr_t + cedrus_h265_frame_info_mv_col_buf_addr(struct cedrus_ctx *ctx, +- unsigned int index, unsigned int field) ++ unsigned int index, ++ const struct v4l2_ctrl_hevc_sps *sps) + { +- return ctx->codec.h265.mv_col_buf_addr + index * +- ctx->codec.h265.mv_col_buf_unit_size + +- field * ctx->codec.h265.mv_col_buf_unit_size / 2; ++ struct cedrus_buffer *cedrus_buf = NULL; ++ struct vb2_buffer *buf = NULL; ++ struct vb2_queue *vq; ++ ++ vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE); ++ if (vq) ++ buf = vb2_get_buffer(vq, index); ++ ++ if (buf) ++ cedrus_buf = vb2_to_cedrus_buffer(buf); ++ ++ if (!cedrus_buf) ++ return 0; ++ ++ if (!cedrus_buf->codec.h265.mv_col_buf_size) { ++ unsigned int ctb_size_luma, width_in_ctb_luma; ++ unsigned int log2_max_luma_coding_block_size; ++ ++ log2_max_luma_coding_block_size = ++ sps->log2_min_luma_coding_block_size_minus3 + 3 + ++ sps->log2_diff_max_min_luma_coding_block_size; ++ ctb_size_luma = 1 << log2_max_luma_coding_block_size; ++ width_in_ctb_luma = DIV_ROUND_UP(sps->pic_width_in_luma_samples, ++ ctb_size_luma); ++ ++ cedrus_buf->codec.h265.mv_col_buf_size = ALIGN(width_in_ctb_luma * ++ DIV_ROUND_UP(sps->pic_height_in_luma_samples, ctb_size_luma) * ++ CEDRUS_H265_MV_COL_BUF_UNIT_CTB_SIZE, 1024); ++ ++ cedrus_buf->codec.h265.mv_col_buf = ++ dma_alloc_attrs(ctx->dev->dev, ++ cedrus_buf->codec.h265.mv_col_buf_size, ++ &cedrus_buf->codec.h265.mv_col_buf_dma, ++ GFP_KERNEL, DMA_ATTR_NO_KERNEL_MAPPING); ++ ++ if (!cedrus_buf->codec.h265.mv_col_buf) { ++ cedrus_buf->codec.h265.mv_col_buf_size = 0; ++ cedrus_buf->codec.h265.mv_col_buf_dma = 0; ++ } ++ } ++ ++ return cedrus_buf->codec.h265.mv_col_buf_dma; + } + + static void cedrus_h265_frame_info_write_single(struct cedrus_ctx *ctx, + unsigned int index, + bool field_pic, + u32 pic_order_cnt[], +- int buffer_index) ++ int buffer_index, ++ const struct v4l2_ctrl_hevc_sps *sps) + { + struct cedrus_dev *dev = ctx->dev; + dma_addr_t dst_luma_addr = cedrus_dst_buf_addr(ctx, buffer_index, 0); + dma_addr_t dst_chroma_addr = cedrus_dst_buf_addr(ctx, buffer_index, 1); + dma_addr_t mv_col_buf_addr[2] = { +- cedrus_h265_frame_info_mv_col_buf_addr(ctx, buffer_index, 0), +- cedrus_h265_frame_info_mv_col_buf_addr(ctx, buffer_index, +- field_pic ? 1 : 0) ++ cedrus_h265_frame_info_mv_col_buf_addr(ctx, buffer_index, sps), ++ cedrus_h265_frame_info_mv_col_buf_addr(ctx, buffer_index, sps) + }; + u32 offset = VE_DEC_H265_SRAM_OFFSET_FRAME_INFO + + VE_DEC_H265_SRAM_OFFSET_FRAME_INFO_UNIT * index; +@@ -134,7 +174,8 @@ static void cedrus_h265_frame_info_write_single(struct cedrus_ctx *ctx, + + static void cedrus_h265_frame_info_write_dpb(struct cedrus_ctx *ctx, + const struct v4l2_hevc_dpb_entry *dpb, +- u8 num_active_dpb_entries) ++ u8 num_active_dpb_entries, ++ const struct v4l2_ctrl_hevc_sps *sps) + { + struct vb2_queue *vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, + V4L2_BUF_TYPE_VIDEO_CAPTURE); +@@ -152,7 +193,7 @@ static void cedrus_h265_frame_info_write_dpb(struct cedrus_ctx *ctx, + + cedrus_h265_frame_info_write_single(ctx, i, dpb[i].field_pic, + pic_order_cnt, +- buffer_index); ++ buffer_index, sps); + } + } + +@@ -416,37 +457,6 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, + width_in_ctb_luma = + DIV_ROUND_UP(sps->pic_width_in_luma_samples, ctb_size_luma); + +- /* MV column buffer size and allocation. */ +- if (!ctx->codec.h265.mv_col_buf_size) { +- unsigned int num_buffers = +- run->dst->vb2_buf.vb2_queue->num_buffers; +- +- /* +- * Each CTB requires a MV col buffer with a specific unit size. +- * Since the address is given with missing lsb bits, 1 KiB is +- * added to each buffer to ensure proper alignment. +- */ +- ctx->codec.h265.mv_col_buf_unit_size = +- DIV_ROUND_UP(ctx->src_fmt.width, ctb_size_luma) * +- DIV_ROUND_UP(ctx->src_fmt.height, ctb_size_luma) * +- CEDRUS_H265_MV_COL_BUF_UNIT_CTB_SIZE + SZ_1K; +- +- ctx->codec.h265.mv_col_buf_size = num_buffers * +- ctx->codec.h265.mv_col_buf_unit_size; +- +- /* Buffer is never accessed by CPU, so we can skip kernel mapping. */ +- ctx->codec.h265.mv_col_buf = +- dma_alloc_attrs(dev->dev, +- ctx->codec.h265.mv_col_buf_size, +- &ctx->codec.h265.mv_col_buf_addr, +- GFP_KERNEL, DMA_ATTR_NO_KERNEL_MAPPING); +- if (!ctx->codec.h265.mv_col_buf) { +- ctx->codec.h265.mv_col_buf_size = 0; +- // TODO: Abort the process here. +- return; +- } +- } +- + /* Activate H265 engine. */ + cedrus_engine_enable(ctx, CEDRUS_CODEC_H265); + +@@ -702,7 +712,7 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, + + /* Write decoded picture buffer in pic list. */ + cedrus_h265_frame_info_write_dpb(ctx, decode_params->dpb, +- decode_params->num_active_dpb_entries); ++ decode_params->num_active_dpb_entries, sps); + + /* Output frame. */ + +@@ -713,7 +723,7 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, + cedrus_h265_frame_info_write_single(ctx, output_pic_list_index, + slice_params->pic_struct != 0, + pic_order_cnt, +- run->dst->vb2_buf.index); ++ run->dst->vb2_buf.index, sps); + + cedrus_write(dev, VE_DEC_H265_OUTPUT_FRAME_IDX, output_pic_list_index); + +@@ -762,9 +772,6 @@ static int cedrus_h265_start(struct cedrus_ctx *ctx) + { + struct cedrus_dev *dev = ctx->dev; + +- /* The buffer size is calculated at setup time. */ +- ctx->codec.h265.mv_col_buf_size = 0; +- + /* Buffer is never accessed by CPU, so we can skip kernel mapping. */ + ctx->codec.h265.neighbor_info_buf = + dma_alloc_attrs(dev->dev, CEDRUS_H265_NEIGHBOR_INFO_BUF_SIZE, +@@ -791,15 +798,6 @@ static void cedrus_h265_stop(struct cedrus_ctx *ctx) + { + struct cedrus_dev *dev = ctx->dev; + +- if (ctx->codec.h265.mv_col_buf_size > 0) { +- dma_free_attrs(dev->dev, ctx->codec.h265.mv_col_buf_size, +- ctx->codec.h265.mv_col_buf, +- ctx->codec.h265.mv_col_buf_addr, +- DMA_ATTR_NO_KERNEL_MAPPING); +- +- ctx->codec.h265.mv_col_buf_size = 0; +- } +- + dma_free_attrs(dev->dev, CEDRUS_H265_NEIGHBOR_INFO_BUF_SIZE, + ctx->codec.h265.neighbor_info_buf, + ctx->codec.h265.neighbor_info_buf_addr, +@@ -816,6 +814,17 @@ static void cedrus_h265_trigger(struct cedrus_ctx *ctx) + cedrus_write(dev, VE_DEC_H265_TRIGGER, VE_DEC_H265_TRIGGER_DEC_SLICE); + } + ++static void cedrus_h265_buf_cleanup(struct cedrus_ctx *ctx, ++ struct cedrus_buffer *buf) ++{ ++ if (buf->codec.h265.mv_col_buf_size) ++ dma_free_attrs(ctx->dev->dev, ++ buf->codec.h265.mv_col_buf_size, ++ buf->codec.h265.mv_col_buf, ++ buf->codec.h265.mv_col_buf_dma, ++ DMA_ATTR_NO_KERNEL_MAPPING); ++} ++ + struct cedrus_dec_ops cedrus_dec_ops_h265 = { + .irq_clear = cedrus_h265_irq_clear, + .irq_disable = cedrus_h265_irq_disable, +@@ -824,4 +833,5 @@ struct cedrus_dec_ops cedrus_dec_ops_h265 = { + .start = cedrus_h265_start, + .stop = cedrus_h265_stop, + .trigger = cedrus_h265_trigger, ++ .buf_cleanup = cedrus_h265_buf_cleanup, + }; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-media-cedrus-hevc-tiles-hack.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-media-cedrus-hevc-tiles-hack.patch new file mode 100644 index 0000000000..ff974aadb1 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-media-cedrus-hevc-tiles-hack.patch @@ -0,0 +1,180 @@ +From 62eb86473f2ccdd278983f4c6f1e41c895edc9b7 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sat, 26 Oct 2019 21:23:55 +0200 +Subject: [PATCH 033/170] drv:media: cedrus: hevc: tiles hack + +Signed-off-by: Jernej Skrabec +--- + drivers/staging/media/sunxi/cedrus/cedrus.h | 2 + + .../staging/media/sunxi/cedrus/cedrus_h265.c | 93 +++++++++++++++++-- + 2 files changed, 89 insertions(+), 6 deletions(-) + +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.h b/drivers/staging/media/sunxi/cedrus/cedrus.h +index 3bc094eb4..9d34e5785 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus.h ++++ b/drivers/staging/media/sunxi/cedrus/cedrus.h +@@ -146,6 +146,8 @@ struct cedrus_ctx { + ssize_t mv_col_buf_unit_size; + void *neighbor_info_buf; + dma_addr_t neighbor_info_buf_addr; ++ void *entry_points_buf; ++ dma_addr_t entry_points_buf_addr; + } h265; + struct { + unsigned int last_frame_p_type; +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c +index 44f385be9..f71ce6f87 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c +@@ -329,6 +329,61 @@ static int cedrus_h265_is_low_delay(struct cedrus_run *run) + return 0; + } + ++static void write_entry_point_list(struct cedrus_ctx *ctx, ++ struct cedrus_run *run, ++ unsigned int ctb_addr_x, ++ unsigned int ctb_addr_y) ++{ ++ const struct v4l2_ctrl_hevc_slice_params *slice_params; ++ const struct v4l2_ctrl_hevc_pps *pps; ++ struct cedrus_dev *dev = ctx->dev; ++ int i, x, tx, y, ty; ++ u32 *entry_points; ++ ++ pps = run->h265.pps; ++ slice_params = run->h265.slice_params; ++ ++ for (x = 0, tx = 0; tx < pps->num_tile_columns_minus1 + 1; tx++) { ++ if (x + pps->column_width_minus1[tx] + 1 > ctb_addr_x) ++ break; ++ ++ x += pps->column_width_minus1[tx] + 1; ++ } ++ ++ for (y = 0, ty = 0; ty < pps->num_tile_rows_minus1 + 1; ty++) { ++ if (y + pps->row_height_minus1[ty] + 1 > ctb_addr_y) ++ break; ++ ++ y += pps->row_height_minus1[ty] + 1; ++ } ++ ++ cedrus_write(dev, VE_DEC_H265_TILE_START_CTB, (y << 16) | (x << 0)); ++ cedrus_write(dev, VE_DEC_H265_TILE_END_CTB, ++ ((y + pps->row_height_minus1[ty]) << 16) | ++ ((x + pps->column_width_minus1[tx]) << 0)); ++ ++ entry_points = ctx->codec.h265.entry_points_buf; ++ if (pps->flags & V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED) { ++ for (i = 0; i < slice_params->num_entry_point_offsets; i++) ++ entry_points[i] = slice_params->entry_point_offset_minus1[i] + 1; ++ } else { ++ for (i = 0; i < slice_params->num_entry_point_offsets; i++) { ++ if (tx + 1 >= pps->num_tile_columns_minus1 + 1) { ++ x = 0; ++ tx = 0; ++ y += pps->row_height_minus1[ty++] + 1; ++ } else { ++ x += pps->column_width_minus1[tx++] + 1; ++ } ++ ++ entry_points[i * 4 + 0] = slice_params->entry_point_offset_minus1[i] + 1; ++ entry_points[i * 4 + 1] = 0x0; ++ entry_points[i * 4 + 2] = (y << 16) | (x << 0); ++ entry_points[i * 4 + 3] = ((y + pps->row_height_minus1[ty]) << 16) | ((x + pps->column_width_minus1[tx]) << 0); ++ } ++ } ++} ++ + static void cedrus_h265_setup(struct cedrus_ctx *ctx, + struct cedrus_run *run) + { +@@ -340,6 +395,7 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, + const struct v4l2_hevc_pred_weight_table *pred_weight_table; + unsigned int width_in_ctb_luma, ctb_size_luma; + unsigned int log2_max_luma_coding_block_size; ++ unsigned int ctb_addr_x, ctb_addr_y; + dma_addr_t src_buf_addr; + dma_addr_t src_buf_end_addr; + u32 chroma_log2_weight_denom; +@@ -419,12 +475,19 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, + cedrus_write(dev, VE_DEC_H265_BITS_END_ADDR, reg); + + /* Coding tree block address */ +- reg = VE_DEC_H265_DEC_CTB_ADDR_X(slice_params->slice_segment_addr % width_in_ctb_luma); +- reg |= VE_DEC_H265_DEC_CTB_ADDR_Y(slice_params->slice_segment_addr / width_in_ctb_luma); ++ ctb_addr_x = slice_params->slice_segment_addr % width_in_ctb_luma; ++ ctb_addr_y = slice_params->slice_segment_addr / width_in_ctb_luma; ++ reg = VE_DEC_H265_DEC_CTB_ADDR_X(ctb_addr_x); ++ reg |= VE_DEC_H265_DEC_CTB_ADDR_Y(ctb_addr_y); + cedrus_write(dev, VE_DEC_H265_DEC_CTB_ADDR, reg); + +- cedrus_write(dev, VE_DEC_H265_TILE_START_CTB, 0); +- cedrus_write(dev, VE_DEC_H265_TILE_END_CTB, 0); ++ if ((pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED) || ++ (pps->flags & V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED)) { ++ write_entry_point_list(ctx, run, ctb_addr_x, ctb_addr_y); ++ } else { ++ cedrus_write(dev, VE_DEC_H265_TILE_START_CTB, 0); ++ cedrus_write(dev, VE_DEC_H265_TILE_END_CTB, 0); ++ } + + /* Clear the number of correctly-decoded coding tree blocks. */ + if (ctx->fh.m2m_ctx->new_frame) +@@ -528,7 +591,9 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, + V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED, + pps->flags); + +- /* TODO: VE_DEC_H265_DEC_PPS_CTRL1_FLAG_TILES_ENABLED */ ++ reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PPS_CTRL1_FLAG_TILES_ENABLED, ++ V4L2_HEVC_PPS_FLAG_TILES_ENABLED, ++ pps->flags); + + reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PPS_CTRL1_FLAG_TRANSQUANT_BYPASS_ENABLED, + V4L2_HEVC_PPS_FLAG_TRANSQUANT_BYPASS_ENABLED, +@@ -606,12 +671,14 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, + + chroma_log2_weight_denom = pred_weight_table->luma_log2_weight_denom + + pred_weight_table->delta_chroma_log2_weight_denom; +- reg = VE_DEC_H265_DEC_SLICE_HDR_INFO2_NUM_ENTRY_POINT_OFFSETS(0) | ++ reg = VE_DEC_H265_DEC_SLICE_HDR_INFO2_NUM_ENTRY_POINT_OFFSETS(slice_params->num_entry_point_offsets) | + VE_DEC_H265_DEC_SLICE_HDR_INFO2_CHROMA_LOG2_WEIGHT_DENOM(chroma_log2_weight_denom) | + VE_DEC_H265_DEC_SLICE_HDR_INFO2_LUMA_LOG2_WEIGHT_DENOM(pred_weight_table->luma_log2_weight_denom); + + cedrus_write(dev, VE_DEC_H265_DEC_SLICE_HDR_INFO2, reg); + ++ cedrus_write(dev, VE_DEC_H265_ENTRY_POINT_OFFSET_ADDR, ctx->codec.h265.entry_points_buf_addr >> 8); ++ + /* Decoded picture size. */ + + reg = VE_DEC_H265_DEC_PIC_SIZE_WIDTH(ctx->src_fmt.width) | +@@ -706,6 +773,17 @@ static int cedrus_h265_start(struct cedrus_ctx *ctx) + if (!ctx->codec.h265.neighbor_info_buf) + return -ENOMEM; + ++ ctx->codec.h265.entry_points_buf = ++ dma_alloc_coherent(dev->dev, CEDRUS_H265_ENTRY_POINTS_BUF_SIZE, ++ &ctx->codec.h265.entry_points_buf_addr, ++ GFP_KERNEL); ++ if (!ctx->codec.h265.entry_points_buf) { ++ dma_free_coherent(dev->dev, CEDRUS_H265_NEIGHBOR_INFO_BUF_SIZE, ++ ctx->codec.h265.neighbor_info_buf, ++ ctx->codec.h265.neighbor_info_buf_addr); ++ return -ENOMEM; ++ } ++ + return 0; + } + +@@ -726,6 +804,9 @@ static void cedrus_h265_stop(struct cedrus_ctx *ctx) + ctx->codec.h265.neighbor_info_buf, + ctx->codec.h265.neighbor_info_buf_addr, + DMA_ATTR_NO_KERNEL_MAPPING); ++ dma_free_coherent(dev->dev, CEDRUS_H265_ENTRY_POINTS_BUF_SIZE, ++ ctx->codec.h265.entry_points_buf, ++ ctx->codec.h265.entry_points_buf_addr); + } + + static void cedrus_h265_trigger(struct cedrus_ctx *ctx) +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-media-dvb-frontends-si2168-fix-cmd-timeout.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-media-dvb-frontends-si2168-fix-cmd-timeout.patch new file mode 100644 index 0000000000..5e4d0aeb26 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-media-dvb-frontends-si2168-fix-cmd-timeout.patch @@ -0,0 +1,28 @@ +From bf1573d8469ba32d61a8b42b61e662ce01141bdf Mon Sep 17 00:00:00 2001 +From: Koumes +Date: Sat, 1 Jun 2019 21:20:26 +0000 +Subject: [PATCH 027/153] drv:media:dvb-frontends:si2168: fix cmd timeout + +Some demuxer si2168 commands may take 130-140 ms. +(DVB-T/T2 tuner MyGica T230C v2). +Details: https://github.com/CoreELEC/CoreELEC/pull/208 +--- + drivers/media/dvb-frontends/si2168.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/media/dvb-frontends/si2168.c b/drivers/media/dvb-frontends/si2168.c +index 2a0e108c5..e7bfb8096 100644 +--- a/drivers/media/dvb-frontends/si2168.c ++++ b/drivers/media/dvb-frontends/si2168.c +@@ -40,7 +40,7 @@ static int si2168_cmd_execute(struct i2c_client *client, struct si2168_cmd *cmd) + + if (cmd->rlen) { + /* wait cmd execution terminate */ +- #define TIMEOUT 70 ++ #define TIMEOUT 200 + timeout = jiffies + msecs_to_jiffies(TIMEOUT); + while (!time_after(jiffies, timeout)) { + ret = i2c_master_recv(client, cmd->args, cmd->rlen); +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-mfd-Add-support-for-AC200.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-mfd-Add-support-for-AC200.patch new file mode 100644 index 0000000000..78c9283ed4 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-mfd-Add-support-for-AC200.patch @@ -0,0 +1,439 @@ +From 945eee6dd75294cd527b1ca6109758afb262a45c Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Fri, 16 Aug 2019 16:38:21 +0200 +Subject: [PATCH 004/153] drv:mfd: Add support for AC200 + +Signed-off-by: Jernej Skrabec +--- + drivers/mfd/Kconfig | 9 ++ + drivers/mfd/Makefile | 1 + + drivers/mfd/ac200.c | 170 +++++++++++++++++++++++++++++++ + include/linux/mfd/ac200.h | 208 ++++++++++++++++++++++++++++++++++++++ + 4 files changed, 388 insertions(+) + create mode 100644 drivers/mfd/ac200.c + create mode 100644 include/linux/mfd/ac200.h + +diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig +index 30db49f31..473359275 100644 +--- a/drivers/mfd/Kconfig ++++ b/drivers/mfd/Kconfig +@@ -190,6 +190,15 @@ config MFD_AC100 + This driver include only the core APIs. You have to select individual + components like codecs or RTC under the corresponding menus. + ++config MFD_AC200 ++ bool "X-Powers AC200" ++ select MFD_CORE ++ depends on I2C ++ help ++ If you say Y here you get support for the X-Powers AC200 IC. ++ This driver include only the core APIs. You have to select individual ++ components like Ethernet PHY or RTC under the corresponding menus. ++ + config MFD_AXP20X + tristate + select MFD_CORE +diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile +index 457471478..b2e69fbce 100644 +--- a/drivers/mfd/Makefile ++++ b/drivers/mfd/Makefile +@@ -141,6 +141,7 @@ obj-$(CONFIG_MFD_DA9052_SPI) += da9052-spi.o + obj-$(CONFIG_MFD_DA9052_I2C) += da9052-i2c.o + + obj-$(CONFIG_MFD_AC100) += ac100.o ++obj-$(CONFIG_MFD_AC200) += ac200.o + obj-$(CONFIG_MFD_AXP20X) += axp20x.o + obj-$(CONFIG_MFD_AXP20X_I2C) += axp20x-i2c.o + obj-$(CONFIG_MFD_AXP20X_RSB) += axp20x-rsb.o +diff --git a/drivers/mfd/ac200.c b/drivers/mfd/ac200.c +new file mode 100644 +index 000000000..570573790 +--- /dev/null ++++ b/drivers/mfd/ac200.c +@@ -0,0 +1,169 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * MFD core driver for X-Powers' AC200 IC ++ * ++ * The AC200 is a chip which is co-packaged with Allwinner H6 SoC and ++ * includes analog audio codec, analog TV encoder, ethernet PHY, eFuse ++ * and RTC. ++ * ++ * Copyright (c) 2020 Jernej Skrabec ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* Interrupts */ ++#define AC200_IRQ_RTC 0 ++#define AC200_IRQ_EPHY 1 ++#define AC200_IRQ_TVE 2 ++ ++/* IRQ enable register */ ++#define AC200_SYS_IRQ_ENABLE_OUT_EN BIT(15) ++#define AC200_SYS_IRQ_ENABLE_RTC BIT(12) ++#define AC200_SYS_IRQ_ENABLE_EPHY BIT(8) ++#define AC200_SYS_IRQ_ENABLE_TVE BIT(4) ++ ++static const struct regmap_range_cfg ac200_range_cfg[] = { ++ { ++ .range_min = AC200_SYS_VERSION, ++ .range_max = AC200_IC_CHARA1, ++ .selector_reg = AC200_TWI_REG_ADDR_H, ++ .selector_mask = 0xff, ++ .selector_shift = 0, ++ .window_start = 0, ++ .window_len = 256, ++ } ++}; ++ ++static const struct regmap_config ac200_regmap_config = { ++ .reg_bits = 8, ++ .val_bits = 16, ++ .ranges = ac200_range_cfg, ++ .num_ranges = ARRAY_SIZE(ac200_range_cfg), ++ .max_register = AC200_IC_CHARA1, ++}; ++ ++static const struct regmap_irq ac200_regmap_irqs[] = { ++ REGMAP_IRQ_REG(AC200_IRQ_RTC, 0, AC200_SYS_IRQ_ENABLE_RTC), ++ REGMAP_IRQ_REG(AC200_IRQ_EPHY, 0, AC200_SYS_IRQ_ENABLE_EPHY), ++ REGMAP_IRQ_REG(AC200_IRQ_TVE, 0, AC200_SYS_IRQ_ENABLE_TVE), ++}; ++ ++static const struct regmap_irq_chip ac200_regmap_irq_chip = { ++ .name = "ac200_irq_chip", ++ .status_base = AC200_SYS_IRQ_STATUS, ++ .mask_base = AC200_SYS_IRQ_ENABLE, ++ .mask_invert = true, ++ .irqs = ac200_regmap_irqs, ++ .num_irqs = ARRAY_SIZE(ac200_regmap_irqs), ++ .num_regs = 1, ++}; ++ ++static const struct resource ephy_resource[] = { ++ DEFINE_RES_IRQ(AC200_IRQ_EPHY), ++}; ++ ++static const struct mfd_cell ac200_cells[] = { ++ { ++ .name = "ac200-ephy", ++ .num_resources = ARRAY_SIZE(ephy_resource), ++ .resources = ephy_resource, ++ .of_compatible = "x-powers,ac200-ephy", ++ }, ++}; ++ ++static int ac200_i2c_probe(struct i2c_client *i2c) ++{ ++ struct device *dev = &i2c->dev; ++ struct ac200_dev *ac200; ++ int ret; ++ ++ ac200 = devm_kzalloc(dev, sizeof(*ac200), GFP_KERNEL); ++ if (!ac200) ++ return -ENOMEM; ++ ++ i2c_set_clientdata(i2c, ac200); ++ ++ ac200->regmap = devm_regmap_init_i2c(i2c, &ac200_regmap_config); ++ if (IS_ERR(ac200->regmap)) { ++ ret = PTR_ERR(ac200->regmap); ++ dev_err(dev, "regmap init failed: %d\n", ret); ++ return ret; ++ } ++ ++ /* do a reset to put chip in a known state */ ++ ++ ret = regmap_write(ac200->regmap, AC200_SYS_CONTROL, 0); ++ if (ret) ++ return ret; ++ ++ ret = regmap_write(ac200->regmap, AC200_SYS_CONTROL, 1); ++ if (ret) ++ return ret; ++ ++ /* enable interrupt pin */ ++ ++ ret = regmap_write(ac200->regmap, AC200_SYS_IRQ_ENABLE, ++ AC200_SYS_IRQ_ENABLE_OUT_EN); ++ if (ret) ++ return ret; ++ ++ ret = regmap_add_irq_chip(ac200->regmap, i2c->irq, IRQF_ONESHOT, 0, ++ &ac200_regmap_irq_chip, &ac200->regmap_irqc); ++ if (ret) ++ return ret; ++ ++ ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE, ac200_cells, ++ ARRAY_SIZE(ac200_cells), NULL, 0, NULL); ++ if (ret) { ++ dev_err(dev, "failed to add MFD devices: %d\n", ret); ++ regmap_del_irq_chip(i2c->irq, ac200->regmap_irqc); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static int ac200_i2c_remove(struct i2c_client *i2c) ++{ ++ struct ac200_dev *ac200 = i2c_get_clientdata(i2c); ++ ++ regmap_write(ac200->regmap, AC200_SYS_CONTROL, 0); ++ ++ mfd_remove_devices(&i2c->dev); ++ regmap_del_irq_chip(i2c->irq, ac200->regmap_irqc); ++ ++ return 0; ++} ++ ++static const struct i2c_device_id ac200_ids[] = { ++ { "ac200", }, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(i2c, ac200_ids); ++ ++static const struct of_device_id ac200_of_match[] = { ++ { .compatible = "x-powers,ac200" }, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, ac200_of_match); ++ ++static struct i2c_driver ac200_i2c_driver = { ++ .driver = { ++ .name = "ac200", ++ .of_match_table = of_match_ptr(ac200_of_match), ++ }, ++ .probe = ac200_i2c_probe, ++ .remove = ac200_i2c_remove, ++ .id_table = ac200_ids, ++}; ++module_i2c_driver(ac200_i2c_driver); ++ ++MODULE_DESCRIPTION("MFD core driver for AC200"); ++MODULE_AUTHOR("Jernej Skrabec "); ++MODULE_LICENSE("GPL v2"); +diff --git a/include/linux/mfd/ac200.h b/include/linux/mfd/ac200.h +new file mode 100644 +index 000000000..0c677094a +--- /dev/null ++++ b/include/linux/mfd/ac200.h +@@ -0,0 +1,208 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++/* ++ * AC200 register list ++ * ++ * Copyright (C) 2019 Jernej Skrabec ++ */ ++ ++#ifndef __LINUX_MFD_AC200_H ++#define __LINUX_MFD_AC200_H ++ ++#include ++ ++/* interface registers (can be accessed from any page) */ ++#define AC200_TWI_CHANGE_TO_RSB 0x3E ++#define AC200_TWI_PAD_DELAY 0xC4 ++#define AC200_TWI_REG_ADDR_H 0xFE ++ ++/* General registers */ ++#define AC200_SYS_VERSION 0x0000 ++#define AC200_SYS_CONTROL 0x0002 ++#define AC200_SYS_IRQ_ENABLE 0x0004 ++#define AC200_SYS_IRQ_STATUS 0x0006 ++#define AC200_SYS_CLK_CTL 0x0008 ++#define AC200_SYS_DLDO_OSC_CTL 0x000A ++#define AC200_SYS_PLL_CTL0 0x000C ++#define AC200_SYS_PLL_CTL1 0x000E ++#define AC200_SYS_AUDIO_CTL0 0x0010 ++#define AC200_SYS_AUDIO_CTL1 0x0012 ++#define AC200_SYS_EPHY_CTL0 0x0014 ++#define AC200_SYS_EPHY_CTL1 0x0016 ++#define AC200_SYS_TVE_CTL0 0x0018 ++#define AC200_SYS_TVE_CTL1 0x001A ++ ++/* Audio Codec registers */ ++#define AC200_AC_SYS_CLK_CTL 0x2000 ++#define AC200_SYS_MOD_RST 0x2002 ++#define AC200_SYS_SAMP_CTL 0x2004 ++#define AC200_I2S_CTL 0x2100 ++#define AC200_I2S_CLK 0x2102 ++#define AC200_I2S_FMT0 0x2104 ++#define AC200_I2S_FMT1 0x2108 ++#define AC200_I2S_MIX_SRC 0x2114 ++#define AC200_I2S_MIX_GAIN 0x2116 ++#define AC200_I2S_DACDAT_DVC 0x2118 ++#define AC200_I2S_ADCDAT_DVC 0x211A ++#define AC200_AC_DAC_DPC 0x2200 ++#define AC200_AC_DAC_MIX_SRC 0x2202 ++#define AC200_AC_DAC_MIX_GAIN 0x2204 ++#define AC200_DACA_OMIXER_CTRL 0x2220 ++#define AC200_OMIXER_SR 0x2222 ++#define AC200_LINEOUT_CTRL 0x2224 ++#define AC200_AC_ADC_DPC 0x2300 ++#define AC200_MBIAS_CTRL 0x2310 ++#define AC200_ADC_MIC_CTRL 0x2320 ++#define AC200_ADCMIXER_SR 0x2322 ++#define AC200_ANALOG_TUNING0 0x232A ++#define AC200_ANALOG_TUNING1 0x232C ++#define AC200_AC_AGC_SEL 0x2480 ++#define AC200_ADC_DAPLCTRL 0x2500 ++#define AC200_ADC_DAPRCTRL 0x2502 ++#define AC200_ADC_DAPLSTA 0x2504 ++#define AC200_ADC_DAPRSTA 0x2506 ++#define AC200_ADC_DAPLTL 0x2508 ++#define AC200_ADC_DAPRTL 0x250A ++#define AC200_ADC_DAPLHAC 0x250C ++#define AC200_ADC_DAPLLAC 0x250E ++#define AC200_ADC_DAPRHAC 0x2510 ++#define AC200_ADC_DAPRLAC 0x2512 ++#define AC200_ADC_DAPLDT 0x2514 ++#define AC200_ADC_DAPLAT 0x2516 ++#define AC200_ADC_DAPRDT 0x2518 ++#define AC200_ADC_DAPRAT 0x251A ++#define AC200_ADC_DAPNTH 0x251C ++#define AC200_ADC_DAPLHNAC 0x251E ++#define AC200_ADC_DAPLLNAC 0x2520 ++#define AC200_ADC_DAPRHNAC 0x2522 ++#define AC200_ADC_DAPRLNAC 0x2524 ++#define AC200_AC_DAPHHPFC 0x2526 ++#define AC200_AC_DAPLHPFC 0x2528 ++#define AC200_AC_DAPOPT 0x252A ++#define AC200_AC_DAC_DAPCTRL 0x3000 ++#define AC200_AC_DRC_HHPFC 0x3002 ++#define AC200_AC_DRC_LHPFC 0x3004 ++#define AC200_AC_DRC_CTRL 0x3006 ++#define AC200_AC_DRC_LPFHAT 0x3008 ++#define AC200_AC_DRC_LPFLAT 0x300A ++#define AC200_AC_DRC_RPFHAT 0x300C ++#define AC200_AC_DRC_RPFLAT 0x300E ++#define AC200_AC_DRC_LPFHRT 0x3010 ++#define AC200_AC_DRC_LPFLRT 0x3012 ++#define AC200_AC_DRC_RPFHRT 0x3014 ++#define AC200_AC_DRC_RPFLRT 0x3016 ++#define AC200_AC_DRC_LRMSHAT 0x3018 ++#define AC200_AC_DRC_LRMSLAT 0x301A ++#define AC200_AC_DRC_RRMSHAT 0x301C ++#define AC200_AC_DRC_RRMSLAT 0x301E ++#define AC200_AC_DRC_HCT 0x3020 ++#define AC200_AC_DRC_LCT 0x3022 ++#define AC200_AC_DRC_HKC 0x3024 ++#define AC200_AC_DRC_LKC 0x3026 ++#define AC200_AC_DRC_HOPC 0x3028 ++#define AC200_AC_DRC_LOPC 0x302A ++#define AC200_AC_DRC_HLT 0x302C ++#define AC200_AC_DRC_LLT 0x302E ++#define AC200_AC_DRC_HKI 0x3030 ++#define AC200_AC_DRC_LKI 0x3032 ++#define AC200_AC_DRC_HOPL 0x3034 ++#define AC200_AC_DRC_LOPL 0x3036 ++#define AC200_AC_DRC_HET 0x3038 ++#define AC200_AC_DRC_LET 0x303A ++#define AC200_AC_DRC_HKE 0x303C ++#define AC200_AC_DRC_LKE 0x303E ++#define AC200_AC_DRC_HOPE 0x3040 ++#define AC200_AC_DRC_LOPE 0x3042 ++#define AC200_AC_DRC_HKN 0x3044 ++#define AC200_AC_DRC_LKN 0x3046 ++#define AC200_AC_DRC_SFHAT 0x3048 ++#define AC200_AC_DRC_SFLAT 0x304A ++#define AC200_AC_DRC_SFHRT 0x304C ++#define AC200_AC_DRC_SFLRT 0x304E ++#define AC200_AC_DRC_MXGHS 0x3050 ++#define AC200_AC_DRC_MXGLS 0x3052 ++#define AC200_AC_DRC_MNGHS 0x3054 ++#define AC200_AC_DRC_MNGLS 0x3056 ++#define AC200_AC_DRC_EPSHC 0x3058 ++#define AC200_AC_DRC_EPSLC 0x305A ++#define AC200_AC_DRC_HPFHGAIN 0x305E ++#define AC200_AC_DRC_HPFLGAIN 0x3060 ++#define AC200_AC_DRC_BISTCR 0x3100 ++#define AC200_AC_DRC_BISTST 0x3102 ++ ++/* TVE registers */ ++#define AC200_TVE_CTL0 0x4000 ++#define AC200_TVE_CTL1 0x4002 ++#define AC200_TVE_MOD0 0x4004 ++#define AC200_TVE_MOD1 0x4006 ++#define AC200_TVE_DAC_CFG0 0x4008 ++#define AC200_TVE_DAC_CFG1 0x400A ++#define AC200_TVE_YC_DELAY 0x400C ++#define AC200_TVE_YC_FILTER 0x400E ++#define AC200_TVE_BURST_FRQ0 0x4010 ++#define AC200_TVE_BURST_FRQ1 0x4012 ++#define AC200_TVE_FRONT_PORCH 0x4014 ++#define AC200_TVE_BACK_PORCH 0x4016 ++#define AC200_TVE_TOTAL_LINE 0x401C ++#define AC200_TVE_FIRST_ACTIVE 0x401E ++#define AC200_TVE_BLACK_LEVEL 0x4020 ++#define AC200_TVE_BLANK_LEVEL 0x4022 ++#define AC200_TVE_PLUG_EN 0x4030 ++#define AC200_TVE_PLUG_IRQ_EN 0x4032 ++#define AC200_TVE_PLUG_IRQ_STA 0x4034 ++#define AC200_TVE_PLUG_STA 0x4038 ++#define AC200_TVE_PLUG_DEBOUNCE 0x4040 ++#define AC200_TVE_DAC_TEST 0x4042 ++#define AC200_TVE_PLUG_PULSE_LEVEL 0x40F4 ++#define AC200_TVE_PLUG_PULSE_START 0x40F8 ++#define AC200_TVE_PLUG_PULSE_PERIOD 0x40FA ++#define AC200_TVE_IF_CTL 0x5000 ++#define AC200_TVE_IF_TIM0 0x5008 ++#define AC200_TVE_IF_TIM1 0x500A ++#define AC200_TVE_IF_TIM2 0x500C ++#define AC200_TVE_IF_TIM3 0x500E ++#define AC200_TVE_IF_SYNC0 0x5010 ++#define AC200_TVE_IF_SYNC1 0x5012 ++#define AC200_TVE_IF_SYNC2 0x5014 ++#define AC200_TVE_IF_TIM4 0x5016 ++#define AC200_TVE_IF_STATUS 0x5018 ++ ++/* EPHY registers */ ++#define AC200_EPHY_CTL 0x6000 ++#define AC200_EPHY_BIST 0x6002 ++ ++/* eFuse registers (0x8000 - 0x9FFF, layout unknown) */ ++ ++/* RTC registers */ ++#define AC200_LOSC_CTRL0 0xA000 ++#define AC200_LOSC_CTRL1 0xA002 ++#define AC200_LOSC_AUTO_SWT_STA 0xA004 ++#define AC200_INTOSC_CLK_PRESCAL 0xA008 ++#define AC200_RTC_YY_MM_DD0 0xA010 ++#define AC200_RTC_YY_MM_DD1 0xA012 ++#define AC200_RTC_HH_MM_SS0 0xA014 ++#define AC200_RTC_HH_MM_SS1 0xA016 ++#define AC200_ALARM0_CUR_VLU0 0xA024 ++#define AC200_ALARM0_CUR_VLU1 0xA026 ++#define AC200_ALARM0_ENABLE 0xA028 ++#define AC200_ALARM0_IRQ_EN 0xA02C ++#define AC200_ALARM0_IRQ_STA 0xA030 ++#define AC200_ALARM1_WK_HH_MM_SS0 0xA040 ++#define AC200_ALARM1_WK_HH_MM_SS1 0xA042 ++#define AC200_ALARM1_ENABLE 0xA044 ++#define AC200_ALARM1_IRQ_EN 0xA048 ++#define AC200_ALARM1_IRQ_STA 0xA04C ++#define AC200_ALARM_CONFIG 0xA050 ++#define AC200_LOSC_OUT_GATING 0xA060 ++#define AC200_GP_DATA(x) (0xA100 + (x) * 2) ++#define AC200_RTC_DEB 0xA170 ++#define AC200_GPL_HOLD_OUTPUT 0xA180 ++#define AC200_VDD_RTC 0xA190 ++#define AC200_IC_CHARA0 0xA1F0 ++#define AC200_IC_CHARA1 0xA1F2 ++ ++struct ac200_dev { ++ struct regmap *regmap; ++ struct regmap_irq_chip_data *regmap_irqc; ++}; ++ ++#endif /* __LINUX_MFD_AC200_H */ +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-mfd-axp20x-add-sysfs-interface.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-mfd-axp20x-add-sysfs-interface.patch new file mode 100644 index 0000000000..acaa88bc8e --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-mfd-axp20x-add-sysfs-interface.patch @@ -0,0 +1,658 @@ +From 7ab2538c0be09a59065aa8c8113d14f4089aeb91 Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Tue, 1 Feb 2022 21:38:26 +0300 +Subject: [PATCH] drv:mfd:axp20x add sysfs interface + +--- + drivers/mfd/axp20x.c | 614 +++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 614 insertions(+) + +diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c +index 695570bcb..057f9244d 100644 +--- a/drivers/mfd/axp20x.c ++++ b/drivers/mfd/axp20x.c +@@ -79,6 +79,7 @@ static const struct regmap_range axp20x_volatile_ranges[] = { + regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IRQ5_STATE), + regmap_reg_range(AXP20X_ACIN_V_ADC_H, AXP20X_IPSOUT_V_HIGH_L), + regmap_reg_range(AXP20X_GPIO20_SS, AXP20X_GPIO3_CTRL), ++ regmap_reg_range(AXP20X_CHRG_CC_31_24, AXP20X_DISCHRG_CC_7_0), + regmap_reg_range(AXP20X_FG_RES, AXP20X_RDC_L), + }; + +@@ -880,6 +881,611 @@ static int axp20x_power_off(struct sys_off_data *data) + return NOTIFY_DONE; + } + ++#define kobj_to_device(x) container_of(x, struct device, kobj) ++ ++int axp20x_get_adc_freq(struct axp20x_dev *axp) ++{ ++ unsigned int res; ++ int ret, freq = 25; ++ ++ ret = regmap_read(axp->regmap, AXP20X_ADC_RATE, &res); ++ if (ret < 0) { ++ dev_warn(axp->dev, "Unable to read ADC sampling frequency: %d\n", ret); ++ return freq; ++ } ++ switch ((res & 0xC0) >> 6) { ++ case 0: ++ freq = 25; ++ break; ++ case 1: ++ freq = 50; ++ break; ++ case 2: ++ freq = 100; ++ break; ++ case 3: ++ freq = 200; ++ break; ++ } ++ return freq; ++} ++ ++static ssize_t axp20x_sysfs_read_bin_file(struct file *filp, ++ struct kobject *kobj, ++ struct bin_attribute *bin_attr, ++ char *buf, loff_t off, size_t count) ++{ ++ int ret; ++ ++ struct device *dev = kobj_to_device(kobj); ++ struct axp20x_dev *axp = dev_get_drvdata(dev); ++ ++ ret = regmap_raw_read(axp->regmap, AXP20X_OCV(off), buf, count); ++ if (ret < 0) ++ { ++ dev_warn(axp->dev, "read_bin_file: error reading: %d\n", ret); ++ return ret; ++ } ++ return count; ++} ++ ++static ssize_t axp20x_sysfs_write_bin_file(struct file *filp, ++ struct kobject *kobj, ++ struct bin_attribute *bin_attr, ++ char *buf, loff_t off, size_t count) ++{ ++ int ret; ++ ++ struct device *dev = kobj_to_device(kobj); ++ struct axp20x_dev *axp = dev_get_drvdata(dev); ++ ++ ret = regmap_raw_write(axp->regmap, AXP20X_OCV(off), buf, count); ++ if (ret < 0) ++ { ++ dev_warn(axp->dev, "write_bin_file: error writing: %d\n", ret); ++ return ret; ++ } ++ return count; ++} ++ ++static ssize_t axp20x_read_special(struct kobject *kobj, struct kobj_attribute *attr, char *buf) ++{ ++ int i, freq, ret = 0; ++ unsigned int res; ++ u32 lval1, lval2; ++ s64 llval; ++ u64 ullval; ++ ++ const char *subsystem = kobject_name(kobj); ++ struct device *dev = kobj_to_device(kobj->parent); ++ struct axp20x_dev *axp = dev_get_drvdata(dev); ++ ++ dev_dbg(axp->dev, "read_special: reading attribute %s of object %s\n", attr->attr.name, subsystem); ++ ++ if (strcmp(subsystem, "battery") == 0) { ++ if (strcmp(attr->attr.name, "power") == 0) { ++ lval1 = 0; ++ for (i = 0; i < 3; i++) { ++ ret |= regmap_read(axp->regmap, AXP20X_PWR_BATT_H + i, &res); ++ lval1 |= res << ((2 - i) * 8); ++ } ++ llval = lval1 * 1100 / 1000; ++ } else if (strcmp(attr->attr.name, "charge") == 0) { ++ ret = regmap_raw_read(axp->regmap, AXP20X_CHRG_CC_31_24, &lval1, sizeof(lval1)); ++ ret |= regmap_raw_read(axp->regmap, AXP20X_DISCHRG_CC_31_24, &lval2, sizeof(lval2)); ++ be32_to_cpus(&lval1); ++ be32_to_cpus(&lval2); ++ ullval = abs((s64)lval1 - (s64)lval2) * 65536 * 500; ++ freq = axp20x_get_adc_freq(axp); ++ do_div(ullval, 3600 * freq); ++ llval = (lval1 < lval2) ? -ullval : ullval; ++ } else if (strcmp(attr->attr.name, "capacity") == 0) { ++ ret = regmap_read(axp->regmap, AXP20X_FG_RES, &res); ++ llval = res & 0x7f; ++ } else ++ return -EINVAL; ++ } else ++ return -EINVAL; ++ ++ if (ret < 0) { ++ dev_warn(axp->dev, "Unable to read parameter: %d\n", ret); ++ return ret; ++ } ++ return sprintf(buf, "%lld\n", llval); ++} ++ ++static ssize_t axp20x_write_int(struct kobject *kobj, struct kobj_attribute *attr, const char *buf, size_t count) ++{ ++ int reg, var, ret = 0, scale, width = 12, offset = 0; ++ unsigned int res; ++ ++ const char *subsystem = kobject_name(kobj); ++ struct device *dev = kobj_to_device(kobj->parent); ++ struct axp20x_dev *axp = dev_get_drvdata(dev); ++ ++ dev_dbg(axp->dev, "write_int: writing attribute %s of object %s\n", attr->attr.name, subsystem); ++ ++ ret = kstrtoint(buf, 10, &var); ++ if (ret < 0) ++ return ret; ++ ++ if (strcmp(subsystem, "control") == 0) { ++ if (strcmp(attr->attr.name, "battery_rdc") == 0) { ++ reg = AXP20X_RDC_H; ++ scale = 1074; ++ width = 13; ++ offset = 537; ++ /* TODO: Disable & enable fuel gauge */ ++ } else ++ return -EINVAL; ++ } else ++ return -EINVAL; ++ ++ res = (var + offset) / scale; ++ ++ ret = regmap_write_bits(axp->regmap, reg, (1U << (width - 8)) - 1, (res >> 8) & 0xFF); ++ ret |= regmap_write_bits(axp->regmap, reg + 1, 0xFF, res & 0xFF); ++ ++ if (ret < 0) { ++ dev_warn(axp->dev, "Unable to write parameter: %d\n", ret); ++ return ret; ++ } ++ return count; ++} ++ ++static ssize_t axp20x_read_bool(struct kobject *kobj, struct kobj_attribute *attr, char *buf) ++{ ++ int val, ret, reg, bit; ++ unsigned int res; ++ ++ const char *subsystem = kobject_name(kobj); ++ struct device *dev = kobj_to_device(kobj->parent); ++ struct axp20x_dev *axp = dev_get_drvdata(dev); ++ ++ dev_dbg(axp->dev, "read_bool: reading attribute %s of object %s\n", attr->attr.name, subsystem); ++ ++ if (strcmp(subsystem, "ac") == 0) { ++ if (strcmp(attr->attr.name, "connected") == 0) { ++ reg = AXP20X_PWR_INPUT_STATUS; ++ bit = 7; ++ } else if (strcmp(attr->attr.name, "used") == 0) { ++ reg = AXP20X_PWR_INPUT_STATUS; ++ bit = 6; ++ } else ++ return -EINVAL; ++ } else if (strcmp(subsystem, "vbus") == 0) { ++ if (strcmp(attr->attr.name, "connected") == 0) { ++ reg = AXP20X_PWR_INPUT_STATUS; ++ bit = 5; ++ } else if (strcmp(attr->attr.name, "used") == 0) { ++ reg = AXP20X_PWR_INPUT_STATUS; ++ bit = 4; ++ } else if (strcmp(attr->attr.name, "strong") == 0) { ++ reg = AXP20X_PWR_INPUT_STATUS; ++ bit = 3; ++ } else ++ return -EINVAL; ++ } else if (strcmp(subsystem, "battery") == 0) { ++ if (strcmp(attr->attr.name, "connected") == 0) { ++ reg = AXP20X_PWR_OP_MODE; ++ bit = 5; ++ } else if (strcmp(attr->attr.name, "charging") == 0) { ++ reg = AXP20X_PWR_INPUT_STATUS; ++ bit = 2; ++ } else ++ return -EINVAL; ++ } else if (strcmp(subsystem, "pmu") == 0) { ++ if (strcmp(attr->attr.name, "overheat") == 0) { ++ reg = AXP20X_PWR_OP_MODE; ++ bit = 7; ++ } else ++ return -EINVAL; ++ } else if (strcmp(subsystem, "charger") == 0) { ++ if (strcmp(attr->attr.name, "charging") == 0) { ++ reg = AXP20X_PWR_OP_MODE; ++ bit = 6; ++ } else if (strcmp(attr->attr.name, "cell_activation") == 0) { ++ reg = AXP20X_PWR_OP_MODE; ++ bit = 3; ++ } else if (strcmp(attr->attr.name, "low_power") == 0) { ++ reg = AXP20X_PWR_OP_MODE; ++ bit = 2; ++ } else ++ return -EINVAL; ++ } else if (strcmp(subsystem, "control") == 0) { ++ if (strcmp(attr->attr.name, "set_vbus_direct_mode") == 0) { ++ reg = AXP20X_VBUS_IPSOUT_MGMT; ++ bit = 6; ++ } else if (strcmp(attr->attr.name, "reset_charge_counter") == 0) { ++ reg = AXP20X_CC_CTRL; ++ bit = 5; ++ } else if (strcmp(attr->attr.name, "charge_rtc_battery") == 0) { ++ reg = AXP20X_CHRG_BAK_CTRL; ++ bit = 7; ++ } else if (strcmp(attr->attr.name, "disable_fuel_gauge") == 0) { ++ reg = AXP20X_FG_RES; ++ bit = 7; ++ } else ++ return -EINVAL; ++ } else ++ return -EINVAL; ++ ++ ret = regmap_read(axp->regmap, reg, &res); ++ if (ret < 0) { ++ dev_warn(axp->dev, "Unable to read parameter: %d\n", ret); ++ return ret; ++ } ++ val = (res & BIT(bit)) == BIT(bit) ? 1 : 0; ++ return sprintf(buf, "%d\n", val); ++} ++ ++static ssize_t axp20x_write_bool(struct kobject *kobj, struct kobj_attribute *attr, const char *buf, size_t count) ++{ ++ int var, ret, reg, bit; ++ ++ const char *subsystem = kobject_name(kobj); ++ struct device *dev = kobj_to_device(kobj->parent); ++ struct axp20x_dev *axp = dev_get_drvdata(dev); ++ ++ dev_dbg(axp->dev, "write_bool: writing attribute %s of object %s", attr->attr.name, subsystem); ++ ++ ret = kstrtoint(buf, 10, &var); ++ if (ret < 0) ++ return ret; ++ ++ if (strcmp(subsystem, "control") == 0) { ++ if (strcmp(attr->attr.name, "set_vbus_direct_mode") == 0) { ++ reg = AXP20X_VBUS_IPSOUT_MGMT; ++ bit = 6; ++ } else if (strcmp(attr->attr.name, "reset_charge_counter") == 0) { ++ reg = AXP20X_CC_CTRL; ++ bit = 5; ++ } else if (strcmp(attr->attr.name, "charge_rtc_battery") == 0) { ++ reg = AXP20X_CHRG_BAK_CTRL; ++ bit = 7; ++ } else if (strcmp(attr->attr.name, "disable_fuel_gauge") == 0) { ++ reg = AXP20X_FG_RES; ++ bit = 7; ++ } else ++ return -EINVAL; ++ } else ++ return -EINVAL; ++ ++ ret = regmap_update_bits(axp->regmap, reg, BIT(bit), var ? BIT(bit) : 0); ++ if (ret) ++ dev_warn(axp->dev, "Unable to write value: %d", ret); ++ return count; ++} ++ ++static int axp20x_averaging_helper(struct regmap *reg_map, int reg_h, ++ int width) ++{ ++ long acc = 0; ++ int ret, i; ++ ++ for (i = 0; i < 3; i++) { ++ ret = axp20x_read_variable_width(reg_map, reg_h, width); ++ if (ret < 0) ++ return ret; ++ acc += ret; ++ msleep(20); /* For 100Hz sampling frequency */ ++ } ++ return (int)(acc / 3); ++} ++ ++static ssize_t axp20x_read_int(struct kobject *kobj, struct kobj_attribute *attr, char *buf) ++{ ++ int val, ret, scale, reg, width = 12, offset = 0; ++ ++ const char *subsystem = kobject_name(kobj); ++ struct device *dev = kobj_to_device(kobj->parent); ++ struct axp20x_dev *axp = dev_get_drvdata(dev); ++ ++ dev_dbg(axp->dev, "read_int: reading attribute %s of object %s\n", attr->attr.name, subsystem); ++ ++ if (strcmp(subsystem, "ac") == 0) { ++ if (strcmp(attr->attr.name, "voltage") == 0) { ++ reg = AXP20X_ACIN_V_ADC_H; ++ scale = 1700; ++ } else if (strcmp(attr->attr.name, "amperage") == 0) { ++ reg = AXP20X_ACIN_I_ADC_H; ++ scale = 625; ++ } else ++ return -EINVAL; ++ } else if (strcmp(subsystem, "vbus") == 0) { ++ if (strcmp(attr->attr.name, "voltage") == 0) { ++ reg = AXP20X_VBUS_V_ADC_H; ++ scale = 1700; ++ } else if (strcmp(attr->attr.name, "amperage") == 0) { ++ reg = AXP20X_VBUS_I_ADC_H; ++ scale = 375; ++ } else ++ return -EINVAL; ++ } else if (strcmp(subsystem, "battery") == 0) { ++ if (strcmp(attr->attr.name, "voltage") == 0) { ++ reg = AXP20X_BATT_V_H; ++ scale = 1100; ++ } else if (strcmp(attr->attr.name, "amperage") == 0) { ++ reg = AXP20X_BATT_DISCHRG_I_H; ++ scale = 500; ++ width = 13; ++ } else if (strcmp(attr->attr.name, "ts_voltage") == 0) { ++ reg = AXP20X_TS_IN_H; ++ scale = 800; ++ } else ++ return -EINVAL; ++ } else if (strcmp(subsystem, "pmu") == 0) { ++ if (strcmp(attr->attr.name, "temp") == 0) { ++ reg = AXP20X_TEMP_ADC_H; ++ scale = 100; ++ offset = 144700; ++ } else if (strcmp(attr->attr.name, "voltage") == 0) { ++ reg = AXP20X_IPSOUT_V_HIGH_H; ++ scale = 1400; ++ } else ++ return -EINVAL; ++ } else if (strcmp(subsystem, "charger") == 0) { ++ if (strcmp(attr->attr.name, "amperage") == 0) { ++ reg = AXP20X_BATT_CHRG_I_H; ++ scale = 500; ++ } else ++ return -EINVAL; ++ } else if (strcmp(subsystem, "control") == 0) { ++ if (strcmp(attr->attr.name, "battery_rdc") == 0) { ++ reg = AXP20X_RDC_H; ++ width = 13; ++ scale = 1074; ++ offset = 537; ++ } else ++ return -EINVAL; ++ } else ++ return -EINVAL; ++ ++ ret = axp20x_averaging_helper(axp->regmap, reg, width); ++ ++ if (ret < 0) { ++ dev_warn(axp->dev, "Unable to read parameter: %d\n", ret); ++ return ret; ++ } ++ val = ret * scale - offset; ++ return sprintf(buf, "%d\n", val); ++} ++ ++/* AC IN */ ++static struct kobj_attribute ac_in_voltage = __ATTR(voltage, S_IRUGO, axp20x_read_int, NULL); ++static struct kobj_attribute ac_in_amperage = __ATTR(amperage, S_IRUGO, axp20x_read_int, NULL); ++static struct kobj_attribute ac_in_connected = __ATTR(connected, S_IRUGO, axp20x_read_bool, NULL); ++static struct kobj_attribute ac_in_used = __ATTR(used, S_IRUGO, axp20x_read_bool, NULL); ++ ++static struct attribute *axp20x_attributes_ac[] = { ++ &ac_in_voltage.attr, ++ &ac_in_amperage.attr, ++ &ac_in_connected.attr, ++ &ac_in_used.attr, ++ NULL, ++}; ++ ++static const struct attribute_group axp20x_group_ac = { ++ .attrs = axp20x_attributes_ac, ++}; ++ ++/* Vbus */ ++static struct kobj_attribute vbus_voltage = __ATTR(voltage, S_IRUGO, axp20x_read_int, NULL); ++static struct kobj_attribute vbus_amperage = __ATTR(amperage, S_IRUGO, axp20x_read_int, NULL); ++static struct kobj_attribute vbus_connected = __ATTR(connected, S_IRUGO, axp20x_read_bool, NULL); ++static struct kobj_attribute vbus_used = __ATTR(used, S_IRUGO, axp20x_read_bool, NULL); ++static struct kobj_attribute vbus_strong = __ATTR(strong, S_IRUGO, axp20x_read_bool, NULL); ++ ++static struct attribute *axp20x_attributes_vbus[] = { ++ &vbus_voltage.attr, ++ &vbus_amperage.attr, ++ &vbus_connected.attr, ++ &vbus_used.attr, ++ &vbus_strong.attr, ++ NULL, ++}; ++ ++static const struct attribute_group axp20x_group_vbus = { ++ .attrs = axp20x_attributes_vbus, ++}; ++ ++/* Battery */ ++static struct kobj_attribute batt_voltage = __ATTR(voltage, S_IRUGO, axp20x_read_int, NULL); ++static struct kobj_attribute batt_amperage = __ATTR(amperage, S_IRUGO, axp20x_read_int, NULL); ++static struct kobj_attribute batt_ts_voltage = __ATTR(ts_voltage, S_IRUGO, axp20x_read_int, NULL); ++static struct kobj_attribute batt_power = __ATTR(power, S_IRUGO, axp20x_read_special, NULL); ++static struct kobj_attribute batt_charge = __ATTR(charge, S_IRUGO, axp20x_read_special, NULL); ++static struct kobj_attribute batt_capacity = __ATTR(capacity, S_IRUGO, axp20x_read_special, NULL); ++static struct kobj_attribute batt_connected = __ATTR(connected, S_IRUGO, axp20x_read_bool, NULL); ++static struct kobj_attribute batt_charging = __ATTR(charging, S_IRUGO, axp20x_read_bool, NULL); ++ ++static struct attribute *axp20x_attributes_battery[] = { ++ &batt_voltage.attr, ++ &batt_amperage.attr, ++ &batt_ts_voltage.attr, ++ &batt_power.attr, ++ &batt_charge.attr, ++ &batt_capacity.attr, ++ &batt_connected.attr, ++ &batt_charging.attr, ++ NULL, ++}; ++ ++static const struct attribute_group axp20x_group_battery = { ++ .attrs = axp20x_attributes_battery, ++}; ++ ++/* PMU */ ++static struct kobj_attribute pmu_temp = __ATTR(temp, S_IRUGO, axp20x_read_int, NULL); ++static struct kobj_attribute pmu_voltage = __ATTR(voltage, S_IRUGO, axp20x_read_int, NULL); ++static struct kobj_attribute pmu_overheat = __ATTR(overheat, S_IRUGO, axp20x_read_bool, NULL); ++ ++static struct attribute *axp20x_attributes_pmu[] = { ++ &pmu_temp.attr, ++ &pmu_voltage.attr, ++ &pmu_overheat.attr, ++ NULL, ++}; ++ ++static const struct attribute_group axp20x_group_pmu = { ++ .attrs = axp20x_attributes_pmu, ++}; ++ ++/* Charger */ ++static struct kobj_attribute charger_amperage = __ATTR(amperage, S_IRUGO, axp20x_read_int, NULL); ++static struct kobj_attribute charger_charging = __ATTR(charging, S_IRUGO, axp20x_read_bool, NULL); ++static struct kobj_attribute charger_cell_activation = __ATTR(cell_activation, S_IRUGO, axp20x_read_bool, NULL); ++static struct kobj_attribute charger_low_power = __ATTR(low_power, S_IRUGO, axp20x_read_bool, NULL); ++ ++static struct attribute *axp20x_attributes_charger[] = { ++ &charger_amperage.attr, ++ &charger_charging.attr, ++ &charger_cell_activation.attr, ++ &charger_low_power.attr, ++ NULL, ++}; ++ ++static const struct attribute_group axp20x_group_charger = { ++ .attrs = axp20x_attributes_charger, ++}; ++ ++/* Control (writeable) */ ++static struct kobj_attribute control_vbus_direct_mode = __ATTR(set_vbus_direct_mode, (S_IRUGO | S_IWUSR), ++ axp20x_read_bool, axp20x_write_bool); ++static struct kobj_attribute control_reset_charge_counter = __ATTR(reset_charge_counter, (S_IRUGO | S_IWUSR), ++ axp20x_read_bool, axp20x_write_bool); ++static struct kobj_attribute control_charge_rtc_battery = __ATTR(charge_rtc_battery, (S_IRUGO | S_IWUSR), ++ axp20x_read_bool, axp20x_write_bool); ++static struct kobj_attribute control_disable_fuel_gauge = __ATTR(disable_fuel_gauge, (S_IRUGO | S_IWUSR), ++ axp20x_read_bool, axp20x_write_bool); ++static struct kobj_attribute control_battery_rdc = __ATTR(battery_rdc, (S_IRUGO | S_IWUSR), ++ axp20x_read_int, axp20x_write_int); ++ ++static struct attribute *axp20x_attributes_control[] = { ++ &control_vbus_direct_mode.attr, ++ &control_reset_charge_counter.attr, ++ &control_charge_rtc_battery.attr, ++ &control_disable_fuel_gauge.attr, ++ &control_battery_rdc.attr, ++ NULL, ++}; ++ ++static const struct attribute_group axp20x_group_control = { ++ .attrs = axp20x_attributes_control, ++}; ++ ++static struct { ++ struct kobject *ac; ++ struct kobject *vbus; ++ struct kobject *battery; ++ struct kobject *pmu; ++ struct kobject *charger; ++ struct kobject *control; ++} subsystems; ++ ++static struct bin_attribute axp20x_ocv_curve = __BIN_ATTR(ocv_curve, S_IRUGO | S_IWUSR, ++ axp20x_sysfs_read_bin_file, axp20x_sysfs_write_bin_file, AXP20X_OCV_MAX + 1); ++ ++static void axp20x_sysfs_create_subgroup(const char name[], struct axp20x_dev *axp, ++ struct kobject *subgroup, const struct attribute_group *attrs) ++{ ++ int ret; ++ struct kobject *parent = &axp->dev->kobj; ++ subgroup = kobject_create_and_add(name, parent); ++ if (subgroup != NULL) { ++ ret = sysfs_create_group(subgroup, attrs); ++ if (ret) { ++ dev_warn(axp->dev, "Unable to register sysfs group: %s: %d", name, ret); ++ kobject_put(subgroup); ++ } ++ } ++} ++ ++static void axp20x_sysfs_remove_subgroup(struct kobject *subgroup, ++ const struct attribute_group *attrs) ++{ ++ sysfs_remove_group(subgroup, attrs); ++ kobject_put(subgroup); ++} ++ ++static int axp20x_sysfs_init(struct axp20x_dev *axp) ++{ ++ int ret; ++ unsigned int res; ++ ++ /* Enable all ADC channels in the first register */ ++ ret = regmap_write(axp->regmap, AXP20X_ADC_EN1, 0xFF); ++ if (ret) ++ dev_warn(axp->dev, "Unable to enable ADC: %d", ret); ++ ++ /* ++ * Set ADC sampling frequency to 100Hz (default is 25) ++ * Always measure battery temperature (default: only when charging) ++ */ ++ ret = regmap_update_bits(axp->regmap, AXP20X_ADC_RATE, 0xC3, 0x82); ++ if (ret) ++ dev_warn(axp->dev, "Unable to set ADC frequency and TS current output: %d", ret); ++ ++ /* Enable fuel gauge and charge counter */ ++ ret = regmap_update_bits(axp->regmap, AXP20X_FG_RES, 0x80, 0x00); ++ if (ret) ++ dev_warn(axp->dev, "Unable to enable battery fuel gauge: %d", ret); ++ /* ret = regmap_update_bits(axp->regmap, AXP20X_CC_CTRL, 0xC0, 0x00); */ ++ ret |= regmap_update_bits(axp->regmap, AXP20X_CC_CTRL, 0xC0, 0x80); ++ if (ret) ++ dev_warn(axp->dev, "Unable to enable battery charge counter: %d", ret); ++ ++ /* Enable battery detection */ ++ ret = regmap_read(axp->regmap, AXP20X_OFF_CTRL, &res); ++ if (ret == 0) { ++ if ((res & 0x40) != 0x40) { ++ dev_info(axp->dev, "Battery detection is disabled, enabling"); ++ ret = regmap_update_bits(axp->regmap, AXP20X_OFF_CTRL, 0x40, 0x40); ++ if (ret) ++ dev_warn(axp->dev, "Unable to enable battery detection: %d", ret); ++ } ++ } else ++ dev_warn(axp->dev, "Unable to read register AXP20X_OFF_CTRL: %d", ret); ++ ++ /* Get info about backup (RTC) battery */ ++ ret = regmap_read(axp->regmap, AXP20X_CHRG_BAK_CTRL, &res); ++ if (ret == 0) { ++ dev_info(axp->dev, "Backup (RTC) battery charging is %s", ++ (res & 0x80) == 0x80 ? "enabled" : "disabled"); ++ if ((res & 0x60) != 0x20) ++ dev_warn(axp->dev, "Backup (RTC) battery target voltage is not 3.0V"); ++ } else ++ dev_warn(axp->dev, "Unable to read register AXP20X_CHRG_BAK_CTRL: %d", ret); ++ ++ axp20x_sysfs_create_subgroup("ac", axp, subsystems.ac, &axp20x_group_ac); ++ axp20x_sysfs_create_subgroup("vbus", axp, subsystems.vbus, &axp20x_group_vbus); ++ axp20x_sysfs_create_subgroup("battery", axp, subsystems.battery, &axp20x_group_battery); ++ axp20x_sysfs_create_subgroup("pmu", axp, subsystems.pmu, &axp20x_group_pmu); ++ axp20x_sysfs_create_subgroup("charger", axp, subsystems.charger, &axp20x_group_charger); ++ axp20x_sysfs_create_subgroup("control", axp, subsystems.control, &axp20x_group_control); ++ ++ ret = sysfs_create_bin_file(&axp->dev->kobj, &axp20x_ocv_curve); ++ if (ret) ++ dev_warn(axp->dev, "Unable to create sysfs ocv_curve file: %d", ret); ++ ++ ret = sysfs_create_link_nowarn(power_kobj, &axp->dev->kobj, "axp_pmu"); ++ if (ret) ++ dev_warn(axp->dev, "Unable to create sysfs symlink: %d", ret); ++ return ret; ++} ++ ++static void axp20x_sysfs_exit(struct axp20x_dev *axp) ++{ ++ sysfs_delete_link(power_kobj, &axp->dev->kobj, "axp_pmu"); ++ sysfs_remove_bin_file(&axp->dev->kobj, &axp20x_ocv_curve); ++ axp20x_sysfs_remove_subgroup(subsystems.control, &axp20x_group_control); ++ axp20x_sysfs_remove_subgroup(subsystems.charger, &axp20x_group_charger); ++ axp20x_sysfs_remove_subgroup(subsystems.pmu, &axp20x_group_pmu); ++ axp20x_sysfs_remove_subgroup(subsystems.battery, &axp20x_group_battery); ++ axp20x_sysfs_remove_subgroup(subsystems.vbus, &axp20x_group_vbus); ++ axp20x_sysfs_remove_subgroup(subsystems.ac, &axp20x_group_ac); ++} ++ + int axp20x_match_device(struct axp20x_dev *axp20x) + { + struct device *dev = axp20x->dev; +@@ -1050,6 +1656,10 @@ int axp20x_device_probe(struct axp20x_dev *axp20x) + SYS_OFF_PRIO_DEFAULT, + axp20x_power_off, axp20x); + ++ if (axp20x->variant == AXP209_ID || axp20x->variant == AXP202_ID) { ++ axp20x_sysfs_init(axp20x); ++ } ++ + dev_info(axp20x->dev, "AXP20X driver loaded\n"); + + return 0; +@@ -1058,6 +1668,10 @@ EXPORT_SYMBOL(axp20x_device_probe); + + void axp20x_device_remove(struct axp20x_dev *axp20x) + { ++ if (axp20x->variant == AXP209_ID || axp20x->variant == AXP202_ID) { ++ axp20x_sysfs_exit(axp20x); ++ } ++ + mfd_remove_devices(axp20x->dev); + regmap_del_irq_chip(axp20x->irq, axp20x->regmap_irqc); + } +-- +2.34.1 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-mmc-host-sunxi-mmc-Disable-DDR52-mode-on-all-A20-based-boar.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-mmc-host-sunxi-mmc-Disable-DDR52-mode-on-all-A20-based-boar.patch new file mode 100644 index 0000000000..09ce5c5491 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-mmc-host-sunxi-mmc-Disable-DDR52-mode-on-all-A20-based-boar.patch @@ -0,0 +1,28 @@ +From 42ed87a6be1aaf8c803aa993b5410834851de2f2 Mon Sep 17 00:00:00 2001 +From: Mitko Gamishev +Date: Wed, 5 Feb 2020 15:31:25 +0200 +Subject: [PATCH 049/153] drv:mmc:host:sunxi-mmc Disable DDR52 mode on all A20 + based boards + +--- + drivers/mmc/host/sunxi-mmc.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c +index 3dc6a0990..306428e77 100644 +--- a/drivers/mmc/host/sunxi-mmc.c ++++ b/drivers/mmc/host/sunxi-mmc.c +@@ -1452,7 +1452,9 @@ static int sunxi_mmc_probe(struct platform_device *pdev) + */ + if ((host->cfg->clk_delays || host->use_new_timings) && + !of_device_is_compatible(pdev->dev.of_node, +- "allwinner,sun50i-h5-emmc")) ++ "allwinner,sun50i-h5-emmc") && ++ !of_machine_is_compatible("allwinner,sun7i-a20") && ++ !of_machine_is_compatible("olimex,a64-olinuxino-2ge8g")) + mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR; + + ret = mmc_of_parse(mmc); +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-mmc-host-sunxi-mmc-add-h5-emmc-compatible.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-mmc-host-sunxi-mmc-add-h5-emmc-compatible.patch new file mode 100644 index 0000000000..a83ede8c58 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-mmc-host-sunxi-mmc-add-h5-emmc-compatible.patch @@ -0,0 +1,38 @@ +From 4d5f19451c2a18e69c2c6fa35be2eae0b16344c7 Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Mon, 24 Jan 2022 13:26:03 +0300 +Subject: [PATCH 036/153] drv:mmc:host:sunxi-mmc: add h5 emmc compatible + +--- + drivers/mmc/host/sunxi-mmc.c | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c +index c5d048411..3dc6a0990 100644 +--- a/drivers/mmc/host/sunxi-mmc.c ++++ b/drivers/mmc/host/sunxi-mmc.c +@@ -1214,6 +1214,13 @@ static const struct sunxi_mmc_cfg sun50i_a100_emmc_cfg = { + .needs_new_timings = true, + }; + ++static const struct sunxi_mmc_cfg sun50i_h5_emmc_cfg = { ++ .idma_des_size_bits = 13, ++ .clk_delays = NULL, ++ .can_calibrate = true, ++ .needs_new_timings = false, ++}; ++ + static const struct of_device_id sunxi_mmc_of_match[] = { + { .compatible = "allwinner,sun4i-a10-mmc", .data = &sun4i_a10_cfg }, + { .compatible = "allwinner,sun5i-a13-mmc", .data = &sun5i_a13_cfg }, +@@ -1225,6 +1232,7 @@ static const struct of_device_id sunxi_mmc_of_match[] = { + { .compatible = "allwinner,sun50i-a64-emmc", .data = &sun50i_a64_emmc_cfg }, + { .compatible = "allwinner,sun50i-a100-mmc", .data = &sun50i_a100_cfg }, + { .compatible = "allwinner,sun50i-a100-emmc", .data = &sun50i_a100_emmc_cfg }, ++ { .compatible = "allwinner,sun50i-h5-emmc", .data = &sun50i_h5_emmc_cfg }, + { /* sentinel */ } + }; + MODULE_DEVICE_TABLE(of, sunxi_mmc_of_match); +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-mtd-nand-raw-nand_ids.c-add-H27UBG8T2BTR-BC-nand.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-mtd-nand-raw-nand_ids.c-add-H27UBG8T2BTR-BC-nand.patch new file mode 100644 index 0000000000..5ee9ad0a75 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-mtd-nand-raw-nand_ids.c-add-H27UBG8T2BTR-BC-nand.patch @@ -0,0 +1,27 @@ +From 488cb5a3cd33def0fef9bb82f1f38237513fe264 Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Tue, 1 Feb 2022 19:47:29 +0300 +Subject: [PATCH 039/153] drv:mtd:nand:raw:nand_ids.c add H27UBG8T2BTR-BC nand + +--- + drivers/mtd/nand/raw/nand_ids.c | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/drivers/mtd/nand/raw/nand_ids.c b/drivers/mtd/nand/raw/nand_ids.c +index dacc5529b..8f4133cd2 100644 +--- a/drivers/mtd/nand/raw/nand_ids.c ++++ b/drivers/mtd/nand/raw/nand_ids.c +@@ -47,6 +47,10 @@ struct nand_flash_dev nand_flash_ids[] = { + {"SDTNRGAMA 64G 3.3V 8-bit", + { .id = {0x45, 0xde, 0x94, 0x93, 0x76, 0x50} }, + SZ_16K, SZ_8K, SZ_4M, 0, 6, 1280, NAND_ECC_INFO(40, SZ_1K) }, ++ {"H27UBG8T2BTR-BC 32G 3.3V 8-bit", ++ { .id = {0xad, 0xd7, 0x94, 0xda, 0x74, 0xc3} }, ++ SZ_8K, SZ_4K, SZ_2M, NAND_NEED_SCRAMBLING, 6, 640, ++ NAND_ECC_INFO(40, SZ_1K) }, + {"H27UCG8T2ATR-BC 64G 3.3V 8-bit", + { .id = {0xad, 0xde, 0x94, 0xda, 0x74, 0xc4} }, + SZ_8K, SZ_8K, SZ_2M, NAND_NEED_SCRAMBLING, 6, 640, +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-net-phy-Add-support-for-AC200-EPHY.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-net-phy-Add-support-for-AC200-EPHY.patch new file mode 100644 index 0000000000..0c0ab54428 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-net-phy-Add-support-for-AC200-EPHY.patch @@ -0,0 +1,272 @@ +From b7c0b9b054e7a9df3d2d0087491017f345d18daf Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Fri, 16 Aug 2019 16:38:57 +0200 +Subject: [PATCH 006/153] drv:net:phy: Add support for AC200 EPHY + +Signed-off-by: Jernej Skrabec +--- + drivers/net/phy/Kconfig | 7 ++ + drivers/net/phy/Makefile | 1 + + drivers/net/phy/ac200.c | 220 +++++++++++++++++++++++++++++++++++++++ + 3 files changed, 228 insertions(+) + create mode 100644 drivers/net/phy/ac200.c + +diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig +index 1327290de..61684250a 100644 +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -62,6 +62,13 @@ config SFP + + comment "MII PHY device drivers" + ++config AC200_PHY ++ tristate "AC200 EPHY" ++ depends on NVMEM ++ depends on OF ++ help ++ Fast ethernet PHY as found in X-Powers AC200 multi-function device. ++ + config AMD_PHY + tristate "AMD PHYs" + help +diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile +index f7138d3c8..9ad2b8cc0 100644 +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -30,6 +30,7 @@ obj-$(CONFIG_SFP) += sfp.o + sfp-obj-$(CONFIG_SFP) += sfp-bus.o + obj-y += $(sfp-obj-y) $(sfp-obj-m) + ++obj-$(CONFIG_AC200_PHY) += ac200.o + obj-$(CONFIG_ADIN_PHY) += adin.o + obj-$(CONFIG_ADIN1100_PHY) += adin1100.o + obj-$(CONFIG_AMD_PHY) += amd.o +diff --git a/drivers/net/phy/ac200.c b/drivers/net/phy/ac200.c +new file mode 100644 +index 000000000..cb713188f +--- /dev/null ++++ b/drivers/net/phy/ac200.c +@@ -0,0 +1,220 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/** ++ * Driver for AC200 Ethernet PHY ++ * ++ * Copyright (c) 2020 Jernej Skrabec ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define AC200_EPHY_ID 0x00441400 ++#define AC200_EPHY_ID_MASK 0x0ffffff0 ++ ++/* macros for system ephy control 0 register */ ++#define AC200_EPHY_RESET_INVALID BIT(0) ++#define AC200_EPHY_SYSCLK_GATING BIT(1) ++ ++/* macros for system ephy control 1 register */ ++#define AC200_EPHY_E_EPHY_MII_IO_EN BIT(0) ++#define AC200_EPHY_E_LNK_LED_IO_EN BIT(1) ++#define AC200_EPHY_E_SPD_LED_IO_EN BIT(2) ++#define AC200_EPHY_E_DPX_LED_IO_EN BIT(3) ++ ++/* macros for ephy control register */ ++#define AC200_EPHY_SHUTDOWN BIT(0) ++#define AC200_EPHY_LED_POL BIT(1) ++#define AC200_EPHY_CLK_SEL BIT(2) ++#define AC200_EPHY_ADDR(x) (((x) & 0x1F) << 4) ++#define AC200_EPHY_XMII_SEL BIT(11) ++#define AC200_EPHY_CALIB(x) (((x) & 0xF) << 12) ++ ++struct ac200_ephy_dev { ++ struct clk *clk; ++ struct phy_driver *ephy; ++ struct regmap *regmap; ++}; ++ ++static char *ac200_phy_name = "AC200 EPHY"; ++ ++static int ac200_ephy_config_init(struct phy_device *phydev) ++{ ++ const struct ac200_ephy_dev *priv = phydev->drv->driver_data; ++ unsigned int value; ++ int ret; ++ ++ phy_write(phydev, 0x1f, 0x0100); /* Switch to Page 1 */ ++ phy_write(phydev, 0x12, 0x4824); /* Disable APS */ ++ ++ phy_write(phydev, 0x1f, 0x0200); /* Switch to Page 2 */ ++ phy_write(phydev, 0x18, 0x0000); /* PHYAFE TRX optimization */ ++ ++ phy_write(phydev, 0x1f, 0x0600); /* Switch to Page 6 */ ++ phy_write(phydev, 0x14, 0x708f); /* PHYAFE TX optimization */ ++ phy_write(phydev, 0x13, 0xF000); /* PHYAFE RX optimization */ ++ phy_write(phydev, 0x15, 0x1530); ++ ++ phy_write(phydev, 0x1f, 0x0800); /* Switch to Page 6 */ ++ phy_write(phydev, 0x18, 0x00bc); /* PHYAFE TRX optimization */ ++ ++ phy_write(phydev, 0x1f, 0x0100); /* switch to page 1 */ ++ phy_clear_bits(phydev, 0x17, BIT(3)); /* disable intelligent IEEE */ ++ ++ /* next two blocks disable 802.3az IEEE */ ++ phy_write(phydev, 0x1f, 0x0200); /* switch to page 2 */ ++ phy_write(phydev, 0x18, 0x0000); ++ ++ phy_write(phydev, 0x1f, 0x0000); /* switch to page 0 */ ++ phy_clear_bits_mmd(phydev, 0x7, 0x3c, BIT(1)); ++ ++ if (phydev->interface == PHY_INTERFACE_MODE_RMII) ++ value = AC200_EPHY_XMII_SEL; ++ else ++ value = 0; ++ ++ ret = regmap_update_bits(priv->regmap, AC200_EPHY_CTL, ++ AC200_EPHY_XMII_SEL, value); ++ if (ret) ++ return ret; ++ ++ /* FIXME: This is H6 specific */ ++ phy_set_bits(phydev, 0x13, BIT(12)); ++ ++ return 0; ++} ++ ++static int ac200_ephy_probe(struct platform_device *pdev) ++{ ++ struct ac200_dev *ac200 = dev_get_drvdata(pdev->dev.parent); ++ struct device *dev = &pdev->dev; ++ struct ac200_ephy_dev *priv; ++ struct nvmem_cell *calcell; ++ struct phy_driver *ephy; ++ u16 *caldata, calib; ++ size_t callen; ++ int ret; ++ ++ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); ++ if (!priv) ++ return -ENOMEM; ++ ++ ephy = devm_kzalloc(dev, sizeof(*ephy), GFP_KERNEL); ++ if (!ephy) ++ return -ENOMEM; ++ ++ priv->clk = devm_clk_get(dev, NULL); ++ if (IS_ERR(priv->clk)) { ++ dev_err(dev, "Can't obtain the clock!\n"); ++ return PTR_ERR(priv->clk); ++ } ++ ++ calcell = devm_nvmem_cell_get(dev, "calibration"); ++ if (IS_ERR(calcell)) { ++ dev_err(dev, "Unable to find calibration data!\n"); ++ return PTR_ERR(calcell); ++ } ++ ++ caldata = nvmem_cell_read(calcell, &callen); ++ if (IS_ERR(caldata)) { ++ dev_err(dev, "Unable to read calibration data!\n"); ++ return PTR_ERR(caldata); ++ } ++ ++ if (callen != 2) { ++ dev_err(dev, "Calibration data has wrong length: 2 != %zu\n", ++ callen); ++ kfree(caldata); ++ return -EINVAL; ++ } ++ ++ calib = *caldata + 3; ++ kfree(caldata); ++ ++ ret = clk_prepare_enable(priv->clk); ++ if (ret) ++ return ret; ++ ++ ephy->phy_id = AC200_EPHY_ID; ++ ephy->phy_id_mask = AC200_EPHY_ID_MASK; ++ ephy->name = ac200_phy_name; ++ ephy->driver_data = priv; ++ ephy->soft_reset = genphy_soft_reset; ++ ephy->config_init = ac200_ephy_config_init; ++ ephy->suspend = genphy_suspend; ++ ephy->resume = genphy_resume; ++ ++ priv->ephy = ephy; ++ priv->regmap = ac200->regmap; ++ platform_set_drvdata(pdev, priv); ++ ++ ret = regmap_write(ac200->regmap, AC200_SYS_EPHY_CTL0, ++ AC200_EPHY_RESET_INVALID | ++ AC200_EPHY_SYSCLK_GATING); ++ if (ret) ++ return ret; ++ ++ ret = regmap_write(ac200->regmap, AC200_SYS_EPHY_CTL1, ++ AC200_EPHY_E_EPHY_MII_IO_EN | ++ AC200_EPHY_E_LNK_LED_IO_EN | ++ AC200_EPHY_E_SPD_LED_IO_EN | ++ AC200_EPHY_E_DPX_LED_IO_EN); ++ if (ret) ++ return ret; ++ ++ ret = regmap_write(ac200->regmap, AC200_EPHY_CTL, ++ AC200_EPHY_LED_POL | ++ AC200_EPHY_CLK_SEL | ++ AC200_EPHY_ADDR(1) | ++ AC200_EPHY_CALIB(calib)); ++ if (ret) ++ return ret; ++ ++ ret = phy_driver_register(priv->ephy, THIS_MODULE); ++ if (ret) { ++ dev_err(dev, "Unable to register phy\n"); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static int ac200_ephy_remove(struct platform_device *pdev) ++{ ++ struct ac200_ephy_dev *priv = platform_get_drvdata(pdev); ++ ++ phy_driver_unregister(priv->ephy); ++ ++ regmap_write(priv->regmap, AC200_EPHY_CTL, AC200_EPHY_SHUTDOWN); ++ regmap_write(priv->regmap, AC200_SYS_EPHY_CTL1, 0); ++ regmap_write(priv->regmap, AC200_SYS_EPHY_CTL0, 0); ++ ++ clk_disable_unprepare(priv->clk); ++ ++ return 0; ++} ++ ++static const struct of_device_id ac200_ephy_match[] = { ++ { .compatible = "x-powers,ac200-ephy" }, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, ac200_ephy_match); ++ ++static struct platform_driver ac200_ephy_driver = { ++ .probe = ac200_ephy_probe, ++ .remove = ac200_ephy_remove, ++ .driver = { ++ .name = "ac200-ephy", ++ .of_match_table = ac200_ephy_match, ++ }, ++}; ++module_platform_driver(ac200_ephy_driver); ++ ++MODULE_AUTHOR("Jernej Skrabec "); ++MODULE_DESCRIPTION("AC200 Ethernet PHY driver"); ++MODULE_LICENSE("GPL"); +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-net-stmmac-dwmac-sun8i-second-EMAC-clock-register.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-net-stmmac-dwmac-sun8i-second-EMAC-clock-register.patch new file mode 100644 index 0000000000..836bf60583 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-net-stmmac-dwmac-sun8i-second-EMAC-clock-register.patch @@ -0,0 +1,65 @@ +From a07bdcc66e753dd1e954c83dce6fe62b0cadd213 Mon Sep 17 00:00:00 2001 +From: Andre Przywara +Date: Thu, 10 Dec 2020 14:42:12 +0000 +Subject: [PATCH 011/153] drv:net:stmmac:dwmac-sun8i: second EMAC clock + register + +The Allwinner H616 SoC has two EMAC controllers, with the second one +being tied to the internal PHY, but also using a separate EMAC clock +register. + +To tell the driver about which clock register to use, we add a parameter +to our syscon phandle. The driver will use this value as an index into +the regmap, so that we can address more than the first register, if +needed. + +Signed-off-by: Andre Przywara +--- + drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 12 ++++++++++-- + 1 file changed, 10 insertions(+), 2 deletions(-) + +diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c +index 3fc0fcee4..c830f0584 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c +@@ -1145,11 +1145,13 @@ static int sun8i_dwmac_probe(struct platform_device *pdev) + struct stmmac_resources stmmac_res; + struct sunxi_priv_data *gmac; + struct device *dev = &pdev->dev; ++ struct reg_field syscon_field; + phy_interface_t interface; + int ret; + struct stmmac_priv *priv; + struct net_device *ndev; + struct regmap *regmap; ++ u32 syscon_idx = 0; + + ret = stmmac_get_platform_resources(pdev, &stmmac_res); + if (ret) +@@ -1204,8 +1206,12 @@ static int sun8i_dwmac_probe(struct platform_device *pdev) + return ret; + } + +- gmac->regmap_field = devm_regmap_field_alloc(dev, regmap, +- *gmac->variant->syscon_field); ++ syscon_field = *gmac->variant->syscon_field; ++ ret = of_property_read_u32_index(pdev->dev.of_node, "syscon", 1, ++ &syscon_idx); ++ if (!ret) ++ syscon_field.reg += syscon_idx * sizeof(u32); ++ gmac->regmap_field = devm_regmap_field_alloc(dev, regmap, syscon_field); + if (IS_ERR(gmac->regmap_field)) { + ret = PTR_ERR(gmac->regmap_field); + dev_err(dev, "Unable to map syscon register: %d\n", ret); +@@ -1334,6 +1340,8 @@ static const struct of_device_id sun8i_dwmac_match[] = { + .data = &emac_variant_a64 }, + { .compatible = "allwinner,sun50i-h6-emac", + .data = &emac_variant_h6 }, ++ { .compatible = "allwinner,sun50i-h616-emac", ++ .data = &emac_variant_h6 }, + { } + }; + MODULE_DEVICE_TABLE(of, sun8i_dwmac_match); +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-nvmem-sunxi_sid-Support-SID-on-H616.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-nvmem-sunxi_sid-Support-SID-on-H616.patch new file mode 100644 index 0000000000..3826983023 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-nvmem-sunxi_sid-Support-SID-on-H616.patch @@ -0,0 +1,41 @@ +From 35d1347e746dd52a2997e13eaa380b5332f42efc Mon Sep 17 00:00:00 2001 +From: Kali Prasad +Date: Sun, 19 Sep 2021 13:28:10 +0530 +Subject: [PATCH 044/153] drv:nvmem:sunxi_sid: Support SID on H616 + +Add support for H616's SID controller. It supports 4K-bit +EFUSE. + +Signed-off-by: Kali Prasad +--- + drivers/nvmem/sunxi_sid.c | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/drivers/nvmem/sunxi_sid.c b/drivers/nvmem/sunxi_sid.c +index 92dfe4cb1..4d69dfb3f 100644 +--- a/drivers/nvmem/sunxi_sid.c ++++ b/drivers/nvmem/sunxi_sid.c +@@ -213,6 +213,12 @@ static const struct sunxi_sid_cfg sun50i_h6_cfg = { + .size = 0x200, + }; + ++static const struct sunxi_sid_cfg sun50i_h616_cfg = { ++ .value_offset = 0x200, ++ .size = 0x100, ++ .need_register_readout = true, ++}; ++ + static const struct of_device_id sunxi_sid_of_match[] = { + { .compatible = "allwinner,sun4i-a10-sid", .data = &sun4i_a10_cfg }, + { .compatible = "allwinner,sun7i-a20-sid", .data = &sun7i_a20_cfg }, +@@ -222,6 +228,7 @@ static const struct of_device_id sunxi_sid_of_match[] = { + { .compatible = "allwinner,sun50i-a64-sid", .data = &sun50i_a64_cfg }, + { .compatible = "allwinner,sun50i-h5-sid", .data = &sun50i_a64_cfg }, + { .compatible = "allwinner,sun50i-h6-sid", .data = &sun50i_h6_cfg }, ++ { .compatible = "allwinner,sun50i-h616-sid", .data = &sun50i_h616_cfg }, + {/* sentinel */}, + }; + MODULE_DEVICE_TABLE(of, sunxi_sid_of_match); +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-of-Device-Tree-Overlay-ConfigFS-interface.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-of-Device-Tree-Overlay-ConfigFS-interface.patch new file mode 100644 index 0000000000..594388334c --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-of-Device-Tree-Overlay-ConfigFS-interface.patch @@ -0,0 +1,342 @@ +From 83e7b1834cab75e396fb8f2c60bb7f9f46b61f2c Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Tue, 1 Feb 2022 19:22:21 +0300 +Subject: [PATCH 106/153] drv:of: Device Tree Overlay ConfigFS interface + +--- + drivers/of/Kconfig | 7 + + drivers/of/Makefile | 1 + + drivers/of/configfs.c | 277 +++++++++++++++++++++++++++++++++++++++ + drivers/of/fdt_address.c | 2 +- + 4 files changed, 286 insertions(+), 1 deletion(-) + create mode 100644 drivers/of/configfs.c + +diff --git a/drivers/of/Kconfig b/drivers/of/Kconfig +index 80b5fd44a..4f1869262 100644 +--- a/drivers/of/Kconfig ++++ b/drivers/of/Kconfig +@@ -87,6 +87,13 @@ config OF_OVERLAY + While this option is selected automatically when needed, you can + enable it manually to improve device tree unit test coverage. + ++config OF_CONFIGFS ++ bool "Device Tree Overlay ConfigFS interface" ++ select CONFIGFS_FS ++ depends on OF_OVERLAY ++ help ++ Enable a simple user-space driven DT overlay interface. ++ + config OF_NUMA + bool + +diff --git a/drivers/of/Makefile b/drivers/of/Makefile +index e0360a443..9d088c759 100644 +--- a/drivers/of/Makefile ++++ b/drivers/of/Makefile +@@ -11,6 +11,7 @@ obj-$(CONFIG_OF_UNITTEST) += unittest.o + obj-$(CONFIG_OF_RESERVED_MEM) += of_reserved_mem.o + obj-$(CONFIG_OF_RESOLVE) += resolver.o + obj-$(CONFIG_OF_OVERLAY) += overlay.o ++obj-$(CONFIG_OF_CONFIGFS) += configfs.o + obj-$(CONFIG_OF_NUMA) += of_numa.o + + ifdef CONFIG_KEXEC_FILE +diff --git a/drivers/of/configfs.c b/drivers/of/configfs.c +new file mode 100644 +index 000000000..ac04301da +--- /dev/null ++++ b/drivers/of/configfs.c +@@ -0,0 +1,277 @@ ++/* ++ * Configfs entries for device-tree ++ * ++ * Copyright (C) 2013 - Pantelis Antoniou ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version ++ * 2 of the License, or (at your option) any later version. ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "of_private.h" ++ ++struct cfs_overlay_item { ++ struct config_item item; ++ ++ char path[PATH_MAX]; ++ ++ const struct firmware *fw; ++ struct device_node *overlay; ++ int ov_id; ++ ++ void *dtbo; ++ int dtbo_size; ++}; ++ ++static inline struct cfs_overlay_item *to_cfs_overlay_item( ++ struct config_item *item) ++{ ++ return item ? container_of(item, struct cfs_overlay_item, item) : NULL; ++} ++ ++static ssize_t cfs_overlay_item_path_show(struct config_item *item, ++ char *page) ++{ ++ struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); ++ return sprintf(page, "%s\n", overlay->path); ++} ++ ++static ssize_t cfs_overlay_item_path_store(struct config_item *item, ++ const char *page, size_t count) ++{ ++ struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); ++ const char *p = page; ++ char *s; ++ int err; ++ ++ /* if it's set do not allow changes */ ++ if (overlay->path[0] != '\0' || overlay->dtbo_size > 0) ++ return -EPERM; ++ ++ /* copy to path buffer (and make sure it's always zero terminated */ ++ count = snprintf(overlay->path, sizeof(overlay->path) - 1, "%s", p); ++ overlay->path[sizeof(overlay->path) - 1] = '\0'; ++ ++ /* strip trailing newlines */ ++ s = overlay->path + strlen(overlay->path); ++ while (s > overlay->path && *--s == '\n') ++ *s = '\0'; ++ ++ pr_debug("%s: path is '%s'\n", __func__, overlay->path); ++ ++ err = request_firmware(&overlay->fw, overlay->path, NULL); ++ if (err != 0) ++ goto out_err; ++ ++ err = of_overlay_fdt_apply((void *)overlay->fw->data, ++ (u32)overlay->fw->size, &overlay->ov_id); ++ if (err != 0) ++ goto out_err; ++ ++ return count; ++ ++out_err: ++ ++ release_firmware(overlay->fw); ++ overlay->fw = NULL; ++ ++ overlay->path[0] = '\0'; ++ return err; ++} ++ ++static ssize_t cfs_overlay_item_status_show(struct config_item *item, ++ char *page) ++{ ++ struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); ++ ++ return sprintf(page, "%s\n", ++ overlay->ov_id > 0 ? "applied" : "unapplied"); ++} ++ ++CONFIGFS_ATTR(cfs_overlay_item_, path); ++CONFIGFS_ATTR_RO(cfs_overlay_item_, status); ++ ++static struct configfs_attribute *cfs_overlay_attrs[] = { ++ &cfs_overlay_item_attr_path, ++ &cfs_overlay_item_attr_status, ++ NULL, ++}; ++ ++ssize_t cfs_overlay_item_dtbo_read(struct config_item *item, ++ void *buf, size_t max_count) ++{ ++ struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); ++ ++ pr_debug("%s: buf=%p max_count=%zu\n", __func__, ++ buf, max_count); ++ ++ if (overlay->dtbo == NULL) ++ return 0; ++ ++ /* copy if buffer provided */ ++ if (buf != NULL) { ++ /* the buffer must be large enough */ ++ if (overlay->dtbo_size > max_count) ++ return -ENOSPC; ++ ++ memcpy(buf, overlay->dtbo, overlay->dtbo_size); ++ } ++ ++ return overlay->dtbo_size; ++} ++ ++ssize_t cfs_overlay_item_dtbo_write(struct config_item *item, ++ const void *buf, size_t count) ++{ ++ struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); ++ int err; ++ ++ /* if it's set do not allow changes */ ++ if (overlay->path[0] != '\0' || overlay->dtbo_size > 0) ++ return -EPERM; ++ ++ /* copy the contents */ ++ overlay->dtbo = kmemdup(buf, count, GFP_KERNEL); ++ if (overlay->dtbo == NULL) ++ return -ENOMEM; ++ ++ overlay->dtbo_size = count; ++ ++ err = of_overlay_fdt_apply(overlay->dtbo, overlay->dtbo_size, ++ &overlay->ov_id); ++ if (err != 0) ++ goto out_err; ++ ++ return count; ++ ++out_err: ++ kfree(overlay->dtbo); ++ overlay->dtbo = NULL; ++ overlay->dtbo_size = 0; ++ overlay->ov_id = 0; ++ ++ return err; ++} ++ ++CONFIGFS_BIN_ATTR(cfs_overlay_item_, dtbo, NULL, SZ_1M); ++ ++static struct configfs_bin_attribute *cfs_overlay_bin_attrs[] = { ++ &cfs_overlay_item_attr_dtbo, ++ NULL, ++}; ++ ++static void cfs_overlay_release(struct config_item *item) ++{ ++ struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); ++ ++ if (overlay->ov_id > 0) ++ of_overlay_remove(&overlay->ov_id); ++ if (overlay->fw) ++ release_firmware(overlay->fw); ++ /* kfree with NULL is safe */ ++ kfree(overlay->dtbo); ++ kfree(overlay); ++} ++ ++static struct configfs_item_operations cfs_overlay_item_ops = { ++ .release = cfs_overlay_release, ++}; ++ ++static struct config_item_type cfs_overlay_type = { ++ .ct_item_ops = &cfs_overlay_item_ops, ++ .ct_attrs = cfs_overlay_attrs, ++ .ct_bin_attrs = cfs_overlay_bin_attrs, ++ .ct_owner = THIS_MODULE, ++}; ++ ++static struct config_item *cfs_overlay_group_make_item( ++ struct config_group *group, const char *name) ++{ ++ struct cfs_overlay_item *overlay; ++ ++ overlay = kzalloc(sizeof(*overlay), GFP_KERNEL); ++ if (!overlay) ++ return ERR_PTR(-ENOMEM); ++ ++ config_item_init_type_name(&overlay->item, name, &cfs_overlay_type); ++ return &overlay->item; ++} ++ ++static void cfs_overlay_group_drop_item(struct config_group *group, ++ struct config_item *item) ++{ ++ struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); ++ ++ config_item_put(&overlay->item); ++} ++ ++static struct configfs_group_operations overlays_ops = { ++ .make_item = cfs_overlay_group_make_item, ++ .drop_item = cfs_overlay_group_drop_item, ++}; ++ ++static struct config_item_type overlays_type = { ++ .ct_group_ops = &overlays_ops, ++ .ct_owner = THIS_MODULE, ++}; ++ ++static struct configfs_group_operations of_cfs_ops = { ++ /* empty - we don't allow anything to be created */ ++}; ++ ++static struct config_item_type of_cfs_type = { ++ .ct_group_ops = &of_cfs_ops, ++ .ct_owner = THIS_MODULE, ++}; ++ ++struct config_group of_cfs_overlay_group; ++ ++static struct configfs_subsystem of_cfs_subsys = { ++ .su_group = { ++ .cg_item = { ++ .ci_namebuf = "device-tree", ++ .ci_type = &of_cfs_type, ++ }, ++ }, ++ .su_mutex = __MUTEX_INITIALIZER(of_cfs_subsys.su_mutex), ++}; ++ ++static int __init of_cfs_init(void) ++{ ++ int ret; ++ ++ pr_info("%s\n", __func__); ++ ++ config_group_init(&of_cfs_subsys.su_group); ++ config_group_init_type_name(&of_cfs_overlay_group, "overlays", ++ &overlays_type); ++ configfs_add_default_group(&of_cfs_overlay_group, ++ &of_cfs_subsys.su_group); ++ ++ ret = configfs_register_subsystem(&of_cfs_subsys); ++ if (ret != 0) { ++ pr_err("%s: failed to register subsys\n", __func__); ++ goto out; ++ } ++ pr_info("%s: OK\n", __func__); ++out: ++ return ret; ++} ++late_initcall(of_cfs_init); +diff --git a/drivers/of/fdt_address.c b/drivers/of/fdt_address.c +index 1dc15ab78..f697f2a52 100644 +--- a/drivers/of/fdt_address.c ++++ b/drivers/of/fdt_address.c +@@ -160,7 +160,7 @@ static int __init fdt_translate_one(const void *blob, int parent, + * that can be mapped to a cpu physical address). This is not really specified + * that way, but this is traditionally the way IBM at least do things + */ +-static u64 __init fdt_translate_address(const void *blob, int node_offset) ++u64 __init fdt_translate_address(const void *blob, int node_offset) + { + int parent, len; + const struct of_bus *bus, *pbus; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-phy-sun4i-usb-Allow-reset-line-to-be-shared.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-phy-sun4i-usb-Allow-reset-line-to-be-shared.patch new file mode 100644 index 0000000000..d7739cc011 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-phy-sun4i-usb-Allow-reset-line-to-be-shared.patch @@ -0,0 +1,36 @@ +From 05630de9be5963bcc0adb08b4e9b20efb3f1bb97 Mon Sep 17 00:00:00 2001 +From: Andre Przywara +Date: Mon, 10 May 2021 11:01:31 +0100 +Subject: [PATCH 012/153] drv:phy: sun4i-usb: Allow reset line to be shared + +The USB HCIs (and PHYs?) in Allwinner's newer generation SoCs (H616) +rely on the reset line of USB PHY 2 to be de-asserted, even when only +one of the other PHYs is actually in use. + +To make those ports work, we include this reset line in the HCIs' resets +property, which requires this line to be shareable. + +Change the call to allocate the reset line to mark it as shared, to +enable the other ports on those SoCs. + +Signed-off-by: Andre Przywara +--- + drivers/phy/allwinner/phy-sun4i-usb.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c +index c05f5de82..4bc98772f 100644 +--- a/drivers/phy/allwinner/phy-sun4i-usb.c ++++ b/drivers/phy/allwinner/phy-sun4i-usb.c +@@ -883,7 +883,7 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev) + } + + snprintf(name, sizeof(name), "usb%d_reset", i); +- phy->reset = devm_reset_control_get(dev, name); ++ phy->reset = devm_reset_control_get_shared(dev, name); + if (IS_ERR(phy->reset)) { + dev_err(dev, "failed to get reset %s\n", name); + return PTR_ERR(phy->reset); +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-pinctrl-pinctrl-sun50i-a64-disable_strict_mode.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-pinctrl-pinctrl-sun50i-a64-disable_strict_mode.patch new file mode 100644 index 0000000000..8cd1177e35 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-pinctrl-pinctrl-sun50i-a64-disable_strict_mode.patch @@ -0,0 +1,30 @@ +From 28f2415d3b43bd7c351c44218d90c49c22f35fa7 Mon Sep 17 00:00:00 2001 +From: WaterByWind +Date: Sun, 14 Apr 2019 16:16:09 -0400 +Subject: [PATCH 005/153] drv:pinctrl: pinctrl-sun50i-a64 disable_strict_mode + +With kernel 4.15.y (and later): +* Strict mode was enabled by default via commit 1396007286b1e2fd5dd10ae6a5ccaaaed51ab762 which can/will cause breakage with existing implementations. +* The ability to configure strict mode was added via commit aae842a3ff3385f27f1df8a9ee1494a416ec032d to allow older drivers to maintain existing behavior and avoid breakage. +* Commit cd70387f892205bcd7b8093b0837269b0739cbe0 had then explicitly disabled strict mode for most other existing SoCs but did not include A64. + +This change is to update the A64 pinctrl driver similar to the other pre-existing SoC pinctrl drivers. +--- + drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c +index 7b83d3755..bea52c5a9 100644 +--- a/drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c ++++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c +@@ -578,6 +578,7 @@ static const struct sunxi_pinctrl_desc a64_pinctrl_data = { + .pins = a64_pins, + .npins = ARRAY_SIZE(a64_pins), + .irq_banks = 3, ++ .disable_strict_mode = true, + }; + + static int a64_pinctrl_probe(struct platform_device *pdev) +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-pinctrl-sunxi-pinctrl-sun50i-h6.c-GPIO-disable_strict_mode.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-pinctrl-sunxi-pinctrl-sun50i-h6.c-GPIO-disable_strict_mode.patch new file mode 100644 index 0000000000..861f6e0b33 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-pinctrl-sunxi-pinctrl-sun50i-h6.c-GPIO-disable_strict_mode.patch @@ -0,0 +1,25 @@ +From 6c8ed785b14b2334a850305869e413ce7028b8d0 Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Tue, 1 Feb 2022 19:11:11 +0300 +Subject: [PATCH 037/153] drv:pinctrl:sunxi:pinctrl-sun50i-h6.c GPIO + disable_strict_mode + +--- + drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c +index 3cc112158..1182cc864 100644 +--- a/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c ++++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c +@@ -588,6 +588,7 @@ static const unsigned int h6_irq_bank_map[] = { 1, 5, 6, 7 }; + static const struct sunxi_pinctrl_desc h6_pinctrl_data = { + .pins = h6_pins, + .npins = ARRAY_SIZE(h6_pins), ++ .disable_strict_mode = true, + .irq_banks = 4, + .irq_bank_map = h6_irq_bank_map, + .irq_read_needs_mux = true, +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-pmic-add-axp313a.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-pmic-add-axp313a.patch new file mode 100644 index 0000000000..18b98af93b --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-pmic-add-axp313a.patch @@ -0,0 +1,310 @@ +From b463f0218eb20a70871ec943aa192b257d47d7a3 Mon Sep 17 00:00:00 2001 +From: Martin Botka +Date: Wed, 18 Jan 2023 21:25:56 +0100 +Subject: [PATCH] axp20x: Add support for AXP313a PMIC + +The X-Powers AXP313a is a PMIC used on some devices with the Allwinner +H616 or H313 SoC. + +Signed-off-by: Martin Botka +Signed-off-by: Andre Przywara +--- + drivers/mfd/axp20x-i2c.c | 2 + + drivers/mfd/axp20x.c | 61 ++++++++++++++++++++++++++++ + drivers/regulator/axp20x-regulator.c | 60 +++++++++++++++++++++++++++ + include/linux/mfd/axp20x.h | 32 +++++++++++++++ + 4 files changed, 155 insertions(+) + +diff --git a/drivers/mfd/axp20x-i2c.c b/drivers/mfd/axp20x-i2c.c +index b4f5cb457117..0635164d39c7 100644 +--- a/drivers/mfd/axp20x-i2c.c ++++ b/drivers/mfd/axp20x-i2c.c +@@ -63,6 +63,7 @@ static const struct of_device_id axp20x_i2c_of_match[] = { + { .compatible = "x-powers,axp209", .data = (void *)AXP209_ID }, + { .compatible = "x-powers,axp221", .data = (void *)AXP221_ID }, + { .compatible = "x-powers,axp223", .data = (void *)AXP223_ID }, ++ { .compatible = "x-powers,axp313a", .data = (void *)AXP313A_ID}, + { .compatible = "x-powers,axp803", .data = (void *)AXP803_ID }, + { .compatible = "x-powers,axp806", .data = (void *)AXP806_ID }, + { .compatible = "x-powers,axp15060", .data = (void *)AXP15060_ID }, +@@ -77,6 +78,7 @@ static const struct i2c_device_id axp20x_i2c_id[] = { + { "axp209", 0 }, + { "axp221", 0 }, + { "axp223", 0 }, ++ { "axp313a", 0 }, + { "axp803", 0 }, + { "axp806", 0 }, + { "axp15060", 0 }, +diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c +index 5416b2ecc8f3..5187b89b5de5 100644 +--- a/drivers/mfd/axp20x.c ++++ b/drivers/mfd/axp20x.c +@@ -39,6 +39,7 @@ static const char * const axp20x_model_names[] = { + "AXP221", + "AXP223", + "AXP288", ++ "AXP313a", + "AXP803", + "AXP806", + "AXP809", +@@ -157,6 +158,24 @@ static const struct regmap_range axp806_writeable_ranges[] = { + regmap_reg_range(AXP806_REG_ADDR_EXT, AXP806_REG_ADDR_EXT), + }; + ++static const struct regmap_range axp313a_writeable_ranges[] = { ++ regmap_reg_range(AXP313A_ON_INDICATE, AXP313A_IRQ_STATE), ++}; ++ ++static const struct regmap_range axp313a_volatile_ranges[] = { ++ regmap_reg_range(AXP313A_ON_INDICATE, AXP313A_IRQ_STATE), ++}; ++ ++static const struct regmap_access_table axp313a_writeable_table = { ++ .yes_ranges = axp313a_writeable_ranges, ++ .n_yes_ranges = ARRAY_SIZE(axp313a_writeable_ranges), ++}; ++ ++static const struct regmap_access_table axp313a_volatile_table = { ++ .yes_ranges = axp313a_volatile_ranges, ++ .n_yes_ranges = ARRAY_SIZE(axp313a_volatile_ranges), ++}; ++ + static const struct regmap_range axp806_volatile_ranges[] = { + regmap_reg_range(AXP20X_IRQ1_STATE, AXP20X_IRQ2_STATE), + }; +@@ -335,6 +354,15 @@ static const struct regmap_config axp288_regmap_config = { + .cache_type = REGCACHE_RBTREE, + }; + ++static const struct regmap_config axp313a_regmap_config = { ++ .reg_bits = 8, ++ .val_bits = 8, ++ .wr_table = &axp313a_writeable_table, ++ .volatile_table = &axp313a_volatile_table, ++ .max_register = AXP313A_IRQ_STATE, ++ .cache_type = REGCACHE_RBTREE, ++}; ++ + static const struct regmap_config axp806_regmap_config = { + .reg_bits = 8, + .val_bits = 8, +@@ -487,6 +515,16 @@ static const struct regmap_irq axp288_regmap_irqs[] = { + INIT_REGMAP_IRQ(AXP288, BC_USB_CHNG, 5, 1), + }; + ++static const struct regmap_irq axp313a_regmap_irqs[] = { ++ INIT_REGMAP_IRQ(AXP313A, PEK_RIS_EDGE, 0, 7), ++ INIT_REGMAP_IRQ(AXP313A, PEK_FAL_EDGE, 0, 6), ++ INIT_REGMAP_IRQ(AXP313A, PEK_SHORT, 0, 5), ++ INIT_REGMAP_IRQ(AXP313A, PEK_LONG, 0, 4), ++ INIT_REGMAP_IRQ(AXP313A, DCDC3_V_LOW, 0, 3), ++ INIT_REGMAP_IRQ(AXP313A, DCDC2_V_LOW, 0, 2), ++ INIT_REGMAP_IRQ(AXP313A, DIE_TEMP_HIGH, 0, 0), ++}; ++ + static const struct regmap_irq axp803_regmap_irqs[] = { + INIT_REGMAP_IRQ(AXP803, ACIN_OVER_V, 0, 7), + INIT_REGMAP_IRQ(AXP803, ACIN_PLUGIN, 0, 6), +@@ -637,6 +675,17 @@ static const struct regmap_irq_chip axp288_regmap_irq_chip = { + + }; + ++static const struct regmap_irq_chip axp313a_regmap_irq_chip = { ++ .name = "axp313a_irq_chip", ++ .status_base = AXP313A_IRQ_STATE, ++ .ack_base = AXP313A_IRQ_STATE, ++ .unmask_base = AXP313A_IRQ_EN, ++ .init_ack_masked = true, ++ .irqs = axp313a_regmap_irqs, ++ .num_irqs = ARRAY_SIZE(axp313a_regmap_irqs), ++ .num_regs = 1, ++}; ++ + static const struct regmap_irq_chip axp803_regmap_irq_chip = { + .name = "axp803", + .status_base = AXP20X_IRQ1_STATE, +@@ -782,6 +831,12 @@ static const struct mfd_cell axp152_cells[] = { + }, + }; + ++static struct mfd_cell axp313a_cells[] = { ++ { ++ .name = "axp20x-regulator", ++ }, ++}; ++ + static const struct resource axp288_adc_resources[] = { + DEFINE_RES_IRQ_NAMED(AXP288_IRQ_GPADC, "GPADC"), + }; +@@ -1627,6 +1682,12 @@ int axp20x_match_device(struct axp20x_dev *axp20x) + axp20x->regmap_irq_chip = &axp288_regmap_irq_chip; + axp20x->irq_flags = IRQF_TRIGGER_LOW; + break; ++ case AXP313A_ID: ++ axp20x->nr_cells = ARRAY_SIZE(axp313a_cells); ++ axp20x->cells = axp313a_cells; ++ axp20x->regmap_cfg = &axp313a_regmap_config; ++ axp20x->regmap_irq_chip = &axp313a_regmap_irq_chip; ++ break; + case AXP803_ID: + axp20x->nr_cells = ARRAY_SIZE(axp803_cells); + axp20x->cells = axp803_cells; +diff --git a/drivers/regulator/axp20x-regulator.c b/drivers/regulator/axp20x-regulator.c +index 2bbbfa9e7ef1..201631dfd4e4 100644 +--- a/drivers/regulator/axp20x-regulator.c ++++ b/drivers/regulator/axp20x-regulator.c +@@ -136,6 +136,11 @@ + #define AXP22X_PWR_OUT_DLDO4_MASK BIT_MASK(6) + #define AXP22X_PWR_OUT_ALDO3_MASK BIT_MASK(7) + ++#define AXP313A_DCDC1_NUM_VOLTAGES 107 ++#define AXP313A_DCDC23_NUM_VOLTAGES 88 ++#define AXP313A_DCDC_V_OUT_MASK GENMASK(6, 0) ++#define AXP313A_LDO_V_OUT_MASK GENMASK(4, 0) ++ + #define AXP803_PWR_OUT_DCDC1_MASK BIT_MASK(0) + #define AXP803_PWR_OUT_DCDC2_MASK BIT_MASK(1) + #define AXP803_PWR_OUT_DCDC3_MASK BIT_MASK(2) +@@ -640,6 +645,48 @@ static const struct regulator_desc axp22x_drivevbus_regulator = { + .ops = &axp20x_ops_sw, + }; + ++static const struct linear_range axp313a_dcdc1_ranges[] = { ++ REGULATOR_LINEAR_RANGE(500000, 0, 70, 10000), ++ REGULATOR_LINEAR_RANGE(1220000, 71, 87, 20000), ++ REGULATOR_LINEAR_RANGE(1600000, 88, 106, 100000), ++}; ++ ++static const struct linear_range axp313a_dcdc2_ranges[] = { ++ REGULATOR_LINEAR_RANGE(500000, 0, 70, 10000), ++ REGULATOR_LINEAR_RANGE(1220000, 71, 87, 20000), ++}; ++ ++/* ++ * This is deviating from the datasheet. The values here are taken from the ++ * BSP driver and have been confirmed by measurements. ++ */ ++static const struct linear_range axp313a_dcdc3_ranges[] = { ++ REGULATOR_LINEAR_RANGE(500000, 0, 70, 10000), ++ REGULATOR_LINEAR_RANGE(1220000, 71, 102, 20000), ++}; ++ ++static const struct regulator_desc axp313a_regulators[] = { ++ AXP_DESC_RANGES(AXP313A, DCDC1, "dcdc1", "vin1", ++ axp313a_dcdc1_ranges, AXP313A_DCDC1_NUM_VOLTAGES, ++ AXP313A_DCDC1_CONRTOL, AXP313A_DCDC_V_OUT_MASK, ++ AXP313A_OUTPUT_CONTROL, BIT(0)), ++ AXP_DESC_RANGES(AXP313A, DCDC2, "dcdc2", "vin2", ++ axp313a_dcdc2_ranges, AXP313A_DCDC23_NUM_VOLTAGES, ++ AXP313A_DCDC2_CONRTOL, AXP313A_DCDC_V_OUT_MASK, ++ AXP313A_OUTPUT_CONTROL, BIT(1)), ++ AXP_DESC_RANGES(AXP313A, DCDC3, "dcdc3", "vin3", ++ axp313a_dcdc3_ranges, AXP313A_DCDC23_NUM_VOLTAGES, ++ AXP313A_DCDC3_CONRTOL, AXP313A_DCDC_V_OUT_MASK, ++ AXP313A_OUTPUT_CONTROL, BIT(2)), ++ AXP_DESC(AXP313A, LDO1, "ldo1", "vin1", 500, 3500, 100, ++ AXP313A_ALDO1_CONRTOL, AXP313A_LDO_V_OUT_MASK, ++ AXP313A_OUTPUT_CONTROL, BIT(3)), ++ AXP_DESC(AXP313A, LDO2, "ldo2", "vin1", 500, 3500, 100, ++ AXP313A_DLDO1_CONRTOL, AXP313A_LDO_V_OUT_MASK, ++ AXP313A_OUTPUT_CONTROL, BIT(4)), ++ AXP_DESC_FIXED(AXP313A, RTC_LDO, "rtc-ldo", "vin1", 1800), ++}; ++ + /* DCDC ranges shared with AXP813 */ + static const struct linear_range axp803_dcdc234_ranges[] = { + REGULATOR_LINEAR_RANGE(500000, +@@ -1042,6 +1089,15 @@ static int axp20x_set_dcdc_freq(struct platform_device *pdev, u32 dcdcfreq) + def = 3000; + step = 150; + break; ++ case AXP313A_ID: ++ /* The DCDC PWM frequency seems to be fixed to 3 MHz. */ ++ if (dcdcfreq != 3000000) { ++ dev_err(&pdev->dev, ++ "DCDC frequency on AXP313a is fixed to 3 MHz.\n"); ++ return -EINVAL; ++ } ++ ++ return 0; + default: + dev_err(&pdev->dev, + "Setting DCDC frequency for unsupported AXP variant\n"); +@@ -1234,6 +1290,10 @@ static int axp20x_regulator_probe(struct platform_device *pdev) + drivevbus = of_property_read_bool(pdev->dev.parent->of_node, + "x-powers,drive-vbus-en"); + break; ++ case AXP313A_ID: ++ regulators = axp313a_regulators; ++ nregulators = AXP313A_REG_ID_MAX; ++ break; + case AXP803_ID: + regulators = axp803_regulators; + nregulators = AXP803_REG_ID_MAX; +diff --git a/include/linux/mfd/axp20x.h b/include/linux/mfd/axp20x.h +index e9c45e3c65c9..298e38cd756f 100644 +--- a/include/linux/mfd/axp20x.h ++++ b/include/linux/mfd/axp20x.h +@@ -17,6 +17,7 @@ enum axp20x_variants { + AXP221_ID, + AXP223_ID, + AXP288_ID, ++ AXP313A_ID, + AXP803_ID, + AXP806_ID, + AXP809_ID, +@@ -92,6 +93,17 @@ enum axp20x_variants { + #define AXP22X_ALDO3_V_OUT 0x2a + #define AXP22X_CHRG_CTRL3 0x35 + ++#define AXP313A_ON_INDICATE 0x00 ++#define AXP313A_OUTPUT_CONTROL 0x10 ++#define AXP313A_DCDC1_CONRTOL 0x13 ++#define AXP313A_DCDC2_CONRTOL 0x14 ++#define AXP313A_DCDC3_CONRTOL 0x15 ++#define AXP313A_ALDO1_CONRTOL 0x16 ++#define AXP313A_DLDO1_CONRTOL 0x17 ++#define AXP313A_OUTPUT_MONITOR 0x1d ++#define AXP313A_IRQ_EN 0x20 ++#define AXP313A_IRQ_STATE 0x21 ++ + #define AXP806_STARTUP_SRC 0x00 + #define AXP806_CHIP_ID 0x03 + #define AXP806_PWR_OUT_CTRL1 0x10 +@@ -364,6 +376,16 @@ enum { + AXP22X_REG_ID_MAX, + }; + ++enum { ++ AXP313A_DCDC1 = 0, ++ AXP313A_DCDC2, ++ AXP313A_DCDC3, ++ AXP313A_LDO1, ++ AXP313A_LDO2, ++ AXP313A_RTC_LDO, ++ AXP313A_REG_ID_MAX, ++}; ++ + enum { + AXP806_DCDCA = 0, + AXP806_DCDCB, +@@ -617,6 +639,16 @@ enum axp288_irqs { + AXP288_IRQ_BC_USB_CHNG, + }; + ++enum axp313a_irqs { ++ AXP313A_IRQ_DIE_TEMP_HIGH, ++ AXP313A_IRQ_DCDC2_V_LOW = 2, ++ AXP313A_IRQ_DCDC3_V_LOW, ++ AXP313A_IRQ_PEK_LONG, ++ AXP313A_IRQ_PEK_SHORT, ++ AXP313A_IRQ_PEK_FAL_EDGE, ++ AXP313A_IRQ_PEK_RIS_EDGE, ++}; ++ + enum axp803_irqs { + AXP803_IRQ_ACIN_OVER_V = 1, + AXP803_IRQ_ACIN_PLUGIN, +-- +2.34.1 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-rgb-add-ws2812.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-rgb-add-ws2812.patch new file mode 100644 index 0000000000..6795508f41 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-rgb-add-ws2812.patch @@ -0,0 +1,276 @@ +From 3686bcadaf45fc312a131435652c75987a4745ab Mon Sep 17 00:00:00 2001 +From: Alan +Date: Sat, 20 May 2023 17:26:21 +0800 +Subject: [PATCH] Add: ws2812 RGB driver for allwinner H616 + +--- + drivers/leds/rgb/Kconfig | 7 + + drivers/leds/rgb/Makefile | 1 + + drivers/leds/rgb/leds-ws2812.c | 230 +++++++++++++++++++++++++++++++++ + 3 files changed, 238 insertions(+) + create mode 100644 drivers/leds/rgb/leds-ws2812.c + +diff --git a/drivers/leds/rgb/Kconfig b/drivers/leds/rgb/Kconfig +index 360c8679c6e2..3b5297d841bf 100644 +--- a/drivers/leds/rgb/Kconfig ++++ b/drivers/leds/rgb/Kconfig +@@ -40,3 +40,10 @@ config LEDS_MT6370_RGB + will be called "leds-mt6370-rgb". + + endif # LEDS_CLASS_MULTICOLOR ++ ++config LEDS_WS2812 ++ tristate "WS2812 RGB support for allwinner H616" ++ depends on PINCTRL_SUN50I_H616 ++ ++ help ++ Say Y here if you want to use the WS2812. +\ No newline at end of file +diff --git a/drivers/leds/rgb/Makefile b/drivers/leds/rgb/Makefile +index 8c01daf63f61..1edcb4942edf 100644 +--- a/drivers/leds/rgb/Makefile ++++ b/drivers/leds/rgb/Makefile +@@ -3,3 +3,4 @@ + obj-$(CONFIG_LEDS_PWM_MULTICOLOR) += leds-pwm-multicolor.o + obj-$(CONFIG_LEDS_QCOM_LPG) += leds-qcom-lpg.o + obj-$(CONFIG_LEDS_MT6370_RGB) += leds-mt6370-rgb.o ++obj-$(CONFIG_LEDS_WS2812) += leds-ws2812.o +diff --git a/drivers/leds/rgb/leds-ws2812.c b/drivers/leds/rgb/leds-ws2812.c +new file mode 100644 +index 000000000000..a89030fe815e +--- /dev/null ++++ b/drivers/leds/rgb/leds-ws2812.c +@@ -0,0 +1,230 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Copyright (c) 2023, The Linux Foundation. All rights reserved. ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define GPIO_BASE 0x0300B000 ++#define GPIO_DAT_OFFSET(n) ((n)*0x0024 + 0x10) ++ ++static uint32_t ws2812_pin = 0; ++static volatile uint32_t *ws2812_gpio_port; ++static volatile uint32_t ws2812_gpio_bit; ++static volatile uint32_t ws2812_set_val = 0; ++static volatile uint32_t ws2812_reset_val = 0; ++ ++DEFINE_SPINLOCK(lock); ++ ++// ws2812 reset ++static void ws2812_rst(void) ++{ ++ *ws2812_gpio_port &= ~ws2812_gpio_bit; ++ udelay(200);// RES low voltage time, Above 50µs ++} ++ ++static void ws2812_Write_24Bits(uint32_t grb) ++{ ++ uint8_t i; ++ for (i = 0; i < 24; i++) ++ { ++ if (grb & 0x800000) ++ { ++ // loop for delay about 700ns ++ *ws2812_gpio_port = ws2812_set_val; ++ *ws2812_gpio_port = ws2812_set_val; ++ *ws2812_gpio_port = ws2812_set_val; ++ *ws2812_gpio_port = ws2812_set_val; ++ *ws2812_gpio_port = ws2812_set_val; ++ *ws2812_gpio_port = ws2812_set_val; ++ *ws2812_gpio_port = ws2812_set_val; ++ // loop for delay about 600ns ++ *ws2812_gpio_port = ws2812_reset_val; ++ *ws2812_gpio_port = ws2812_reset_val; ++ *ws2812_gpio_port = ws2812_reset_val; ++ *ws2812_gpio_port = ws2812_reset_val; ++ *ws2812_gpio_port = ws2812_reset_val; ++ *ws2812_gpio_port = ws2812_reset_val; ++ } ++ else ++ { ++ // loop for delay about 200ns ++ *ws2812_gpio_port = ws2812_set_val; ++ *ws2812_gpio_port = ws2812_set_val; ++ // loop for delay about 800ns ++ *ws2812_gpio_port = ws2812_reset_val; ++ *ws2812_gpio_port = ws2812_reset_val; ++ *ws2812_gpio_port = ws2812_reset_val; ++ *ws2812_gpio_port = ws2812_reset_val; ++ *ws2812_gpio_port = ws2812_reset_val; ++ *ws2812_gpio_port = ws2812_reset_val; ++ *ws2812_gpio_port = ws2812_reset_val; ++ *ws2812_gpio_port = ws2812_reset_val; ++ } ++ grb <<= 1; ++ } ++} ++ ++static void ws2812_write_array(uint32_t *rgb, uint32_t cnt) ++{ ++ uint32_t i = 0; ++ unsigned long flags; ++ ++ for (i = 0; i < cnt; i++) ++ { ++ // rgb -> grb ++ rgb[i] = (((rgb[i] >> 16) & 0xff) << 8) | (((rgb[i] >> 8) & 0xff) << 16) | ((rgb[i]) & 0xff); ++ } ++ ++ spin_lock_irqsave(&lock, flags); ++ ws2812_set_val = *ws2812_gpio_port | ws2812_gpio_bit; ++ ws2812_reset_val = *ws2812_gpio_port & (~ws2812_gpio_bit); ++ ws2812_rst(); ++ for (i = 0; i < cnt; i++) ++ { ++ ws2812_Write_24Bits(rgb[i]); ++ } ++ spin_unlock_irqrestore(&lock, flags); ++} ++ ++ssize_t ws2812_read(struct file *file, char __user *user, size_t bytesize, loff_t *this_loff_t) ++{ ++ return 0; ++} ++ ++ssize_t ws2812_write(struct file *file, const char __user *user_buf, size_t count, loff_t *ppos) ++{ ++ uint32_t rgb[255]; ++ unsigned long ret = 0; ++ ++ if (count > 255 * 4) count = 255 * 4; ++ ret = copy_from_user(&rgb[0], user_buf, count); ++ if (ret < 0) ++ { ++ printk("copy_from_user fail!!!\n"); ++ return -1; ++ } ++ ++ ws2812_write_array((uint32_t *)rgb, count / 4); ++ ++ return 0; ++} ++ ++int ws2812_open(struct inode *inode, struct file *file) ++{ ++ return 0; ++} ++ ++int ws2812_close(struct inode *inode, struct file *file) ++{ ++ return 0; ++} ++ ++static struct file_operations ws2812_ops = { ++ .owner = THIS_MODULE, ++ .open = ws2812_open, ++ .release = ws2812_close, ++ .write = ws2812_write, ++}; ++ ++static struct miscdevice ws2812_misc_dev = { ++ .minor = MISC_DYNAMIC_MINOR, ++ .name = "ws2812-led", ++ .fops = &ws2812_ops, ++}; ++ ++static int ws2812_probe(struct platform_device *pdev) ++{ ++ int ret; ++ enum of_gpio_flags flag; ++ struct device_node *ws2812_gpio_node = pdev->dev.of_node; ++ uint32_t rgb_cnt = 0; ++ uint32_t rgb[255]; ++ ++ of_property_read_u32(ws2812_gpio_node, "rgb_cnt", &rgb_cnt); ++ if (rgb_cnt > 255) ++ rgb_cnt = 255; ++ ++ of_property_read_u32_array(ws2812_gpio_node, "rgb_value", rgb, rgb_cnt); ++ ws2812_pin = of_get_named_gpio_flags(ws2812_gpio_node, "gpios", 0, &flag); ++ if (!gpio_is_valid(ws2812_pin)) ++ { ++ printk(KERN_ERR "ws2812: gpio: %d is invalid\n", ws2812_pin); ++ return -ENODEV; ++ } ++ ++ ws2812_gpio_port = ioremap(GPIO_BASE + GPIO_DAT_OFFSET((ws2812_pin >> 5)), 4); ++ ws2812_gpio_bit = 1 << (ws2812_pin & 0x001F); ++ ++ if (gpio_request(ws2812_pin, "ws2812-gpio")) ++ { ++ printk(KERN_ERR "ws2812: gpio %d request failed!\n", ws2812_pin); ++ gpio_free(ws2812_pin); ++ return -ENODEV; ++ } ++ gpio_direction_output(ws2812_pin, 0); ++ ++ ret = misc_register(&ws2812_misc_dev); ++ msleep(50); ++ ++ ws2812_write_array(rgb, rgb_cnt); ++ ++ return 0; ++} ++ ++static int ws2812_remove(struct platform_device *pdev) ++{ ++ misc_deregister(&ws2812_misc_dev); ++ gpio_free(ws2812_pin); ++ ++ return 0; ++} ++ ++static const struct of_device_id ws2812_of_match[] = { ++ {.compatible = "rgb-ws2812"}, ++ {/* sentinel */}}; ++ ++MODULE_DEVICE_TABLE(of, ws2812_of_match); ++ ++static struct platform_driver ws2812_driver = { ++ .probe = ws2812_probe, ++ .remove = ws2812_remove, ++ .driver = { ++ .name = "ws2812_ctl", ++ .of_match_table = ws2812_of_match, ++ }, ++}; ++ ++module_platform_driver(ws2812_driver); ++ ++MODULE_AUTHOR("MacLodge, Alan Ma "); ++MODULE_DESCRIPTION("WS2812 RGB driver for Allwinner"); ++MODULE_LICENSE("GPL"); ++MODULE_ALIAS("platform:ws2812_ctl"); +-- +2.34.1 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-rtc-sun6i-Add-Allwinner-H616-support.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-rtc-sun6i-Add-Allwinner-H616-support.patch new file mode 100644 index 0000000000..4b9658cdd8 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-rtc-sun6i-Add-Allwinner-H616-support.patch @@ -0,0 +1,45 @@ +From 5049a970b604afb2be749b1383fc33ce62c36946 Mon Sep 17 00:00:00 2001 +From: Andre Przywara +Date: Wed, 21 Apr 2021 12:46:43 +0100 +Subject: [PATCH] drv:rtc: sun6i: Add Allwinner H616 support + +The H616 RTC changes its day storage to the newly introduced linear day +scheme, so pair the new compatible string with this feature flag. +The clock part is missing an external 32768 Hz oscillator input pin, +for future expansion we must thus ignore any provided clock for now. + +Signed-off-by: Andre Przywara +--- + drivers/rtc/rtc-sun6i.c | 16 ++++++++++++++++ + 1 file changed, 16 insertions(+) + +diff --git a/drivers/rtc/rtc-sun6i.c b/drivers/rtc/rtc-sun6i.c +index afc9efa3c..7dff3e563 100644 +--- a/drivers/rtc/rtc-sun6i.c ++++ b/drivers/rtc/rtc-sun6i.c +@@ -389,6 +389,22 @@ static void __init sun50i_h6_rtc_clk_init(struct device_node *node) + CLK_OF_DECLARE_DRIVER(sun50i_h6_rtc_clk, "allwinner,sun50i-h6-rtc", + sun50i_h6_rtc_clk_init); + ++static const struct sun6i_rtc_clk_data sun50i_h616_rtc_data = { ++ .rc_osc_rate = 16000000, ++ .fixed_prescaler = 32, ++ .has_prescaler = 1, ++ .has_out_clk = 1, ++ .no_ext_losc = 1, ++}; ++ ++static void __init sun50i_h616_rtc_clk_init(struct device_node *node) ++{ ++ sun6i_rtc_clk_init(node, &sun50i_h616_rtc_data); ++} ++ ++CLK_OF_DECLARE_DRIVER(sun50i_h616_rtc_clk, "allwinner,sun50i-h616-rtc", ++ sun50i_h616_rtc_clk_init); ++ + /* + * The R40 user manual is self-conflicting on whether the prescaler is + * fixed or configurable. The clock diagram shows it as fixed, but there +-- +2.34.1 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-rtc-sun6i-support-RTCs-without-external-LOSCs.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-rtc-sun6i-support-RTCs-without-external-LOSCs.patch new file mode 100644 index 0000000000..75780d68d8 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-rtc-sun6i-support-RTCs-without-external-LOSCs.patch @@ -0,0 +1,68 @@ +From 39a581f3767abc3548b649ed6c9f0211d549a639 Mon Sep 17 00:00:00 2001 +From: Andre Przywara +Date: Mon, 14 Jun 2021 23:02:45 +0100 +Subject: [PATCH] drv:rtc:sun6i: support RTCs without external LOSCs + +Some newer Allwinner RTCs (for instance the one in the H616 SoC) lack +a pin for an external 32768 Hz oscillator. As a consequence, this LOSC +can't be selected as the RTC clock source, and we must rely on the +internal RC oscillator. +To allow additions of clocks to the RTC node, add a feature bit to ignore +any provided clocks for now (the current code would think this is the +external LOSC). Later DTs and code can then for instance add the PLL +based clock input, and older kernel won't get confused. + +Signed-off-by: Andre Przywara +Acked-by: Jernej Skrabec +--- + drivers/rtc/rtc-sun6i.c | 16 +++++++++++----- + 1 file changed, 11 insertions(+), 5 deletions(-) + +diff --git a/drivers/rtc/rtc-sun6i.c b/drivers/rtc/rtc-sun6i.c +index c7fe6d1356df..055d2503c9da 100644 +--- a/drivers/rtc/rtc-sun6i.c ++++ b/drivers/rtc/rtc-sun6i.c +@@ -138,6 +138,7 @@ struct sun6i_rtc_clk_data { + unsigned int has_out_clk : 1; + unsigned int has_losc_en : 1; + unsigned int has_auto_swt : 1; ++ unsigned int no_ext_losc : 1; + }; + + #define RTC_LINEAR_DAY BIT(0) +@@ -260,7 +261,7 @@ static void __init sun6i_rtc_clk_init(struct device_node *node, + } + + /* Switch to the external, more precise, oscillator, if present */ +- if (of_property_present(node, "clocks")) { ++ if (!rtc->data->no_ext_losc && of_get_property(node, "clocks", NULL)) { + reg |= SUN6I_LOSC_CTRL_EXT_OSC; + if (rtc->data->has_losc_en) + reg |= SUN6I_LOSC_CTRL_EXT_LOSC_EN; +@@ -284,14 +285,19 @@ static void __init sun6i_rtc_clk_init(struct device_node *node, + } + + parents[0] = clk_hw_get_name(rtc->int_osc); +- /* If there is no external oscillator, this will be NULL and ... */ +- parents[1] = of_clk_get_parent_name(node, 0); ++ if (rtc->data->no_ext_losc) { ++ parents[1] = NULL; ++ init.num_parents = 1; ++ } else { ++ /* If there is no external oscillator, this will be NULL and */ ++ parents[1] = of_clk_get_parent_name(node, 0); ++ /* ... number of clock parents will be 1. */ ++ init.num_parents = of_clk_get_parent_count(node) + 1; ++ } + + rtc->hw.init = &init; + + init.parent_names = parents; +- /* ... number of clock parents will be 1. */ +- init.num_parents = of_clk_get_parent_count(node) + 1; + of_property_read_string_index(node, "clock-output-names", 0, + &init.name); + +-- +2.34.1 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-soc-sunxi-sram-Add-SRAM-C1-H616-handling.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-soc-sunxi-sram-Add-SRAM-C1-H616-handling.patch new file mode 100644 index 0000000000..ab5b385acf --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-soc-sunxi-sram-Add-SRAM-C1-H616-handling.patch @@ -0,0 +1,41 @@ +From 63f440a2ab720b8d147aa4b78090c80469a45961 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sat, 16 Oct 2021 21:26:41 +0200 +Subject: [PATCH 026/153] drv:soc: sunxi: sram: Add SRAM C1 H616 handling + +Signed-off-by: Jernej Skrabec +--- + drivers/soc/sunxi/sunxi_sram.c | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +diff --git a/drivers/soc/sunxi/sunxi_sram.c b/drivers/soc/sunxi/sunxi_sram.c +index 92f9186c1..69c2685a2 100644 +--- a/drivers/soc/sunxi/sunxi_sram.c ++++ b/drivers/soc/sunxi/sunxi_sram.c +@@ -70,6 +70,12 @@ static struct sunxi_sram_desc sun4i_a10_sram_c1 = { + SUNXI_SRAM_MAP(0x7fffffff, 1, "ve")), + }; + ++static struct sunxi_sram_desc sun50i_h616_sram_c1 = { ++ .data = SUNXI_SRAM_DATA("C1", 0x0, 0x0, 31, ++ SUNXI_SRAM_MAP(0x7fffffff, 0, "cpu"), ++ SUNXI_SRAM_MAP(0, 1, "ve")), ++}; ++ + static struct sunxi_sram_desc sun4i_a10_sram_d = { + .data = SUNXI_SRAM_DATA("D", 0x4, 0x0, 1, + SUNXI_SRAM_MAP(0, 0, "cpu"), +@@ -99,6 +105,10 @@ static const struct of_device_id sunxi_sram_dt_ids[] = { + .compatible = "allwinner,sun50i-a64-sram-c", + .data = &sun50i_a64_sram_c.data, + }, ++ { ++ .compatible = "allwinner,sun50i-h616-sram-c1", ++ .data = &sun50i_h616_sram_c1.data, ++ }, + {} + }; + +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-spi-spi-sun4i.c-spi-bug-low-on-sck.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-spi-spi-sun4i.c-spi-bug-low-on-sck.patch new file mode 100644 index 0000000000..111d6e04a8 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-spi-spi-sun4i.c-spi-bug-low-on-sck.patch @@ -0,0 +1,36 @@ +From 5af44e9b267f377ea8b1e949db5c6d1b4906b0c9 Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Wed, 2 Feb 2022 14:16:31 +0300 +Subject: [PATCH 042/153] drv:spi:spi-sun4i.c spi bug low on sck + +--- + drivers/spi/spi-sun4i.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/drivers/spi/spi-sun4i.c b/drivers/spi/spi-sun4i.c +index 6000d0761..513f81d91 100644 +--- a/drivers/spi/spi-sun4i.c ++++ b/drivers/spi/spi-sun4i.c +@@ -389,6 +389,7 @@ static int sun4i_spi_runtime_resume(struct device *dev) + struct spi_master *master = dev_get_drvdata(dev); + struct sun4i_spi *sspi = spi_master_get_devdata(master); + int ret; ++ u32 reg; + + ret = clk_prepare_enable(sspi->hclk); + if (ret) { +@@ -401,9 +402,10 @@ static int sun4i_spi_runtime_resume(struct device *dev) + dev_err(dev, "Couldn't enable module clock\n"); + goto err; + } ++ reg = sun4i_spi_read(sspi, SUN4I_CTL_REG); + + sun4i_spi_write(sspi, SUN4I_CTL_REG, +- SUN4I_CTL_ENABLE | SUN4I_CTL_MASTER | SUN4I_CTL_TP); ++ reg | SUN4I_CTL_ENABLE | SUN4I_CTL_MASTER | SUN4I_CTL_TP); + + return 0; + +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-spi-spidev-Add-armbian-spi-dev-compatible.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-spi-spidev-Add-armbian-spi-dev-compatible.patch new file mode 100644 index 0000000000..b69a3fa723 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-spi-spidev-Add-armbian-spi-dev-compatible.patch @@ -0,0 +1,37 @@ +From 539ff3682d8c15aa3d9687dbdfcbab7b1343e6bf Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Wed, 2 Feb 2022 11:56:51 +0300 +Subject: [PATCH] drv:spi:spidev Add armbian spi-dev compatible + +--- + drivers/spi/spidev.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/drivers/spi/spidev.c b/drivers/spi/spidev.c +index 5a038c667..ab68dc7f4 100644 +--- a/drivers/spi/spidev.c ++++ b/drivers/spi/spidev.c +@@ -703,6 +703,7 @@ static const struct file_operations spidev_fops = { + static struct class *spidev_class; + + static const struct spi_device_id spidev_spi_ids[] = { ++ { .name = "spi-dev" }, + { .name = "dh2228fv" }, + { .name = "ltc2488" }, + { .name = "sx1301" }, +@@ -727,10 +728,12 @@ static int spidev_of_check(struct device *dev) + return 0; + + dev_err(dev, "spidev listed directly in DT is not supported\n"); ++ dev_info(dev, "Use a compatible alias string like spi-dev in DT\n"); + return -EINVAL; + } + + static const struct of_device_id spidev_dt_ids[] = { ++ { .compatible = "armbian,spi-dev", .data = &spidev_of_check }, + { .compatible = "cisco,spi-petra", .data = &spidev_of_check }, + { .compatible = "dh,dhcom-board", .data = &spidev_of_check }, + { .compatible = "lineartechnology,ltc2488", .data = &spidev_of_check }, +-- +2.34.1 + diff --git a/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-staging-fbtft-add-st7796s.patch b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-staging-fbtft-add-st7796s.patch new file mode 100644 index 0000000000..7c4075cd0c --- /dev/null +++ b/patch/kernel/archive/sunxi-6.4/patches.armbian/drv-staging-fbtft-add-st7796s.patch @@ -0,0 +1,154 @@ +From 90e98efc54a4d7d538553061287eb8b4f7a5dad8 Mon Sep 17 00:00:00 2001 +From: Alan +Date: Sat, 20 May 2023 14:33:52 +0800 +Subject: [PATCH 09/13] Add: FB_TFT ST7796S driver + +--- + drivers/staging/fbtft/Kconfig | 10 +++ + drivers/staging/fbtft/Makefile | 1 + + drivers/staging/fbtft/fb_st7796s.c | 100 +++++++++++++++++++++++++++++ + 3 files changed, 111 insertions(+) + create mode 100644 drivers/staging/fbtft/fb_st7796s.c + +diff --git a/drivers/staging/fbtft/Kconfig b/drivers/staging/fbtft/Kconfig +index 4d29e8c1014e..e46688e92419 100644 +--- a/drivers/staging/fbtft/Kconfig ++++ b/drivers/staging/fbtft/Kconfig +@@ -171,6 +171,16 @@ config FB_TFT_ST7789V + + Say Y if you have such a display that utilizes this controller. + ++config FB_TFT_ST7796S ++ tristate "FB driver for the ST7796S LCD Controller" ++ depends on FB_TFT ++ help ++ This enables generic framebuffer support for the Sitronix ST7796S ++ display controller. The controller is intended for small color ++ displays with a resolution of up to 480x320 pixels. ++ ++ Say Y if you have such a display that utilizes this controller. ++ + config FB_TFT_TINYLCD + tristate "FB driver for tinylcd.com display" + depends on FB_TFT +diff --git a/drivers/staging/fbtft/Makefile b/drivers/staging/fbtft/Makefile +index e9cdf0f0a7da..7b2098b8a1bd 100644 +--- a/drivers/staging/fbtft/Makefile ++++ b/drivers/staging/fbtft/Makefile +@@ -31,6 +31,7 @@ obj-$(CONFIG_FB_TFT_SSD1331) += fb_ssd1331.o + obj-$(CONFIG_FB_TFT_SSD1351) += fb_ssd1351.o + obj-$(CONFIG_FB_TFT_ST7735R) += fb_st7735r.o + obj-$(CONFIG_FB_TFT_ST7789V) += fb_st7789v.o ++obj-$(CONFIG_FB_TFT_ST7796S) += fb_st7796s.o + obj-$(CONFIG_FB_TFT_TINYLCD) += fb_tinylcd.o + obj-$(CONFIG_FB_TFT_TLS8204) += fb_tls8204.o + obj-$(CONFIG_FB_TFT_UC1611) += fb_uc1611.o +diff --git a/drivers/staging/fbtft/fb_st7796s.c b/drivers/staging/fbtft/fb_st7796s.c +new file mode 100644 +index 000000000000..cad489cef595 +--- /dev/null ++++ b/drivers/staging/fbtft/fb_st7796s.c +@@ -0,0 +1,100 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * FB driver for the ST7796S LCD Controller ++ * ++ * Copyright (c) 2023 Alan Ma ++ * Copyright (c) 2014 Petr Olivka ++ * Copyright (c) 2013 Noralf Tronnes ++ */ ++ ++#include ++#include ++#include ++#include ++#include