From 343facaa9220b54955221c08348d474b98d0dad4 Mon Sep 17 00:00:00 2001 From: Igor Pecovnik Date: Thu, 5 Nov 2020 21:10:13 +0100 Subject: [PATCH] Move Meson64 to 5.9.y HDMI audio works on C4 and N2, tested desktop builds --- config/kernel/linux-meson64-current.config | 123 +++-- .../families/include/meson64_common.inc | 2 +- ...eson-gxbb-add-playback-audio-devices.patch | 48 -- ...rcc-Add-modifier-definitions-for-des.patch | 111 ----- ...eson-add-Amlogic-Video-FBC-registers.patch | 60 --- ...on-overlay-setup-overlay-for-Amlogic.patch | 425 ------------------ ...on-crtc-handle-commit-of-Amlogic-FBC.patch | 160 ------- ...oC-meson-add-2-8-channel-constraints.patch | 62 --- ...ard-khadas-vim3-change-LED-behaviour.patch | 4 +- ...ard-khadas-vim3l-add-audio-playback-.patch | 133 ------ ...x-drive-strength-register-and-bit-ca.patch | 41 -- .../meson64-current/odroid-c4-audio-1.patch | 140 ------ .../meson64-current/odroid-n2-audio-1.patch | 128 ------ .../meson64-current/odroid-n2-audio-2.patch | 174 ------- ...atchdog-to-g12-common-dtsi.patch.txt.patch | 30 ++ 15 files changed, 121 insertions(+), 1520 deletions(-) delete mode 100644 patch/kernel/meson64-current/0053-WIP-arm64-dts-meson-gxbb-add-playback-audio-devices.patch delete mode 100644 patch/kernel/meson64-current/0076-FROMLIST-drm-fourcc-Add-modifier-definitions-for-des.patch delete mode 100644 patch/kernel/meson64-current/0077-FROMLIST-drm-meson-add-Amlogic-Video-FBC-registers.patch delete mode 100644 patch/kernel/meson64-current/0078-FROMLIST-drm-meson-overlay-setup-overlay-for-Amlogic.patch delete mode 100644 patch/kernel/meson64-current/0079-FROMLIST-drm-meson-crtc-handle-commit-of-Amlogic-FBC.patch delete mode 100644 patch/kernel/meson64-current/0085-WIP-ASoC-meson-add-2-8-channel-constraints.patch delete mode 100644 patch/kernel/meson64-current/board-khadas-vim3l-add-audio-playback-.patch delete mode 100644 patch/kernel/meson64-current/hardkernel-0022-pinctrl-meson-fix-drive-strength-register-and-bit-ca.patch delete mode 100644 patch/kernel/meson64-current/odroid-c4-audio-1.patch delete mode 100644 patch/kernel/meson64-current/odroid-n2-audio-1.patch delete mode 100644 patch/kernel/meson64-current/odroid-n2-audio-2.patch create mode 100644 patch/kernel/meson64-dev/dts-meson-add-watchdog-to-g12-common-dtsi.patch.txt.patch diff --git a/config/kernel/linux-meson64-current.config b/config/kernel/linux-meson64-current.config index 408a5556cc..2f087f7f21 100644 --- a/config/kernel/linux-meson64-current.config +++ b/config/kernel/linux-meson64-current.config @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm64 5.8.16 Kernel Configuration +# Linux/arm64 5.9.6 Kernel Configuration # CONFIG_CC_VERSION_TEXT="aarch64-none-linux-gnu-gcc (GNU Toolchain for the A-profile Architecture 9.2-2019.12 (arm-9.10)) 9.2.1 20191025" CONFIG_CC_IS_GCC=y @@ -163,6 +163,7 @@ CONFIG_CGROUP_BPF=y CONFIG_SOCK_CGROUP_DATA=y CONFIG_NAMESPACES=y CONFIG_UTS_NS=y +CONFIG_TIME_NS=y CONFIG_IPC_NS=y CONFIG_USER_NS=y CONFIG_PID_NS=y @@ -179,6 +180,7 @@ CONFIG_RD_LZMA=y CONFIG_RD_XZ=y CONFIG_RD_LZO=y CONFIG_RD_LZ4=y +CONFIG_RD_ZSTD=y # CONFIG_BOOT_CONFIG is not set CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -290,10 +292,12 @@ CONFIG_ARCH_PROC_KCORE_TEXT=y # CONFIG_ARCH_BITMAIN is not set # CONFIG_ARCH_BRCMSTB is not set # CONFIG_ARCH_EXYNOS is not set +# CONFIG_ARCH_SPARX5 is not set # CONFIG_ARCH_K3 is not set # CONFIG_ARCH_LAYERSCAPE is not set # CONFIG_ARCH_LG1K is not set # CONFIG_ARCH_HISI is not set +# CONFIG_ARCH_KEEMBAY is not set # CONFIG_ARCH_MEDIATEK is not set CONFIG_ARCH_MESON=y # CONFIG_ARCH_MVEBU is not set @@ -405,7 +409,6 @@ CONFIG_XEN=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_UNMAP_KERNEL_AT_EL0=y CONFIG_HARDEN_BRANCH_PREDICTOR=y -CONFIG_HARDEN_EL2_VECTORS=y CONFIG_ARM64_SSBD=y CONFIG_RODATA_FULL_DEFAULT_ENABLED=y # CONFIG_ARM64_SW_TTBR0_PAN is not set @@ -450,6 +453,8 @@ CONFIG_AS_HAS_CFI_NEGATE_RA_STATE=y # ARMv8.4 architectural features # CONFIG_ARM64_AMU_EXTN=y +CONFIG_AS_HAS_ARMV8_4=y +CONFIG_ARM64_TLB_RANGE=y # end of ARMv8.4 architectural features # @@ -530,6 +535,7 @@ CONFIG_DT_IDLE_STATES=y # CONFIG_ARM_CPUIDLE=y CONFIG_ARM_PSCI_CPUIDLE=y +CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y # end of ARM CPU Idle Drivers # end of CPU Idle @@ -603,6 +609,7 @@ CONFIG_ARM_PSCI_FW=y # CONFIG_ARM_PSCI_CHECKER is not set CONFIG_HAVE_ARM_SMCCC=y CONFIG_HAVE_ARM_SMCCC_DISCOVERY=y +CONFIG_ARM_SMCCC_SOC_ID=y # # Tegra firmware driver @@ -734,7 +741,6 @@ CONFIG_HAVE_ARCH_SECCOMP_FILTER=y CONFIG_SECCOMP_FILTER=y CONFIG_HAVE_ARCH_STACKLEAK=y CONFIG_HAVE_STACKPROTECTOR=y -CONFIG_CC_HAS_STACKPROTECTOR_NONE=y CONFIG_STACKPROTECTOR=y CONFIG_STACKPROTECTOR_STRONG=y CONFIG_HAVE_CONTEXT_TRACKING=y @@ -750,7 +756,6 @@ CONFIG_ARCH_MMAP_RND_BITS=18 CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11 CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y -CONFIG_HAVE_COPY_THREAD_TLS=y CONFIG_CLONE_BACKWARDS=y CONFIG_OLD_SIGSUSPEND3=y CONFIG_COMPAT_OLD_SIGACTION=y @@ -880,7 +885,6 @@ CONFIG_SELECT_MEMORY_MODEL=y CONFIG_SPARSEMEM_MANUAL=y CONFIG_SPARSEMEM=y CONFIG_NEED_MULTIPLE_NODES=y -CONFIG_HAVE_MEMORY_PRESENT=y CONFIG_SPARSEMEM_EXTREME=y CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y CONFIG_SPARSEMEM_VMEMMAP=y @@ -1066,8 +1070,9 @@ CONFIG_IPV6_PIMSM_V2=y # CONFIG_IPV6_RPL_LWTUNNEL is not set CONFIG_NETLABEL=y CONFIG_MPTCP=y +CONFIG_INET_MPTCP_DIAG=m CONFIG_MPTCP_IPV6=y -# CONFIG_MPTCP_HMAC_TEST is not set +CONFIG_MPTCP_KUNIT_TESTS=m CONFIG_NETWORK_SECMARK=y CONFIG_NET_PTP_CLASSIFY=y CONFIG_NETWORK_PHY_TIMESTAMPING=y @@ -1495,6 +1500,7 @@ CONFIG_NET_DSA_TAG_DSA=m CONFIG_NET_DSA_TAG_EDSA=m CONFIG_NET_DSA_TAG_MTK=m CONFIG_NET_DSA_TAG_KSZ=m +CONFIG_NET_DSA_TAG_RTL4_A=m CONFIG_NET_DSA_TAG_OCELOT=m CONFIG_NET_DSA_TAG_QCA=m CONFIG_NET_DSA_TAG_LAN9303=m @@ -1576,6 +1582,7 @@ CONFIG_NET_SCH_DEFAULT=y # CONFIG_DEFAULT_FQ is not set # CONFIG_DEFAULT_CODEL is not set # CONFIG_DEFAULT_FQ_CODEL is not set +# CONFIG_DEFAULT_FQ_PIE is not set # CONFIG_DEFAULT_SFQ is not set CONFIG_DEFAULT_PFIFO_FAST=y CONFIG_DEFAULT_NET_SCH="pfifo_fast" @@ -2012,6 +2019,7 @@ CONFIG_PCI_MESON=y # Cadence PCIe controllers support # # CONFIG_PCIE_CADENCE_PLAT_HOST is not set +# CONFIG_PCI_J721E_HOST is not set # end of Cadence PCIe controllers support # end of PCI controller drivers @@ -2044,8 +2052,10 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y # Firmware loader # CONFIG_FW_LOADER=y +CONFIG_FW_LOADER_PAGED_BUF=y CONFIG_EXTRA_FIRMWARE="" -# CONFIG_FW_LOADER_USER_HELPER is not set +CONFIG_FW_LOADER_USER_HELPER=y +# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set # CONFIG_FW_LOADER_COMPRESS is not set CONFIG_FW_CACHE=y # end of Firmware loader @@ -2171,6 +2181,9 @@ CONFIG_MTD_PCI=m # CONFIG_MTD_DOCG3 is not set # end of Self-contained MTD device drivers +# +# NAND +# CONFIG_MTD_NAND_CORE=m # CONFIG_MTD_ONENAND is not set CONFIG_MTD_NAND_ECC_SW_HAMMING=m @@ -2204,6 +2217,7 @@ CONFIG_MTD_NAND_DISKONCHIP=m CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0 # CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE is not set CONFIG_MTD_SPI_NAND=m +# end of NAND # # LPDDR & LPDDR2 PCM memory drivers @@ -2213,7 +2227,6 @@ CONFIG_MTD_SPI_NAND=m CONFIG_MTD_SPI_NOR=y CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y -# CONFIG_SPI_CADENCE_QUADSPI is not set # CONFIG_MTD_UBI is not set CONFIG_MTD_HYPERBUS=m CONFIG_HBMC_AM654=m @@ -2458,7 +2471,7 @@ CONFIG_MD_CLUSTER=m CONFIG_BCACHE=y # CONFIG_BCACHE_DEBUG is not set # CONFIG_BCACHE_CLOSURES_DEBUG is not set -# CONFIG_BCACHE_ASYNC_REGISTRAION is not set +# CONFIG_BCACHE_ASYNC_REGISTRATION is not set CONFIG_BLK_DEV_DM_BUILTIN=y CONFIG_BLK_DEV_DM=m CONFIG_DM_DEBUG=y @@ -2742,8 +2755,8 @@ CONFIG_NET_VENDOR_MICROCHIP=y # CONFIG_ENCX24J600 is not set # CONFIG_LAN743X is not set CONFIG_NET_VENDOR_MICROSEMI=y +CONFIG_MSCC_OCELOT_SWITCH_LIB=m CONFIG_MSCC_OCELOT_SWITCH=m -CONFIG_MSCC_OCELOT_SWITCH_OCELOT=m CONFIG_NET_VENDOR_MYRI=y # CONFIG_MYRI10GE is not set # CONFIG_FEALNX is not set @@ -2840,6 +2853,7 @@ CONFIG_XILINX_LL_TEMAC=m # CONFIG_NET_SB1000 is not set CONFIG_MDIO_DEVICE=y CONFIG_MDIO_BUS=y +CONFIG_MDIO_DEVRES=y CONFIG_MDIO_BCM_UNIMAC=m CONFIG_MDIO_BITBANG=y CONFIG_MDIO_BUS_MUX=y @@ -3095,6 +3109,7 @@ CONFIG_MT7601U=m CONFIG_MT76_CORE=m CONFIG_MT76_LEDS=y CONFIG_MT76_USB=m +CONFIG_MT76_SDIO=m CONFIG_MT76x02_LIB=m CONFIG_MT76x02_USB=m CONFIG_MT76x0_COMMON=m @@ -3106,8 +3121,13 @@ CONFIG_MT76x2U=m CONFIG_MT7603E=m CONFIG_MT7615_COMMON=m CONFIG_MT7615E=m +CONFIG_MT7663_USB_SDIO_COMMON=m # CONFIG_MT7663U is not set +CONFIG_MT7663S=m # CONFIG_MT7915E is not set +CONFIG_WLAN_VENDOR_MICROCHIP=y +# CONFIG_WILC1000_SDIO is not set +# CONFIG_WILC1000_SPI is not set CONFIG_WLAN_VENDOR_RALINK=y CONFIG_RT2X00=m CONFIG_RT2400PCI=m @@ -3161,9 +3181,15 @@ CONFIG_RTLBTCOEXIST=m CONFIG_RTL8XXXU=m # CONFIG_RTL8XXXU_UNTESTED is not set CONFIG_RTW88=m +CONFIG_RTW88_CORE=m +CONFIG_RTW88_PCI=m +CONFIG_RTW88_8821C=m # CONFIG_RTW88_8822BE is not set # CONFIG_RTW88_8822CE is not set # CONFIG_RTW88_8723DE is not set +CONFIG_RTW88_8821CE=m +# CONFIG_RTW88_DEBUG is not set +# CONFIG_RTW88_DEBUGFS is not set CONFIG_WLAN_VENDOR_RSI=y CONFIG_RSI_91X=m # CONFIG_RSI_DEBUGFS is not set @@ -3623,6 +3649,7 @@ CONFIG_IPMI_POWEROFF=m # CONFIG_IPMB_DEVICE_INTERFACE is not set CONFIG_HW_RANDOM=y CONFIG_HW_RANDOM_TIMERIOMEM=m +CONFIG_HW_RANDOM_BA431=m CONFIG_HW_RANDOM_VIRTIO=m CONFIG_HW_RANDOM_HISI_V2=m CONFIG_HW_RANDOM_MESON=m @@ -3780,6 +3807,7 @@ CONFIG_SPI_ALTERA=m CONFIG_SPI_AXI_SPI_ENGINE=m CONFIG_SPI_BITBANG=m CONFIG_SPI_CADENCE=m +# CONFIG_SPI_CADENCE_QUADSPI is not set CONFIG_SPI_DESIGNWARE=m # CONFIG_SPI_DW_DMA is not set CONFIG_SPI_DW_PCI=m @@ -3936,6 +3964,7 @@ CONFIG_GPIO_MAX7300=m CONFIG_GPIO_MAX732X=m CONFIG_GPIO_PCA953X=m # CONFIG_GPIO_PCA953X_IRQ is not set +CONFIG_GPIO_PCA9570=m CONFIG_GPIO_PCF857X=m CONFIG_GPIO_TPIC2810=m # end of I2C GPIO expanders @@ -4115,6 +4144,7 @@ CONFIG_CHARGER_BQ2415X=m CONFIG_CHARGER_BQ24190=m CONFIG_CHARGER_BQ24257=m CONFIG_CHARGER_BQ24735=m +CONFIG_CHARGER_BQ2515X=m CONFIG_CHARGER_BQ25890=m CONFIG_CHARGER_SMB347=m CONFIG_CHARGER_TPS65090=m @@ -4156,6 +4186,7 @@ CONFIG_SENSORS_ARM_SCMI=m CONFIG_SENSORS_ARM_SCPI=m CONFIG_SENSORS_ASPEED=m CONFIG_SENSORS_ATXP1=m +CONFIG_SENSORS_CORSAIR_CPRO=m CONFIG_SENSORS_DS620=m CONFIG_SENSORS_DS1621=m CONFIG_SENSORS_DA9052_ADC=m @@ -4320,6 +4351,7 @@ CONFIG_SENSORS_XGENE=m # CONFIG_SENSORS_ACPI_POWER=m CONFIG_THERMAL=y +# CONFIG_THERMAL_NETLINK is not set CONFIG_THERMAL_STATISTICS=y CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 CONFIG_THERMAL_HWMON=y @@ -4334,7 +4366,6 @@ CONFIG_THERMAL_GOV_BANG_BANG=y CONFIG_THERMAL_GOV_USER_SPACE=y CONFIG_CPU_THERMAL=y CONFIG_CPU_FREQ_THERMAL=y -CONFIG_CLOCK_THERMAL=y CONFIG_DEVFREQ_THERMAL=y CONFIG_THERMAL_EMULATION=y CONFIG_THERMAL_MMIO=m @@ -4343,6 +4374,7 @@ CONFIG_ROCKCHIP_THERMAL=m CONFIG_DA9062_THERMAL=m CONFIG_AMLOGIC_THERMAL=y CONFIG_GENERIC_ADC_THERMAL=m +CONFIG_KHADAS_MCU_FAN_THERMAL=m CONFIG_WATCHDOG=y CONFIG_WATCHDOG_CORE=y # CONFIG_WATCHDOG_NOWAYOUT is not set @@ -4509,7 +4541,6 @@ CONFIG_MFD_SI476X_CORE=m CONFIG_MFD_SM501=m CONFIG_MFD_SM501_GPIO=y CONFIG_MFD_SKY81452=m -CONFIG_MFD_SMSC=y CONFIG_ABX500_CORE=y CONFIG_AB3100_CORE=y CONFIG_AB3100_OTP=m @@ -4564,6 +4595,7 @@ CONFIG_MFD_WM8994=m CONFIG_MFD_ROHM_BD71828=m # CONFIG_MFD_STPMIC1 is not set # CONFIG_MFD_STMFX is not set +CONFIG_MFD_KHADAS_MCU=m CONFIG_MFD_VEXPRESS_SYSREG=y CONFIG_RAVE_SP_CORE=m # end of Multifunction device drivers @@ -4589,6 +4621,7 @@ CONFIG_REGULATOR_BCM590XX=m CONFIG_REGULATOR_BD71828=m CONFIG_REGULATOR_BD9571MWV=m CONFIG_REGULATOR_CPCAP=m +CONFIG_REGULATOR_CROS_EC=m CONFIG_REGULATOR_DA903X=m CONFIG_REGULATOR_DA9052=m CONFIG_REGULATOR_DA9055=m @@ -4597,6 +4630,7 @@ CONFIG_REGULATOR_DA9063=m CONFIG_REGULATOR_DA9210=m CONFIG_REGULATOR_DA9211=m CONFIG_REGULATOR_FAN53555=y +CONFIG_REGULATOR_FAN53880=m CONFIG_REGULATOR_GPIO=y # CONFIG_REGULATOR_HI6421 is not set # CONFIG_REGULATOR_HI6421V530 is not set @@ -4640,6 +4674,7 @@ CONFIG_REGULATOR_MAX77826=m CONFIG_REGULATOR_MT6358=m # CONFIG_REGULATOR_MT6397 is not set # CONFIG_REGULATOR_PALMAS is not set +CONFIG_REGULATOR_PCA9450=m # CONFIG_REGULATOR_PCAP is not set # CONFIG_REGULATOR_PCF50633 is not set CONFIG_REGULATOR_PFUZE100=y @@ -4648,6 +4683,7 @@ CONFIG_REGULATOR_PFUZE100=y # CONFIG_REGULATOR_PV88090 is not set CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_QCOM_SPMI=m +CONFIG_REGULATOR_QCOM_USB_VBUS=m # CONFIG_REGULATOR_RC5T583 is not set CONFIG_REGULATOR_RK808=y # CONFIG_REGULATOR_RN5T618 is not set @@ -4660,6 +4696,7 @@ CONFIG_REGULATOR_S2MPS11=y # CONFIG_REGULATOR_SLG51000 is not set # CONFIG_REGULATOR_SY8106A is not set # CONFIG_REGULATOR_SY8824X is not set +CONFIG_REGULATOR_SY8827N=m # CONFIG_REGULATOR_TPS51632 is not set CONFIG_REGULATOR_TPS6105X=m CONFIG_REGULATOR_TPS62360=m @@ -4682,6 +4719,7 @@ CONFIG_REGULATOR_WM831X=m CONFIG_REGULATOR_WM8350=m CONFIG_REGULATOR_WM8400=m CONFIG_REGULATOR_WM8994=m +CONFIG_REGULATOR_QCOM_LABIBB=m CONFIG_RC_CORE=m CONFIG_RC_MAP=m CONFIG_LIRC=y @@ -4722,12 +4760,14 @@ CONFIG_IR_SERIAL=m CONFIG_IR_SERIAL_TRANSMITTER=y CONFIG_IR_SIR=m CONFIG_RC_XBOX_DVD=m +CONFIG_IR_TOY=m CONFIG_CEC_CORE=m CONFIG_CEC_NOTIFIER=y CONFIG_CEC_PIN=y # CONFIG_MEDIA_CEC_RC is not set CONFIG_CEC_PIN_ERROR_INJ=y CONFIG_MEDIA_CEC_SUPPORT=y +CONFIG_CEC_CH7322=m # CONFIG_CEC_CROS_EC is not set # CONFIG_CEC_MESON_AO is not set # CONFIG_CEC_MESON_G12A_AO is not set @@ -5087,6 +5127,7 @@ CONFIG_VIDEO_CADENCE_CSI2TX=m CONFIG_VIDEO_ASPEED=m CONFIG_VIDEO_MUX=m CONFIG_VIDEO_XILINX=m +CONFIG_VIDEO_XILINX_CSI2RXSS=m CONFIG_VIDEO_XILINX_TPG=m CONFIG_VIDEO_XILINX_VTC=m CONFIG_V4L_MEM2MEM_DRIVERS=y @@ -5172,6 +5213,7 @@ CONFIG_VIDEO_TW9903=m CONFIG_VIDEO_TW9906=m CONFIG_VIDEO_TW9910=m CONFIG_VIDEO_VPX3220=m +CONFIG_VIDEO_MAX9286=m # # Video and audio decoders @@ -5271,6 +5313,7 @@ CONFIG_VIDEO_MT9V111=m CONFIG_VIDEO_SR030PC30=m CONFIG_VIDEO_NOON010PC30=m CONFIG_VIDEO_M5MOLS=m +CONFIG_VIDEO_RDACM20=m CONFIG_VIDEO_RJ54N1=m CONFIG_VIDEO_S5K6AA=m CONFIG_VIDEO_S5K6A3=m @@ -5287,6 +5330,7 @@ CONFIG_VIDEO_S5C73M3=m CONFIG_VIDEO_AD5820=m CONFIG_VIDEO_AK7375=m CONFIG_VIDEO_DW9714=m +CONFIG_VIDEO_DW9768=m CONFIG_VIDEO_DW9807_VCM=m # end of Lens drivers @@ -5619,7 +5663,6 @@ CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00=m CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m CONFIG_DRM_PANEL_RAYDIUM_RM67191=m CONFIG_DRM_PANEL_RAYDIUM_RM68200=m -CONFIG_DRM_PANEL_ROCKTECH_JH057N00900=m CONFIG_DRM_PANEL_RONBO_RB070D30=m CONFIG_DRM_PANEL_SAMSUNG_S6D16D0=m CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2=m @@ -5632,6 +5675,7 @@ CONFIG_DRM_PANEL_SHARP_LQ101R1SX01=m CONFIG_DRM_PANEL_SHARP_LS037V7DW01=m CONFIG_DRM_PANEL_SHARP_LS043T1LE01=m CONFIG_DRM_PANEL_SITRONIX_ST7701=m +CONFIG_DRM_PANEL_SITRONIX_ST7703=m # CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set CONFIG_DRM_PANEL_SONY_ACX424AKP=m CONFIG_DRM_PANEL_SONY_ACX565AKM=m @@ -5791,7 +5835,6 @@ CONFIG_LCD_CLASS_DEVICE=m # CONFIG_LCD_HX8357 is not set CONFIG_LCD_OTM3225A=m CONFIG_BACKLIGHT_CLASS_DEVICE=y -CONFIG_BACKLIGHT_GENERIC=m CONFIG_BACKLIGHT_LM3533=m CONFIG_BACKLIGHT_PWM=m CONFIG_BACKLIGHT_DA903X=m @@ -5999,6 +6042,7 @@ CONFIG_SND_SOC_FSL_MICFIL=m # CONFIG_SND_I2S_HI6210_I2S is not set # CONFIG_SND_SOC_IMG is not set +CONFIG_SND_SOC_INTEL_KEEMBAY=m # CONFIG_SND_SOC_MTK_BTCVSD is not set # @@ -6115,6 +6159,7 @@ CONFIG_SND_SOC_MAX98504=m CONFIG_SND_SOC_MAX9867=m CONFIG_SND_SOC_MAX98927=m CONFIG_SND_SOC_MAX98373=m +CONFIG_SND_SOC_MAX98373_I2C=m CONFIG_SND_SOC_MAX98390=m CONFIG_SND_SOC_MAX9860=m CONFIG_SND_SOC_MSM8916_WCD_ANALOG=m @@ -6381,8 +6426,8 @@ CONFIG_USB_ANNOUNCE_NEW_DEVICES=y CONFIG_USB_DEFAULT_PERSIST=y # CONFIG_USB_DYNAMIC_MINORS is not set CONFIG_USB_OTG=y -# CONFIG_USB_OTG_WHITELIST is not set -# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_OTG_PRODUCTLIST is not set +# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set CONFIG_USB_OTG_FSM=m CONFIG_USB_LEDS_TRIGGER_USBPORT=y CONFIG_USB_AUTOSUSPEND_DELAY=2 @@ -6822,6 +6867,7 @@ CONFIG_MMC_SDHCI_AM654=m CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y # CONFIG_LEDS_CLASS_FLASH is not set +CONFIG_LEDS_CLASS_MULTICOLOR=m # CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set # @@ -6845,6 +6891,7 @@ CONFIG_LEDS_MT6323=m CONFIG_LEDS_GPIO=y # CONFIG_LEDS_LP3944 is not set # CONFIG_LEDS_LP3952 is not set +CONFIG_LEDS_LP55XX_COMMON=m # CONFIG_LEDS_LP5521 is not set # CONFIG_LEDS_LP5523 is not set # CONFIG_LEDS_LP5562 is not set @@ -7088,6 +7135,7 @@ CONFIG_PL330_DMA=y CONFIG_PLX_DMA=m # CONFIG_XILINX_DMA is not set # CONFIG_XILINX_ZYNQMP_DMA is not set +CONFIG_XILINX_ZYNQMP_DPDMA=m CONFIG_QCOM_HIDMA_MGMT=y CONFIG_QCOM_HIDMA=y # CONFIG_DW_DMAC is not set @@ -7259,21 +7307,10 @@ CONFIG_AD9834=m # end of IIO staging drivers CONFIG_FB_SM750=m - -# -# Speakup console speech -# -# CONFIG_SPEAKUP is not set -# end of Speakup console speech - CONFIG_STAGING_MEDIA=y # CONFIG_VIDEO_HANTRO is not set CONFIG_VIDEO_MESON_VDEC=m # CONFIG_VIDEO_ROCKCHIP_VDEC is not set - -# -# soc_camera sensor drivers -# CONFIG_PHY_ROCKCHIP_DPHY_RX0=m CONFIG_VIDEO_ROCKCHIP_ISP1=m CONFIG_VIDEO_USBVISION=m @@ -7287,7 +7324,6 @@ CONFIG_VIDEO_USBVISION=m # CONFIG_LTE_GDM724X is not set # CONFIG_GS_FPGABOOT is not set # CONFIG_UNISYSSPAR is not set -# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set CONFIG_FB_TFT=m CONFIG_FB_TFT_AGM1264K_FL=m CONFIG_FB_TFT_BD663474=m @@ -7321,8 +7357,6 @@ CONFIG_FB_TFT_UC1611=m CONFIG_FB_TFT_UC1701=m CONFIG_FB_TFT_UPD161704=m CONFIG_FB_TFT_WATTEROTT=m -# CONFIG_WILC1000_SDIO is not set -# CONFIG_WILC1000_SPI is not set CONFIG_MOST_COMPONENTS=m # CONFIG_MOST_CDEV is not set # CONFIG_MOST_NET is not set @@ -7330,7 +7364,6 @@ CONFIG_MOST_COMPONENTS=m # CONFIG_MOST_VIDEO is not set # CONFIG_MOST_DIM2 is not set # CONFIG_MOST_I2C is not set -# CONFIG_MOST_USB is not set # CONFIG_KS7010 is not set # CONFIG_PI433 is not set @@ -7397,16 +7430,16 @@ CONFIG_COMMON_CLK_BD718XX=m CONFIG_COMMON_CLK_MESON_REGMAP=y CONFIG_COMMON_CLK_MESON_DUALDIV=y CONFIG_COMMON_CLK_MESON_MPLL=y -CONFIG_COMMON_CLK_MESON_PHASE=y +CONFIG_COMMON_CLK_MESON_PHASE=m CONFIG_COMMON_CLK_MESON_PLL=y -CONFIG_COMMON_CLK_MESON_SCLK_DIV=y +CONFIG_COMMON_CLK_MESON_SCLK_DIV=m CONFIG_COMMON_CLK_MESON_VID_PLL_DIV=y CONFIG_COMMON_CLK_MESON_AO_CLKC=y CONFIG_COMMON_CLK_MESON_EE_CLKC=y CONFIG_COMMON_CLK_MESON_CPU_DYNDIV=y CONFIG_COMMON_CLK_GXBB=y CONFIG_COMMON_CLK_AXG=y -# CONFIG_COMMON_CLK_AXG_AUDIO is not set +CONFIG_COMMON_CLK_AXG_AUDIO=m CONFIG_COMMON_CLK_G12A=y CONFIG_HWSPINLOCK=y @@ -7600,6 +7633,7 @@ CONFIG_BMA180=m CONFIG_BMA220=m CONFIG_BMA400=m CONFIG_BMA400_I2C=m +CONFIG_BMA400_SPI=m CONFIG_BMC150_ACCEL=m CONFIG_BMC150_ACCEL_I2C=m CONFIG_BMC150_ACCEL_SPI=m @@ -7738,6 +7772,9 @@ CONFIG_BME680_SPI=m # CONFIG_CCS811 is not set # CONFIG_IAQCORE is not set CONFIG_PMS7003=m +CONFIG_SCD30_CORE=m +CONFIG_SCD30_I2C=m +CONFIG_SCD30_SERIAL=m CONFIG_SENSIRION_SGP30=m CONFIG_SPS30=m # CONFIG_VZ89X is not set @@ -7895,6 +7932,9 @@ CONFIG_FXOS8700=m CONFIG_FXOS8700_I2C=m CONFIG_FXOS8700_SPI=m # CONFIG_KMX61 is not set +CONFIG_INV_ICM42600=m +CONFIG_INV_ICM42600_I2C=m +CONFIG_INV_ICM42600_SPI=m # CONFIG_INV_MPU6050_I2C is not set # CONFIG_INV_MPU6050_SPI is not set # CONFIG_IIO_ST_LSM6DSX is not set @@ -8251,7 +8291,9 @@ CONFIG_PM_OPP=y # CONFIG_INTERCONNECT is not set CONFIG_COUNTER=m CONFIG_FTM_QUADDEC=m +CONFIG_MICROCHIP_TCB_CAPTURE=m CONFIG_MOST=m +CONFIG_MOST_USB_HDM=m # end of Device Drivers # @@ -8407,6 +8449,7 @@ CONFIG_SYSFS=y CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y CONFIG_TMPFS_XATTR=y +# CONFIG_TMPFS_INODE64 is not set CONFIG_HUGETLBFS=y CONFIG_HUGETLB_PAGE=y CONFIG_MEMFD_CREATE=y @@ -8533,6 +8576,7 @@ CONFIG_NFSD_PNFS=y CONFIG_NFSD_BLOCKLAYOUT=y CONFIG_NFSD_SCSILAYOUT=y CONFIG_NFSD_FLEXFILELAYOUT=y +# CONFIG_NFSD_V4_2_INTER_SSC is not set CONFIG_NFSD_V4_SECURITY_LABEL=y CONFIG_GRACE_PERIOD=m CONFIG_LOCKD=m @@ -9009,6 +9053,7 @@ CONFIG_DECOMPRESS_LZMA=y CONFIG_DECOMPRESS_XZ=y CONFIG_DECOMPRESS_LZO=y CONFIG_DECOMPRESS_LZ4=y +CONFIG_DECOMPRESS_ZSTD=y CONFIG_GENERIC_ALLOCATOR=y CONFIG_REED_SOLOMON=m CONFIG_REED_SOLOMON_ENC8=y @@ -9025,6 +9070,7 @@ CONFIG_ASSOCIATIVE_ARRAY=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT_MAP=y CONFIG_HAS_DMA=y +CONFIG_DMA_OPS=y CONFIG_NEED_SG_DMA_LENGTH=y CONFIG_NEED_DMA_MAP_STATE=y CONFIG_ARCH_DMA_ADDR_T_64BIT=y @@ -9068,6 +9114,7 @@ CONFIG_OID_REGISTRY=y CONFIG_UCS2_STRING=y CONFIG_HAVE_GENERIC_VDSO=y CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_VDSO_TIME_NS=y CONFIG_FONT_SUPPORT=y CONFIG_FONTS=y CONFIG_FONT_8x8=y @@ -9118,6 +9165,7 @@ CONFIG_FRAME_WARN=1024 # CONFIG_HEADERS_INSTALL is not set # CONFIG_DEBUG_SECTION_MISMATCH is not set CONFIG_SECTION_MISMATCH_WARN_ONLY=y +# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_32B is not set CONFIG_ARCH_WANT_FRAME_POINTERS=y CONFIG_FRAME_POINTER=y # CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set @@ -9131,6 +9179,9 @@ CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 CONFIG_MAGIC_SYSRQ_SERIAL=y CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE="" CONFIG_DEBUG_FS=y +CONFIG_DEBUG_FS_ALLOW_ALL=y +# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set +# CONFIG_DEBUG_FS_ALLOW_NONE is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y @@ -9171,7 +9222,6 @@ CONFIG_HAVE_ARCH_KASAN_SW_TAGS=y CONFIG_CC_HAS_KASAN_GENERIC=y CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y # CONFIG_KASAN is not set -CONFIG_KASAN_STACK=1 # end of Memory Debugging # CONFIG_DEBUG_SHIRQ is not set @@ -9240,6 +9290,7 @@ CONFIG_HAVE_DEBUG_BUGVERBOSE=y CONFIG_TORTURE_TEST=m CONFIG_RCU_PERF_TEST=m CONFIG_RCU_TORTURE_TEST=m +CONFIG_RCU_REF_SCALE_TEST=m CONFIG_RCU_CPU_STALL_TIMEOUT=60 CONFIG_RCU_TRACE=y # CONFIG_RCU_EQS_DEBUG is not set @@ -9322,12 +9373,14 @@ CONFIG_TEST_BLACKHOLE_DEV=m CONFIG_SYSCTL_KUNIT_TEST=m CONFIG_LIST_KUNIT_TEST=m CONFIG_LINEAR_RANGES_TEST=m +CONFIG_BITS_TEST=m # CONFIG_TEST_UDELAY is not set # CONFIG_TEST_STATIC_KEYS is not set # CONFIG_TEST_KMOD is not set CONFIG_TEST_MEMCAT_P=m CONFIG_TEST_STACKINIT=m # CONFIG_TEST_MEMINIT is not set +CONFIG_TEST_FREE_PAGES=m CONFIG_MEMTEST=y # end of Kernel Testing and Coverage # end of Kernel hacking diff --git a/config/sources/families/include/meson64_common.inc b/config/sources/families/include/meson64_common.inc index 0121b08c5e..8823ca40a1 100644 --- a/config/sources/families/include/meson64_common.inc +++ b/config/sources/families/include/meson64_common.inc @@ -27,7 +27,7 @@ case $BRANCH in ;; current) - KERNELBRANCH='branch:linux-5.8.y' + KERNELBRANCH='branch:linux-5.9.y' KERNELPATCHDIR='meson64-current' ;; diff --git a/patch/kernel/meson64-current/0053-WIP-arm64-dts-meson-gxbb-add-playback-audio-devices.patch b/patch/kernel/meson64-current/0053-WIP-arm64-dts-meson-gxbb-add-playback-audio-devices.patch deleted file mode 100644 index 041c640c4d..0000000000 --- a/patch/kernel/meson64-current/0053-WIP-arm64-dts-meson-gxbb-add-playback-audio-devices.patch +++ /dev/null @@ -1,48 +0,0 @@ -From f31c2092f357f1c7ec4931418dc6dfa849c45b81 Mon Sep 17 00:00:00 2001 -From: Christian Hewitt -Date: Tue, 18 Feb 2020 12:23:31 +0000 -Subject: [PATCH 053/101] WIP: arm64: dts: meson-gxbb: add playback audio - devices - -Signed-off-by: Christian Hewitt ---- - arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 23 +++++++++++++++++++++ - 1 file changed, 23 insertions(+) - -diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi -index 0cb40326b0d3..ccaa1a8e28c5 100644 ---- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi -+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi -@@ -241,6 +241,29 @@ - }; - }; - -+&aiu { -+ compatible = "amlogic,aiu-gxbb", "amlogic,aiu"; -+ clocks = <&clkc CLKID_AIU_GLUE>, -+ <&clkc CLKID_I2S_OUT>, -+ <&clkc CLKID_AOCLK_GATE>, -+ <&clkc CLKID_CTS_AMCLK>, -+ <&clkc CLKID_MIXER_IFACE>, -+ <&clkc CLKID_IEC958>, -+ <&clkc CLKID_IEC958_GATE>, -+ <&clkc CLKID_CTS_MCLK_I958>, -+ <&clkc CLKID_CTS_I958>; -+ clock-names = "pclk", -+ "i2s_pclk", -+ "i2s_aoclk", -+ "i2s_mclk", -+ "i2s_mixer", -+ "spdif_pclk", -+ "spdif_aoclk", -+ "spdif_mclk", -+ "spdif_mclk_sel"; -+ resets = <&reset RESET_AIU>; -+}; -+ - &apb { - mali: gpu@c0000 { - compatible = "amlogic,meson-gxbb-mali", "arm,mali-450"; --- -2.17.1 - diff --git a/patch/kernel/meson64-current/0076-FROMLIST-drm-fourcc-Add-modifier-definitions-for-des.patch b/patch/kernel/meson64-current/0076-FROMLIST-drm-fourcc-Add-modifier-definitions-for-des.patch deleted file mode 100644 index 7c10ee6d59..0000000000 --- a/patch/kernel/meson64-current/0076-FROMLIST-drm-fourcc-Add-modifier-definitions-for-des.patch +++ /dev/null @@ -1,111 +0,0 @@ -From fac579148d3775144bbe922ef013bd4e134fc6df Mon Sep 17 00:00:00 2001 -From: Neil Armstrong -Date: Thu, 20 Feb 2020 17:13:26 +0000 -Subject: [PATCH 076/101] FROMLIST: drm/fourcc: Add modifier definitions for - describing Amlogic Video Framebuffer Compression - -Amlogic uses a proprietary lossless image compression protocol and format -for their hardware video codec accelerators, either video decoders or -video input encoders. - -It considerably reduces memory bandwidth while writing and reading -frames in memory. - -The underlying storage is considered to be 3 components, 8bit or 10-bit -per component, YCbCr 420, single plane : -- DRM_FORMAT_YUV420_8BIT -- DRM_FORMAT_YUV420_10BIT - -This modifier will be notably added to DMA-BUF frames imported from the V4L2 -Amlogic VDEC decoder. - -At least two options are supported : -- Scatter mode: the buffer is filled with a IOMMU scatter table referring - to the encoder current memory layout. This mode if more efficient in terms - of memory allocation but frames are not dumpable and only valid during until - the buffer is freed and back in control of the encoder -- Memory saving: when the pixel bpp is 8b, the size of the superblock can - be reduced, thus saving memory. - -Signed-off-by: Neil Armstrong ---- - include/uapi/drm/drm_fourcc.h | 56 +++++++++++++++++++++++++++++++++++ - 1 file changed, 56 insertions(+) - -diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h -index 8bc0b31597d8..8a6e87bacadb 100644 ---- a/include/uapi/drm/drm_fourcc.h -+++ b/include/uapi/drm/drm_fourcc.h -@@ -309,6 +309,7 @@ extern "C" { - #define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07 - #define DRM_FORMAT_MOD_VENDOR_ARM 0x08 - #define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09 -+#define DRM_FORMAT_MOD_VENDOR_AMLOGIC 0x0a - - /* add more to the end as needed */ - -@@ -804,6 +805,61 @@ extern "C" { - */ - #define DRM_FORMAT_MOD_ALLWINNER_TILED fourcc_mod_code(ALLWINNER, 1) - -+/* -+ * Amlogic Video Framebuffer Compression modifiers -+ * -+ * Amlogic uses a proprietary lossless image compression protocol and format -+ * for their hardware video codec accelerators, either video decoders or -+ * video input encoders. -+ * -+ * It considerably reduces memory bandwidth while writing and reading -+ * frames in memory. -+ * Implementation details may be platform and SoC specific, and shared -+ * between the producer and the decoder on the same platform. -+ * -+ * The underlying storage is considered to be 3 components, 8bit or 10-bit -+ * per component YCbCr 420, single plane : -+ * - DRM_FORMAT_YUV420_8BIT -+ * - DRM_FORMAT_YUV420_10BIT -+ * -+ * The classic memory storage is composed of: -+ * - a body content organized in 64x32 superblocks with 4096 bytes per -+ * superblock in default mode. -+ * - a 32 bytes per 128x64 header block -+ */ -+#define DRM_FORMAT_MOD_AMLOGIC_FBC_DEFAULT fourcc_mod_code(AMLOGIC, 0) -+ -+/* -+ * Amlogic Video Framebuffer Compression Options -+ * -+ * Two optional features are available which may not supported/used on every -+ * SoCs and Compressed Framebuffer producers. -+ */ -+#define DRM_FORMAT_MOD_AMLOGIC_FBC(__modes) fourcc_mod_code(AMLOGIC, __modes) -+ -+/* -+ * Amlogic FBC Scatter Memory layout -+ * -+ * Indicates the header contains IOMMU references to the compressed -+ * frames content to optimize memory access and layout. -+ * In this mode, only the header memory address is needed, thus the -+ * content memory organization is tied to the current producer -+ * execution and cannot be saved/dumped. -+ */ -+#define DRM_FORMAT_MOD_AMLOGIC_FBC_SCATTER (1ULL << 0) -+ -+/* -+ * Amlogic FBC Memory Saving mode -+ * -+ * Indicates the storage is packed when pixel size is multiple of word -+ * boudaries, i.e. 8bit should be stored in this mode to save allocation -+ * memory. -+ * -+ * This mode reduces body layout to 3072 bytes per 64x32 superblock and -+ * 3200 bytes per 64x32 superblock combined with scatter mode. -+ */ -+#define DRM_FORMAT_MOD_AMLOGIC_FBC_MEM_SAVING (1ULL << 1) -+ - #if defined(__cplusplus) - } - #endif --- -2.17.1 - diff --git a/patch/kernel/meson64-current/0077-FROMLIST-drm-meson-add-Amlogic-Video-FBC-registers.patch b/patch/kernel/meson64-current/0077-FROMLIST-drm-meson-add-Amlogic-Video-FBC-registers.patch deleted file mode 100644 index c9309470d0..0000000000 --- a/patch/kernel/meson64-current/0077-FROMLIST-drm-meson-add-Amlogic-Video-FBC-registers.patch +++ /dev/null @@ -1,60 +0,0 @@ -From b0faff15e4b82132d69b8b534ff3b9689370961e Mon Sep 17 00:00:00 2001 -From: Neil Armstrong -Date: Thu, 20 Feb 2020 17:14:31 +0000 -Subject: [PATCH 077/101] FROMLIST: drm/meson: add Amlogic Video FBC registers - -Add the registers of the VPU VD1 Amlogic FBC decoder module, and routing -register. - -Signed-off-by: Neil Armstrong ---- - drivers/gpu/drm/meson/meson_registers.h | 22 ++++++++++++++++++++++ - 1 file changed, 22 insertions(+) - -diff --git a/drivers/gpu/drm/meson/meson_registers.h b/drivers/gpu/drm/meson/meson_registers.h -index 8ea00546cd4e..08631fdfe4b9 100644 ---- a/drivers/gpu/drm/meson/meson_registers.h -+++ b/drivers/gpu/drm/meson/meson_registers.h -@@ -144,10 +144,15 @@ - #define VIU_SW_RESET_OSD1 BIT(0) - #define VIU_MISC_CTRL0 0x1a06 - #define VIU_CTRL0_VD1_AFBC_MASK 0x170000 -+#define VIU_CTRL0_AFBC_TO_VD1 BIT(20) - #define VIU_MISC_CTRL1 0x1a07 - #define MALI_AFBC_MISC GENMASK(15, 8) - #define D2D3_INTF_LENGTH 0x1a08 - #define D2D3_INTF_CTRL0 0x1a09 -+#define VD1_AFBCD0_MISC_CTRL 0x1a0a -+#define VD1_AXI_SEL_AFBC (1 << 12) -+#define AFBC_VD1_SEL (1 << 10) -+#define VD2_AFBCD1_MISC_CTRL 0x1a0b - #define VIU_OSD1_CTRL_STAT 0x1a10 - #define VIU_OSD1_OSD_BLK_ENABLE BIT(0) - #define VIU_OSD1_OSD_MEM_MODE_LINEAR BIT(2) -@@ -365,6 +370,23 @@ - #define VIU_OSD1_OETF_LUT_ADDR_PORT 0x1add - #define VIU_OSD1_OETF_LUT_DATA_PORT 0x1ade - #define AFBC_ENABLE 0x1ae0 -+#define AFBC_MODE 0x1ae1 -+#define AFBC_SIZE_IN 0x1ae2 -+#define AFBC_DEC_DEF_COLOR 0x1ae3 -+#define AFBC_CONV_CTRL 0x1ae4 -+#define AFBC_LBUF_DEPTH 0x1ae5 -+#define AFBC_HEAD_BADDR 0x1ae6 -+#define AFBC_BODY_BADDR 0x1ae7 -+#define AFBC_SIZE_OUT 0x1ae8 -+#define AFBC_OUT_YSCOPE 0x1ae9 -+#define AFBC_STAT 0x1aea -+#define AFBC_VD_CFMT_CTRL 0x1aeb -+#define AFBC_VD_CFMT_W 0x1aec -+#define AFBC_MIF_HOR_SCOPE 0x1aed -+#define AFBC_MIF_VER_SCOPE 0x1aee -+#define AFBC_PIXEL_HOR_SCOPE 0x1aef -+#define AFBC_PIXEL_VER_SCOPE 0x1af0 -+#define AFBC_VD_CFMT_H 0x1af1 - - /* vpp */ - #define VPP_DUMMY_DATA 0x1d00 --- -2.17.1 - diff --git a/patch/kernel/meson64-current/0078-FROMLIST-drm-meson-overlay-setup-overlay-for-Amlogic.patch b/patch/kernel/meson64-current/0078-FROMLIST-drm-meson-overlay-setup-overlay-for-Amlogic.patch deleted file mode 100644 index 88d0cbc26e..0000000000 --- a/patch/kernel/meson64-current/0078-FROMLIST-drm-meson-overlay-setup-overlay-for-Amlogic.patch +++ /dev/null @@ -1,425 +0,0 @@ -From 4f179b75fd372aad1f4031ace69b92614693dae0 Mon Sep 17 00:00:00 2001 -From: Neil Armstrong -Date: Thu, 20 Feb 2020 17:15:43 +0000 -Subject: [PATCH 078/101] FROMLIST: drm/meson: overlay: setup overlay for - Amlogic FBC - -Setup the Amlogic FBC decoder for the VD1 video overlay plane. - -The VD1 Amlogic FBC decoder is integrated in the pipeline like the -YUV pixel reading/formatter but used a direct memory address instead. - -The default mode needs to calculate the content body size since the header -is allocated after. - -The scatter mode needs a simplier management since only the header is needed, -since it contains an IOMMU scatter table to locate the superblocks in memory. - -Signed-off-by: Neil Armstrong ---- - drivers/gpu/drm/meson/meson_drv.h | 16 ++ - drivers/gpu/drm/meson/meson_overlay.c | 257 +++++++++++++++++++++++++- - 2 files changed, 265 insertions(+), 8 deletions(-) - -diff --git a/drivers/gpu/drm/meson/meson_drv.h b/drivers/gpu/drm/meson/meson_drv.h -index 04fdf3826643..da951964e988 100644 ---- a/drivers/gpu/drm/meson/meson_drv.h -+++ b/drivers/gpu/drm/meson/meson_drv.h -@@ -80,6 +80,7 @@ struct meson_drm { - - bool vd1_enabled; - bool vd1_commit; -+ bool vd1_afbc; - unsigned int vd1_planes; - uint32_t vd1_if0_gen_reg; - uint32_t vd1_if0_luma_x0; -@@ -105,6 +106,21 @@ struct meson_drm { - uint32_t vd1_height0; - uint32_t vd1_height1; - uint32_t vd1_height2; -+ uint32_t vd1_afbc_mode; -+ uint32_t vd1_afbc_en; -+ uint32_t vd1_afbc_head_addr; -+ uint32_t vd1_afbc_body_addr; -+ uint32_t vd1_afbc_conv_ctrl; -+ uint32_t vd1_afbc_dec_def_color; -+ uint32_t vd1_afbc_vd_cfmt_ctrl; -+ uint32_t vd1_afbc_vd_cfmt_w; -+ uint32_t vd1_afbc_vd_cfmt_h; -+ uint32_t vd1_afbc_mif_hor_scope; -+ uint32_t vd1_afbc_mif_ver_scope; -+ uint32_t vd1_afbc_size_out; -+ uint32_t vd1_afbc_pixel_hor_scope; -+ uint32_t vd1_afbc_pixel_ver_scope; -+ uint32_t vd1_afbc_size_in; - uint32_t vpp_pic_in_height; - uint32_t vpp_postblend_vd1_h_start_end; - uint32_t vpp_postblend_vd1_v_start_end; -diff --git a/drivers/gpu/drm/meson/meson_overlay.c b/drivers/gpu/drm/meson/meson_overlay.c -index 2468b0212d52..1fbb81732e9a 100644 ---- a/drivers/gpu/drm/meson/meson_overlay.c -+++ b/drivers/gpu/drm/meson/meson_overlay.c -@@ -5,6 +5,7 @@ - * Copyright (C) 2015 Amlogic, Inc. All rights reserved. - */ - -+#define DEBUG - #include - - #include -@@ -76,6 +77,84 @@ - #define VD_REGION24_START(value) FIELD_PREP(GENMASK(11, 0), value) - #define VD_REGION13_END(value) FIELD_PREP(GENMASK(27, 16), value) - -+/* AFBC_ENABLE */ -+#define AFBC_DEC_ENABLE BIT(8) -+#define AFBC_FRM_START BIT(0) -+ -+/* AFBC_MODE */ -+#define AFBC_HORZ_SKIP_UV(value) FIELD_PREP(GENMASK(1, 0), value) -+#define AFBC_VERT_SKIP_UV(value) FIELD_PREP(GENMASK(3, 2), value) -+#define AFBC_HORZ_SKIP_Y(value) FIELD_PREP(GENMASK(5, 4), value) -+#define AFBC_VERT_SKIP_Y(value) FIELD_PREP(GENMASK(7, 6), value) -+#define AFBC_COMPBITS_YUV(value) FIELD_PREP(GENMASK(13, 8), value) -+#define AFBC_COMPBITS_8BIT 0 -+#define AFBC_COMPBITS_10BIT (2 | (2 << 2) | (2 << 4)) -+#define AFBC_BURST_LEN(value) FIELD_PREP(GENMASK(15, 14), value) -+#define AFBC_HOLD_LINE_NUM(value) FIELD_PREP(GENMASK(22, 16), value) -+#define AFBC_MIF_URGENT(value) FIELD_PREP(GENMASK(25, 24), value) -+#define AFBC_REV_MODE(value) FIELD_PREP(GENMASK(27, 26), value) -+#define AFBC_BLK_MEM_MODE BIT(28) -+#define AFBC_SCATTER_MODE BIT(29) -+#define AFBC_SOFT_RESET BIT(31) -+ -+/* AFBC_SIZE_IN */ -+#define AFBC_HSIZE_IN(value) FIELD_PREP(GENMASK(28, 16), value) -+#define AFBC_VSIZE_IN(value) FIELD_PREP(GENMASK(12, 0), value) -+ -+/* AFBC_DEC_DEF_COLOR */ -+#define AFBC_DEF_COLOR_Y(value) FIELD_PREP(GENMASK(29, 20), value) -+#define AFBC_DEF_COLOR_U(value) FIELD_PREP(GENMASK(19, 10), value) -+#define AFBC_DEF_COLOR_V(value) FIELD_PREP(GENMASK(9, 0), value) -+ -+/* AFBC_CONV_CTRL */ -+#define AFBC_CONV_LBUF_LEN(value) FIELD_PREP(GENMASK(11, 0), value) -+ -+/* AFBC_LBUF_DEPTH */ -+#define AFBC_DEC_LBUF_DEPTH(value) FIELD_PREP(GENMASK(27, 16), value) -+#define AFBC_MIF_LBUF_DEPTH(value) FIELD_PREP(GENMASK(11, 0), value) -+ -+/* AFBC_OUT_XSCOPE/AFBC_SIZE_OUT */ -+#define AFBC_HSIZE_OUT(value) FIELD_PREP(GENMASK(28, 16), value) -+#define AFBC_VSIZE_OUT(value) FIELD_PREP(GENMASK(12, 0), value) -+#define AFBC_OUT_HORZ_BGN(value) FIELD_PREP(GENMASK(28, 16), value) -+#define AFBC_OUT_HORZ_END(value) FIELD_PREP(GENMASK(12, 0), value) -+ -+/* AFBC_OUT_YSCOPE */ -+#define AFBC_OUT_VERT_BGN(value) FIELD_PREP(GENMASK(28, 16), value) -+#define AFBC_OUT_VERT_END(value) FIELD_PREP(GENMASK(12, 0), value) -+ -+/* AFBC_VD_CFMT_CTRL */ -+#define AFBC_HORZ_RPT_PIXEL0 BIT(23) -+#define AFBC_HORZ_Y_C_RATIO(value) FIELD_PREP(GENMASK(22, 21), value) -+#define AFBC_HORZ_FMT_EN BIT(20) -+#define AFBC_VERT_RPT_LINE0 BIT(16) -+#define AFBC_VERT_INITIAL_PHASE(value) FIELD_PREP(GENMASK(11, 8), value) -+#define AFBC_VERT_PHASE_STEP(value) FIELD_PREP(GENMASK(7, 1), value) -+#define AFBC_VERT_FMT_EN BIT(0) -+ -+/* AFBC_VD_CFMT_W */ -+#define AFBC_VD_V_WIDTH(value) FIELD_PREP(GENMASK(11, 0), value) -+#define AFBC_VD_H_WIDTH(value) FIELD_PREP(GENMASK(27, 16), value) -+ -+/* AFBC_MIF_HOR_SCOPE */ -+#define AFBC_MIF_BLK_BGN_H(value) FIELD_PREP(GENMASK(25, 16), value) -+#define AFBC_MIF_BLK_END_H(value) FIELD_PREP(GENMASK(9, 0), value) -+ -+/* AFBC_MIF_VER_SCOPE */ -+#define AFBC_MIF_BLK_BGN_V(value) FIELD_PREP(GENMASK(27, 16), value) -+#define AFBC_MIF_BLK_END_V(value) FIELD_PREP(GENMASK(11, 0), value) -+ -+/* AFBC_PIXEL_HOR_SCOPE */ -+#define AFBC_DEC_PIXEL_BGN_H(value) FIELD_PREP(GENMASK(28, 16), value) -+#define AFBC_DEC_PIXEL_END_H(value) FIELD_PREP(GENMASK(12, 0), value) -+ -+/* AFBC_PIXEL_VER_SCOPE */ -+#define AFBC_DEC_PIXEL_BGN_V(value) FIELD_PREP(GENMASK(28, 16), value) -+#define AFBC_DEC_PIXEL_END_V(value) FIELD_PREP(GENMASK(12, 0), value) -+ -+/* AFBC_VD_CFMT_H */ -+#define AFBC_VD_HEIGHT(value) FIELD_PREP(GENMASK(12, 0), value) -+ - struct meson_overlay { - struct drm_plane base; - struct meson_drm *priv; -@@ -157,6 +236,9 @@ static void meson_overlay_setup_scaler_params(struct meson_drm *priv, - unsigned int ratio_x, ratio_y; - int temp_height, temp_width; - unsigned int w_in, h_in; -+ int afbc_left, afbc_right; -+ int afbc_top_src, afbc_bottom_src; -+ int afbc_top, afbc_bottom; - int temp, start, end; - - if (!crtc_state) { -@@ -169,7 +251,7 @@ static void meson_overlay_setup_scaler_params(struct meson_drm *priv, - - w_in = fixed16_to_int(state->src_w); - h_in = fixed16_to_int(state->src_h); -- crop_top = fixed16_to_int(state->src_x); -+ crop_top = fixed16_to_int(state->src_y); - crop_left = fixed16_to_int(state->src_x); - - video_top = state->crtc_y; -@@ -243,6 +325,14 @@ static void meson_overlay_setup_scaler_params(struct meson_drm *priv, - DRM_DEBUG("vsc startp %d endp %d start_lines %d end_lines %d\n", - vsc_startp, vsc_endp, vd_start_lines, vd_end_lines); - -+ afbc_top = round_down(vd_start_lines, 4); -+ afbc_bottom = round_up(vd_end_lines + 1, 4); -+ afbc_top_src = 0; -+ afbc_bottom_src = round_up(h_in + 1, 4); -+ -+ DRM_DEBUG("afbc top %d (src %d) bottom %d (src %d)\n", -+ afbc_top, afbc_top_src, afbc_bottom, afbc_bottom_src); -+ - /* Horizontal */ - - start = video_left + video_width / 2 - ((w_in << 17) / ratio_x); -@@ -278,6 +368,16 @@ static void meson_overlay_setup_scaler_params(struct meson_drm *priv, - DRM_DEBUG("hsc startp %d endp %d start_lines %d end_lines %d\n", - hsc_startp, hsc_endp, hd_start_lines, hd_end_lines); - -+ if (hd_start_lines > 0 || (hd_end_lines < w_in)) { -+ afbc_left = 0; -+ afbc_right = round_up(w_in, 32); -+ } else { -+ afbc_left = round_down(hd_start_lines, 32); -+ afbc_right = round_up(hd_end_lines + 1, 32); -+ } -+ -+ DRM_DEBUG("afbc left %d right %d\n", afbc_left, afbc_right); -+ - priv->viu.vpp_vsc_start_phase_step = ratio_y << 6; - - priv->viu.vpp_vsc_ini_phase = vphase << 8; -@@ -293,6 +393,35 @@ static void meson_overlay_setup_scaler_params(struct meson_drm *priv, - VD_H_WIDTH(hd_end_lines - hd_start_lines + 1) | - VD_V_WIDTH(hd_end_lines/2 - hd_start_lines/2 + 1); - -+ priv->viu.vd1_afbc_vd_cfmt_w = -+ AFBC_VD_H_WIDTH(afbc_right - afbc_left) | -+ AFBC_VD_V_WIDTH(afbc_right / 2 - afbc_left / 2); -+ -+ priv->viu.vd1_afbc_vd_cfmt_h = -+ AFBC_VD_HEIGHT((afbc_bottom - afbc_top) / 2); -+ -+ priv->viu.vd1_afbc_mif_hor_scope = AFBC_MIF_BLK_BGN_H(afbc_left / 32) | -+ AFBC_MIF_BLK_END_H((afbc_right / 32) - 1); -+ -+ priv->viu.vd1_afbc_mif_ver_scope = AFBC_MIF_BLK_BGN_V(afbc_top / 4) | -+ AFBC_MIF_BLK_END_H((afbc_bottom / 4) - 1); -+ -+ priv->viu.vd1_afbc_size_out = -+ AFBC_HSIZE_OUT(afbc_right - afbc_left) | -+ AFBC_VSIZE_OUT(afbc_bottom - afbc_top); -+ -+ priv->viu.vd1_afbc_pixel_hor_scope = -+ AFBC_DEC_PIXEL_BGN_H(hd_start_lines - afbc_left) | -+ AFBC_DEC_PIXEL_END_H(hd_end_lines - afbc_left); -+ -+ priv->viu.vd1_afbc_pixel_ver_scope = -+ AFBC_DEC_PIXEL_BGN_V(vd_start_lines - afbc_top) | -+ AFBC_DEC_PIXEL_END_V(vd_end_lines - afbc_top); -+ -+ priv->viu.vd1_afbc_size_in = -+ AFBC_HSIZE_IN(afbc_right - afbc_left) | -+ AFBC_VSIZE_IN(afbc_bottom_src - afbc_top_src); -+ - priv->viu.vd1_if0_luma_y0 = VD_Y_START(vd_start_lines) | - VD_Y_END(vd_end_lines); - -@@ -350,11 +479,63 @@ static void meson_overlay_atomic_update(struct drm_plane *plane, - - spin_lock_irqsave(&priv->drm->event_lock, flags); - -- priv->viu.vd1_if0_gen_reg = VD_URGENT_CHROMA | -- VD_URGENT_LUMA | -- VD_HOLD_LINES(9) | -- VD_CHRO_RPT_LASTL_CTRL | -- VD_ENABLE; -+ if ((fb->modifier & DRM_FORMAT_MOD_AMLOGIC_FBC(0)) == -+ DRM_FORMAT_MOD_AMLOGIC_FBC(0)) { -+ priv->viu.vd1_afbc = true; -+ -+ priv->viu.vd1_afbc_mode = AFBC_MIF_URGENT(3) | -+ AFBC_HOLD_LINE_NUM(8) | -+ AFBC_BURST_LEN(2); -+ -+ if (fb->modifier & DRM_FORMAT_MOD_AMLOGIC_FBC_SCATTER) -+ priv->viu.vd1_afbc_mode |= AFBC_SCATTER_MODE; -+ -+ if (fb->modifier & DRM_FORMAT_MOD_AMLOGIC_FBC_MEM_SAVING) -+ priv->viu.vd1_afbc_mode |= AFBC_BLK_MEM_MODE; -+ -+ priv->viu.vd1_afbc_en = 0x1600 | AFBC_DEC_ENABLE; -+ -+ priv->viu.vd1_afbc_conv_ctrl = AFBC_CONV_LBUF_LEN(256); -+ -+ priv->viu.vd1_afbc_dec_def_color = AFBC_DEF_COLOR_Y(1023); -+ -+ /* 420: horizontal / 2, vertical / 4 */ -+ priv->viu.vd1_afbc_vd_cfmt_ctrl = AFBC_HORZ_RPT_PIXEL0 | -+ AFBC_HORZ_Y_C_RATIO(1) | -+ AFBC_HORZ_FMT_EN | -+ AFBC_VERT_RPT_LINE0 | -+ AFBC_VERT_INITIAL_PHASE(12) | -+ AFBC_VERT_PHASE_STEP(8) | -+ AFBC_VERT_FMT_EN; -+ -+ switch (fb->format->format) { -+ /* AFBC Only formats */ -+ case DRM_FORMAT_YUV420_10BIT: -+ priv->viu.vd1_afbc_mode |= -+ AFBC_COMPBITS_YUV(AFBC_COMPBITS_10BIT); -+ priv->viu.vd1_afbc_dec_def_color |= -+ AFBC_DEF_COLOR_U(512) | -+ AFBC_DEF_COLOR_V(512); -+ break; -+ case DRM_FORMAT_YUV420_8BIT: -+ priv->viu.vd1_afbc_dec_def_color |= -+ AFBC_DEF_COLOR_U(128) | -+ AFBC_DEF_COLOR_V(128); -+ break; -+ } -+ -+ priv->viu.vd1_if0_gen_reg = 0; -+ priv->viu.vd1_if0_canvas0 = 0; -+ priv->viu.viu_vd1_fmt_ctrl = 0; -+ } else { -+ priv->viu.vd1_afbc = false; -+ -+ priv->viu.vd1_if0_gen_reg = VD_URGENT_CHROMA | -+ VD_URGENT_LUMA | -+ VD_HOLD_LINES(9) | -+ VD_CHRO_RPT_LASTL_CTRL | -+ VD_ENABLE; -+ } - - /* Setup scaler params */ - meson_overlay_setup_scaler_params(priv, plane, interlace_mode); -@@ -370,6 +551,7 @@ static void meson_overlay_atomic_update(struct drm_plane *plane, - priv->viu.vd1_if0_gen_reg2 = 0; - priv->viu.viu_vd1_fmt_ctrl = 0; - -+ /* None will match for AFBC Only formats */ - switch (fb->format->format) { - /* TOFIX DRM_FORMAT_RGB888 should be supported */ - case DRM_FORMAT_YUYV: -@@ -488,13 +670,42 @@ static void meson_overlay_atomic_update(struct drm_plane *plane, - priv->viu.vd1_stride0 = fb->pitches[0]; - priv->viu.vd1_height0 = - drm_format_info_plane_height(fb->format, -- fb->height, 0); -+ fb->height, 0); - DRM_DEBUG("plane 0 addr 0x%x stride %d height %d\n", - priv->viu.vd1_addr0, - priv->viu.vd1_stride0, - priv->viu.vd1_height0); - } - -+ if (priv->viu.vd1_afbc) { -+ if (priv->viu.vd1_afbc_mode & AFBC_SCATTER_MODE) { -+ /* -+ * In Scatter mode, the header contains the physical -+ * body content layout, thus the body content -+ * size isn't needed. -+ */ -+ priv->viu.vd1_afbc_head_addr = priv->viu.vd1_addr0 >> 4; -+ priv->viu.vd1_afbc_body_addr = 0; -+ } else { -+ /* Default mode is 4k per superblock */ -+ unsigned long block_size = 4096; -+ unsigned long body_size; -+ -+ /* 8bit mem saving mode is 3072bytes per superblock */ -+ if (priv->viu.vd1_afbc_mode & AFBC_BLK_MEM_MODE) -+ block_size = 3072; -+ -+ body_size = (ALIGN(priv->viu.vd1_stride0, 64) / 64) * -+ (ALIGN(priv->viu.vd1_height0, 32) / 32) * -+ block_size; -+ -+ priv->viu.vd1_afbc_body_addr = priv->viu.vd1_addr0 >> 4; -+ /* Header is after body content */ -+ priv->viu.vd1_afbc_head_addr = (priv->viu.vd1_addr0 + -+ body_size) >> 4; -+ } -+ } -+ - priv->viu.vd1_enabled = true; - - spin_unlock_irqrestore(&priv->drm->event_lock, flags); -@@ -531,6 +742,23 @@ static const struct drm_plane_helper_funcs meson_overlay_helper_funcs = { - .prepare_fb = drm_gem_fb_prepare_fb, - }; - -+static bool meson_overlay_format_mod_supported(struct drm_plane *plane, -+ u32 format, u64 modifier) -+{ -+ if (modifier == DRM_FORMAT_MOD_LINEAR && -+ format != DRM_FORMAT_YUV420_8BIT && -+ format != DRM_FORMAT_YUV420_10BIT) -+ return true; -+ -+ if ((modifier & DRM_FORMAT_MOD_AMLOGIC_FBC(0)) == -+ DRM_FORMAT_MOD_AMLOGIC_FBC(0) && -+ (format == DRM_FORMAT_YUV420_8BIT || -+ format == DRM_FORMAT_YUV420_10BIT)) -+ return true; -+ -+ return false; -+} -+ - static const struct drm_plane_funcs meson_overlay_funcs = { - .update_plane = drm_atomic_helper_update_plane, - .disable_plane = drm_atomic_helper_disable_plane, -@@ -538,6 +766,7 @@ static const struct drm_plane_funcs meson_overlay_funcs = { - .reset = drm_atomic_helper_plane_reset, - .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, - .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, -+ .format_mod_supported = meson_overlay_format_mod_supported, - }; - - static const uint32_t supported_drm_formats[] = { -@@ -549,6 +778,18 @@ static const uint32_t supported_drm_formats[] = { - DRM_FORMAT_YUV420, - DRM_FORMAT_YUV411, - DRM_FORMAT_YUV410, -+ DRM_FORMAT_YUV420_8BIT, /* Amlogic FBC Only */ -+ DRM_FORMAT_YUV420_10BIT, /* Amlogic FBC Only */ -+}; -+ -+static const uint64_t format_modifiers[] = { -+ DRM_FORMAT_MOD_AMLOGIC_FBC(DRM_FORMAT_MOD_AMLOGIC_FBC_SCATTER | -+ DRM_FORMAT_MOD_AMLOGIC_FBC_MEM_SAVING), -+ DRM_FORMAT_MOD_AMLOGIC_FBC(DRM_FORMAT_MOD_AMLOGIC_FBC_SCATTER), -+ DRM_FORMAT_MOD_AMLOGIC_FBC(DRM_FORMAT_MOD_AMLOGIC_FBC_MEM_SAVING), -+ DRM_FORMAT_MOD_AMLOGIC_FBC_DEFAULT, -+ DRM_FORMAT_MOD_LINEAR, -+ DRM_FORMAT_MOD_INVALID, - }; - - int meson_overlay_create(struct meson_drm *priv) -@@ -570,7 +811,7 @@ int meson_overlay_create(struct meson_drm *priv) - &meson_overlay_funcs, - supported_drm_formats, - ARRAY_SIZE(supported_drm_formats), -- NULL, -+ format_modifiers, - DRM_PLANE_TYPE_OVERLAY, "meson_overlay_plane"); - - drm_plane_helper_add(plane, &meson_overlay_helper_funcs); --- -2.17.1 - diff --git a/patch/kernel/meson64-current/0079-FROMLIST-drm-meson-crtc-handle-commit-of-Amlogic-FBC.patch b/patch/kernel/meson64-current/0079-FROMLIST-drm-meson-crtc-handle-commit-of-Amlogic-FBC.patch deleted file mode 100644 index 1e2fd016b5..0000000000 --- a/patch/kernel/meson64-current/0079-FROMLIST-drm-meson-crtc-handle-commit-of-Amlogic-FBC.patch +++ /dev/null @@ -1,160 +0,0 @@ -From 8e6c592ce9779efbcdab03312a058887297eaeaf Mon Sep 17 00:00:00 2001 -From: Neil Armstrong -Date: Thu, 20 Feb 2020 17:16:57 +0000 -Subject: [PATCH 079/101] FROMLIST: drm/meson: crtc: handle commit of Amlogic - FBC frames - -Since the VD1 Amlogic FBC decoder is now configured by the overlay driver, -commit the right registers to decode the Amlogic FBC frame. - -Signed-off-by: Neil Armstrong ---- - drivers/gpu/drm/meson/meson_crtc.c | 118 +++++++++++++++++++++-------- - 1 file changed, 88 insertions(+), 30 deletions(-) - -diff --git a/drivers/gpu/drm/meson/meson_crtc.c b/drivers/gpu/drm/meson/meson_crtc.c -index e66b6271ff58..d6dcfd654e9c 100644 ---- a/drivers/gpu/drm/meson/meson_crtc.c -+++ b/drivers/gpu/drm/meson/meson_crtc.c -@@ -291,6 +291,10 @@ static void meson_crtc_enable_vd1(struct meson_drm *priv) - VPP_VD1_PREBLEND | VPP_VD1_POSTBLEND | - VPP_COLOR_MNG_ENABLE, - priv->io_base + _REG(VPP_MISC)); -+ -+ writel_bits_relaxed(VIU_CTRL0_AFBC_TO_VD1, -+ priv->viu.vd1_afbc ? VIU_CTRL0_AFBC_TO_VD1 : 0, -+ priv->io_base + _REG(VIU_MISC_CTRL0)); - } - - static void meson_g12a_crtc_enable_vd1(struct meson_drm *priv) -@@ -300,6 +304,10 @@ static void meson_g12a_crtc_enable_vd1(struct meson_drm *priv) - VD_BLEND_POSTBLD_SRC_VD1 | - VD_BLEND_POSTBLD_PREMULT_EN, - priv->io_base + _REG(VD1_BLEND_SRC_CTRL)); -+ -+ writel_relaxed(priv->viu.vd1_afbc ? -+ (VD1_AXI_SEL_AFBC | AFBC_VD1_SEL) : 0, -+ priv->io_base + _REG(VD1_AFBCD0_MISC_CTRL)); - } - - void meson_crtc_irq(struct meson_drm *priv) -@@ -383,36 +391,86 @@ void meson_crtc_irq(struct meson_drm *priv) - /* Update the VD1 registers */ - if (priv->viu.vd1_enabled && priv->viu.vd1_commit) { - -- switch (priv->viu.vd1_planes) { -- case 3: -- meson_canvas_config(priv->canvas, -- priv->canvas_id_vd1_2, -- priv->viu.vd1_addr2, -- priv->viu.vd1_stride2, -- priv->viu.vd1_height2, -- MESON_CANVAS_WRAP_NONE, -- MESON_CANVAS_BLKMODE_LINEAR, -- MESON_CANVAS_ENDIAN_SWAP64); -- /* fallthrough */ -- case 2: -- meson_canvas_config(priv->canvas, -- priv->canvas_id_vd1_1, -- priv->viu.vd1_addr1, -- priv->viu.vd1_stride1, -- priv->viu.vd1_height1, -- MESON_CANVAS_WRAP_NONE, -- MESON_CANVAS_BLKMODE_LINEAR, -- MESON_CANVAS_ENDIAN_SWAP64); -- /* fallthrough */ -- case 1: -- meson_canvas_config(priv->canvas, -- priv->canvas_id_vd1_0, -- priv->viu.vd1_addr0, -- priv->viu.vd1_stride0, -- priv->viu.vd1_height0, -- MESON_CANVAS_WRAP_NONE, -- MESON_CANVAS_BLKMODE_LINEAR, -- MESON_CANVAS_ENDIAN_SWAP64); -+ if (priv->viu.vd1_afbc) { -+ writel_relaxed(priv->viu.vd1_afbc_head_addr, -+ priv->io_base + -+ _REG(AFBC_HEAD_BADDR)); -+ writel_relaxed(priv->viu.vd1_afbc_body_addr, -+ priv->io_base + -+ _REG(AFBC_BODY_BADDR)); -+ writel_relaxed(priv->viu.vd1_afbc_en, -+ priv->io_base + -+ _REG(AFBC_ENABLE)); -+ writel_relaxed(priv->viu.vd1_afbc_mode, -+ priv->io_base + -+ _REG(AFBC_MODE)); -+ writel_relaxed(priv->viu.vd1_afbc_size_in, -+ priv->io_base + -+ _REG(AFBC_SIZE_IN)); -+ writel_relaxed(priv->viu.vd1_afbc_dec_def_color, -+ priv->io_base + -+ _REG(AFBC_DEC_DEF_COLOR)); -+ writel_relaxed(priv->viu.vd1_afbc_conv_ctrl, -+ priv->io_base + -+ _REG(AFBC_CONV_CTRL)); -+ writel_relaxed(priv->viu.vd1_afbc_size_out, -+ priv->io_base + -+ _REG(AFBC_SIZE_OUT)); -+ writel_relaxed(priv->viu.vd1_afbc_vd_cfmt_ctrl, -+ priv->io_base + -+ _REG(AFBC_VD_CFMT_CTRL)); -+ writel_relaxed(priv->viu.vd1_afbc_vd_cfmt_w, -+ priv->io_base + -+ _REG(AFBC_VD_CFMT_W)); -+ writel_relaxed(priv->viu.vd1_afbc_mif_hor_scope, -+ priv->io_base + -+ _REG(AFBC_MIF_HOR_SCOPE)); -+ writel_relaxed(priv->viu.vd1_afbc_mif_ver_scope, -+ priv->io_base + -+ _REG(AFBC_MIF_VER_SCOPE)); -+ writel_relaxed(priv->viu.vd1_afbc_pixel_hor_scope, -+ priv->io_base+ -+ _REG(AFBC_PIXEL_HOR_SCOPE)); -+ writel_relaxed(priv->viu.vd1_afbc_pixel_ver_scope, -+ priv->io_base + -+ _REG(AFBC_PIXEL_VER_SCOPE)); -+ writel_relaxed(priv->viu.vd1_afbc_vd_cfmt_h, -+ priv->io_base + -+ _REG(AFBC_VD_CFMT_H)); -+ } else { -+ switch (priv->viu.vd1_planes) { -+ case 3: -+ meson_canvas_config(priv->canvas, -+ priv->canvas_id_vd1_2, -+ priv->viu.vd1_addr2, -+ priv->viu.vd1_stride2, -+ priv->viu.vd1_height2, -+ MESON_CANVAS_WRAP_NONE, -+ MESON_CANVAS_BLKMODE_LINEAR, -+ MESON_CANVAS_ENDIAN_SWAP64); -+ /* fallthrough */ -+ case 2: -+ meson_canvas_config(priv->canvas, -+ priv->canvas_id_vd1_1, -+ priv->viu.vd1_addr1, -+ priv->viu.vd1_stride1, -+ priv->viu.vd1_height1, -+ MESON_CANVAS_WRAP_NONE, -+ MESON_CANVAS_BLKMODE_LINEAR, -+ MESON_CANVAS_ENDIAN_SWAP64); -+ /* fallthrough */ -+ case 1: -+ meson_canvas_config(priv->canvas, -+ priv->canvas_id_vd1_0, -+ priv->viu.vd1_addr0, -+ priv->viu.vd1_stride0, -+ priv->viu.vd1_height0, -+ MESON_CANVAS_WRAP_NONE, -+ MESON_CANVAS_BLKMODE_LINEAR, -+ MESON_CANVAS_ENDIAN_SWAP64); -+ } -+ -+ writel_relaxed(0, priv->io_base + _REG(AFBC_ENABLE)); - } - - writel_relaxed(priv->viu.vd1_if0_gen_reg, --- -2.17.1 - diff --git a/patch/kernel/meson64-current/0085-WIP-ASoC-meson-add-2-8-channel-constraints.patch b/patch/kernel/meson64-current/0085-WIP-ASoC-meson-add-2-8-channel-constraints.patch deleted file mode 100644 index e8fd55d0d1..0000000000 --- a/patch/kernel/meson64-current/0085-WIP-ASoC-meson-add-2-8-channel-constraints.patch +++ /dev/null @@ -1,62 +0,0 @@ -From 6f010e1f35e82ba7d05e7738b391b8b7b53eb1cf Mon Sep 17 00:00:00 2001 -From: Neil Armstrong -Date: Thu, 20 Feb 2020 15:58:14 +0000 -Subject: [PATCH 085/101] WIP: ASoC: meson: add 2/8 channel constraints - -The audio hardware can output in 2 or 8 channels only, so we need must -ensure we start in only these two configurations. - -Signed-off-by: Neil Armstrong ---- - sound/soc/meson/aiu-fifo-i2s.c | 27 ++++++++++++++++++++++++++- - 1 file changed, 26 insertions(+), 1 deletion(-) - -diff --git a/sound/soc/meson/aiu-fifo-i2s.c b/sound/soc/meson/aiu-fifo-i2s.c -index 9a5271ce80fe..87e0c85eacc8 100644 ---- a/sound/soc/meson/aiu-fifo-i2s.c -+++ b/sound/soc/meson/aiu-fifo-i2s.c -@@ -118,15 +118,40 @@ static int aiu_fifo_i2s_hw_params(struct snd_pcm_substream *substream, - snd_soc_component_update_bits(component, AIU_MEM_I2S_MASKS, - AIU_MEM_I2S_MASKS_IRQ_BLOCK, val); - -+ snd_soc_component_write(component, AIU_RST_SOFT, -+ AIU_RST_SOFT_I2S_FAST); -+ snd_soc_component_read(component, AIU_I2S_SYNC, &val); -+ - return 0; - } - -+static const unsigned int channels_2_8[] = { -+ 2, 8 -+}; -+ -+static const struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = { -+ .count = ARRAY_SIZE(channels_2_8), -+ .list = channels_2_8, -+ .mask = 0, -+}; -+ -+static int aiu_fifo_i2s_startup(struct snd_pcm_substream *substream, -+ struct snd_soc_dai *dai) -+{ -+ /* Make sure either 2ch or 8ch is selected */ -+ snd_pcm_hw_constraint_list(substream->runtime, 0, -+ SNDRV_PCM_HW_PARAM_CHANNELS, -+ &hw_constraints_2_8_channels); -+ -+ return aiu_fifo_startup(substream, dai); -+} -+ - const struct snd_soc_dai_ops aiu_fifo_i2s_dai_ops = { - .trigger = aiu_fifo_i2s_trigger, - .prepare = aiu_fifo_i2s_prepare, - .hw_params = aiu_fifo_i2s_hw_params, - .hw_free = aiu_fifo_hw_free, -- .startup = aiu_fifo_startup, -+ .startup = aiu_fifo_i2s_startup, - .shutdown = aiu_fifo_shutdown, - }; - --- -2.17.1 - diff --git a/patch/kernel/meson64-current/board-khadas-vim3-change-LED-behaviour.patch b/patch/kernel/meson64-current/board-khadas-vim3-change-LED-behaviour.patch index 2852d43466..f77e63097a 100644 --- a/patch/kernel/meson64-current/board-khadas-vim3-change-LED-behaviour.patch +++ b/patch/kernel/meson64-current/board-khadas-vim3-change-LED-behaviour.patch @@ -26,7 +26,7 @@ index 6022805d2032..6d0163f56b0d 100644 led-white { - label = "vim3:white:sys"; -- gpios = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_LOW>; +- gpios = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; + label = "vim3:white:power"; + gpios = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_HIGH>; @@ -35,7 +35,7 @@ index 6022805d2032..6d0163f56b0d 100644 led-red { label = "vim3:red"; -- gpios = <&gpio_expander 5 GPIO_ACTIVE_LOW>; +- gpios = <&gpio_expander 5 GPIO_ACTIVE_HIGH>; + gpios = <&gpio_expander 5 GPIO_ACTIVE_HIGH>; }; }; diff --git a/patch/kernel/meson64-current/board-khadas-vim3l-add-audio-playback-.patch b/patch/kernel/meson64-current/board-khadas-vim3l-add-audio-playback-.patch deleted file mode 100644 index 4d9001cf5c..0000000000 --- a/patch/kernel/meson64-current/board-khadas-vim3l-add-audio-playback-.patch +++ /dev/null @@ -1,133 +0,0 @@ -From a1f62e3991b56958ab61e9a70f921881202d09d8 Mon Sep 17 00:00:00 2001 -From: Christian Hewitt -Date: Thu, 20 Feb 2020 16:59:34 +0000 -Subject: [PATCH 088/101] WIP: arm64: dts: meson: khadas-vim3l: add audio - playback to vim3l - -Add the sound and related audio nodes to the VIM3L device-tree. - -Signed-off-by: Christian Hewitt ---- - .../dts/amlogic/meson-sm1-khadas-vim3l.dts | 88 +++++++++++++++++++ - 1 file changed, 88 insertions(+) - -diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts -index dbbf29a0dbf6..0ccb268589df 100644 ---- a/arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts -+++ b/arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts -@@ -8,6 +8,7 @@ - - #include "meson-sm1.dtsi" - #include "meson-khadas-vim3.dtsi" -+#include - - / { - compatible = "khadas,vim3l", "amlogic,sm1"; -@@ -31,6 +32,69 @@ - regulator-boot-on; - regulator-always-on; - }; -+ -+ sound { -+ compatible = "amlogic,axg-sound-card"; -+ model = "SM1-KHADAS-VIM3L"; -+ audio-aux-devs = <&tdmout_b>; -+ audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", -+ "TDMOUT_B IN 1", "FRDDR_B OUT 1", -+ "TDMOUT_B IN 2", "FRDDR_C OUT 1", -+ "TDM_B Playback", "TDMOUT_B OUT"; -+ -+ assigned-clocks = <&clkc CLKID_MPLL2>, -+ <&clkc CLKID_MPLL0>, -+ <&clkc CLKID_MPLL1>; -+ assigned-clock-parents = <0>, <0>, <0>; -+ assigned-clock-rates = <294912000>, -+ <270950400>, -+ <393216000>; -+ status = "okay"; -+ -+ dai-link-0 { -+ sound-dai = <&frddr_a>; -+ }; -+ -+ dai-link-1 { -+ sound-dai = <&frddr_b>; -+ }; -+ -+ dai-link-2 { -+ sound-dai = <&frddr_c>; -+ }; -+ -+ /* 8ch hdmi interface */ -+ dai-link-3 { -+ sound-dai = <&tdmif_b>; -+ dai-format = "i2s"; -+ dai-tdm-slot-tx-mask-0 = <1 1>; -+ dai-tdm-slot-tx-mask-1 = <1 1>; -+ dai-tdm-slot-tx-mask-2 = <1 1>; -+ dai-tdm-slot-tx-mask-3 = <1 1>; -+ mclk-fs = <256>; -+ -+ codec { -+ sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; -+ }; -+ }; -+ -+ /* hdmi glue */ -+ dai-link-4 { -+ sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; -+ -+ codec { -+ sound-dai = <&hdmi_tx>; -+ }; -+ }; -+ }; -+}; -+ -+&arb { -+ status = "okay"; -+}; -+ -+&clkc_audio { -+ status = "okay"; - }; - - &cpu0 { -@@ -61,6 +125,18 @@ - clock-latency = <50000>; - }; - -+&frddr_a { -+ status = "okay"; -+}; -+ -+&frddr_b { -+ status = "okay"; -+}; -+ -+&frddr_c { -+ status = "okay"; -+}; -+ - &pwm_AO_cd { - pinctrl-0 = <&pwm_ao_d_e_pins>; - pinctrl-names = "default"; -@@ -93,3 +169,15 @@ - phy-names = "usb2-phy0", "usb2-phy1"; - }; - */ -+ -+&tdmif_b { -+ status = "okay"; -+}; -+ -+&tdmout_b { -+ status = "okay"; -+}; -+ -+&tohdmitx { -+ status = "okay"; -+}; --- -2.17.1 - diff --git a/patch/kernel/meson64-current/hardkernel-0022-pinctrl-meson-fix-drive-strength-register-and-bit-ca.patch b/patch/kernel/meson64-current/hardkernel-0022-pinctrl-meson-fix-drive-strength-register-and-bit-ca.patch deleted file mode 100644 index 154d454b0f..0000000000 --- a/patch/kernel/meson64-current/hardkernel-0022-pinctrl-meson-fix-drive-strength-register-and-bit-ca.patch +++ /dev/null @@ -1,41 +0,0 @@ -From 8a4510a8da6f43d13022cfba13b695819a263c83 Mon Sep 17 00:00:00 2001 -From: Hyeonki Hong -Date: Wed, 10 Jun 2020 12:54:06 +0900 -Subject: [PATCH 22/74] pinctrl: meson: fix drive strength register and bit - calculation - -If a GPIO bank has greater than 16 pins, PAD_DS_REG is split into two -registers. However, when register and bit were calculated, the first -register defined in the bank was used, and the bit was calculated based -on the first pin. This causes problems in setting the driving strength. - -Solved the problem by changing the bit using a mask and selecting the -next register when the bit exceeds 15. - -Signed-off-by: Hyeonki Hong -Change-Id: Ie0b046e50f6c92603030b0b490838219e81f5408 ---- - drivers/pinctrl/meson/pinctrl-meson.c | 7 +++++++ - 1 file changed, 7 insertions(+) - -diff --git a/drivers/pinctrl/meson/pinctrl-meson.c b/drivers/pinctrl/meson/pinctrl-meson.c -index 079f8ee8d353..aa2898c6c1e5 100644 ---- a/drivers/pinctrl/meson/pinctrl-meson.c -+++ b/drivers/pinctrl/meson/pinctrl-meson.c -@@ -98,6 +98,13 @@ static void meson_calc_reg_and_bit(struct meson_bank *bank, unsigned int pin, - - *reg = desc->reg * 4; - *bit = desc->bit + pin - bank->first; -+ -+ if (reg_type == REG_DS) { -+ if (*bit > 15) { -+ *bit &= 0xf; -+ *reg += 4; -+ } -+ } - } - - static int meson_get_groups_count(struct pinctrl_dev *pcdev) --- -2.25.1 - diff --git a/patch/kernel/meson64-current/odroid-c4-audio-1.patch b/patch/kernel/meson64-current/odroid-c4-audio-1.patch deleted file mode 100644 index 5a36875eac..0000000000 --- a/patch/kernel/meson64-current/odroid-c4-audio-1.patch +++ /dev/null @@ -1,140 +0,0 @@ -From 725da67ce4d77540d4d6f7ecc3ac5a885a684716 Mon Sep 17 00:00:00 2001 -From: Christian Hewitt -Date: Sat, 18 Jul 2020 07:25:31 +0000 -Subject: arm64: dts: meson: add audio playback to odroid-c4 - -Add initial audio support limited to HDMI i2s. - -Signed-off-by: Christian Hewitt -Signed-off-by: Kevin Hilman -Acked-by: Jerome Brunet -Link: https://lore.kernel.org/r/20200718072532.8427-2-christianshewitt@gmail.com ---- - .../arm64/boot/dts/amlogic/meson-sm1-odroid-c4.dts | 88 ++++++++++++++++++++++ - 1 file changed, 88 insertions(+) - -(limited to 'arch/arm64/boot/dts/amlogic') - -diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-c4.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-c4.dts -index 00d90b30f8b49..cf5a98f0e47c8 100644 ---- a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-c4.dts -+++ b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-c4.dts -@@ -8,6 +8,7 @@ - #include "meson-sm1.dtsi" - #include - #include -+#include - - / { - compatible = "hardkernel,odroid-c4", "amlogic,sm1"; -@@ -186,6 +187,69 @@ - }; - }; - }; -+ -+ sound { -+ compatible = "amlogic,axg-sound-card"; -+ model = "SM1-ODROID-C4"; -+ audio-aux-devs = <&tdmout_b>; -+ audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", -+ "TDMOUT_B IN 1", "FRDDR_B OUT 1", -+ "TDMOUT_B IN 2", "FRDDR_C OUT 1", -+ "TDM_B Playback", "TDMOUT_B OUT"; -+ -+ assigned-clocks = <&clkc CLKID_MPLL2>, -+ <&clkc CLKID_MPLL0>, -+ <&clkc CLKID_MPLL1>; -+ assigned-clock-parents = <0>, <0>, <0>; -+ assigned-clock-rates = <294912000>, -+ <270950400>, -+ <393216000>; -+ status = "okay"; -+ -+ dai-link-0 { -+ sound-dai = <&frddr_a>; -+ }; -+ -+ dai-link-1 { -+ sound-dai = <&frddr_b>; -+ }; -+ -+ dai-link-2 { -+ sound-dai = <&frddr_c>; -+ }; -+ -+ /* 8ch hdmi interface */ -+ dai-link-3 { -+ sound-dai = <&tdmif_b>; -+ dai-format = "i2s"; -+ dai-tdm-slot-tx-mask-0 = <1 1>; -+ dai-tdm-slot-tx-mask-1 = <1 1>; -+ dai-tdm-slot-tx-mask-2 = <1 1>; -+ dai-tdm-slot-tx-mask-3 = <1 1>; -+ mclk-fs = <256>; -+ -+ codec { -+ sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; -+ }; -+ }; -+ -+ /* hdmi glue */ -+ dai-link-4 { -+ sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; -+ -+ codec { -+ sound-dai = <&hdmi_tx>; -+ }; -+ }; -+ }; -+}; -+ -+&arb { -+ status = "okay"; -+}; -+ -+&clkc_audio { -+ status = "okay"; - }; - - &cpu0 { -@@ -237,6 +301,18 @@ - amlogic,tx-delay-ns = <2>; - }; - -+&frddr_a { -+ status = "okay"; -+}; -+ -+&frddr_b { -+ status = "okay"; -+}; -+ -+&frddr_c { -+ status = "okay"; -+}; -+ - &gpio { - gpio-line-names = - /* GPIOZ */ -@@ -381,6 +457,18 @@ - vqmmc-supply = <&flash_1v8>; - }; - -+&tdmif_b { -+ status = "okay"; -+}; -+ -+&tdmout_b { -+ status = "okay"; -+}; -+ -+&tohdmitx { -+ status = "okay"; -+}; -+ - &uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; --- -cgit 1.2.3-1.el7 - diff --git a/patch/kernel/meson64-current/odroid-n2-audio-1.patch b/patch/kernel/meson64-current/odroid-n2-audio-1.patch deleted file mode 100644 index 2d7b4c809a..0000000000 --- a/patch/kernel/meson64-current/odroid-n2-audio-1.patch +++ /dev/null @@ -1,128 +0,0 @@ -From a7a80474069842c27282a5e991704a0a1f26f243 Mon Sep 17 00:00:00 2001 -From: Jerome Brunet -Date: Wed, 1 Jul 2020 11:45:55 +0200 -Subject: arm64: dts: meson: odroid-n2: enable audio loopback - -Add capture pcm interfaces and loopback routes to the odroid-n2 - -Signed-off-by: Jerome Brunet -Signed-off-by: Kevin Hilman -Reviewed-by: Neil Armstrong -Link: https://lore.kernel.org/r/20200701094556.194498-2-jbrunet@baylibre.com ---- - .../boot/dts/amlogic/meson-g12b-odroid-n2.dts | 65 ++++++++++++++++++++-- - 1 file changed, 61 insertions(+), 4 deletions(-) - -(limited to 'arch/arm64/boot/dts/amlogic') - -diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts -index 169ea283d4ee3..d4421ad164bde 100644 ---- a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts -+++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts -@@ -209,11 +209,28 @@ - sound { - compatible = "amlogic,axg-sound-card"; - model = "G12B-ODROID-N2"; -- audio-aux-devs = <&tdmout_b>; -+ audio-aux-devs = <&tdmout_b>, <&tdmin_a>, <&tdmin_b>, -+ <&tdmin_c>, <&tdmin_lb>; - audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", - "TDMOUT_B IN 1", "FRDDR_B OUT 1", - "TDMOUT_B IN 2", "FRDDR_C OUT 1", -- "TDM_B Playback", "TDMOUT_B OUT"; -+ "TDM_B Playback", "TDMOUT_B OUT", -+ "TDMIN_A IN 4", "TDM_B Loopback", -+ "TDMIN_B IN 4", "TDM_B Loopback", -+ "TDMIN_C IN 4", "TDM_B Loopback", -+ "TDMIN_LB IN 1", "TDM_B Loopback", -+ "TODDR_A IN 0", "TDMIN_A OUT", -+ "TODDR_B IN 0", "TDMIN_A OUT", -+ "TODDR_C IN 0", "TDMIN_A OUT", -+ "TODDR_A IN 1", "TDMIN_B OUT", -+ "TODDR_B IN 1", "TDMIN_B OUT", -+ "TODDR_C IN 1", "TDMIN_B OUT", -+ "TODDR_A IN 2", "TDMIN_C OUT", -+ "TODDR_B IN 2", "TDMIN_C OUT", -+ "TODDR_C IN 2", "TDMIN_C OUT", -+ "TODDR_A IN 6", "TDMIN_LB OUT", -+ "TODDR_B IN 6", "TDMIN_LB OUT", -+ "TODDR_C IN 6", "TDMIN_LB OUT"; - - assigned-clocks = <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL0>, -@@ -236,8 +253,20 @@ - sound-dai = <&frddr_c>; - }; - -- /* 8ch hdmi interface */ - dai-link-3 { -+ sound-dai = <&toddr_a>; -+ }; -+ -+ dai-link-4 { -+ sound-dai = <&toddr_b>; -+ }; -+ -+ dai-link-5 { -+ sound-dai = <&toddr_c>; -+ }; -+ -+ /* 8ch hdmi interface */ -+ dai-link-6 { - sound-dai = <&tdmif_b>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-0 = <1 1>; -@@ -252,7 +281,7 @@ - }; - - /* hdmi glue */ -- dai-link-4 { -+ dai-link-7 { - sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; - - codec { -@@ -476,6 +505,22 @@ - status = "okay"; - }; - -+&tdmin_a { -+ status = "okay"; -+}; -+ -+&tdmin_b { -+ status = "okay"; -+}; -+ -+&tdmin_c { -+ status = "okay"; -+}; -+ -+&tdmin_lb { -+ status = "okay"; -+}; -+ - &tdmout_b { - status = "okay"; - }; -@@ -484,6 +529,18 @@ - status = "okay"; - }; - -+&toddr_a { -+ status = "okay"; -+}; -+ -+&toddr_b { -+ status = "okay"; -+}; -+ -+&toddr_c { -+ status = "okay"; -+}; -+ - &uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; --- -cgit 1.2.3-1.el7 - diff --git a/patch/kernel/meson64-current/odroid-n2-audio-2.patch b/patch/kernel/meson64-current/odroid-n2-audio-2.patch deleted file mode 100644 index 303d80b125..0000000000 --- a/patch/kernel/meson64-current/odroid-n2-audio-2.patch +++ /dev/null @@ -1,174 +0,0 @@ -From 67d141c1f8e604a9c02d6a60f7827443d7f44762 Mon Sep 17 00:00:00 2001 -From: Jerome Brunet -Date: Wed, 1 Jul 2020 11:45:56 +0200 -Subject: arm64: dts: meson: odroid-n2: add jack audio output support - -Add support for audio on jack socket of the odroid-n2 - -Signed-off-by: Jerome Brunet -Signed-off-by: Kevin Hilman -Reviewed-by: Neil Armstrong -Link: https://lore.kernel.org/r/20200701094556.194498-3-jbrunet@baylibre.com ---- - .../boot/dts/amlogic/meson-g12b-odroid-n2.dts | 79 ++++++++++++++++++++-- - 1 file changed, 74 insertions(+), 5 deletions(-) - -(limited to 'arch/arm64/boot/dts/amlogic') - -diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts -index d4421ad164bde..34fffa6d859db 100644 ---- a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts -+++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts -@@ -9,6 +9,7 @@ - #include "meson-g12b-s922x.dtsi" - #include - #include -+#include - #include - - / { -@@ -20,6 +21,14 @@ - ethernet0 = ðmac; - }; - -+ dioo2133: audio-amplifier-0 { -+ compatible = "simple-audio-amplifier"; -+ enable-gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>; -+ VCC-supply = <&vcc_5v>; -+ sound-name-prefix = "U19"; -+ status = "okay"; -+ }; -+ - chosen { - stdout-path = "serial0:115200n8"; - }; -@@ -209,16 +218,26 @@ - sound { - compatible = "amlogic,axg-sound-card"; - model = "G12B-ODROID-N2"; -- audio-aux-devs = <&tdmout_b>, <&tdmin_a>, <&tdmin_b>, -- <&tdmin_c>, <&tdmin_lb>; -+ audio-widgets = "Line", "Lineout"; -+ audio-aux-devs = <&tdmout_b>, <&tdmout_c>, <&tdmin_a>, -+ <&tdmin_b>, <&tdmin_c>, <&tdmin_lb>, -+ <&dioo2133>; - audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", - "TDMOUT_B IN 1", "FRDDR_B OUT 1", - "TDMOUT_B IN 2", "FRDDR_C OUT 1", - "TDM_B Playback", "TDMOUT_B OUT", -+ "TDMOUT_C IN 0", "FRDDR_A OUT 2", -+ "TDMOUT_C IN 1", "FRDDR_B OUT 2", -+ "TDMOUT_C IN 2", "FRDDR_C OUT 2", -+ "TDM_C Playback", "TDMOUT_C OUT", - "TDMIN_A IN 4", "TDM_B Loopback", - "TDMIN_B IN 4", "TDM_B Loopback", - "TDMIN_C IN 4", "TDM_B Loopback", - "TDMIN_LB IN 1", "TDM_B Loopback", -+ "TDMIN_A IN 5", "TDM_C Loopback", -+ "TDMIN_B IN 5", "TDM_C Loopback", -+ "TDMIN_C IN 5", "TDM_C Loopback", -+ "TDMIN_LB IN 2", "TDM_C Loopback", - "TODDR_A IN 0", "TDMIN_A OUT", - "TODDR_B IN 0", "TDMIN_A OUT", - "TODDR_C IN 0", "TDMIN_A OUT", -@@ -230,7 +249,11 @@ - "TODDR_C IN 2", "TDMIN_C OUT", - "TODDR_A IN 6", "TDMIN_LB OUT", - "TODDR_B IN 6", "TDMIN_LB OUT", -- "TODDR_C IN 6", "TDMIN_LB OUT"; -+ "TODDR_C IN 6", "TDMIN_LB OUT", -+ "U19 INL", "ACODEC LOLP", -+ "U19 INR", "ACODEC LORP", -+ "Lineout", "U19 OUTL", -+ "Lineout", "U19 OUTR"; - - assigned-clocks = <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL0>, -@@ -275,22 +298,56 @@ - dai-tdm-slot-tx-mask-3 = <1 1>; - mclk-fs = <256>; - -- codec { -+ codec-0 { - sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; - }; -+ -+ codec-1 { -+ sound-dai = <&toacodec TOACODEC_IN_B>; -+ }; - }; - -- /* hdmi glue */ -+ /* i2s jack output interface */ - dai-link-7 { -+ sound-dai = <&tdmif_c>; -+ dai-format = "i2s"; -+ dai-tdm-slot-tx-mask-0 = <1 1>; -+ mclk-fs = <256>; -+ -+ codec-0 { -+ sound-dai = <&tohdmitx TOHDMITX_I2S_IN_C>; -+ }; -+ -+ codec-1 { -+ sound-dai = <&toacodec TOACODEC_IN_C>; -+ }; -+ }; -+ -+ /* hdmi glue */ -+ dai-link-8 { - sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; - - codec { - sound-dai = <&hdmi_tx>; - }; - }; -+ -+ /* acodec glue */ -+ dai-link-9 { -+ sound-dai = <&toacodec TOACODEC_OUT>; -+ -+ codec { -+ sound-dai = <&acodec>; -+ }; -+ }; - }; - }; - -+&acodec { -+ AVDD-supply = <&vddao_1v8>; -+ status = "okay"; -+}; -+ - &arb { - status = "okay"; - }; -@@ -505,6 +562,10 @@ - status = "okay"; - }; - -+&tdmif_c { -+ status = "okay"; -+}; -+ - &tdmin_a { - status = "okay"; - }; -@@ -525,6 +586,14 @@ - status = "okay"; - }; - -+&tdmout_c { -+ status = "okay"; -+}; -+ -+&toacodec { -+ status = "okay"; -+}; -+ - &tohdmitx { - status = "okay"; - }; --- -cgit 1.2.3-1.el7 - diff --git a/patch/kernel/meson64-dev/dts-meson-add-watchdog-to-g12-common-dtsi.patch.txt.patch b/patch/kernel/meson64-dev/dts-meson-add-watchdog-to-g12-common-dtsi.patch.txt.patch new file mode 100644 index 0000000000..8457d49eac --- /dev/null +++ b/patch/kernel/meson64-dev/dts-meson-add-watchdog-to-g12-common-dtsi.patch.txt.patch @@ -0,0 +1,30 @@ +Subject: [PATCH] arm64: dts: meson: add watchdog to g12-common dtsi +Date: Fri, 30 Oct 2020 18:00:57 +0000 +Message-Id: <20201030180057.23886-1-christianshewitt@gmail.com> + +G12 vendor kernels show the watchdog on the same address as AXG +so add the node to meson-g12-common.dtsi. GX boards inherit the +same from meson-gx.dtsi. + +Signed-off-by: Christian Hewitt +--- + arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi +index 1e83ec5b8c91..92afec3ffb2d 100644 +--- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi ++++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi +@@ -2179,6 +2179,12 @@ + amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; + }; + ++ watchdog: wdt@f0d0 { ++ compatible = "amlogic,meson-gxbb-wdt"; ++ reg = <0x0 0xf0d0 0x0 0x10>; ++ clocks = <&xtal>; ++ }; ++ + spicc0: spi@13000 { + compatible = "amlogic,meson-g12a-spicc"; + reg = <0x0 0x13000 0x0 0x44>;