diff --git a/patch/kernel/archive/rk322x-5.15/board-rk322x-box.patch b/patch/kernel/archive/rk322x-5.15/board-rk322x-box.patch
index 693cd2ca11..812887bcd1 100644
--- a/patch/kernel/archive/rk322x-5.15/board-rk322x-box.patch
+++ b/patch/kernel/archive/rk322x-5.15/board-rk322x-box.patch
@@ -1,9 +1,9 @@
 diff --git a/arch/arm/boot/dts/rk322x-box.dts b/arch/arm/boot/dts/rk322x-box.dts
 new file mode 100644
-index 000000000000..f6e249bf81b6
+index 00000000000..a498bad3a4f
 --- /dev/null
 +++ b/arch/arm/boot/dts/rk322x-box.dts
-@@ -0,0 +1,753 @@
+@@ -0,0 +1,766 @@
 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 +
 +/dts-v1/;
@@ -741,6 +741,19 @@ index 000000000000..f6e249bf81b6
 +	rockchip,hw-tshut-mode = <0>;
 +	rockchip,hw-tshut-polarity = <1>;
 +	rockchip,hw-tshut-temp = <110000>;
++	
++	/* delete the pinctrl-* properties because, on mainline kernel, they (in particular "default")
++	   change the GPIO configuration of the associated PIN. On most boards that pin is not connected
++	   so it does not do anything, but some other boards (X96-Mini) have that pin connected to
++	   a reset pin of the soc or whatever, thus changing the configuration of the pin at boot 
++	   causes them to bootloop.
++	   We don't really need these ones though, because since hw-tshut-mode is set to 0, the CRU
++	   unit of the SoC does the reboot*/	
++	/delete-property/ pinctrl-names;
++	/delete-property/ pinctrl-0;
++	/delete-property/ pinctrl-1;
++	/delete-property/ pinctrl-2;
++
 +	status = "okay";
 +};
 +
diff --git a/patch/kernel/archive/rk322x-6.1/board-rk322x-box.patch b/patch/kernel/archive/rk322x-6.1/board-rk322x-box.patch
index 4df207b0dd..f262705dca 100644
--- a/patch/kernel/archive/rk322x-6.1/board-rk322x-box.patch
+++ b/patch/kernel/archive/rk322x-6.1/board-rk322x-box.patch
@@ -1,9 +1,9 @@
 diff --git a/arch/arm/boot/dts/rk322x-box.dts b/arch/arm/boot/dts/rk322x-box.dts
 new file mode 100644
-index 000000000000..f6e249bf81b6
+index 00000000000..a498bad3a4f
 --- /dev/null
 +++ b/arch/arm/boot/dts/rk322x-box.dts
-@@ -0,0 +1,753 @@
+@@ -0,0 +1,766 @@
 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 +
 +/dts-v1/;
@@ -741,6 +741,19 @@ index 000000000000..f6e249bf81b6
 +	rockchip,hw-tshut-mode = <0>;
 +	rockchip,hw-tshut-polarity = <1>;
 +	rockchip,hw-tshut-temp = <110000>;
++	
++	/* delete the pinctrl-* properties because, on mainline kernel, they (in particular "default")
++	   change the GPIO configuration of the associated PIN. On most boards that pin is not connected
++	   so it does not do anything, but some other boards (X96-Mini) have that pin connected to
++	   a reset pin of the soc or whatever, thus changing the configuration of the pin at boot 
++	   causes them to bootloop.
++	   We don't really need these ones though, because since hw-tshut-mode is set to 0, the CRU
++	   unit of the SoC does the reboot*/	
++	/delete-property/ pinctrl-names;
++	/delete-property/ pinctrl-0;
++	/delete-property/ pinctrl-1;
++	/delete-property/ pinctrl-2;
++
 +	status = "okay";
 +};
 +