From 23be92c454d797e26449288ca611cb912e403434 Mon Sep 17 00:00:00 2001 From: Muhammed Efe Cetin Date: Mon, 11 Sep 2023 20:59:52 +0300 Subject: [PATCH] Update rk3588-edge to 6.6-rc1 kernel --- .../kernel/linux-rockchip-rk3588-edge.config | 197 ++-- config/sources/families/rockchip-rk3588.conf | 4 +- .../0020-Add-RK3588-SATA-support.patch | 235 ----- .../0021-Add-RK3588-USB2-Support.patch | 962 ------------------ .../0022-RK3588-PCIe-support.patch | 779 -------------- 5 files changed, 130 insertions(+), 2047 deletions(-) delete mode 100644 patch/kernel/rockchip-rk3588-edge/0020-Add-RK3588-SATA-support.patch delete mode 100644 patch/kernel/rockchip-rk3588-edge/0021-Add-RK3588-USB2-Support.patch delete mode 100644 patch/kernel/rockchip-rk3588-edge/0022-RK3588-PCIe-support.patch diff --git a/config/kernel/linux-rockchip-rk3588-edge.config b/config/kernel/linux-rockchip-rk3588-edge.config index 5d66f3ec71..eecefcc35c 100644 --- a/config/kernel/linux-rockchip-rk3588-edge.config +++ b/config/kernel/linux-rockchip-rk3588-edge.config @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm64 6.5.0-rc5 Kernel Configuration +# Linux/arm64 6.6.0-rc1 Kernel Configuration # CONFIG_CC_VERSION_TEXT="aarch64-linux-gnu-gcc (Ubuntu 11.3.0-1ubuntu1~22.04) 11.3.0" CONFIG_CC_IS_GCC=y @@ -163,6 +163,7 @@ CONFIG_GENERIC_SCHED_CLOCK=y # end of Scheduler features CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y +CONFIG_ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH=y CONFIG_CC_HAS_INT128=y CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" CONFIG_GCC11_NO_ARRAY_BOUNDS=y @@ -256,7 +257,6 @@ CONFIG_KCMP=y CONFIG_RSEQ=y CONFIG_CACHESTAT_SYSCALL=y # CONFIG_DEBUG_RSEQ is not set -CONFIG_EMBEDDED=y CONFIG_HAVE_PERF_EVENTS=y CONFIG_GUEST_PERF_EVENTS=y # CONFIG_PC104 is not set @@ -271,6 +271,18 @@ CONFIG_PERF_EVENTS=y CONFIG_SYSTEM_DATA_VERIFICATION=y CONFIG_PROFILING=y CONFIG_TRACEPOINTS=y + +# +# Kexec and crash features +# +CONFIG_CRASH_CORE=y +CONFIG_KEXEC_CORE=y +CONFIG_HAVE_IMA_KEXEC=y +CONFIG_KEXEC=y +CONFIG_KEXEC_FILE=y +# CONFIG_KEXEC_SIG is not set +# CONFIG_CRASH_DUMP is not set +# end of Kexec and crash features # end of General setup CONFIG_ARM64=y @@ -292,7 +304,6 @@ CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CSUM=y CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y CONFIG_SMP=y CONFIG_KERNEL_MODE_NEON=y CONFIG_FIX_EARLYCON_MEM=y @@ -426,10 +437,13 @@ CONFIG_ARCH_SPARSEMEM_ENABLE=y CONFIG_HW_PERF_EVENTS=y CONFIG_PARAVIRT=y CONFIG_PARAVIRT_TIME_ACCOUNTING=y -CONFIG_KEXEC=y -CONFIG_KEXEC_FILE=y -# CONFIG_KEXEC_SIG is not set -# CONFIG_CRASH_DUMP is not set +CONFIG_ARCH_SUPPORTS_KEXEC=y +CONFIG_ARCH_SUPPORTS_KEXEC_FILE=y +CONFIG_ARCH_SELECTS_KEXEC_FILE=y +CONFIG_ARCH_SUPPORTS_KEXEC_SIG=y +CONFIG_ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG=y +CONFIG_ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG=y +CONFIG_ARCH_SUPPORTS_CRASH_DUMP=y CONFIG_TRANS_TABLE=y CONFIG_XEN_DOM0=y CONFIG_XEN=y @@ -452,7 +466,6 @@ CONFIG_SETEND_EMULATION=y # CONFIG_ARM64_HW_AFDBM=y CONFIG_ARM64_PAN=y -CONFIG_AS_HAS_LDAPR=y CONFIG_AS_HAS_LSE_ATOMICS=y CONFIG_ARM64_LSE_ATOMICS=y CONFIG_ARM64_USE_LSE_ATOMICS=y @@ -477,6 +490,7 @@ CONFIG_CC_HAS_BRANCH_PROT_PAC_RET=y CONFIG_CC_HAS_SIGN_RETURN_ADDRESS=y CONFIG_AS_HAS_ARMV8_3=y CONFIG_AS_HAS_CFI_NEGATE_RA_STATE=y +CONFIG_AS_HAS_LDAPR=y # end of ARMv8.3 architectural features # @@ -676,7 +690,6 @@ CONFIG_KVM_MMIO=y CONFIG_HAVE_KVM_MSI=y CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT=y CONFIG_KVM_VFIO=y -CONFIG_HAVE_KVM_ARCH_TLB_FLUSH_ALL=y CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y CONFIG_HAVE_KVM_IRQ_BYPASS=y CONFIG_HAVE_KVM_VCPU_RUN_PID_CHANGE=y @@ -689,9 +702,6 @@ CONFIG_KVM=y # # General architecture-dependent options # -CONFIG_CRASH_CORE=y -CONFIG_KEXEC_CORE=y -CONFIG_HAVE_IMA_KEXEC=y CONFIG_ARCH_HAS_SUBPAGE_FAULTS=y CONFIG_HOTPLUG_CORE_SYNC=y CONFIG_HOTPLUG_CORE_SYNC_DEAD=y @@ -761,6 +771,7 @@ CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y CONFIG_HAVE_ARCH_HUGE_VMAP=y CONFIG_HAVE_ARCH_HUGE_VMALLOC=y CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y +CONFIG_ARCH_WANT_PMD_MKWRITE=y CONFIG_HAVE_MOD_ARCH_SPECIFIC=y CONFIG_MODULES_USE_ELF_RELA=y CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK=y @@ -963,6 +974,7 @@ CONFIG_SLAB_FREELIST_RANDOM=y # CONFIG_SLAB_FREELIST_HARDENED is not set # CONFIG_SLUB_STATS is not set CONFIG_SLUB_CPU_PARTIAL=y +# CONFIG_RANDOM_KMALLOC_CACHES is not set # end of SLAB allocator options # CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set @@ -978,6 +990,7 @@ CONFIG_EXCLUSIVE_SYSTEM_RAM=y CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y # CONFIG_MEMORY_HOTPLUG is not set +CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y CONFIG_MEMORY_BALLOON=y @@ -1006,7 +1019,6 @@ CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y CONFIG_USE_PERCPU_NUMA_NODE_ID=y CONFIG_HAVE_SETUP_PER_CPU_AREA=y -CONFIG_FRONTSWAP=y CONFIG_CMA=y # CONFIG_CMA_DEBUG is not set # CONFIG_CMA_DEBUGFS is not set @@ -1031,6 +1043,7 @@ CONFIG_PERCPU_STATS=y # CONFIG_DMAPOOL_TEST is not set CONFIG_ARCH_HAS_PTE_SPECIAL=y CONFIG_MAPPING_DIRTY_HELPERS=y +CONFIG_MEMFD_CREATE=y CONFIG_SECRETMEM=y # CONFIG_ANON_VMA_NAME is not set # CONFIG_USERFAULTFD is not set @@ -1052,6 +1065,7 @@ CONFIG_NET=y CONFIG_COMPAT_NETLINK_MESSAGES=y CONFIG_NET_INGRESS=y CONFIG_NET_EGRESS=y +CONFIG_NET_XGRESS=y CONFIG_NET_REDIRECT=y CONFIG_SKB_EXTENSIONS=y @@ -2043,6 +2057,7 @@ CONFIG_PCI_IOV=y CONFIG_PCI_PRI=y CONFIG_PCI_PASID=y CONFIG_PCI_LABEL=y +# CONFIG_PCI_DYNAMIC_OF_NODES is not set # CONFIG_PCIE_BUS_TUNE_OFF is not set CONFIG_PCIE_BUS_DEFAULT=y # CONFIG_PCIE_BUS_SAFE is not set @@ -2168,12 +2183,14 @@ CONFIG_DEV_COREDUMP=y # CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set CONFIG_HMEM_REPORTING=y # CONFIG_TEST_ASYNC_DRIVER_PROBE is not set +# CONFIG_DM_KUNIT_TEST is not set CONFIG_SYS_HYPERVISOR=y CONFIG_GENERIC_CPU_AUTOPROBE=y CONFIG_GENERIC_CPU_VULNERABILITIES=y CONFIG_SOC_BUS=y CONFIG_REGMAP=y # CONFIG_REGMAP_KUNIT is not set +# CONFIG_REGMAP_BUILD is not set CONFIG_REGMAP_I2C=y CONFIG_REGMAP_SLIMBUS=m CONFIG_REGMAP_SPI=m @@ -2205,6 +2222,11 @@ CONFIG_MHI_BUS_PCI_GENERIC=m # CONFIG_MHI_BUS_EP is not set # end of Bus devices +# +# Cache Drivers +# +# end of Cache Drivers + CONFIG_CONNECTOR=m # @@ -2820,6 +2842,7 @@ CONFIG_ATA_GENERIC=y CONFIG_MD=y CONFIG_BLK_DEV_MD=y CONFIG_MD_AUTODETECT=y +CONFIG_MD_BITMAP_FILE=y CONFIG_MD_LINEAR=m CONFIG_MD_RAID0=m CONFIG_MD_RAID1=m @@ -2924,6 +2947,7 @@ CONFIG_AMT=m CONFIG_MACSEC=m CONFIG_NETCONSOLE=y CONFIG_NETCONSOLE_DYNAMIC=y +# CONFIG_NETCONSOLE_EXTENDED_LOG is not set CONFIG_NETPOLL=y CONFIG_NET_POLL_CONTROLLER=y CONFIG_TUN=m @@ -3172,7 +3196,7 @@ CONFIG_MLX5_ESWITCH=y CONFIG_MLX5_BRIDGE=y CONFIG_MLX5_CORE_EN_DCB=y # CONFIG_MLX5_CORE_IPOIB is not set -# CONFIG_MLX5_EN_MACSEC is not set +# CONFIG_MLX5_MACSEC is not set # CONFIG_MLX5_EN_IPSEC is not set # CONFIG_MLX5_EN_TLS is not set CONFIG_MLX5_SW_STEERING=y @@ -3336,9 +3360,11 @@ CONFIG_LXT_PHY=m CONFIG_LSI_ET1011C_PHY=m CONFIG_MARVELL_PHY=m CONFIG_MARVELL_10G_PHY=m +# CONFIG_MARVELL_88Q2XXX_PHY is not set CONFIG_MARVELL_88X2222_PHY=m CONFIG_MAXLINEAR_GPHY=m CONFIG_MEDIATEK_GE_PHY=m +# CONFIG_MEDIATEK_GE_SOC_PHY is not set CONFIG_MICREL_PHY=y # CONFIG_MICROCHIP_T1S_PHY is not set CONFIG_MICROCHIP_PHY=m @@ -3724,6 +3750,8 @@ CONFIG_MT76_SDIO=m CONFIG_MT76x02_LIB=m CONFIG_MT76x02_USB=m CONFIG_MT76_CONNAC_LIB=m +CONFIG_MT792x_LIB=m +CONFIG_MT792x_USB=m CONFIG_MT76x0_COMMON=m CONFIG_MT76x0U=m CONFIG_MT76x0E=m @@ -4144,6 +4172,7 @@ CONFIG_TOUCHSCREEN_ZFORCE=m CONFIG_TOUCHSCREEN_COLIBRI_VF50=m CONFIG_TOUCHSCREEN_ROHM_BU21023=m CONFIG_TOUCHSCREEN_IQS5XX=m +# CONFIG_TOUCHSCREEN_IQS7211 is not set CONFIG_TOUCHSCREEN_ZINITIX=m # CONFIG_TOUCHSCREEN_HIMAX_HX83112B is not set CONFIG_INPUT_MISC=y @@ -4212,8 +4241,6 @@ CONFIG_SERIO_ARC_PS2=m # CONFIG_SERIO_GPIO_PS2 is not set # CONFIG_USERIO is not set CONFIG_GAMEPORT=m -# CONFIG_GAMEPORT_NS558 is not set -# CONFIG_GAMEPORT_L4 is not set # CONFIG_GAMEPORT_EMU10K1 is not set # CONFIG_GAMEPORT_FM801 is not set # end of Hardware I/O ports @@ -4307,7 +4334,6 @@ CONFIG_SERIAL_MCTRL_GPIO=y CONFIG_SERIAL_NONSTANDARD=y CONFIG_MOXA_INTELLIO=m CONFIG_MOXA_SMARTIO=m -CONFIG_SYNCLINK_GT=m CONFIG_N_HDLC=m CONFIG_N_GSM=m CONFIG_NOZOMI=m @@ -4394,6 +4420,7 @@ CONFIG_I2C_DEMUX_PINCTRL=m CONFIG_I2C_MUX_MLXCPLD=m # end of Multiplexer I2C Chip support +# CONFIG_I2C_ATR is not set CONFIG_I2C_HELPER_AUTO=y CONFIG_I2C_SMBUS=m CONFIG_I2C_ALGOBIT=m @@ -4463,6 +4490,7 @@ CONFIG_I2C_TINY_USB=m # # Other I2C/SMBus bus drivers # +# CONFIG_I2C_MLXCPLD is not set CONFIG_I2C_CROS_EC_TUNNEL=y CONFIG_I2C_VIRTIO=m # end of I2C Hardware Bus support @@ -4565,6 +4593,7 @@ CONFIG_PTP_1588_CLOCK_INES=m CONFIG_PTP_1588_CLOCK_KVM=m CONFIG_PTP_1588_CLOCK_IDT82P33=m CONFIG_PTP_1588_CLOCK_IDTCM=m +# CONFIG_PTP_1588_CLOCK_MOCK is not set CONFIG_PTP_1588_CLOCK_OCP=m # end of PTP clock support @@ -4602,6 +4631,7 @@ CONFIG_GPIO_SYSFS=y CONFIG_GPIO_CDEV=y CONFIG_GPIO_CDEV_V1=y CONFIG_GPIO_GENERIC=y +CONFIG_GPIO_REGMAP=m CONFIG_GPIO_MAX730X=m CONFIG_GPIO_IDIO_16=m @@ -4635,6 +4665,7 @@ CONFIG_GPIO_AMD_FCH=m # CONFIG_GPIO_ADNP=m # CONFIG_GPIO_FXL6408 is not set +# CONFIG_GPIO_DS4520 is not set CONFIG_GPIO_GW_PLD=m CONFIG_GPIO_MAX7300=m CONFIG_GPIO_MAX732X=m @@ -4836,6 +4867,7 @@ CONFIG_SENSORS_G760A=m CONFIG_SENSORS_G762=m CONFIG_SENSORS_GPIO_FAN=m CONFIG_SENSORS_HIH6130=m +# CONFIG_SENSORS_HS3001 is not set CONFIG_SENSORS_IBMAEM=m CONFIG_SENSORS_IBMPEX=m CONFIG_SENSORS_IIO_HWMON=m @@ -4981,7 +5013,6 @@ CONFIG_SENSORS_SCH56XX_COMMON=m CONFIG_SENSORS_SCH5627=m CONFIG_SENSORS_SCH5636=m CONFIG_SENSORS_STTS751=m -CONFIG_SENSORS_SMM665=m CONFIG_SENSORS_ADC128D818=m CONFIG_SENSORS_ADS7828=m CONFIG_SENSORS_ADS7871=m @@ -5129,6 +5160,8 @@ CONFIG_MFD_CORE=y # CONFIG_MFD_BD9571MWV is not set # CONFIG_MFD_AXP20X_I2C is not set CONFIG_MFD_CROS_EC_DEV=y +# CONFIG_MFD_CS42L43_I2C is not set +# CONFIG_MFD_CS42L43_SDW is not set # CONFIG_MFD_MADERA is not set # CONFIG_MFD_MAX5970 is not set # CONFIG_PMIC_DA903X is not set @@ -5182,7 +5215,7 @@ CONFIG_MFD_RDC321X=m # CONFIG_MFD_RT5033 is not set # CONFIG_MFD_RT5120 is not set # CONFIG_MFD_RC5T583 is not set -CONFIG_MFD_RK8XX=y +CONFIG_MFD_RK8XX=m CONFIG_MFD_RK8XX_I2C=m CONFIG_MFD_RK8XX_SPI=m # CONFIG_MFD_RN5T618 is not set @@ -5254,6 +5287,7 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_ACT8865=y # CONFIG_REGULATOR_AD5398 is not set # CONFIG_REGULATOR_ARM_SCMI is not set +# CONFIG_REGULATOR_AW37503 is not set # CONFIG_REGULATOR_CROS_EC is not set # CONFIG_REGULATOR_DA9121 is not set # CONFIG_REGULATOR_DA9210 is not set @@ -5270,6 +5304,7 @@ CONFIG_REGULATOR_GPIO=y # CONFIG_REGULATOR_LTC3589 is not set # CONFIG_REGULATOR_LTC3676 is not set # CONFIG_REGULATOR_MAX1586 is not set +# CONFIG_REGULATOR_MAX77857 is not set # CONFIG_REGULATOR_MAX8649 is not set # CONFIG_REGULATOR_MAX8660 is not set CONFIG_REGULATOR_MAX8893=m @@ -5297,7 +5332,7 @@ CONFIG_REGULATOR_QCOM_SPMI=y # CONFIG_REGULATOR_QCOM_USB_VBUS is not set # CONFIG_REGULATOR_RAA215300 is not set # CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set -CONFIG_REGULATOR_RK808=y +CONFIG_REGULATOR_RK808=m # CONFIG_REGULATOR_RT4801 is not set # CONFIG_REGULATOR_RT4803 is not set # CONFIG_REGULATOR_RT5190A is not set @@ -5309,6 +5344,7 @@ CONFIG_REGULATOR_RT6245=m CONFIG_REGULATOR_RTQ2134=m # CONFIG_REGULATOR_RTMV20 is not set CONFIG_REGULATOR_RTQ6752=m +# CONFIG_REGULATOR_RTQ2208 is not set CONFIG_REGULATOR_SLG51000=m # CONFIG_REGULATOR_SY8106A is not set CONFIG_REGULATOR_SY8824X=m @@ -5414,8 +5450,8 @@ CONFIG_V4L2_MEM2MEM_DEV=m CONFIG_V4L2_FLASH_LED_CLASS=m CONFIG_V4L2_FWNODE=m CONFIG_V4L2_ASYNC=m -CONFIG_VIDEOBUF_GEN=m -CONFIG_VIDEOBUF_DMA_SG=m +CONFIG_V4L2_CCI=m +CONFIG_V4L2_CCI_I2C=m # end of Video4Linux options # @@ -5853,10 +5889,7 @@ CONFIG_MEDIA_ATTACH=y # IR I2C driver auto-selected by 'Autoselect ancillary drivers' # CONFIG_VIDEO_IR_I2C=m - -# -# Camera sensor devices -# +CONFIG_VIDEO_CAMERA_SENSOR=y CONFIG_VIDEO_APTINA_PLL=m CONFIG_VIDEO_CCS_PLL=m # CONFIG_VIDEO_AR0521 is not set @@ -5927,7 +5960,6 @@ CONFIG_VIDEO_S5K6A3=m # CONFIG_VIDEO_ST_VGXY61 is not set CONFIG_VIDEO_CCS=m CONFIG_VIDEO_ET8EK8=m -# end of Camera sensor devices # # Lens drivers @@ -5935,6 +5967,7 @@ CONFIG_VIDEO_ET8EK8=m CONFIG_VIDEO_AD5820=m CONFIG_VIDEO_AK7375=m CONFIG_VIDEO_DW9714=m +# CONFIG_VIDEO_DW9719 is not set CONFIG_VIDEO_DW9768=m CONFIG_VIDEO_DW9807_VCM=m # end of Lens drivers @@ -6053,6 +6086,14 @@ CONFIG_VIDEO_ST_MIPID02=m CONFIG_VIDEO_THS7303=m # end of Miscellaneous helper chips +# +# Video serializers and deserializers +# +# CONFIG_VIDEO_DS90UB913 is not set +# CONFIG_VIDEO_DS90UB953 is not set +# CONFIG_VIDEO_DS90UB960 is not set +# end of Video serializers and deserializers + # # Media SPI Adapters # @@ -6281,6 +6322,7 @@ CONFIG_DVB_DUMMY_FE=m CONFIG_APERTURE_HELPERS=y CONFIG_VIDEO_CMDLINE=y CONFIG_VIDEO_NOMODESET=y +# CONFIG_AUXDISPLAY is not set CONFIG_DRM=m CONFIG_DRM_MIPI_DBI=m CONFIG_DRM_MIPI_DSI=y @@ -6301,6 +6343,8 @@ CONFIG_DRM_DISPLAY_HDMI_HELPER=y # CONFIG_DRM_DP_AUX_CHARDEV is not set CONFIG_DRM_DP_CEC=y CONFIG_DRM_TTM=m +# CONFIG_DRM_TTM_KUNIT_TEST is not set +CONFIG_DRM_EXEC=m CONFIG_DRM_BUDDY=m CONFIG_DRM_VRAM_HELPER=m CONFIG_DRM_TTM_HELPER=m @@ -6427,6 +6471,7 @@ CONFIG_DRM_PANEL_SITRONIX_ST7701=m CONFIG_DRM_PANEL_SONY_ACX565AKM=m # CONFIG_DRM_PANEL_SONY_TD4353_JDI is not set # CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521 is not set +# CONFIG_DRM_PANEL_STARTEK_KD070FHFID015 is not set CONFIG_DRM_PANEL_TDO_TL070WSH30=m CONFIG_DRM_PANEL_TPO_TD028TTEC1=m CONFIG_DRM_PANEL_TPO_TD043MTEA1=m @@ -6434,6 +6479,7 @@ CONFIG_DRM_PANEL_TPO_TPG110=m CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m # CONFIG_DRM_PANEL_VISIONOX_RM69299 is not set # CONFIG_DRM_PANEL_VISIONOX_VTDR6130 is not set +# CONFIG_DRM_PANEL_VISIONOX_R66451 is not set CONFIG_DRM_PANEL_WIDECHIPS_WS2401=m CONFIG_DRM_PANEL_XINPENG_XPP055C272=m # end of Display Panels @@ -6494,6 +6540,7 @@ CONFIG_DRM_DW_HDMI_CEC=m CONFIG_DRM_DW_MIPI_DSI=m # end of Display Interface Bridges +# CONFIG_DRM_LOONGSON is not set CONFIG_DRM_ETNAVIV=m CONFIG_DRM_ETNAVIV_THERMAL=y CONFIG_DRM_HISI_HIBMC=m @@ -6532,27 +6579,7 @@ CONFIG_DRM_LIB_RANDOM=y # # Frame buffer Devices # -CONFIG_FB_NOTIFY=y CONFIG_FB=y -CONFIG_FIRMWARE_EDID=y -CONFIG_FB_CFB_FILLRECT=y -CONFIG_FB_CFB_COPYAREA=y -CONFIG_FB_CFB_IMAGEBLIT=y -CONFIG_FB_SYS_FILLRECT=y -CONFIG_FB_SYS_COPYAREA=y -CONFIG_FB_SYS_IMAGEBLIT=y -# CONFIG_FB_FOREIGN_ENDIAN is not set -CONFIG_FB_SYS_FOPS=y -CONFIG_FB_DEFERRED_IO=y -CONFIG_FB_SYS_HELPERS=y -CONFIG_FB_SYS_HELPERS_DEFERRED=y -CONFIG_FB_BACKLIGHT=m -CONFIG_FB_MODE_HELPERS=y -CONFIG_FB_TILEBLITTING=y - -# -# Frame buffer hardware drivers -# # CONFIG_FB_CIRRUS is not set # CONFIG_FB_PM2 is not set CONFIG_FB_ARMCLCD=y @@ -6592,6 +6619,26 @@ CONFIG_XEN_FBDEV_FRONTEND=y CONFIG_FB_SIMPLE=m CONFIG_FB_SSD1307=m # CONFIG_FB_SM712 is not set +CONFIG_FB_CORE=y +CONFIG_FB_NOTIFY=y +CONFIG_FIRMWARE_EDID=y +CONFIG_FB_DEVICE=y +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +CONFIG_FB_SYS_FILLRECT=y +CONFIG_FB_SYS_COPYAREA=y +CONFIG_FB_SYS_IMAGEBLIT=y +# CONFIG_FB_FOREIGN_ENDIAN is not set +CONFIG_FB_SYS_FOPS=y +CONFIG_FB_DEFERRED_IO=y +CONFIG_FB_DMAMEM_HELPERS=y +CONFIG_FB_IOMEM_HELPERS=y +CONFIG_FB_SYSMEM_HELPERS=y +CONFIG_FB_SYSMEM_HELPERS_DEFERRED=y +CONFIG_FB_BACKLIGHT=m +CONFIG_FB_MODE_HELPERS=y +CONFIG_FB_TILEBLITTING=y # end of Frame buffer Devices # @@ -6788,6 +6835,9 @@ CONFIG_SND_HDA_SCODEC_CS35L41=m CONFIG_SND_HDA_CS_DSP_CONTROLS=m CONFIG_SND_HDA_SCODEC_CS35L41_I2C=m CONFIG_SND_HDA_SCODEC_CS35L41_SPI=m +# CONFIG_SND_HDA_SCODEC_CS35L56_I2C is not set +# CONFIG_SND_HDA_SCODEC_CS35L56_SPI is not set +# CONFIG_SND_HDA_SCODEC_TAS2781_I2C is not set CONFIG_SND_HDA_CODEC_REALTEK=m CONFIG_SND_HDA_CODEC_ANALOG=m CONFIG_SND_HDA_CODEC_SIGMATEL=m @@ -6834,6 +6884,7 @@ CONFIG_SND_SOC=m CONFIG_SND_SOC_AC97_BUS=y CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y CONFIG_SND_SOC_COMPRESS=y +# CONFIG_SND_SOC_TOPOLOGY_BUILD is not set CONFIG_SND_SOC_UTILS_KUNIT_TEST=m CONFIG_SND_SOC_ACPI=m CONFIG_SND_SOC_ADI=m @@ -6937,8 +6988,10 @@ CONFIG_SND_SOC_AK4642=m CONFIG_SND_SOC_AK5386=m CONFIG_SND_SOC_AK5558=m CONFIG_SND_SOC_ALC5623=m +# CONFIG_SND_SOC_AUDIO_IIO_AUX is not set CONFIG_SND_SOC_AW8738=m # CONFIG_SND_SOC_AW88395 is not set +# CONFIG_SND_SOC_AW88261 is not set CONFIG_SND_SOC_BD28623=m CONFIG_SND_SOC_BT_SCO=m # CONFIG_SND_SOC_CHV3_CODEC is not set @@ -7036,6 +7089,7 @@ CONFIG_SND_SOC_PCM512x_SPI=m CONFIG_SND_SOC_RK3328=m # CONFIG_SND_SOC_RK817 is not set CONFIG_SND_SOC_RL6231=m +# CONFIG_SND_SOC_RT1017_SDCA_SDW is not set CONFIG_SND_SOC_RT1308_SDW=m CONFIG_SND_SOC_RT1316_SDW=m # CONFIG_SND_SOC_RT1318_SDW is not set @@ -7112,6 +7166,7 @@ CONFIG_SND_SOC_TS3A227E=m CONFIG_SND_SOC_TSCS42XX=m CONFIG_SND_SOC_TSCS454=m CONFIG_SND_SOC_UDA1334=m +CONFIG_SND_SOC_WCD_CLASSH=m CONFIG_SND_SOC_WCD9335=m CONFIG_SND_SOC_WCD_MBHC=m CONFIG_SND_SOC_WCD938X=m @@ -7223,6 +7278,7 @@ CONFIG_HID_HOLTEK=m CONFIG_HOLTEK_FF=y CONFIG_HID_VIVALDI_COMMON=m CONFIG_HID_GOOGLE_HAMMER=m +# CONFIG_HID_GOOGLE_STADIA_FF is not set CONFIG_HID_VIVALDI=m CONFIG_HID_GT683R=m CONFIG_HID_KEYTOUCH=m @@ -7676,6 +7732,7 @@ CONFIG_USB_CONFIGFS_F_UAC1=y CONFIG_USB_CONFIGFS_F_UAC1_LEGACY=y CONFIG_USB_CONFIGFS_F_UAC2=y CONFIG_USB_CONFIGFS_F_MIDI=y +# CONFIG_USB_CONFIGFS_F_MIDI2 is not set CONFIG_USB_CONFIGFS_F_HID=y CONFIG_USB_CONFIGFS_F_UVC=y CONFIG_USB_CONFIGFS_F_PRINTER=y @@ -7805,7 +7862,6 @@ CONFIG_MMC_SDHCI_EXTERNAL_DMA=y # CONFIG_MMC_LITEX is not set CONFIG_SCSI_UFSHCD=y # CONFIG_SCSI_UFS_BSG is not set -CONFIG_SCSI_UFS_HPB=y CONFIG_SCSI_UFS_HWMON=y CONFIG_SCSI_UFSHCD_PCI=m # CONFIG_SCSI_UFS_DWC_TC_PCI is not set @@ -7842,6 +7898,7 @@ CONFIG_LEDS_GPIO=y # CONFIG_LEDS_LP8860 is not set # CONFIG_LEDS_PCA955X is not set # CONFIG_LEDS_PCA963X is not set +# CONFIG_LEDS_PCA995X is not set # CONFIG_LEDS_DAC124S085 is not set CONFIG_LEDS_PWM=m CONFIG_LEDS_REGULATOR=m @@ -7950,7 +8007,7 @@ CONFIG_RTC_INTF_DEV=y CONFIG_RTC_DRV_HYM8563=y # CONFIG_RTC_DRV_MAX6900 is not set # CONFIG_RTC_DRV_NCT3018Y is not set -CONFIG_RTC_DRV_RK808=y +CONFIG_RTC_DRV_RK808=m # CONFIG_RTC_DRV_RS5C372 is not set # CONFIG_RTC_DRV_ISL1208 is not set # CONFIG_RTC_DRV_ISL12022 is not set @@ -8016,7 +8073,6 @@ CONFIG_RTC_I2C_AND_SPI=y # CONFIG_RTC_DRV_M48T35 is not set # CONFIG_RTC_DRV_M48T59 is not set # CONFIG_RTC_DRV_MSM6242 is not set -# CONFIG_RTC_DRV_BQ4802 is not set # CONFIG_RTC_DRV_RP5C01 is not set CONFIG_RTC_DRV_OPTEE=m # CONFIG_RTC_DRV_ZYNQMP is not set @@ -8093,7 +8149,6 @@ CONFIG_DMABUF_HEAPS_SYSTEM=y CONFIG_DMABUF_HEAPS_CMA=y # end of DMABUF options -# CONFIG_AUXDISPLAY is not set CONFIG_UIO=m CONFIG_UIO_CIF=m # CONFIG_UIO_PDRV_GENIRQ is not set @@ -8105,6 +8160,7 @@ CONFIG_UIO_PCI_GENERIC=m # CONFIG_UIO_PRUSS is not set # CONFIG_UIO_MF624 is not set CONFIG_VFIO=y +CONFIG_VFIO_GROUP=y CONFIG_VFIO_CONTAINER=y CONFIG_VFIO_IOMMU_TYPE1=y # CONFIG_VFIO_NOIOMMU is not set @@ -8361,7 +8417,7 @@ CONFIG_COMMON_CLK=y # CONFIG_LMK04832 is not set # CONFIG_COMMON_CLK_MAX9485 is not set -CONFIG_COMMON_CLK_RK808=y +CONFIG_COMMON_CLK_RK808=m CONFIG_COMMON_CLK_SCMI=y # CONFIG_COMMON_CLK_SCPI is not set # CONFIG_COMMON_CLK_SI5341 is not set @@ -8377,6 +8433,7 @@ CONFIG_COMMON_CLK_SCMI=y CONFIG_COMMON_CLK_PWM=y # CONFIG_COMMON_CLK_RS9_PCIE is not set # CONFIG_COMMON_CLK_SI521XX is not set +# CONFIG_COMMON_CLK_VC3 is not set # CONFIG_COMMON_CLK_VC5 is not set # CONFIG_COMMON_CLK_VC7 is not set # CONFIG_COMMON_CLK_FIXED_MMIO is not set @@ -8847,6 +8904,7 @@ CONFIG_LTC1660=m # CONFIG_MAX5522 is not set # CONFIG_MAX5821 is not set # CONFIG_MCP4725 is not set +# CONFIG_MCP4728 is not set # CONFIG_MCP4922 is not set # CONFIG_TI_DAC082S085 is not set CONFIG_TI_DAC5571=m @@ -9148,6 +9206,7 @@ CONFIG_MPL3115=m # Proximity and distance sensors # CONFIG_CROS_EC_MKBP_PROXIMITY=m +# CONFIG_IRSD200 is not set CONFIG_ISL29501=m # CONFIG_LIDAR_LITE_V2 is not set CONFIG_MB1232=m @@ -9251,6 +9310,8 @@ CONFIG_PHY_MAPPHONE_MDM6600=m # CONFIG_PHY_OCELOT_SERDES is not set CONFIG_PHY_QCOM_USB_HS=y CONFIG_PHY_QCOM_USB_HSIC=y +# CONFIG_PHY_RTK_RTD_USB2PHY is not set +# CONFIG_PHY_RTK_RTD_USB3PHY is not set CONFIG_PHY_ROCKCHIP_DP=y CONFIG_PHY_ROCKCHIP_DPHY_RX0=m CONFIG_PHY_ROCKCHIP_EMMC=y @@ -9384,6 +9445,7 @@ CONFIG_MOST_SND=m CONFIG_DCACHE_WORD_ACCESS=y CONFIG_VALIDATE_FS_PARSER=y CONFIG_FS_IOMAP=y +CONFIG_BUFFER_HEAD=y CONFIG_LEGACY_DIRECT_IO=y CONFIG_EXT2_FS=y CONFIG_EXT2_FS_XATTR=y @@ -9482,6 +9544,7 @@ CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y # CONFIG_OVERLAY_FS_INDEX is not set CONFIG_OVERLAY_FS_XINO_AUTO=y # CONFIG_OVERLAY_FS_METACOPY is not set +# CONFIG_OVERLAY_FS_DEBUG is not set # # Caches @@ -9540,10 +9603,10 @@ CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y CONFIG_TMPFS_XATTR=y # CONFIG_TMPFS_INODE64 is not set +# CONFIG_TMPFS_QUOTA is not set CONFIG_ARCH_SUPPORTS_HUGETLBFS=y CONFIG_HUGETLBFS=y CONFIG_HUGETLB_PAGE=y -CONFIG_MEMFD_CREATE=y CONFIG_ARCH_HAS_GIGANTIC_PAGE=y CONFIG_CONFIGFS_FS=y CONFIG_EFIVAR_FS=y @@ -9622,16 +9685,7 @@ CONFIG_ROMFS_BACKED_BY_BLOCK=y CONFIG_ROMFS_ON_BLOCK=y CONFIG_PSTORE=y CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240 -CONFIG_PSTORE_DEFLATE_COMPRESS=y -# CONFIG_PSTORE_LZO_COMPRESS is not set -# CONFIG_PSTORE_LZ4_COMPRESS is not set -CONFIG_PSTORE_LZ4HC_COMPRESS=m -# CONFIG_PSTORE_842_COMPRESS is not set -# CONFIG_PSTORE_ZSTD_COMPRESS is not set CONFIG_PSTORE_COMPRESS=y -CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y -# CONFIG_PSTORE_LZ4HC_COMPRESS_DEFAULT is not set -CONFIG_PSTORE_COMPRESS_DEFAULT="deflate" # CONFIG_PSTORE_CONSOLE is not set # CONFIG_PSTORE_PMSG is not set CONFIG_PSTORE_RAM=m @@ -9692,8 +9746,6 @@ CONFIG_SUNRPC_GSS=m CONFIG_SUNRPC_BACKCHANNEL=y CONFIG_SUNRPC_SWAP=y CONFIG_RPCSEC_GSS_KRB5=m -CONFIG_RPCSEC_GSS_KRB5_CRYPTOSYSTEM=y -# CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_DES is not set CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_AES_SHA1=y # CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_CAMELLIA is not set # CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_AES_SHA2 is not set @@ -9779,6 +9831,7 @@ CONFIG_NLS_MAC_INUIT=m CONFIG_NLS_MAC_ROMANIAN=m CONFIG_NLS_MAC_TURKISH=m CONFIG_NLS_UTF8=m +CONFIG_NLS_UCS2_UTILS=m CONFIG_DLM=m # CONFIG_DLM_DEBUG is not set CONFIG_UNICODE=y @@ -9814,6 +9867,7 @@ CONFIG_SECURITY_SELINUX_DEVELOP=y CONFIG_SECURITY_SELINUX_AVC_STATS=y CONFIG_SECURITY_SELINUX_SIDTAB_HASH_BITS=9 CONFIG_SECURITY_SELINUX_SID2STR_CACHE_SIZE=256 +# CONFIG_SECURITY_SELINUX_DEBUG is not set CONFIG_SECURITY_SMACK=y # CONFIG_SECURITY_SMACK_BRINGUP is not set CONFIG_SECURITY_SMACK_NETFILTER=y @@ -9864,10 +9918,7 @@ CONFIG_IMA_APPRAISE=y # CONFIG_IMA_APPRAISE_BUILD_POLICY is not set CONFIG_IMA_APPRAISE_BOOTPARAM=y # CONFIG_IMA_APPRAISE_MODSIG is not set -CONFIG_IMA_TRUSTED_KEYRING=y # CONFIG_IMA_KEYRINGS_PERMIT_SIGNED_BY_BUILTIN_OR_SECONDARY is not set -# CONFIG_IMA_BLACKLIST_KEYRING is not set -# CONFIG_IMA_LOAD_X509 is not set CONFIG_IMA_MEASURE_ASYMMETRIC_KEYS=y CONFIG_IMA_QUEUE_EARLY_BOOT_KEYS=y # CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT is not set @@ -9898,6 +9949,13 @@ CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y # CONFIG_ZERO_CALL_USED_REGS is not set # end of Memory initialization +# +# Hardening of kernel data structures +# +# CONFIG_LIST_HARDENED is not set +# CONFIG_BUG_ON_DATA_CORRUPTION is not set +# end of Hardening of kernel data structures + CONFIG_RANDSTRUCT_NONE=y # end of Kernel hardening options # end of Security options @@ -10299,13 +10357,14 @@ CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y CONFIG_SWIOTLB=y +# CONFIG_SWIOTLB_DYNAMIC is not set CONFIG_DMA_BOUNCE_UNALIGNED_KMALLOC=y CONFIG_DMA_RESTRICTED_POOL=y CONFIG_DMA_NONCOHERENT_MMAP=y CONFIG_DMA_COHERENT_POOL=y CONFIG_DMA_DIRECT_REMAP=y CONFIG_DMA_CMA=y -CONFIG_DMA_PERNUMA_CMA=y +# CONFIG_DMA_NUMA_CMA is not set # # Default contiguous memory area size: @@ -10540,7 +10599,6 @@ CONFIG_STACKTRACE=y # CONFIG_DEBUG_PLIST is not set # CONFIG_DEBUG_SG is not set # CONFIG_DEBUG_NOTIFIERS is not set -# CONFIG_BUG_ON_DATA_CORRUPTION is not set # CONFIG_DEBUG_MAPLE_TREE is not set # end of Debug kernel data structures @@ -10649,6 +10707,7 @@ CONFIG_RUNTIME_TESTING_MENU=y CONFIG_TEST_MIN_HEAP=m # CONFIG_TEST_SORT is not set CONFIG_TEST_DIV64=m +# CONFIG_TEST_IOV_ITER is not set # CONFIG_KPROBES_SANITY_TEST is not set CONFIG_BACKTRACE_SELF_TEST=m # CONFIG_TEST_REF_TRACKER is not set diff --git a/config/sources/families/rockchip-rk3588.conf b/config/sources/families/rockchip-rk3588.conf index b82dd1e7ee..3006a436eb 100644 --- a/config/sources/families/rockchip-rk3588.conf +++ b/config/sources/families/rockchip-rk3588.conf @@ -33,8 +33,8 @@ case $BRANCH in SKIP_BOOTSPLASH="yes" LINUXFAMILY=rockchip-rk3588 LINUXCONFIG='linux-rockchip-rk3588-'$BRANCH - KERNEL_MAJOR_MINOR="6.5" # Major and minor versions of this kernel. - KERNELBRANCH='tag:v6.5-rc5' + KERNEL_MAJOR_MINOR="6.6" # Major and minor versions of this kernel. + KERNELBRANCH='tag:v6.6-rc1' KERNELPATCHDIR='rockchip-rk3588-edge' ;; diff --git a/patch/kernel/rockchip-rk3588-edge/0020-Add-RK3588-SATA-support.patch b/patch/kernel/rockchip-rk3588-edge/0020-Add-RK3588-SATA-support.patch deleted file mode 100644 index aef07c3a9e..0000000000 --- a/patch/kernel/rockchip-rk3588-edge/0020-Add-RK3588-SATA-support.patch +++ /dev/null @@ -1,235 +0,0 @@ -From 247de7bf585066872070164e33bfc17802af72ac Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Mon, 12 Jun 2023 19:13:36 +0200 -Subject: [PATCH 1/2] arm64: dts: rockchip: add combo PHYs to rk3588 - -Add all 3 combo PHYs that can be found in RK3588. -They are used for SATA, PCIe or USB3. - -Signed-off-by: Sebastian Reichel -Link: https://lore.kernel.org/r/20230612171337.74576-5-sebastian.reichel@collabora.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3588.dtsi | 21 ++++++++++++ - arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 42 +++++++++++++++++++++++ - 2 files changed, 63 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi -index 8be75556af8f..5a5fe3acf3e9 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi -@@ -7,6 +7,11 @@ - #include "rk3588-pinctrl.dtsi" - - / { -+ pipe_phy1_grf: syscon@fd5c0000 { -+ compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; -+ reg = <0x0 0xfd5c0000 0x0 0x100>; -+ }; -+ - i2s8_8ch: i2s@fddc8000 { - compatible = "rockchip,rk3588-i2s-tdm"; - reg = <0x0 0xfddc8000 0x0 0x1000>; -@@ -123,4 +128,20 @@ gmac0_mtl_tx_setup: tx-queues-config { - queue1 {}; - }; - }; -+ -+ combphy1_ps: phy@fee10000 { -+ compatible = "rockchip,rk3588-naneng-combphy"; -+ reg = <0x0 0xfee10000 0x0 0x100>; -+ clocks = <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>, -+ <&cru PCLK_PHP_ROOT>; -+ clock-names = "ref", "apb", "pipe"; -+ assigned-clocks = <&cru CLK_REF_PIPE_PHY1>; -+ assigned-clock-rates = <100000000>; -+ #phy-cells = <1>; -+ resets = <&cru SRST_REF_PIPE_PHY1>, <&cru SRST_P_PCIE2_PHY1>; -+ reset-names = "phy", "apb"; -+ rockchip,pipe-grf = <&php_grf>; -+ rockchip,pipe-phy-grf = <&pipe_phy1_grf>; -+ status = "disabled"; -+ }; - }; -diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -index 1576f9bfd6de..fce1ebe42423 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -@@ -407,6 +407,16 @@ php_grf: syscon@fd5b0000 { - reg = <0x0 0xfd5b0000 0x0 0x1000>; - }; - -+ pipe_phy0_grf: syscon@fd5bc000 { -+ compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; -+ reg = <0x0 0xfd5bc000 0x0 0x100>; -+ }; -+ -+ pipe_phy2_grf: syscon@fd5c4000 { -+ compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; -+ reg = <0x0 0xfd5c4000 0x0 0x100>; -+ }; -+ - ioc: syscon@fd5f0000 { - compatible = "rockchip,rk3588-ioc", "syscon"; - reg = <0x0 0xfd5f0000 0x0 0x10000>; -@@ -1943,6 +1953,38 @@ dmac2: dma-controller@fed10000 { - #dma-cells = <1>; - }; - -+ combphy0_ps: phy@fee00000 { -+ compatible = "rockchip,rk3588-naneng-combphy"; -+ reg = <0x0 0xfee00000 0x0 0x100>; -+ clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>, -+ <&cru PCLK_PHP_ROOT>; -+ clock-names = "ref", "apb", "pipe"; -+ assigned-clocks = <&cru CLK_REF_PIPE_PHY0>; -+ assigned-clock-rates = <100000000>; -+ #phy-cells = <1>; -+ resets = <&cru SRST_REF_PIPE_PHY0>, <&cru SRST_P_PCIE2_PHY0>; -+ reset-names = "phy", "apb"; -+ rockchip,pipe-grf = <&php_grf>; -+ rockchip,pipe-phy-grf = <&pipe_phy0_grf>; -+ status = "disabled"; -+ }; -+ -+ combphy2_psu: phy@fee20000 { -+ compatible = "rockchip,rk3588-naneng-combphy"; -+ reg = <0x0 0xfee20000 0x0 0x100>; -+ clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>, -+ <&cru PCLK_PHP_ROOT>; -+ clock-names = "ref", "apb", "pipe"; -+ assigned-clocks = <&cru CLK_REF_PIPE_PHY2>; -+ assigned-clock-rates = <100000000>; -+ #phy-cells = <1>; -+ resets = <&cru SRST_REF_PIPE_PHY2>, <&cru SRST_P_PCIE2_PHY2>; -+ reset-names = "phy", "apb"; -+ rockchip,pipe-grf = <&php_grf>; -+ rockchip,pipe-phy-grf = <&pipe_phy2_grf>; -+ status = "disabled"; -+ }; -+ - system_sram2: sram@ff001000 { - compatible = "mmio-sram"; - reg = <0x0 0xff001000 0x0 0xef000>; --- -2.41.0 - - -From 43010bf5cb5d3270b73e37d08a2bd5c60558bc3e Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Mon, 12 Jun 2023 19:13:37 +0200 -Subject: [PATCH 2/2] arm64: dts: rockchip: add SATA support to rk3588 - -Add all three SATA IP blocks to the RK3588 DT. - -Signed-off-by: Sebastian Reichel -Link: https://lore.kernel.org/r/20230612171337.74576-6-sebastian.reichel@collabora.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3588.dtsi | 23 +++++++++++ - arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 48 +++++++++++++++++++++++ - 2 files changed, 71 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi -index 5a5fe3acf3e9..6be9bf81c09c 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi -@@ -129,6 +129,29 @@ gmac0_mtl_tx_setup: tx-queues-config { - }; - }; - -+ sata1: sata@fe220000 { -+ compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; -+ reg = <0 0xfe220000 0 0x1000>; -+ interrupts = ; -+ clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>, -+ <&cru CLK_RXOOB1>, <&cru CLK_PIPEPHY1_REF>, -+ <&cru CLK_PIPEPHY1_PIPE_ASIC_G>; -+ clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; -+ ports-implemented = <0x1>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ sata-port@0 { -+ reg = <0>; -+ hba-port-cap = ; -+ phys = <&combphy1_ps PHY_TYPE_SATA>; -+ phy-names = "sata-phy"; -+ snps,rx-ts-max = <32>; -+ snps,tx-ts-max = <32>; -+ }; -+ }; -+ - combphy1_ps: phy@fee10000 { - compatible = "rockchip,rk3588-naneng-combphy"; - reg = <0x0 0xfee10000 0x0 0x100>; -diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -index fce1ebe42423..8243e52bce59 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -@@ -8,6 +8,8 @@ - #include - #include - #include -+#include -+#include - - / { - compatible = "rockchip,rk3588"; -@@ -1180,6 +1182,52 @@ gmac1_mtl_tx_setup: tx-queues-config { - }; - }; - -+ sata0: sata@fe210000 { -+ compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; -+ reg = <0 0xfe210000 0 0x1000>; -+ interrupts = ; -+ clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>, -+ <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>, -+ <&cru CLK_PIPEPHY0_PIPE_ASIC_G>; -+ clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; -+ ports-implemented = <0x1>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ sata-port@0 { -+ reg = <0>; -+ hba-port-cap = ; -+ phys = <&combphy0_ps PHY_TYPE_SATA>; -+ phy-names = "sata-phy"; -+ snps,rx-ts-max = <32>; -+ snps,tx-ts-max = <32>; -+ }; -+ }; -+ -+ sata2: sata@fe230000 { -+ compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; -+ reg = <0 0xfe230000 0 0x1000>; -+ interrupts = ; -+ clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>, -+ <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>, -+ <&cru CLK_PIPEPHY2_PIPE_ASIC_G>; -+ clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; -+ ports-implemented = <0x1>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ sata-port@0 { -+ reg = <0>; -+ hba-port-cap = ; -+ phys = <&combphy2_psu PHY_TYPE_SATA>; -+ phy-names = "sata-phy"; -+ snps,rx-ts-max = <32>; -+ snps,tx-ts-max = <32>; -+ }; -+ }; -+ - sdmmc: mmc@fe2c0000 { - compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xfe2c0000 0x0 0x4000>; --- -2.41.0 - diff --git a/patch/kernel/rockchip-rk3588-edge/0021-Add-RK3588-USB2-Support.patch b/patch/kernel/rockchip-rk3588-edge/0021-Add-RK3588-USB2-Support.patch deleted file mode 100644 index 0a8b3abf43..0000000000 --- a/patch/kernel/rockchip-rk3588-edge/0021-Add-RK3588-USB2-Support.patch +++ /dev/null @@ -1,962 +0,0 @@ -From a88864d5e1cf0a634162ac76a5392be6595521ea Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Thu, 30 Mar 2023 16:25:20 +0200 -Subject: [PATCH 1/8] dt-bindings: phy: rockchip,inno-usb2phy: add rk3588 - -Add compatible for the USB2 phy in the Rockchip RK3588 SoC. - -Reviewed-by: Rob Herring -Signed-off-by: Sebastian Reichel ---- - .../bindings/phy/rockchip,inno-usb2phy.yaml | 21 ++++++++++++++++--- - 1 file changed, 18 insertions(+), 3 deletions(-) - -diff --git a/Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml b/Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml -index 0d6b8c28be07..5254413137c6 100644 ---- a/Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml -+++ b/Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml -@@ -20,6 +20,7 @@ properties: - - rockchip,rk3366-usb2phy - - rockchip,rk3399-usb2phy - - rockchip,rk3568-usb2phy -+ - rockchip,rk3588-usb2phy - - rockchip,rv1108-usb2phy - - reg: -@@ -56,6 +57,14 @@ properties: - description: Muxed interrupt for both ports - maxItems: 1 - -+ resets: -+ maxItems: 2 -+ -+ reset-names: -+ items: -+ - const: phy -+ - const: apb -+ - rockchip,usbgrf: - $ref: /schemas/types.yaml#/definitions/phandle - description: -@@ -120,15 +129,21 @@ required: - - reg - - clock-output-names - - "#clock-cells" -- - host-port -- - otg-port -+ -+anyOf: -+ - required: -+ - otg-port -+ - required: -+ - host-port - - allOf: - - if: - properties: - compatible: - contains: -- const: rockchip,rk3568-usb2phy -+ enum: -+ - rockchip,rk3568-usb2phy -+ - rockchip,rk3588-usb2phy - - then: - properties: --- -2.41.0 - - -From 0c333328e73ea034e26979aca1194e30c52ad451 Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Thu, 12 Jan 2023 19:15:52 +0100 -Subject: [PATCH 2/8] phy: phy-rockchip-inno-usb2: add rk3588 support - -Add basic support for the USB2 PHY found in the Rockchip RK3588. - -Co-developed-by: William Wu -Signed-off-by: William Wu -Signed-off-by: Sebastian Reichel ---- - drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 226 ++++++++++++++++-- - 1 file changed, 211 insertions(+), 15 deletions(-) - -diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -index a0bc10aa7961..2c4683c67a8e 100644 ---- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -@@ -116,6 +116,12 @@ struct rockchip_chg_det_reg { - * @bvalid_det_en: vbus valid rise detection enable register. - * @bvalid_det_st: vbus valid rise detection status register. - * @bvalid_det_clr: vbus valid rise detection clear register. -+ * @disfall_en: host disconnect fall edge detection enable. -+ * @disfall_st: host disconnect fall edge detection state. -+ * @disfall_clr: host disconnect fall edge detection clear. -+ * @disrise_en: host disconnect rise edge detection enable. -+ * @disrise_st: host disconnect rise edge detection state. -+ * @disrise_clr: host disconnect rise edge detection clear. - * @id_det_en: id detection enable register. - * @id_det_st: id detection state register. - * @id_det_clr: id detection clear register. -@@ -133,6 +139,12 @@ struct rockchip_usb2phy_port_cfg { - struct usb2phy_reg bvalid_det_en; - struct usb2phy_reg bvalid_det_st; - struct usb2phy_reg bvalid_det_clr; -+ struct usb2phy_reg disfall_en; -+ struct usb2phy_reg disfall_st; -+ struct usb2phy_reg disfall_clr; -+ struct usb2phy_reg disrise_en; -+ struct usb2phy_reg disrise_st; -+ struct usb2phy_reg disrise_clr; - struct usb2phy_reg id_det_en; - struct usb2phy_reg id_det_st; - struct usb2phy_reg id_det_clr; -@@ -168,6 +180,7 @@ struct rockchip_usb2phy_cfg { - * @port_id: flag for otg port or host port. - * @suspended: phy suspended flag. - * @vbus_attached: otg device vbus status. -+ * @host_disconnect: usb host disconnect status. - * @bvalid_irq: IRQ number assigned for vbus valid rise detection. - * @id_irq: IRQ number assigned for ID pin detection. - * @ls_irq: IRQ number assigned for linestate detection. -@@ -187,6 +200,7 @@ struct rockchip_usb2phy_port { - unsigned int port_id; - bool suspended; - bool vbus_attached; -+ bool host_disconnect; - int bvalid_irq; - int id_irq; - int ls_irq; -@@ -405,6 +419,27 @@ static int rockchip_usb2phy_extcon_register(struct rockchip_usb2phy *rphy) - return 0; - } - -+static int rockchip_usb2phy_enable_host_disc_irq(struct rockchip_usb2phy *rphy, -+ struct rockchip_usb2phy_port *rport, -+ bool en) -+{ -+ int ret; -+ -+ ret = property_enable(rphy->grf, &rport->port_cfg->disfall_clr, true); -+ if (ret) -+ return ret; -+ -+ ret = property_enable(rphy->grf, &rport->port_cfg->disfall_en, en); -+ if (ret) -+ return ret; -+ -+ ret = property_enable(rphy->grf, &rport->port_cfg->disrise_clr, true); -+ if (ret) -+ return ret; -+ -+ return property_enable(rphy->grf, &rport->port_cfg->disrise_en, en); -+} -+ - static int rockchip_usb2phy_init(struct phy *phy) - { - struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy); -@@ -449,6 +484,15 @@ static int rockchip_usb2phy_init(struct phy *phy) - dev_dbg(&rport->phy->dev, "mode %d\n", rport->mode); - } - } else if (rport->port_id == USB2PHY_PORT_HOST) { -+ if (rport->port_cfg->disfall_en.offset) { -+ rport->host_disconnect = true; -+ ret = rockchip_usb2phy_enable_host_disc_irq(rphy, rport, true); -+ if (ret) { -+ dev_err(rphy->dev, "failed to enable disconnect irq\n"); -+ goto out; -+ } -+ } -+ - /* clear linestate and enable linestate detect irq */ - ret = property_enable(rphy->grf, - &rport->port_cfg->ls_det_clr, true); -@@ -810,9 +854,7 @@ static void rockchip_usb2phy_sm_work(struct work_struct *work) - struct rockchip_usb2phy_port *rport = - container_of(work, struct rockchip_usb2phy_port, sm_work.work); - struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent); -- unsigned int sh = rport->port_cfg->utmi_hstdet.bitend - -- rport->port_cfg->utmi_hstdet.bitstart + 1; -- unsigned int ul, uhd, state; -+ unsigned int sh, ul, uhd, state; - unsigned int ul_mask, uhd_mask; - int ret; - -@@ -822,18 +864,26 @@ static void rockchip_usb2phy_sm_work(struct work_struct *work) - if (ret < 0) - goto next_schedule; - -- ret = regmap_read(rphy->grf, rport->port_cfg->utmi_hstdet.offset, &uhd); -- if (ret < 0) -- goto next_schedule; -- -- uhd_mask = GENMASK(rport->port_cfg->utmi_hstdet.bitend, -- rport->port_cfg->utmi_hstdet.bitstart); - ul_mask = GENMASK(rport->port_cfg->utmi_ls.bitend, - rport->port_cfg->utmi_ls.bitstart); - -- /* stitch on utmi_ls and utmi_hstdet as phy state */ -- state = ((uhd & uhd_mask) >> rport->port_cfg->utmi_hstdet.bitstart) | -- (((ul & ul_mask) >> rport->port_cfg->utmi_ls.bitstart) << sh); -+ if (rport->port_cfg->utmi_hstdet.offset) { -+ ret = regmap_read(rphy->grf, rport->port_cfg->utmi_hstdet.offset, &uhd); -+ if (ret < 0) -+ goto next_schedule; -+ -+ uhd_mask = GENMASK(rport->port_cfg->utmi_hstdet.bitend, -+ rport->port_cfg->utmi_hstdet.bitstart); -+ -+ sh = rport->port_cfg->utmi_hstdet.bitend - -+ rport->port_cfg->utmi_hstdet.bitstart + 1; -+ /* stitch on utmi_ls and utmi_hstdet as phy state */ -+ state = ((uhd & uhd_mask) >> rport->port_cfg->utmi_hstdet.bitstart) | -+ (((ul & ul_mask) >> rport->port_cfg->utmi_ls.bitstart) << sh); -+ } else { -+ state = ((ul & ul_mask) >> rport->port_cfg->utmi_ls.bitstart) << 1 | -+ rport->host_disconnect; -+ } - - switch (state) { - case PHY_STATE_HS_ONLINE: -@@ -966,6 +1016,31 @@ static irqreturn_t rockchip_usb2phy_otg_mux_irq(int irq, void *data) - return ret; - } - -+static irqreturn_t rockchip_usb2phy_host_disc_irq(int irq, void *data) -+{ -+ struct rockchip_usb2phy_port *rport = data; -+ struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent); -+ -+ if (!property_enabled(rphy->grf, &rport->port_cfg->disfall_st) && -+ !property_enabled(rphy->grf, &rport->port_cfg->disrise_st)) -+ return IRQ_NONE; -+ -+ mutex_lock(&rport->mutex); -+ -+ /* clear disconnect fall or rise detect irq pending status */ -+ if (property_enabled(rphy->grf, &rport->port_cfg->disfall_st)) { -+ property_enable(rphy->grf, &rport->port_cfg->disfall_clr, true); -+ rport->host_disconnect = false; -+ } else if (property_enabled(rphy->grf, &rport->port_cfg->disrise_st)) { -+ property_enable(rphy->grf, &rport->port_cfg->disrise_clr, true); -+ rport->host_disconnect = true; -+ } -+ -+ mutex_unlock(&rport->mutex); -+ -+ return IRQ_HANDLED; -+} -+ - static irqreturn_t rockchip_usb2phy_irq(int irq, void *data) - { - struct rockchip_usb2phy *rphy = data; -@@ -978,6 +1053,10 @@ static irqreturn_t rockchip_usb2phy_irq(int irq, void *data) - if (!rport->phy) - continue; - -+ if (rport->port_id == USB2PHY_PORT_HOST && -+ rport->port_cfg->disfall_en.offset) -+ ret |= rockchip_usb2phy_host_disc_irq(irq, rport); -+ - switch (rport->port_id) { - case USB2PHY_PORT_OTG: - if (rport->mode != USB_DR_MODE_HOST && -@@ -1233,7 +1312,7 @@ static int rockchip_usb2phy_probe(struct platform_device *pdev) - } - - /* support address_cells=2 */ -- if (reg == 0) { -+ if (of_property_count_u32_elems(np, "reg") > 2 && reg == 0) { - if (of_property_read_u32_index(np, "reg", 1, ®)) { - dev_err(dev, "the reg property is not assigned in %pOFn node\n", - np); -@@ -1254,14 +1333,14 @@ static int rockchip_usb2phy_probe(struct platform_device *pdev) - - /* find out a proper config which can be matched with dt. */ - index = 0; -- while (phy_cfgs[index].reg) { -+ do { - if (phy_cfgs[index].reg == reg) { - rphy->phy_cfg = &phy_cfgs[index]; - break; - } - - ++index; -- } -+ } while (phy_cfgs[index].reg); - - if (!rphy->phy_cfg) { - dev_err(dev, "no phy-config can be matched with %pOFn node\n", -@@ -1664,6 +1743,122 @@ static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = { - { /* sentinel */ } - }; - -+static const struct rockchip_usb2phy_cfg rk3588_phy_cfgs[] = { -+ { -+ .reg = 0x0000, -+ .num_ports = 1, -+ .clkout_ctl = { 0x0000, 0, 0, 1, 0 }, -+ .port_cfgs = { -+ [USB2PHY_PORT_OTG] = { -+ .phy_sus = { 0x000c, 11, 11, 0, 1 }, -+ .bvalid_det_en = { 0x0080, 1, 1, 0, 1 }, -+ .bvalid_det_st = { 0x0084, 1, 1, 0, 1 }, -+ .bvalid_det_clr = { 0x0088, 1, 1, 0, 1 }, -+ .ls_det_en = { 0x0080, 0, 0, 0, 1 }, -+ .ls_det_st = { 0x0084, 0, 0, 0, 1 }, -+ .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, -+ .disfall_en = { 0x0080, 6, 6, 0, 1 }, -+ .disfall_st = { 0x0084, 6, 6, 0, 1 }, -+ .disfall_clr = { 0x0088, 6, 6, 0, 1 }, -+ .disrise_en = { 0x0080, 5, 5, 0, 1 }, -+ .disrise_st = { 0x0084, 5, 5, 0, 1 }, -+ .disrise_clr = { 0x0088, 5, 5, 0, 1 }, -+ .utmi_avalid = { 0x00c0, 7, 7, 0, 1 }, -+ .utmi_bvalid = { 0x00c0, 6, 6, 0, 1 }, -+ .utmi_ls = { 0x00c0, 10, 9, 0, 1 }, -+ } -+ }, -+ .chg_det = { -+ .cp_det = { 0x00c0, 0, 0, 0, 1 }, -+ .dcp_det = { 0x00c0, 0, 0, 0, 1 }, -+ .dp_det = { 0x00c0, 1, 1, 1, 0 }, -+ .idm_sink_en = { 0x0008, 5, 5, 1, 0 }, -+ .idp_sink_en = { 0x0008, 5, 5, 0, 1 }, -+ .idp_src_en = { 0x0008, 14, 14, 0, 1 }, -+ .rdm_pdwn_en = { 0x0008, 14, 14, 0, 1 }, -+ .vdm_src_en = { 0x0008, 7, 6, 0, 3 }, -+ .vdp_src_en = { 0x0008, 7, 6, 0, 3 }, -+ }, -+ }, -+ { -+ .reg = 0x4000, -+ .num_ports = 1, -+ .clkout_ctl = { 0x0000, 0, 0, 1, 0 }, -+ .port_cfgs = { -+ [USB2PHY_PORT_OTG] = { -+ .phy_sus = { 0x000c, 11, 11, 0, 1 }, -+ .bvalid_det_en = { 0x0080, 1, 1, 0, 1 }, -+ .bvalid_det_st = { 0x0084, 1, 1, 0, 1 }, -+ .bvalid_det_clr = { 0x0088, 1, 1, 0, 1 }, -+ .ls_det_en = { 0x0080, 0, 0, 0, 1 }, -+ .ls_det_st = { 0x0084, 0, 0, 0, 1 }, -+ .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, -+ .disfall_en = { 0x0080, 6, 6, 0, 1 }, -+ .disfall_st = { 0x0084, 6, 6, 0, 1 }, -+ .disfall_clr = { 0x0088, 6, 6, 0, 1 }, -+ .disrise_en = { 0x0080, 5, 5, 0, 1 }, -+ .disrise_st = { 0x0084, 5, 5, 0, 1 }, -+ .disrise_clr = { 0x0088, 5, 5, 0, 1 }, -+ .utmi_avalid = { 0x00c0, 7, 7, 0, 1 }, -+ .utmi_bvalid = { 0x00c0, 6, 6, 0, 1 }, -+ .utmi_ls = { 0x00c0, 10, 9, 0, 1 }, -+ } -+ }, -+ .chg_det = { -+ .cp_det = { 0x00c0, 0, 0, 0, 1 }, -+ .dcp_det = { 0x00c0, 0, 0, 0, 1 }, -+ .dp_det = { 0x00c0, 1, 1, 1, 0 }, -+ .idm_sink_en = { 0x0008, 5, 5, 1, 0 }, -+ .idp_sink_en = { 0x0008, 5, 5, 0, 1 }, -+ .idp_src_en = { 0x0008, 14, 14, 0, 1 }, -+ .rdm_pdwn_en = { 0x0008, 14, 14, 0, 1 }, -+ .vdm_src_en = { 0x0008, 7, 6, 0, 3 }, -+ .vdp_src_en = { 0x0008, 7, 6, 0, 3 }, -+ }, -+ }, -+ { -+ .reg = 0x8000, -+ .num_ports = 1, -+ .clkout_ctl = { 0x0000, 0, 0, 1, 0 }, -+ .port_cfgs = { -+ [USB2PHY_PORT_HOST] = { -+ .phy_sus = { 0x0008, 2, 2, 0, 1 }, -+ .ls_det_en = { 0x0080, 0, 0, 0, 1 }, -+ .ls_det_st = { 0x0084, 0, 0, 0, 1 }, -+ .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, -+ .disfall_en = { 0x0080, 6, 6, 0, 1 }, -+ .disfall_st = { 0x0084, 6, 6, 0, 1 }, -+ .disfall_clr = { 0x0088, 6, 6, 0, 1 }, -+ .disrise_en = { 0x0080, 5, 5, 0, 1 }, -+ .disrise_st = { 0x0084, 5, 5, 0, 1 }, -+ .disrise_clr = { 0x0088, 5, 5, 0, 1 }, -+ .utmi_ls = { 0x00c0, 10, 9, 0, 1 }, -+ } -+ }, -+ }, -+ { -+ .reg = 0xc000, -+ .num_ports = 1, -+ .clkout_ctl = { 0x0000, 0, 0, 1, 0 }, -+ .port_cfgs = { -+ [USB2PHY_PORT_HOST] = { -+ .phy_sus = { 0x0008, 2, 2, 0, 1 }, -+ .ls_det_en = { 0x0080, 0, 0, 0, 1 }, -+ .ls_det_st = { 0x0084, 0, 0, 0, 1 }, -+ .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, -+ .disfall_en = { 0x0080, 6, 6, 0, 1 }, -+ .disfall_st = { 0x0084, 6, 6, 0, 1 }, -+ .disfall_clr = { 0x0088, 6, 6, 0, 1 }, -+ .disrise_en = { 0x0080, 5, 5, 0, 1 }, -+ .disrise_st = { 0x0084, 5, 5, 0, 1 }, -+ .disrise_clr = { 0x0088, 5, 5, 0, 1 }, -+ .utmi_ls = { 0x00c0, 10, 9, 0, 1 }, -+ } -+ }, -+ }, -+ { /* sentinel */ } -+}; -+ - static const struct rockchip_usb2phy_cfg rv1108_phy_cfgs[] = { - { - .reg = 0x100, -@@ -1714,6 +1909,7 @@ static const struct of_device_id rockchip_usb2phy_dt_match[] = { - { .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs }, - { .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs }, - { .compatible = "rockchip,rk3568-usb2phy", .data = &rk3568_phy_cfgs }, -+ { .compatible = "rockchip,rk3588-usb2phy", .data = &rk3588_phy_cfgs }, - { .compatible = "rockchip,rv1108-usb2phy", .data = &rv1108_phy_cfgs }, - {} - }; --- -2.41.0 - - -From f75cafaef5a575289fbf91bf52dd44765ddc9153 Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Mon, 3 Apr 2023 20:23:14 +0200 -Subject: [PATCH 3/8] phy: phy-rockchip-inno-usb2: add reset support - -Add reset handling support, which is needed for proper -operation with RK3588. - -Signed-off-by: Sebastian Reichel ---- - drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 38 +++++++++++++++++++ - 1 file changed, 38 insertions(+) - -diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -index 2c4683c67a8e..101b46939f0b 100644 ---- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -@@ -24,6 +24,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -223,6 +224,7 @@ struct rockchip_usb2phy_port { - * @clk: clock struct of phy input clk. - * @clk480m: clock struct of phy output clk. - * @clk480m_hw: clock struct of phy output clk management. -+ * @phy_reset: phy reset control. - * @chg_state: states involved in USB charger detection. - * @chg_type: USB charger types. - * @dcd_retries: The retry count used to track Data contact -@@ -239,6 +241,7 @@ struct rockchip_usb2phy { - struct clk *clk; - struct clk *clk480m; - struct clk_hw clk480m_hw; -+ struct reset_control *phy_reset; - enum usb_chg_state chg_state; - enum power_supply_type chg_type; - u8 dcd_retries; -@@ -280,6 +283,25 @@ static inline bool property_enabled(struct regmap *base, - return tmp != reg->disable; - } - -+static int rockchip_usb2phy_reset(struct rockchip_usb2phy *rphy) -+{ -+ int ret; -+ -+ ret = reset_control_assert(rphy->phy_reset); -+ if (ret) -+ return ret; -+ -+ udelay(10); -+ -+ ret = reset_control_deassert(rphy->phy_reset); -+ if (ret) -+ return ret; -+ -+ usleep_range(100, 200); -+ -+ return 0; -+} -+ - static int rockchip_usb2phy_clk480m_prepare(struct clk_hw *hw) - { - struct rockchip_usb2phy *rphy = -@@ -534,6 +556,18 @@ static int rockchip_usb2phy_power_on(struct phy *phy) - return ret; - } - -+ /* -+ * For rk3588, it needs to reset phy when exit from -+ * suspend mode with common_on_n 1'b1(aka REFCLK_LOGIC, -+ * Bias, and PLL blocks are powered down) for lower -+ * power consumption. If you don't want to reset phy, -+ * please keep the common_on_n 1'b0 to set these blocks -+ * remain powered. -+ */ -+ ret = rockchip_usb2phy_reset(rphy); -+ if (ret) -+ return ret; -+ - /* waiting for the utmi_clk to become stable */ - usleep_range(1500, 2000); - -@@ -1348,6 +1382,10 @@ static int rockchip_usb2phy_probe(struct platform_device *pdev) - return -EINVAL; - } - -+ rphy->phy_reset = devm_reset_control_get_optional(dev, "phy"); -+ if (IS_ERR(rphy->phy_reset)) -+ return PTR_ERR(rphy->phy_reset); -+ - rphy->clk = of_clk_get_by_name(np, "phyclk"); - if (!IS_ERR(rphy->clk)) { - clk_prepare_enable(rphy->clk); --- -2.41.0 - - -From 5c943deee0209dabd236a4f130961c52531358c4 Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Mon, 3 Apr 2023 20:24:06 +0200 -Subject: [PATCH 4/8] phy: phy-rockchip-inno-usb2: add rk3588 phy tuning - support - -On RK3588 some registers need to be tweaked to support waking up from -suspend when a USB device is plugged into a port from a suspended PHY. -Without this change USB devices only work when they are plugged at -boot time. - -Apart from that it optimizes settings to avoid devices toggling -between fullspeed and highspeed mode. - -Signed-off-by: Sebastian Reichel ---- - drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 63 +++++++++++++++++++ - 1 file changed, 63 insertions(+) - -diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -index 101b46939f0b..aa8c55609c0d 100644 ---- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -@@ -33,6 +33,8 @@ - #define SCHEDULE_DELAY (60 * HZ) - #define OTG_SCHEDULE_DELAY (2 * HZ) - -+struct rockchip_usb2phy; -+ - enum rockchip_usb2phy_port_id { - USB2PHY_PORT_OTG, - USB2PHY_PORT_HOST, -@@ -163,6 +165,7 @@ struct rockchip_usb2phy_port_cfg { - * struct rockchip_usb2phy_cfg - usb-phy configuration. - * @reg: the address offset of grf for usb-phy config. - * @num_ports: specify how many ports that the phy has. -+ * @phy_tuning: phy default parameters tuning. - * @clkout_ctl: keep on/turn off output clk of phy. - * @port_cfgs: usb-phy port configurations. - * @chg_det: charger detection registers. -@@ -170,6 +173,7 @@ struct rockchip_usb2phy_port_cfg { - struct rockchip_usb2phy_cfg { - unsigned int reg; - unsigned int num_ports; -+ int (*phy_tuning)(struct rockchip_usb2phy *rphy); - struct usb2phy_reg clkout_ctl; - const struct rockchip_usb2phy_port_cfg port_cfgs[USB2PHY_NUM_PORTS]; - const struct rockchip_chg_det_reg chg_det; -@@ -1400,6 +1404,12 @@ static int rockchip_usb2phy_probe(struct platform_device *pdev) - goto disable_clks; - } - -+ if (rphy->phy_cfg->phy_tuning) { -+ ret = rphy->phy_cfg->phy_tuning(rphy); -+ if (ret) -+ goto disable_clks; -+ } -+ - index = 0; - for_each_available_child_of_node(np, child_np) { - struct rockchip_usb2phy_port *rport = &rphy->ports[index]; -@@ -1468,6 +1478,55 @@ static int rockchip_usb2phy_probe(struct platform_device *pdev) - return ret; - } - -+static int rk3588_usb2phy_tuning(struct rockchip_usb2phy *rphy) -+{ -+ int ret; -+ bool usb3otg = false; -+ /* -+ * utmi_termselect = 1'b1 (en FS terminations) -+ * utmi_xcvrselect = 2'b01 (FS transceiver) -+ */ -+ int suspend_cfg = 0x14; -+ -+ if (rphy->phy_cfg->reg == 0x0000 || rphy->phy_cfg->reg == 0x4000) { -+ /* USB2 config for USB3_0 and USB3_1 */ -+ suspend_cfg |= 0x01; /* utmi_opmode = 2'b01 (no-driving) */ -+ usb3otg = true; -+ } else if (rphy->phy_cfg->reg == 0x8000 || rphy->phy_cfg->reg == 0xc000) { -+ /* USB2 config for USB2_0 and USB2_1 */ -+ suspend_cfg |= 0x00; /* utmi_opmode = 2'b00 (normal) */ -+ } else { -+ return -EINVAL; -+ } -+ -+ /* Deassert SIDDQ to power on analog block */ -+ ret = regmap_write(rphy->grf, 0x0008, GENMASK(29, 29) | 0x0000); -+ if (ret) -+ return ret; -+ -+ /* Do reset after exit IDDQ mode */ -+ ret = rockchip_usb2phy_reset(rphy); -+ if (ret) -+ return ret; -+ -+ /* suspend configuration */ -+ ret |= regmap_write(rphy->grf, 0x000c, GENMASK(20, 16) | suspend_cfg); -+ -+ /* HS DC Voltage Level Adjustment 4'b1001 : +5.89% */ -+ ret |= regmap_write(rphy->grf, 0x0004, GENMASK(27, 24) | 0x0900); -+ -+ /* HS Transmitter Pre-Emphasis Current Control 2'b10 : 2x */ -+ ret |= regmap_write(rphy->grf, 0x0008, GENMASK(20, 19) | 0x0010); -+ -+ if (!usb3otg) -+ return ret; -+ -+ /* Pullup iddig pin for USB3_0 OTG mode */ -+ ret |= regmap_write(rphy->grf, 0x0010, GENMASK(17, 16) | 0x0003); -+ -+ return ret; -+} -+ - static const struct rockchip_usb2phy_cfg rk3228_phy_cfgs[] = { - { - .reg = 0x760, -@@ -1785,6 +1844,7 @@ static const struct rockchip_usb2phy_cfg rk3588_phy_cfgs[] = { - { - .reg = 0x0000, - .num_ports = 1, -+ .phy_tuning = rk3588_usb2phy_tuning, - .clkout_ctl = { 0x0000, 0, 0, 1, 0 }, - .port_cfgs = { - [USB2PHY_PORT_OTG] = { -@@ -1821,6 +1881,7 @@ static const struct rockchip_usb2phy_cfg rk3588_phy_cfgs[] = { - { - .reg = 0x4000, - .num_ports = 1, -+ .phy_tuning = rk3588_usb2phy_tuning, - .clkout_ctl = { 0x0000, 0, 0, 1, 0 }, - .port_cfgs = { - [USB2PHY_PORT_OTG] = { -@@ -1857,6 +1918,7 @@ static const struct rockchip_usb2phy_cfg rk3588_phy_cfgs[] = { - { - .reg = 0x8000, - .num_ports = 1, -+ .phy_tuning = rk3588_usb2phy_tuning, - .clkout_ctl = { 0x0000, 0, 0, 1, 0 }, - .port_cfgs = { - [USB2PHY_PORT_HOST] = { -@@ -1877,6 +1939,7 @@ static const struct rockchip_usb2phy_cfg rk3588_phy_cfgs[] = { - { - .reg = 0xc000, - .num_ports = 1, -+ .phy_tuning = rk3588_usb2phy_tuning, - .clkout_ctl = { 0x0000, 0, 0, 1, 0 }, - .port_cfgs = { - [USB2PHY_PORT_HOST] = { --- -2.41.0 - - -From 1c15099f3d65101fc2ede3bbddbe135cb6fe9acd Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Mon, 3 Apr 2023 21:49:58 +0200 -Subject: [PATCH 5/8] phy: phy-rockchip-inno-usb2: simplify phy clock handling - -Simplify phyclk handling by using devm_clk_get_optional_enabled to -acquire and enable the optional clock. This also fixes a resource -leak in driver remove path and adds proper error handling. - -Signed-off-by: Sebastian Reichel ---- - drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 19 ++++++------------- - 1 file changed, 6 insertions(+), 13 deletions(-) - -diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -index aa8c55609c0d..1cf84869e78b 100644 ---- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -@@ -1390,24 +1390,22 @@ static int rockchip_usb2phy_probe(struct platform_device *pdev) - if (IS_ERR(rphy->phy_reset)) - return PTR_ERR(rphy->phy_reset); - -- rphy->clk = of_clk_get_by_name(np, "phyclk"); -- if (!IS_ERR(rphy->clk)) { -- clk_prepare_enable(rphy->clk); -- } else { -- dev_info(&pdev->dev, "no phyclk specified\n"); -- rphy->clk = NULL; -+ rphy->clk = devm_clk_get_optional_enabled(dev, "phyclk"); -+ if (IS_ERR(rphy->clk)) { -+ return dev_err_probe(&pdev->dev, PTR_ERR(rphy->clk), -+ "failed to get phyclk\n"); - } - - ret = rockchip_usb2phy_clk480m_register(rphy); - if (ret) { - dev_err(dev, "failed to register 480m output clock\n"); -- goto disable_clks; -+ return ret; - } - - if (rphy->phy_cfg->phy_tuning) { - ret = rphy->phy_cfg->phy_tuning(rphy); - if (ret) -- goto disable_clks; -+ return ret; - } - - index = 0; -@@ -1470,11 +1468,6 @@ static int rockchip_usb2phy_probe(struct platform_device *pdev) - - put_child: - of_node_put(child_np); --disable_clks: -- if (rphy->clk) { -- clk_disable_unprepare(rphy->clk); -- clk_put(rphy->clk); -- } - return ret; - } - --- -2.41.0 - - -From 06431641fd8ea3bc836c74f3506bd83992c3c17d Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Mon, 3 Apr 2023 22:01:14 +0200 -Subject: [PATCH 6/8] phy: phy-rockchip-inno-usb2: simplify getting match data - -Simplify the code by directly getting the match data via -device_get_match_data() instead of open coding its functionality. - -Signed-off-by: Sebastian Reichel ---- - drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 12 ++++-------- - 1 file changed, 4 insertions(+), 8 deletions(-) - -diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -index 1cf84869e78b..f5c30f117cba 100644 ---- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -@@ -1305,7 +1305,6 @@ static int rockchip_usb2phy_probe(struct platform_device *pdev) - struct phy_provider *provider; - struct rockchip_usb2phy *rphy; - const struct rockchip_usb2phy_cfg *phy_cfgs; -- const struct of_device_id *match; - unsigned int reg; - int index, ret; - -@@ -1313,12 +1312,6 @@ static int rockchip_usb2phy_probe(struct platform_device *pdev) - if (!rphy) - return -ENOMEM; - -- match = of_match_device(dev->driver->of_match_table, dev); -- if (!match || !match->data) { -- dev_err(dev, "phy configs are not assigned!\n"); -- return -EINVAL; -- } -- - if (!dev->parent || !dev->parent->of_node) { - rphy->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,usbgrf"); - if (IS_ERR(rphy->grf)) { -@@ -1359,12 +1352,15 @@ static int rockchip_usb2phy_probe(struct platform_device *pdev) - } - - rphy->dev = dev; -- phy_cfgs = match->data; -+ phy_cfgs = device_get_match_data(dev); - rphy->chg_state = USB_CHG_STATE_UNDEFINED; - rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN; - rphy->irq = platform_get_irq_optional(pdev, 0); - platform_set_drvdata(pdev, rphy); - -+ if (!phy_cfgs) -+ return dev_err_probe(dev, -EINVAL, "phy configs are not assigned!\n"); -+ - ret = rockchip_usb2phy_extcon_register(rphy); - if (ret) - return ret; --- -2.41.0 - - -From 9fcaf91f0cc30115f592c8b42ce7e0ebd2ec03eb Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Mon, 15 May 2023 18:40:42 +0200 -Subject: [PATCH 7/8] phy: phy-rockchip-inno-usb2: improve error message - -Printing the OF node is not useful, since we get the same information -from the device context. Instead print the reg address, that could -not be found. - -Signed-off-by: Sebastian Reichel ---- - drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 3 +-- - 1 file changed, 1 insertion(+), 2 deletions(-) - -diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -index f5c30f117cba..b982c3f0d4b5 100644 ---- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -@@ -1377,8 +1377,7 @@ static int rockchip_usb2phy_probe(struct platform_device *pdev) - } while (phy_cfgs[index].reg); - - if (!rphy->phy_cfg) { -- dev_err(dev, "no phy-config can be matched with %pOFn node\n", -- np); -+ dev_err(dev, "could not find phy config for reg=0x%08x\n", reg); - return -EINVAL; - } - --- -2.41.0 - - -From be0f85d5bc7f6f342f3d32092a8f8603ac4ec21d Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Thu, 12 Jan 2023 19:20:37 +0100 -Subject: [PATCH 8/8] arm64: dts: rockchip: rk3588: add USB2 support - -This adds USB2 (EHCI & OHCI) ports including the related PHYs -and GRF modules to the rk3588(s) device tree. - -Signed-off-by: Sebastian Reichel ---- - arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 94 +++++++++++++++++++++++ - 1 file changed, 94 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -index 8243e52bce59..c9f9dd2472f5 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -@@ -399,6 +399,50 @@ scmi_shmem: sram@0 { - }; - }; - -+ usb_host0_ehci: usb@fc800000 { -+ compatible = "rockchip,rk3588-ehci", "generic-ehci"; -+ reg = <0x0 0xfc800000 0x0 0x40000>; -+ interrupts = ; -+ clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>; -+ phys = <&u2phy2_host>; -+ phy-names = "usb"; -+ power-domains = <&power RK3588_PD_USB>; -+ status = "disabled"; -+ }; -+ -+ usb_host0_ohci: usb@fc840000 { -+ compatible = "rockchip,rk3588-ohci", "generic-ohci"; -+ reg = <0x0 0xfc840000 0x0 0x40000>; -+ interrupts = ; -+ clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>; -+ phys = <&u2phy2_host>; -+ phy-names = "usb"; -+ power-domains = <&power RK3588_PD_USB>; -+ status = "disabled"; -+ }; -+ -+ usb_host1_ehci: usb@fc880000 { -+ compatible = "rockchip,rk3588-ehci", "generic-ehci"; -+ reg = <0x0 0xfc880000 0x0 0x40000>; -+ interrupts = ; -+ clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>; -+ phys = <&u2phy3_host>; -+ phy-names = "usb"; -+ power-domains = <&power RK3588_PD_USB>; -+ status = "disabled"; -+ }; -+ -+ usb_host1_ohci: usb@fc8c0000 { -+ compatible = "rockchip,rk3588-ohci", "generic-ohci"; -+ reg = <0x0 0xfc8c0000 0x0 0x40000>; -+ interrupts = ; -+ clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>; -+ phys = <&u2phy3_host>; -+ phy-names = "usb"; -+ power-domains = <&power RK3588_PD_USB>; -+ status = "disabled"; -+ }; -+ - sys_grf: syscon@fd58c000 { - compatible = "rockchip,rk3588-sys-grf", "syscon"; - reg = <0x0 0xfd58c000 0x0 0x1000>; -@@ -419,6 +463,56 @@ pipe_phy2_grf: syscon@fd5c4000 { - reg = <0x0 0xfd5c4000 0x0 0x100>; - }; - -+ usb2phy2_grf: syscon@fd5d8000 { -+ compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; -+ reg = <0x0 0xfd5d8000 0x0 0x4000>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ u2phy2: usb2-phy@8000 { -+ compatible = "rockchip,rk3588-usb2phy"; -+ reg = <0x8000 0x10>; -+ interrupts = ; -+ resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>; -+ reset-names = "phy", "apb"; -+ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; -+ clock-names = "phyclk"; -+ clock-output-names = "usb480m_phy2"; -+ #clock-cells = <0>; -+ status = "disabled"; -+ -+ u2phy2_host: host-port { -+ #phy-cells = <0>; -+ status = "disabled"; -+ }; -+ }; -+ }; -+ -+ usb2phy3_grf: syscon@fd5dc000 { -+ compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; -+ reg = <0x0 0xfd5dc000 0x0 0x4000>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ u2phy3: usb2-phy@c000 { -+ compatible = "rockchip,rk3588-usb2phy"; -+ reg = <0xc000 0x10>; -+ interrupts = ; -+ resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>; -+ reset-names = "phy", "apb"; -+ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; -+ clock-names = "phyclk"; -+ clock-output-names = "usb480m_phy3"; -+ #clock-cells = <0>; -+ status = "disabled"; -+ -+ u2phy3_host: host-port { -+ #phy-cells = <0>; -+ status = "disabled"; -+ }; -+ }; -+ }; -+ - ioc: syscon@fd5f0000 { - compatible = "rockchip,rk3588-ioc", "syscon"; - reg = <0x0 0xfd5f0000 0x0 0x10000>; --- -2.41.0 - diff --git a/patch/kernel/rockchip-rk3588-edge/0022-RK3588-PCIe-support.patch b/patch/kernel/rockchip-rk3588-edge/0022-RK3588-PCIe-support.patch deleted file mode 100644 index 96ee17282e..0000000000 --- a/patch/kernel/rockchip-rk3588-edge/0022-RK3588-PCIe-support.patch +++ /dev/null @@ -1,779 +0,0 @@ -From e88e8fae43d48db2f95cd425d117234c07250257 Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Mon, 10 Jul 2023 19:51:11 +0200 -Subject: [PATCH 1/9] dt-bindings: phy: rockchip: add RK3588 PCIe v3 phy - -When the RK3568 PCIe v3 PHY supported has been upstreamed, RK3588 -support was included, but the DT binding does not reflect this. -This adds the missing bits. - -Reviewed-by: Conor Dooley -Signed-off-by: Sebastian Reichel ---- - .../bindings/phy/rockchip,pcie3-phy.yaml | 33 ++++++++++++++++--- - 1 file changed, 28 insertions(+), 5 deletions(-) - -diff --git a/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml -index 9f2d8d2cc7a5..c4fbffcde6e4 100644 ---- a/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml -+++ b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml -@@ -13,19 +13,18 @@ properties: - compatible: - enum: - - rockchip,rk3568-pcie3-phy -+ - rockchip,rk3588-pcie3-phy - - reg: - maxItems: 1 - - clocks: -- minItems: 3 -+ minItems: 1 - maxItems: 3 - - clock-names: -- items: -- - const: refclk_m -- - const: refclk_n -- - const: pclk -+ minItems: 1 -+ maxItems: 3 - - data-lanes: - description: which lanes (by position) should be mapped to which -@@ -61,6 +60,30 @@ required: - - rockchip,phy-grf - - "#phy-cells" - -+allOf: -+ - if: -+ properties: -+ compatible: -+ enum: -+ - rockchip,rk3588-pcie3-phy -+ then: -+ properties: -+ clocks: -+ maxItems: 1 -+ clock-names: -+ items: -+ - const: pclk -+ else: -+ properties: -+ clocks: -+ minItems: 3 -+ -+ clock-names: -+ items: -+ - const: refclk_m -+ - const: refclk_n -+ - const: pclk -+ - additionalProperties: false - - examples: --- -2.41.0 - - -From 8f4060c74f79630b85ccdf134f9033e2ee637805 Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Sat, 15 Jul 2023 00:37:44 +0200 -Subject: [PATCH 2/9] dt-bindings: PCI: dwc: improve msi handling - -Allow missing "msi" interrupt, iff the node has a "msi-map" property. - -Signed-off-by: Sebastian Reichel ---- - .../devicetree/bindings/pci/snps,dw-pcie.yaml | 12 +++++++++--- - 1 file changed, 9 insertions(+), 3 deletions(-) - -diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml -index 1a83f0f65f19..abc1bcef13ec 100644 ---- a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml -+++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml -@@ -25,6 +25,15 @@ select: - allOf: - - $ref: /schemas/pci/pci-bus.yaml# - - $ref: /schemas/pci/snps,dw-pcie-common.yaml# -+ - if: -+ not: -+ required: -+ - msi-map -+ then: -+ properties: -+ interrupt-names: -+ contains: -+ const: "msi" - - properties: - reg: -@@ -193,9 +202,6 @@ properties: - oneOf: - - description: See native "app" IRQ for details - enum: [ intr ] -- allOf: -- - contains: -- const: msi - - additionalProperties: true - --- -2.41.0 - - -From 0ac1f4ac95ae783a362ef317367e137ddd1ec71b Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Sat, 15 Jul 2023 00:39:28 +0200 -Subject: [PATCH 3/9] dt-bindings: PCI: dwc: rockchip: Fix interrupt-names - issue - -The RK356x (and RK3588) have 5 ganged interrupts. For example the -"legacy" interrupt combines "inta/intb/intc/intd" with a register -providing the details. - -Currently the binding is not specifying these interrupts resulting -in a bunch of errors for all rk356x boards using PCIe. - -Fix this by specifying the interrupts and add them to the example -to prevent regressions. - -This changes the reference from snps,dw-pcie.yaml to -snps,dw-pcie-common.yaml, since the interrupts are vendor -specific and should not be listed in the generic file. The -only other bit from the generic binding are the reg-names, -which are overwritten by this binding. - -Signed-off-by: Sebastian Reichel ---- - .../bindings/pci/rockchip-dw-pcie.yaml | 43 ++++++++++++++++++- - 1 file changed, 42 insertions(+), 1 deletion(-) - -diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml -index a4f61ced5e88..7836b9a5547c 100644 ---- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml -+++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml -@@ -17,7 +17,8 @@ description: |+ - snps,dw-pcie.yaml. - - allOf: -- - $ref: /schemas/pci/snps,dw-pcie.yaml# -+ - $ref: /schemas/pci/pci-bus.yaml# -+ - $ref: /schemas/pci/snps,dw-pcie-common.yaml# - - properties: - compatible: -@@ -60,6 +61,39 @@ properties: - - const: aux - - const: pipe - -+ interrupts: -+ items: -+ - description: -+ Combined system interrupt, which is used to signal the following -+ interrupts - phy_link_up, dll_link_up, link_req_rst_not, hp_pme, -+ hp, hp_msi, link_auto_bw, link_auto_bw_msi, bw_mgt, bw_mgt_msi, -+ edma_wr, edma_rd, dpa_sub_upd, rbar_update, link_eq_req, ep_elbi_app -+ - description: -+ Combined PM interrupt, which is used to signal the following -+ interrupts - linkst_in_l1sub, linkst_in_l1, linkst_in_l2, -+ linkst_in_l0s, linkst_out_l1sub, linkst_out_l1, linkst_out_l2, -+ linkst_out_l0s, pm_dstate_update -+ - description: -+ Combined message interrupt, which is used to signal the following -+ interrupts - ven_msg, unlock_msg, ltr_msg, cfg_pme, cfg_pme_msi, -+ pm_pme, pm_to_ack, pm_turnoff, obff_idle, obff_obff, obff_cpu_active -+ - description: -+ Combined legacy interrupt, which is used to signal the following -+ interrupts - inta, intb, intc, intd -+ - description: -+ Combined error interrupt, which is used to signal the following -+ interrupts - aer_rc_err, aer_rc_err_msi, rx_cpl_timeout, -+ tx_cpl_timeout, cor_err_sent, nf_err_sent, f_err_sent, cor_err_rx, -+ nf_err_rx, f_err_rx, radm_qoverflow -+ -+ interrupt-names: -+ items: -+ - const: sys -+ - const: pmc -+ - const: msg -+ - const: legacy -+ - const: err -+ - msi-map: true - - num-lanes: true -@@ -108,6 +142,7 @@ unevaluatedProperties: false - - examples: - - | -+ #include - - bus { - #address-cells = <2>; -@@ -127,6 +162,12 @@ examples: - "aclk_dbi", "pclk", - "aux"; - device_type = "pci"; -+ interrupts = , -+ , -+ , -+ , -+ ; -+ interrupt-names = "sys", "pmc", "msg", "legacy", "err"; - linux,pci-domain = <2>; - max-link-speed = <2>; - msi-map = <0x2000 &its 0x2000 0x1000>; --- -2.41.0 - - -From 9475d7f1d48bcb32afcb2796cb9edf6080f566ef Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Mon, 17 Jul 2023 17:07:48 +0200 -Subject: [PATCH 4/9] dt-bindings: PCI: dwc: rockchip: Use generic binding - -Use the generic binding for Rockchip. This should either be -ignored/dropped or squashed into the previous commit. - -Signed-off-by: Sebastian Reichel ---- - Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml | 3 +-- - Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml | 6 +++++- - 2 files changed, 6 insertions(+), 3 deletions(-) - -diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml -index 7836b9a5547c..ad9954f7fe02 100644 ---- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml -+++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml -@@ -17,8 +17,7 @@ description: |+ - snps,dw-pcie.yaml. - - allOf: -- - $ref: /schemas/pci/pci-bus.yaml# -- - $ref: /schemas/pci/snps,dw-pcie-common.yaml# -+ - $ref: /schemas/pci/snps,dw-pcie.yaml# - - properties: - compatible: -diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml -index abc1bcef13ec..95d343c75485 100644 ---- a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml -+++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml -@@ -196,12 +196,16 @@ properties: - Status register (the event is supposed to be unmasked in the - Link Control register). - const: bw_mg -+ - description: -+ Combined Legacy A/B/C/D interrupt signal. See "^int(a|b|c|d)$" for -+ details. -+ const: legacy - - description: - Vendor-specific IRQ names. Consider using the generic names above - for new bindings. - oneOf: - - description: See native "app" IRQ for details -- enum: [ intr ] -+ enum: [ intr, sys, pmc, msg, err ] - - additionalProperties: true - --- -2.41.0 - - -From 276778343f47aa3851a1b9317e733cdaf6c9726e Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Wed, 19 Apr 2023 18:27:12 +0200 -Subject: [PATCH 5/9] dt-bindings: PCI: dwc: rockchip: Add missing - legacy-interrupt-controller - -Rockchip RK356x and RK3588 handle legacy interrupts via a ganged -interrupts. The RK356x DT implements this via a sub-node named -"legacy-interrupt-controller", just like a couple of other PCIe -implementations. This adds proper documentation for this and updates -the example to avoid regressions. - -Reviewed-by: Rob Herring -Signed-off-by: Sebastian Reichel ---- - .../bindings/pci/rockchip-dw-pcie.yaml | 30 +++++++++++++++++++ - 1 file changed, 30 insertions(+) - -diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml -index ad9954f7fe02..1ae8dcfa072c 100644 ---- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml -+++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml -@@ -93,6 +93,28 @@ properties: - - const: legacy - - const: err - -+ legacy-interrupt-controller: -+ description: Interrupt controller node for handling legacy PCI interrupts. -+ type: object -+ additionalProperties: false -+ properties: -+ "#address-cells": -+ const: 0 -+ -+ "#interrupt-cells": -+ const: 1 -+ -+ interrupt-controller: true -+ -+ interrupts: -+ items: -+ - description: combined legacy interrupt -+ required: -+ - "#address-cells" -+ - "#interrupt-cells" -+ - interrupt-controller -+ - interrupts -+ - msi-map: true - - num-lanes: true -@@ -180,6 +202,14 @@ examples: - reset-names = "pipe"; - #address-cells = <3>; - #size-cells = <2>; -+ -+ legacy-interrupt-controller { -+ interrupt-controller; -+ #address-cells = <0>; -+ #interrupt-cells = <1>; -+ interrupt-parent = <&gic>; -+ interrupts = ; -+ }; - }; - }; - ... --- -2.41.0 - - -From 4662ec75d1cfe3c7ccfa6f688485c063d4adb725 Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Mon, 17 Apr 2023 20:03:08 +0200 -Subject: [PATCH 6/9] arm64: dts: rockchip: rk3588: add PCIe2 support - -Add all three PCIe2 IP blocks to the RK3588 DT. Note, that RK3588 -also has two PCIe3 IP blocks, that will be handled separately. - -Co-developed-by: Kever Yang -Signed-off-by: Kever Yang -Tested-by: Jagan Teki # edgeble-neu6a, 6b -Reviewed-by: Jagan Teki -Signed-off-by: Sebastian Reichel ---- - arch/arm64/boot/dts/rockchip/rk3588.dtsi | 51 +++++++++++ - arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 102 ++++++++++++++++++++++ - 2 files changed, 153 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi -index 6be9bf81c09c..88d702575db2 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi -@@ -80,6 +80,57 @@ i2s10_8ch: i2s@fde00000 { - status = "disabled"; - }; - -+ pcie2x1l0: pcie@fe170000 { -+ compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ bus-range = <0x20 0x2f>; -+ clocks = <&cru ACLK_PCIE_1L0_MSTR>, <&cru ACLK_PCIE_1L0_SLV>, -+ <&cru ACLK_PCIE_1L0_DBI>, <&cru PCLK_PCIE_1L0>, -+ <&cru CLK_PCIE_AUX2>, <&cru CLK_PCIE1L0_PIPE>; -+ clock-names = "aclk_mst", "aclk_slv", -+ "aclk_dbi", "pclk", -+ "aux", "pipe"; -+ device_type = "pci"; -+ interrupts = , -+ , -+ , -+ , -+ ; -+ interrupt-names = "sys", "pmc", "msg", "legacy", "err"; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0 0 0 1 &pcie2x1l0_intc 0>, -+ <0 0 0 2 &pcie2x1l0_intc 1>, -+ <0 0 0 3 &pcie2x1l0_intc 2>, -+ <0 0 0 4 &pcie2x1l0_intc 3>; -+ linux,pci-domain = <2>; -+ max-link-speed = <2>; -+ msi-map = <0x2000 &its0 0x2000 0x1000>; -+ num-lanes = <1>; -+ phys = <&combphy1_ps PHY_TYPE_PCIE>; -+ phy-names = "pcie-phy"; -+ power-domains = <&power RK3588_PD_PCIE>; -+ ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>, -+ <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x00e00000>, -+ <0x03000000 0x0 0x40000000 0x9 0x80000000 0x0 0x40000000>; -+ reg = <0xa 0x40800000 0x0 0x00400000>, -+ <0x0 0xfe170000 0x0 0x00010000>, -+ <0x0 0xf2000000 0x0 0x00100000>; -+ reg-names = "dbi", "apb", "config"; -+ resets = <&cru SRST_PCIE2_POWER_UP>, <&cru SRST_P_PCIE2>; -+ reset-names = "pwr", "pipe"; -+ status = "disabled"; -+ -+ pcie2x1l0_intc: legacy-interrupt-controller { -+ interrupt-controller; -+ #address-cells = <0>; -+ #interrupt-cells = <1>; -+ interrupt-parent = <&gic>; -+ interrupts = ; -+ }; -+ }; -+ - gmac0: ethernet@fe1b0000 { - compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; - reg = <0x0 0xfe1b0000 0x0 0x10000>; -diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -index c9f9dd2472f5..b9b509257aaa 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -@@ -1227,6 +1227,108 @@ qos_vop_m1: qos@fdf82200 { - reg = <0x0 0xfdf82200 0x0 0x20>; - }; - -+ pcie2x1l1: pcie@fe180000 { -+ compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ bus-range = <0x30 0x3f>; -+ clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>, -+ <&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>, -+ <&cru CLK_PCIE_AUX3>, <&cru CLK_PCIE1L1_PIPE>; -+ clock-names = "aclk_mst", "aclk_slv", -+ "aclk_dbi", "pclk", -+ "aux", "pipe"; -+ device_type = "pci"; -+ interrupts = , -+ , -+ , -+ , -+ ; -+ interrupt-names = "sys", "pmc", "msg", "legacy", "err"; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>, -+ <0 0 0 2 &pcie2x1l1_intc 1>, -+ <0 0 0 3 &pcie2x1l1_intc 2>, -+ <0 0 0 4 &pcie2x1l1_intc 3>; -+ linux,pci-domain = <3>; -+ max-link-speed = <2>; -+ msi-map = <0x3000 &its0 0x3000 0x1000>; -+ num-lanes = <1>; -+ phys = <&combphy2_psu PHY_TYPE_PCIE>; -+ phy-names = "pcie-phy"; -+ power-domains = <&power RK3588_PD_PCIE>; -+ ranges = <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>, -+ <0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>, -+ <0x03000000 0x0 0x40000000 0x9 0xc0000000 0x0 0x40000000>; -+ reg = <0xa 0x40c00000 0x0 0x00400000>, -+ <0x0 0xfe180000 0x0 0x00010000>, -+ <0x0 0xf3000000 0x0 0x00100000>; -+ reg-names = "dbi", "apb", "config"; -+ resets = <&cru SRST_PCIE3_POWER_UP>, <&cru SRST_P_PCIE3>; -+ reset-names = "pwr", "pipe"; -+ status = "disabled"; -+ -+ pcie2x1l1_intc: legacy-interrupt-controller { -+ interrupt-controller; -+ #address-cells = <0>; -+ #interrupt-cells = <1>; -+ interrupt-parent = <&gic>; -+ interrupts = ; -+ }; -+ }; -+ -+ pcie2x1l2: pcie@fe190000 { -+ compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ bus-range = <0x40 0x4f>; -+ clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>, -+ <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>, -+ <&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>; -+ clock-names = "aclk_mst", "aclk_slv", -+ "aclk_dbi", "pclk", -+ "aux", "pipe"; -+ device_type = "pci"; -+ interrupts = , -+ , -+ , -+ , -+ ; -+ interrupt-names = "sys", "pmc", "msg", "legacy", "err"; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>, -+ <0 0 0 2 &pcie2x1l2_intc 1>, -+ <0 0 0 3 &pcie2x1l2_intc 2>, -+ <0 0 0 4 &pcie2x1l2_intc 3>; -+ linux,pci-domain = <4>; -+ max-link-speed = <2>; -+ msi-map = <0x4000 &its0 0x4000 0x1000>; -+ num-lanes = <1>; -+ phys = <&combphy0_ps PHY_TYPE_PCIE>; -+ phy-names = "pcie-phy"; -+ power-domains = <&power RK3588_PD_PCIE>; -+ ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>, -+ <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>, -+ <0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>; -+ reg = <0xa 0x41000000 0x0 0x00400000>, -+ <0x0 0xfe190000 0x0 0x00010000>, -+ <0x0 0xf4000000 0x0 0x00100000>; -+ reg-names = "dbi", "apb", "config"; -+ resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>; -+ reset-names = "pwr", "pipe"; -+ status = "disabled"; -+ -+ pcie2x1l2_intc: legacy-interrupt-controller { -+ interrupt-controller; -+ #address-cells = <0>; -+ #interrupt-cells = <1>; -+ interrupt-parent = <&gic>; -+ interrupts = ; -+ }; -+ }; -+ - gmac1: ethernet@fe1c0000 { - compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; - reg = <0x0 0xfe1c0000 0x0 0x10000>; --- -2.41.0 - - -From 373368400bba7f14466beb6c15cb24e94ff01cd4 Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Mon, 10 Jul 2023 19:54:03 +0200 -Subject: [PATCH 7/9] arm64: dts: rockchip: rk3588: add PCIe3 support - -Add both PCIe3 controllers together with the shared PHY. - -Signed-off-by: Sebastian Reichel ---- - arch/arm64/boot/dts/rockchip/rk3588.dtsi | 120 +++++++++++++++++++++++ - 1 file changed, 120 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi -index 88d702575db2..8f210f002fac 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi -@@ -7,6 +7,11 @@ - #include "rk3588-pinctrl.dtsi" - - / { -+ pcie30_phy_grf: syscon@fd5b8000 { -+ compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon"; -+ reg = <0x0 0xfd5b8000 0x0 0x10000>; -+ }; -+ - pipe_phy1_grf: syscon@fd5c0000 { - compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; - reg = <0x0 0xfd5c0000 0x0 0x100>; -@@ -80,6 +85,108 @@ i2s10_8ch: i2s@fde00000 { - status = "disabled"; - }; - -+ pcie3x4: pcie@fe150000 { -+ compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ bus-range = <0x00 0x0f>; -+ clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, -+ <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, -+ <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>; -+ clock-names = "aclk_mst", "aclk_slv", -+ "aclk_dbi", "pclk", -+ "aux", "pipe"; -+ device_type = "pci"; -+ interrupts = , -+ , -+ , -+ , -+ ; -+ interrupt-names = "sys", "pmc", "msg", "legacy", "err"; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0 0 0 1 &pcie3x4_intc 0>, -+ <0 0 0 2 &pcie3x4_intc 1>, -+ <0 0 0 3 &pcie3x4_intc 2>, -+ <0 0 0 4 &pcie3x4_intc 3>; -+ linux,pci-domain = <0>; -+ max-link-speed = <3>; -+ msi-map = <0x0000 &its1 0x0000 0x1000>; -+ num-lanes = <4>; -+ phys = <&pcie30phy>; -+ phy-names = "pcie-phy"; -+ power-domains = <&power RK3588_PD_PCIE>; -+ ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>, -+ <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x00e00000>, -+ <0x03000000 0x0 0x40000000 0x9 0x00000000 0x0 0x40000000>; -+ reg = <0xa 0x40000000 0x0 0x00400000>, -+ <0x0 0xfe150000 0x0 0x00010000>, -+ <0x0 0xf0000000 0x0 0x00100000>; -+ reg-names = "dbi", "apb", "config"; -+ resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; -+ reset-names = "pwr", "pipe"; -+ status = "disabled"; -+ -+ pcie3x4_intc: legacy-interrupt-controller { -+ interrupt-controller; -+ #address-cells = <0>; -+ #interrupt-cells = <1>; -+ interrupt-parent = <&gic>; -+ interrupts = ; -+ }; -+ }; -+ -+ pcie3x2: pcie@fe160000 { -+ compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ bus-range = <0x10 0x1f>; -+ clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>, -+ <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>, -+ <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>; -+ clock-names = "aclk_mst", "aclk_slv", -+ "aclk_dbi", "pclk", -+ "aux", "pipe"; -+ device_type = "pci"; -+ interrupts = , -+ , -+ , -+ , -+ ; -+ interrupt-names = "sys", "pmc", "msg", "legacy", "err"; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0 0 0 1 &pcie3x2_intc 0>, -+ <0 0 0 2 &pcie3x2_intc 1>, -+ <0 0 0 3 &pcie3x2_intc 2>, -+ <0 0 0 4 &pcie3x2_intc 3>; -+ linux,pci-domain = <1>; -+ max-link-speed = <3>; -+ msi-map = <0x1000 &its1 0x1000 0x1000>; -+ num-lanes = <2>; -+ phys = <&pcie30phy>; -+ phy-names = "pcie-phy"; -+ power-domains = <&power RK3588_PD_PCIE>; -+ ranges = <0x01000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x00100000>, -+ <0x02000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00e00000>, -+ <0x03000000 0x0 0x40000000 0x9 0x40000000 0x0 0x40000000>; -+ reg = <0xa 0x40400000 0x0 0x00400000>, -+ <0x0 0xfe160000 0x0 0x00010000>, -+ <0x0 0xf1000000 0x0 0x00100000>; -+ reg-names = "dbi", "apb", "config"; -+ resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>; -+ reset-names = "pwr", "pipe"; -+ status = "disabled"; -+ -+ pcie3x2_intc: legacy-interrupt-controller { -+ interrupt-controller; -+ #address-cells = <0>; -+ #interrupt-cells = <1>; -+ interrupt-parent = <&gic>; -+ interrupts = ; -+ }; -+ }; -+ - pcie2x1l0: pcie@fe170000 { - compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; - #address-cells = <3>; -@@ -218,4 +325,17 @@ combphy1_ps: phy@fee10000 { - rockchip,pipe-phy-grf = <&pipe_phy1_grf>; - status = "disabled"; - }; -+ -+ pcie30phy: phy@fee80000 { -+ compatible = "rockchip,rk3588-pcie3-phy"; -+ reg = <0x0 0xfee80000 0x0 0x20000>; -+ #phy-cells = <0>; -+ clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>; -+ clock-names = "pclk"; -+ resets = <&cru SRST_PCIE30_PHY>; -+ reset-names = "phy"; -+ rockchip,pipe-grf = <&php_grf>; -+ rockchip,phy-grf = <&pcie30_phy_grf>; -+ status = "disabled"; -+ }; - }; --- -2.41.0 - - -From dfd2816658f3c3eceb0c3fb3c71fb409861571fb Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Thu, 23 Mar 2023 12:27:19 +0000 -Subject: [PATCH 8/9] arm64: defconfig: enable RK3588 PCIe support - -Add support for RK3588 PCIe, which is used for ethernet by -many boards. Note, that this involves two different PHY -drivers, because the SoC has some PCIe v3 controllers and -some PCIe v2 controllers. - -Signed-off-by: Sebastian Reichel ---- - arch/arm64/configs/defconfig | 3 +++ - 1 file changed, 3 insertions(+) - -diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig -index 0777bcae9104..50a127bb6299 100644 ---- a/arch/arm64/configs/defconfig -+++ b/arch/arm64/configs/defconfig -@@ -221,6 +221,7 @@ CONFIG_PCIE_ALTERA=y - CONFIG_PCIE_ALTERA_MSI=y - CONFIG_PCI_HOST_THUNDER_PEM=y - CONFIG_PCI_HOST_THUNDER_ECAM=y -+CONFIG_PCIE_ROCKCHIP_DW_HOST=y - CONFIG_PCIE_ROCKCHIP_HOST=m - CONFIG_PCIE_MEDIATEK_GEN3=m - CONFIG_PCIE_BRCMSTB=m -@@ -1388,7 +1389,9 @@ CONFIG_PHY_ROCKCHIP_EMMC=y - CONFIG_PHY_ROCKCHIP_INNO_HDMI=m - CONFIG_PHY_ROCKCHIP_INNO_USB2=y - CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=m -+CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y - CONFIG_PHY_ROCKCHIP_PCIE=m -+CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=m - CONFIG_PHY_ROCKCHIP_TYPEC=y - CONFIG_PHY_SAMSUNG_UFS=y - CONFIG_PHY_UNIPHIER_USB2=y --- -2.41.0 - - -From f44dcdc5fd4f9e7f70e359033c6f5f467f15c9c1 Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Tue, 25 Jul 2023 15:47:18 +0200 -Subject: [PATCH 9/9] arm64: defconfig: enable Synopsys AHCI SATA support - -Enable support for the DesignWare AHCI Host Controller. It is used -by recent Rockchip SoCs. - -Signed-off-by: Sebastian Reichel ---- - arch/arm64/configs/defconfig | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig -index 50a127bb6299..32ea406360fd 100644 ---- a/arch/arm64/configs/defconfig -+++ b/arch/arm64/configs/defconfig -@@ -299,6 +299,7 @@ CONFIG_SATA_AHCI=y - CONFIG_SATA_AHCI_PLATFORM=y - CONFIG_AHCI_BRCM=m - CONFIG_AHCI_CEVA=y -+CONFIG_AHCI_DWC=m - CONFIG_AHCI_MVEBU=y - CONFIG_AHCI_XGENE=y - CONFIG_AHCI_QORIQ=y --- -2.41.0 -