diff --git a/patch/kernel/pine64-dev/spi-sun6i-allow-large-transfers.patch b/patch/kernel/pine64-dev/spi-sun6i-allow-large-transfers.patch
index e54dfb3b20..4dbf46ad8a 100644
--- a/patch/kernel/pine64-dev/spi-sun6i-allow-large-transfers.patch
+++ b/patch/kernel/pine64-dev/spi-sun6i-allow-large-transfers.patch
@@ -1,8 +1,8 @@
 diff --git a/drivers/spi/spi-sun6i.c b/drivers/spi/spi-sun6i.c
-index e3114832c485..6e9ca93db9bf 100644
+index e3114832..03a773a9 100644
 --- a/drivers/spi/spi-sun6i.c
 +++ b/drivers/spi/spi-sun6i.c
-@@ -46,13 +46,19 @@ 
+@@ -46,13 +46,19 @@
  #define SUN6I_TFR_CTL_XCH			BIT(31)
  
  #define SUN6I_INT_CTL_REG		0x10
@@ -22,7 +22,7 @@ index e3114832c485..6e9ca93db9bf 100644
  #define SUN6I_FIFO_CTL_TF_RST			BIT(31)
  
  #define SUN6I_FIFO_STA_REG		0x1c
-@@ -68,14 +74,16 @@ 
+@@ -68,14 +74,16 @@
  #define SUN6I_CLK_CTL_CDR1(div)			(((div) & SUN6I_CLK_CTL_CDR1_MASK) << 8)
  #define SUN6I_CLK_CTL_DRS			BIT(12)
  
@@ -42,7 +42,7 @@ index e3114832c485..6e9ca93db9bf 100644
  
  #define SUN6I_TXDATA_REG		0x200
  #define SUN6I_RXDATA_REG		0x300
-@@ -105,6 +113,31 @@  static inline void sun6i_spi_write(struct sun6i_spi *sspi, u32 reg, u32 value)
+@@ -105,6 +113,31 @@ static inline void sun6i_spi_write(struct sun6i_spi *sspi, u32 reg, u32 value)
  	writel(value, sspi->base_addr + reg);
  }
  
@@ -74,7 +74,7 @@ index e3114832c485..6e9ca93db9bf 100644
  static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi, int len)
  {
  	u32 reg, cnt;
-@@ -127,10 +160,13 @@  static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi, int len)
+@@ -127,10 +160,13 @@ static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi, int len)
  
  static inline void sun6i_spi_fill_fifo(struct sun6i_spi *sspi, int len)
  {
@@ -90,7 +90,18 @@ index e3114832c485..6e9ca93db9bf 100644
  
  	while (len--) {
  		byte = sspi->tx_buf ? *sspi->tx_buf++ : 0;
-@@ -170,12 +206,12 @@  static int sun6i_spi_transfer_one(struct spi_master *master,
+@@ -158,9 +194,7 @@ static void sun6i_spi_set_cs(struct spi_device *spi, bool enable)
+ 
+ static size_t sun6i_spi_max_transfer_size(struct spi_device *spi)
+ {
+-	struct sun6i_spi *sspi = spi_master_get_devdata(spi->master);
+-
+-	return sspi->fifo_depth - 1;
++	return SUN6I_MAX_XFER_SIZE - 1;
+ }
+ 
+ static int sun6i_spi_transfer_one(struct spi_master *master,
+@@ -170,12 +204,12 @@ static int sun6i_spi_transfer_one(struct spi_master *master,
  	struct sun6i_spi *sspi = spi_master_get_devdata(master);
  	unsigned int mclk_rate, div, timeout;
  	unsigned int start, end, tx_time;
@@ -105,7 +116,7 @@ index e3114832c485..6e9ca93db9bf 100644
  		return -EINVAL;
  
  	reinit_completion(&sspi->done);
-@@ -191,6 +227,17 @@  static int sun6i_spi_transfer_one(struct spi_master *master,
+@@ -191,6 +225,17 @@ static int sun6i_spi_transfer_one(struct spi_master *master,
  			SUN6I_FIFO_CTL_RF_RST | SUN6I_FIFO_CTL_TF_RST);
  
  	/*
@@ -123,7 +134,7 @@ index e3114832c485..6e9ca93db9bf 100644
  	 * Setup the transfer control register: Chip Select,
  	 * polarities, etc.
  	 */
-@@ -274,6 +321,10 @@  static int sun6i_spi_transfer_one(struct spi_master *master,
+@@ -274,6 +319,10 @@ static int sun6i_spi_transfer_one(struct spi_master *master,
  
  	/* Enable the interrupts */
  	sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, SUN6I_INT_CTL_TC);
@@ -134,7 +145,7 @@ index e3114832c485..6e9ca93db9bf 100644
  
  	/* Start the transfer */
  	reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
-@@ -293,8 +344,6 @@  static int sun6i_spi_transfer_one(struct spi_master *master,
+@@ -293,8 +342,6 @@ static int sun6i_spi_transfer_one(struct spi_master *master,
  		goto out;
  	}
  
@@ -143,7 +154,7 @@ index e3114832c485..6e9ca93db9bf 100644
  out:
  	sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, 0);
  
-@@ -309,10 +358,33 @@  static irqreturn_t sun6i_spi_handler(int irq, void *dev_id)
+@@ -309,10 +356,33 @@ static irqreturn_t sun6i_spi_handler(int irq, void *dev_id)
  	/* Transfer complete */
  	if (status & SUN6I_INT_CTL_TC) {
  		sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TC);
@@ -177,4 +188,3 @@ index e3114832c485..6e9ca93db9bf 100644
  	return IRQ_NONE;
  }
  
-
diff --git a/patch/kernel/sun50iw2-dev/spi-sun6i-allow-large-transfers.patch b/patch/kernel/sun50iw2-dev/spi-sun6i-allow-large-transfers.patch
index e54dfb3b20..4dbf46ad8a 100644
--- a/patch/kernel/sun50iw2-dev/spi-sun6i-allow-large-transfers.patch
+++ b/patch/kernel/sun50iw2-dev/spi-sun6i-allow-large-transfers.patch
@@ -1,8 +1,8 @@
 diff --git a/drivers/spi/spi-sun6i.c b/drivers/spi/spi-sun6i.c
-index e3114832c485..6e9ca93db9bf 100644
+index e3114832..03a773a9 100644
 --- a/drivers/spi/spi-sun6i.c
 +++ b/drivers/spi/spi-sun6i.c
-@@ -46,13 +46,19 @@ 
+@@ -46,13 +46,19 @@
  #define SUN6I_TFR_CTL_XCH			BIT(31)
  
  #define SUN6I_INT_CTL_REG		0x10
@@ -22,7 +22,7 @@ index e3114832c485..6e9ca93db9bf 100644
  #define SUN6I_FIFO_CTL_TF_RST			BIT(31)
  
  #define SUN6I_FIFO_STA_REG		0x1c
-@@ -68,14 +74,16 @@ 
+@@ -68,14 +74,16 @@
  #define SUN6I_CLK_CTL_CDR1(div)			(((div) & SUN6I_CLK_CTL_CDR1_MASK) << 8)
  #define SUN6I_CLK_CTL_DRS			BIT(12)
  
@@ -42,7 +42,7 @@ index e3114832c485..6e9ca93db9bf 100644
  
  #define SUN6I_TXDATA_REG		0x200
  #define SUN6I_RXDATA_REG		0x300
-@@ -105,6 +113,31 @@  static inline void sun6i_spi_write(struct sun6i_spi *sspi, u32 reg, u32 value)
+@@ -105,6 +113,31 @@ static inline void sun6i_spi_write(struct sun6i_spi *sspi, u32 reg, u32 value)
  	writel(value, sspi->base_addr + reg);
  }
  
@@ -74,7 +74,7 @@ index e3114832c485..6e9ca93db9bf 100644
  static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi, int len)
  {
  	u32 reg, cnt;
-@@ -127,10 +160,13 @@  static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi, int len)
+@@ -127,10 +160,13 @@ static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi, int len)
  
  static inline void sun6i_spi_fill_fifo(struct sun6i_spi *sspi, int len)
  {
@@ -90,7 +90,18 @@ index e3114832c485..6e9ca93db9bf 100644
  
  	while (len--) {
  		byte = sspi->tx_buf ? *sspi->tx_buf++ : 0;
-@@ -170,12 +206,12 @@  static int sun6i_spi_transfer_one(struct spi_master *master,
+@@ -158,9 +194,7 @@ static void sun6i_spi_set_cs(struct spi_device *spi, bool enable)
+ 
+ static size_t sun6i_spi_max_transfer_size(struct spi_device *spi)
+ {
+-	struct sun6i_spi *sspi = spi_master_get_devdata(spi->master);
+-
+-	return sspi->fifo_depth - 1;
++	return SUN6I_MAX_XFER_SIZE - 1;
+ }
+ 
+ static int sun6i_spi_transfer_one(struct spi_master *master,
+@@ -170,12 +204,12 @@ static int sun6i_spi_transfer_one(struct spi_master *master,
  	struct sun6i_spi *sspi = spi_master_get_devdata(master);
  	unsigned int mclk_rate, div, timeout;
  	unsigned int start, end, tx_time;
@@ -105,7 +116,7 @@ index e3114832c485..6e9ca93db9bf 100644
  		return -EINVAL;
  
  	reinit_completion(&sspi->done);
-@@ -191,6 +227,17 @@  static int sun6i_spi_transfer_one(struct spi_master *master,
+@@ -191,6 +225,17 @@ static int sun6i_spi_transfer_one(struct spi_master *master,
  			SUN6I_FIFO_CTL_RF_RST | SUN6I_FIFO_CTL_TF_RST);
  
  	/*
@@ -123,7 +134,7 @@ index e3114832c485..6e9ca93db9bf 100644
  	 * Setup the transfer control register: Chip Select,
  	 * polarities, etc.
  	 */
-@@ -274,6 +321,10 @@  static int sun6i_spi_transfer_one(struct spi_master *master,
+@@ -274,6 +319,10 @@ static int sun6i_spi_transfer_one(struct spi_master *master,
  
  	/* Enable the interrupts */
  	sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, SUN6I_INT_CTL_TC);
@@ -134,7 +145,7 @@ index e3114832c485..6e9ca93db9bf 100644
  
  	/* Start the transfer */
  	reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
-@@ -293,8 +344,6 @@  static int sun6i_spi_transfer_one(struct spi_master *master,
+@@ -293,8 +342,6 @@ static int sun6i_spi_transfer_one(struct spi_master *master,
  		goto out;
  	}
  
@@ -143,7 +154,7 @@ index e3114832c485..6e9ca93db9bf 100644
  out:
  	sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, 0);
  
-@@ -309,10 +358,33 @@  static irqreturn_t sun6i_spi_handler(int irq, void *dev_id)
+@@ -309,10 +356,33 @@ static irqreturn_t sun6i_spi_handler(int irq, void *dev_id)
  	/* Transfer complete */
  	if (status & SUN6I_INT_CTL_TC) {
  		sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TC);
@@ -177,4 +188,3 @@ index e3114832c485..6e9ca93db9bf 100644
  	return IRQ_NONE;
  }
  
-
diff --git a/patch/kernel/sun8i-dev/spi-sun6i-allow-large-transfers.patch b/patch/kernel/sun8i-dev/spi-sun6i-allow-large-transfers.patch
index e54dfb3b20..4dbf46ad8a 100644
--- a/patch/kernel/sun8i-dev/spi-sun6i-allow-large-transfers.patch
+++ b/patch/kernel/sun8i-dev/spi-sun6i-allow-large-transfers.patch
@@ -1,8 +1,8 @@
 diff --git a/drivers/spi/spi-sun6i.c b/drivers/spi/spi-sun6i.c
-index e3114832c485..6e9ca93db9bf 100644
+index e3114832..03a773a9 100644
 --- a/drivers/spi/spi-sun6i.c
 +++ b/drivers/spi/spi-sun6i.c
-@@ -46,13 +46,19 @@ 
+@@ -46,13 +46,19 @@
  #define SUN6I_TFR_CTL_XCH			BIT(31)
  
  #define SUN6I_INT_CTL_REG		0x10
@@ -22,7 +22,7 @@ index e3114832c485..6e9ca93db9bf 100644
  #define SUN6I_FIFO_CTL_TF_RST			BIT(31)
  
  #define SUN6I_FIFO_STA_REG		0x1c
-@@ -68,14 +74,16 @@ 
+@@ -68,14 +74,16 @@
  #define SUN6I_CLK_CTL_CDR1(div)			(((div) & SUN6I_CLK_CTL_CDR1_MASK) << 8)
  #define SUN6I_CLK_CTL_DRS			BIT(12)
  
@@ -42,7 +42,7 @@ index e3114832c485..6e9ca93db9bf 100644
  
  #define SUN6I_TXDATA_REG		0x200
  #define SUN6I_RXDATA_REG		0x300
-@@ -105,6 +113,31 @@  static inline void sun6i_spi_write(struct sun6i_spi *sspi, u32 reg, u32 value)
+@@ -105,6 +113,31 @@ static inline void sun6i_spi_write(struct sun6i_spi *sspi, u32 reg, u32 value)
  	writel(value, sspi->base_addr + reg);
  }
  
@@ -74,7 +74,7 @@ index e3114832c485..6e9ca93db9bf 100644
  static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi, int len)
  {
  	u32 reg, cnt;
-@@ -127,10 +160,13 @@  static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi, int len)
+@@ -127,10 +160,13 @@ static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi, int len)
  
  static inline void sun6i_spi_fill_fifo(struct sun6i_spi *sspi, int len)
  {
@@ -90,7 +90,18 @@ index e3114832c485..6e9ca93db9bf 100644
  
  	while (len--) {
  		byte = sspi->tx_buf ? *sspi->tx_buf++ : 0;
-@@ -170,12 +206,12 @@  static int sun6i_spi_transfer_one(struct spi_master *master,
+@@ -158,9 +194,7 @@ static void sun6i_spi_set_cs(struct spi_device *spi, bool enable)
+ 
+ static size_t sun6i_spi_max_transfer_size(struct spi_device *spi)
+ {
+-	struct sun6i_spi *sspi = spi_master_get_devdata(spi->master);
+-
+-	return sspi->fifo_depth - 1;
++	return SUN6I_MAX_XFER_SIZE - 1;
+ }
+ 
+ static int sun6i_spi_transfer_one(struct spi_master *master,
+@@ -170,12 +204,12 @@ static int sun6i_spi_transfer_one(struct spi_master *master,
  	struct sun6i_spi *sspi = spi_master_get_devdata(master);
  	unsigned int mclk_rate, div, timeout;
  	unsigned int start, end, tx_time;
@@ -105,7 +116,7 @@ index e3114832c485..6e9ca93db9bf 100644
  		return -EINVAL;
  
  	reinit_completion(&sspi->done);
-@@ -191,6 +227,17 @@  static int sun6i_spi_transfer_one(struct spi_master *master,
+@@ -191,6 +225,17 @@ static int sun6i_spi_transfer_one(struct spi_master *master,
  			SUN6I_FIFO_CTL_RF_RST | SUN6I_FIFO_CTL_TF_RST);
  
  	/*
@@ -123,7 +134,7 @@ index e3114832c485..6e9ca93db9bf 100644
  	 * Setup the transfer control register: Chip Select,
  	 * polarities, etc.
  	 */
-@@ -274,6 +321,10 @@  static int sun6i_spi_transfer_one(struct spi_master *master,
+@@ -274,6 +319,10 @@ static int sun6i_spi_transfer_one(struct spi_master *master,
  
  	/* Enable the interrupts */
  	sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, SUN6I_INT_CTL_TC);
@@ -134,7 +145,7 @@ index e3114832c485..6e9ca93db9bf 100644
  
  	/* Start the transfer */
  	reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
-@@ -293,8 +344,6 @@  static int sun6i_spi_transfer_one(struct spi_master *master,
+@@ -293,8 +342,6 @@ static int sun6i_spi_transfer_one(struct spi_master *master,
  		goto out;
  	}
  
@@ -143,7 +154,7 @@ index e3114832c485..6e9ca93db9bf 100644
  out:
  	sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, 0);
  
-@@ -309,10 +358,33 @@  static irqreturn_t sun6i_spi_handler(int irq, void *dev_id)
+@@ -309,10 +356,33 @@ static irqreturn_t sun6i_spi_handler(int irq, void *dev_id)
  	/* Transfer complete */
  	if (status & SUN6I_INT_CTL_TC) {
  		sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TC);
@@ -177,4 +188,3 @@ index e3114832c485..6e9ca93db9bf 100644
  	return IRQ_NONE;
  }
  
-