From 0c65b422d4717d8c68615928a7dd835cab86d7ac Mon Sep 17 00:00:00 2001 From: Igor Pecovnik Date: Mon, 11 Apr 2016 12:50:21 +0200 Subject: [PATCH] Added Hummingboard 2 to legacy kernel, bugfixes to boot script and removing BT loading from defaults --- boards.sh | 2 +- config/boot-cubox.cmd | 3 +- patch/kernel/cubox-default/hb2.patch | 1129 ++++++++++++++++++++++++++ 3 files changed, 1132 insertions(+), 2 deletions(-) create mode 100644 patch/kernel/cubox-default/hb2.patch diff --git a/boards.sh b/boards.sh index 7c23f65024..8def83fc42 100644 --- a/boards.sh +++ b/boards.sh @@ -110,7 +110,7 @@ install_board_specific (){ cp $SRC/lib/scripts/brcm4330 $CACHEDIR/sdcard/etc/default cp $SRC/lib/scripts/brcm4330-patch $CACHEDIR/sdcard/etc/init.d chroot $CACHEDIR/sdcard /bin/bash -c "chmod +x /etc/init.d/brcm4330-patch" - chroot $CACHEDIR/sdcard /bin/bash -c "LC_ALL=C LANG=C update-rc.d brcm4330-patch defaults>> /dev/null" + #chroot $CACHEDIR/sdcard /bin/bash -c "LC_ALL=C LANG=C update-rc.d brcm4330-patch defaults>> /dev/null" fi diff --git a/config/boot-cubox.cmd b/config/boot-cubox.cmd index b7c5416a33..00965fa8b9 100644 --- a/config/boot-cubox.cmd +++ b/config/boot-cubox.cmd @@ -1,5 +1,6 @@ +run autodetectfdt setenv bootargs "root=/dev/mmcblk0p1 rootfstype=ext4 rootwait console=ttymxc0,115200 console=tty1 video=mxcfb0:dev=hdmi,1920x1080M@60,if=RGB24,bpp=32 rd.dm=0 rd.luks=0 rd.lvm=0 raid=noautodetect pci=nomsi ahci_imx.hotplug=1 consoleblank=0 vt.global_cursor_default=0 quiet loglevel=1" -ext2load mmc 0 ${fdt_addr} /boot/dtb/${fdt_file} || fatload mmc 0 ${fdt_addr} /dtb/${fdtfile} || ext4load mmc 0 ${fdt_addr} /dtb/${fdtfile} +ext2load mmc 0 ${fdt_addr} /boot/dtb/${fdt_file} || fatload mmc 0 ${fdt_addr} /dtb/${fdt_file} || ext4load mmc 0 ${fdt_addr} /dtb/${fdt_file} ext2load mmc 0 ${loadaddr} /boot/zImage || fatload mmc 0 ${loadaddr} zImage || ext4load mmc 0 ${loadaddr} zImage bootz ${loadaddr} - ${fdt_addr} # Recompile with: diff --git a/patch/kernel/cubox-default/hb2.patch b/patch/kernel/cubox-default/hb2.patch new file mode 100644 index 0000000000..0997a79c8d --- /dev/null +++ b/patch/kernel/cubox-default/hb2.patch @@ -0,0 +1,1129 @@ +diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile +index f363929..2b24748 100644 +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -160,6 +160,7 @@ dtb-$(CONFIG_ARCH_MXC) += \ + imx6dl-gw53xx.dtb \ + imx6dl-gw54xx.dtb \ + imx6dl-hummingboard.dtb \ ++ imx6dl-hummingboard2.dtb \ + imx6dl-nitrogen6x.dtb \ + imx6dl-phytec-pbab01.dtb \ + imx6dl-sabreauto.dtb \ +@@ -171,6 +172,7 @@ dtb-$(CONFIG_ARCH_MXC) += \ + imx6q-cm-fx6.dtb \ + imx6q-cubox-i.dtb \ + imx6q-hummingboard.dtb \ ++ imx6q-hummingboard2.dtb \ + imx6q-dfi-fs700-m60.dtb \ + imx6q-dmo-edmqmx6.dtb \ + imx6q-gk802.dtb \ +diff --git a/arch/arm/boot/dts/imx6dl-hummingboard2.dts b/arch/arm/boot/dts/imx6dl-hummingboard2.dts +new file mode 100644 +index 0000000..990b505 +--- /dev/null ++++ b/arch/arm/boot/dts/imx6dl-hummingboard2.dts +@@ -0,0 +1,52 @@ ++/* ++ * Device Tree file for SolidRun HummingBoard2 ++ * Copyright (C) 2015 Rabeeh Khoury ++ * Based on work by Russell King ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This file is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License. ++ * ++ * This file is distributed in the hope that it will be useful ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++/dts-v1/; ++ ++#include "imx6dl.dtsi" ++#include "imx6qdl-hummingboard2.dtsi" ++ ++/ { ++ model = "SolidRun HummingBoard2 Solo/DualLite"; ++ compatible = "solidrun,hummingboard2/dl", "fsl,imx6dl"; ++}; +diff --git a/arch/arm/boot/dts/imx6q-hummingboard2.dts b/arch/arm/boot/dts/imx6q-hummingboard2.dts +new file mode 100644 +index 0000000..f5eec91 +--- /dev/null ++++ b/arch/arm/boot/dts/imx6q-hummingboard2.dts +@@ -0,0 +1,60 @@ ++/* ++ * Device Tree file for SolidRun HummingBoard2 ++ * Copyright (C) 2015 Rabeeh Khoury ++ * Based on work by Russell King ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This file is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License. ++ * ++ * This file is distributed in the hope that it will be useful ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++/dts-v1/; ++ ++#include "imx6q.dtsi" ++#include "imx6qdl-hummingboard2.dtsi" ++ ++/ { ++ model = "SolidRun HummingBoard2 Dual/Quad"; ++ compatible = "solidrun,hummingboard2/q", "fsl,imx6q"; ++}; ++ ++&sata { ++ status = "okay"; ++ fsl,transmit-level-mV = <1104>; ++ fsl,transmit-boost-mdB = <0>; ++ fsl,transmit-atten-16ths = <9>; ++ fsl,no-spread-spectrum; ++}; +diff --git a/arch/arm/boot/dts/imx6qdl-hummingboard2.dtsi b/arch/arm/boot/dts/imx6qdl-hummingboard2.dtsi +new file mode 100644 +index 0000000..139d2c4 +--- /dev/null ++++ b/arch/arm/boot/dts/imx6qdl-hummingboard2.dtsi +@@ -0,0 +1,699 @@ ++/* ++ * Device Tree file for SolidRun HummingBoard2 ++ * Copyright (C) 2015 Rabeeh Khoury ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This file is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License. ++ * ++ * This file is distributed in the hope that it will be useful ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++#include "imx6qdl-microsom.dtsi" ++#include "imx6qdl-microsom-ar8035.dtsi" ++ ++/ { ++ aliases { ++ mmc0 = &usdhc2; ++ mxcfb0 = &mxcfb1; ++ mxcfb2 = &mxcfb2; ++ }; ++ ++ chosen { ++ bootargs = "quiet console=ttymxc0,115200 root=/dev/mmcblk0p2 rw"; ++ stdout-path = &uart1; ++ }; ++ ++ ir_recv: ir-receiver { ++ compatible = "gpio-ir-receiver"; ++ gpios = <&gpio7 9 1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_hummingboard2_gpio7_9>; ++ linux,rc-map-name = "rc-rc6-mce"; ++ }; ++ ++ mxcfb1: fb@0 { ++ compatible = "fsl,mxc_sdc_fb"; ++ disp_dev = "hdmi"; ++ interface_pix_fmt = "RGB24"; ++ mode_str ="1920x1080M@60"; ++ default_bpp = <32>; ++ int_clk = <0>; ++ late_init = <0>; ++ status = "okay"; ++ }; ++ ++ mxcfb2: fb@1 { ++ compatible = "fsl,mxc_sdc_fb"; ++ disp_dev = "ldb"; ++ interface_pix_fmt = "RGB666"; ++ default_bpp = <16>; ++ int_clk = <0>; ++ late_init = <0>; ++ status = "disabled"; ++ }; ++ ++ regulators { ++ compatible = "simple-bus"; ++ ++ reg_3p3v: 3p3v { ++ compatible = "regulator-fixed"; ++ regulator-name = "3P3V"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ }; ++ ++ reg_1p8v: 1p8v { ++ compatible = "regulator-fixed"; ++ regulator-name = "1P8V"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ }; ++ ++ reg_usbh1_vbus: usb-h1-vbus { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio1 0 0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_hummingboard2_usbh1_vbus>; ++ regulator-name = "usb_h1_vbus"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ }; ++ ++ reg_usbotg_vbus: usb-otg-vbus { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio3 22 0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_hummingboard2_usbotg_vbus>; ++ regulator-name = "usb_otg_vbus"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ }; ++ ++ reg_usbh2_vbus: usb-h2-vbus { ++ compatible = "regulator-gpio"; ++ enable-active-high; ++ enable-gpio = <&gpio2 13 0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_hummingboard2_usbh2_vbus>; ++ regulator-name = "usb_h2_vbus"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-boot-on; ++ }; ++ ++ reg_usbh3_vbus: usb-h3-vbus { ++ compatible = "regulator-gpio"; ++ enable-active-high; ++ enable-gpio = <&gpio7 10 0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_hummingboard2_usbh3_vbus>; ++ regulator-name = "usb_h3_vbus"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-boot-on; ++ }; ++ ++ reg_usdhc2_vbus: usdhc-2-vbus { ++ compatible = "regulator-fixed"; ++ regulator-name = "USDHC2-VBUS"; ++ gpio = <&gpio4 30 0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_hummingboard2_usdhc2_pwr>; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ }; ++ }; ++ ++ sound-sgtl5000 { ++ audio-codec = <&sgtl5000>; ++ audio-routing = ++ "MIC_IN", "Mic Jack", ++ "Mic Jack", "Mic Bias", ++ "Headphone Jack", "HP_OUT"; ++ compatible = "fsl,imx-audio-sgtl5000"; ++ model = "On-board Codec"; ++ mux-ext-port = <5>; ++ mux-int-port = <1>; ++ cpu-dai = <&ssi1>; ++ }; ++ ++ sound-hdmi { ++ compatible = "fsl,imx6q-audio-hdmi", ++ "fsl,imx-audio-hdmi"; ++ model = "imx-audio-hdmi"; ++ hdmi-controller = <&hdmi_audio>; ++ }; ++ ++ v4l2_cap_0 { ++ compatible = "fsl,imx6q-v4l2-capture"; ++ ipu_id = <0>; ++ csi_id = <1>; ++ mclk_source = <0>; ++ mipi_camera = <1>; ++ default_input = <0>; ++ status = "okay"; ++ }; ++ ++ v4l2_out { ++ compatible = "fsl,mxc_v4l2_output"; ++ status = "okay"; ++ }; ++}; ++ ++&audmux { ++ status = "okay"; ++}; ++ ++&dcic1 { ++ dcic_id = <0>; ++ dcic_mux = "dcic-hdmi"; ++ status = "okay"; ++}; ++ ++&dcic2 { ++ dcic_id = <1>; ++ dcic_mux = "dcic-lvds1"; ++ status = "okay"; ++}; ++ ++&ecspi2 { ++ fsl,spi-num-chipselects = <1>; ++ cs-gpios = <&gpio2 26 0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_hummingboard2_ecspi2>; ++ status = "okay"; ++ ++ spidev0: spi@0 { ++ compatible = "spidev"; ++ reg = <0>; ++ spi-max-frequency = <20000000>; ++ }; ++}; ++ ++&gpc { ++ fsl,cpu_pupscr_sw2iso = <0xf>; ++ fsl,cpu_pupscr_sw = <0xf>; ++ fsl,cpu_pdnscr_iso2sw = <0x1>; ++ fsl,cpu_pdnscr_iso = <0x1>; ++}; ++ ++&hdmi_core { ++ ipu_id = <0>; ++ disp_id = <0>; ++ status = "okay"; ++}; ++ ++&hdmi_video { ++ fsl,phy_reg_vlev = <0x0294>; ++ fsl,phy_reg_cksymtx = <0x800d>; ++ status = "okay"; ++}; ++ ++&hdmi_audio { ++ status = "okay"; ++}; ++ ++&hdmi_cec { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_hummingboard2_hdmi>; ++ status = "okay"; ++}; ++ ++&i2c1 { ++ clock-frequency = <100000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_hummingboard2_i2c1>; ++ status = "okay"; ++ ++ ov5640_mipi: ov5640_mipi@3c { ++ compatible = "ovti,ov5640_mipi"; ++ reg = <0x3c>; ++ clocks = <&clks IMX6QDL_CLK_CKO2>; ++ clock-names = "csi_mclk"; ++/* ++ DOVDD-supply = <®_3p3v>; ++ AVDD-supply = <®_3p3v>; ++ DVDD-supply = <®_3p3v>; ++*/ ++ pwn-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; ++ rst-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; ++ ipu_id = <0>; ++ csi_id = <1>; ++ mclk = <24000000>; ++ mclk_source = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_hummingboard2_mipi>; ++ extended-buffer; ++ }; ++ ++ rtc: pcf8523@68 { ++ compatible = "nxp,pcf8523"; ++ reg = <0x68>; ++ nxp,12p5_pf; ++ }; ++ ++ sgtl5000: sgtl5000@0a { ++ compatible = "fsl,sgtl5000"; ++ reg = <0x0a>; ++ clocks = <&clks IMX6QDL_CLK_CKO>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_hummingboard2_sgtl5000>; ++ VDDA-supply = <®_3p3v>; ++ VDDIO-supply = <®_3p3v>; ++ }; ++}; ++ ++&i2c2 { ++ clock-frequency = <100000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_hummingboard2_i2c2>; ++ status = "okay"; ++ ++ ddc: imx6_hdmi_i2c@50 { ++ compatible = "fsl,imx6-hdmi-i2c"; ++ reg = <0x50>; ++ }; ++}; ++ ++&i2c3 { ++ clock-frequency = <100000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_hummingboard2_i2c3>; ++ status = "okay"; ++}; ++ ++&iomuxc { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_hog>; ++ hummingboard2 { ++ pinctrl_hog: hoggrp { ++ fsl,pins = < ++ /* ++ * 36 pin headers GPIO description. The pins ++ * numbering as following - ++ * ++ * 3.2v 5v 74 75 ++ * 73 72 71 70 ++ * 69 68 67 66 ++ * ++ * 77 78 79 76 ++ * 65 64 61 60 ++ * 53 52 51 50 ++ * 49 48 166 132 ++ * 95 94 90 91 ++ * GND 54 24 204 ++ * ++ * The GPIO numbers can be extracted using ++ * signal name from below. ++ * Example - ++ * MX6QDL_PAD_EIM_DA10__GPIO3_IO10 is ++ * GPIO(3,10) which is (3-1)*32+10 = gpio 74 ++ * ++ * i.e. The mapping of GPIO(X,Y) to Linux gpio ++ * number is : gpio number = (X-1) * 32 + Y ++ */ ++ /* DI1_PIN15 */ ++ MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x400130b1 ++ /* DI1_PIN02 */ ++ MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x400130b1 ++ /* DISP1_DATA00 */ ++ MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x400130b1 ++ /* DISP1_DATA01 */ ++ MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x400130b1 ++ /* DISP1_DATA02 */ ++ MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x400130b1 ++ /* DISP1_DATA03 */ ++ MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x400130b1 ++ /* DISP1_DATA04 */ ++ MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x400130b1 ++ /* DISP1_DATA05 */ ++ MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x400130b1 ++ /* DISP1_DATA06 */ ++ MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x400130b1 ++ /* DISP1_DATA07 */ ++ MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x400130b1 ++ /* DI1_D0_CS */ ++ MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x400130b1 ++ /* DI1_D1_CS */ ++ MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x400130b1 ++ /* DI1_PIN01 */ ++ MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x400130b1 ++ /* DI1_PIN03 */ ++ MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x400130b1 ++ /* DISP1_DATA08 */ ++ MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x400130b1 ++ /* DISP1_DATA09 */ ++ MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x400130b1 ++ /* DISP1_DATA10 */ ++ MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x400130b1 ++ /* DISP1_DATA11 */ ++ MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x400130b1 ++ /* DISP1_DATA12 */ ++ MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x400130b1 ++ /* DISP1_DATA13 */ ++ MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x400130b1 ++ /* DISP1_DATA14 */ ++ MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x400130b1 ++ /* DISP1_DATA15 */ ++ MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x400130b1 ++ /* DISP1_DATA16 */ ++ MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x400130b1 ++ /* DISP1_DATA17 */ ++ MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x400130b1 ++ /* DISP1_DATA18 */ ++ MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x400130b1 ++ /* DISP1_DATA19 */ ++ MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x400130b1 ++ /* DISP1_DATA20 */ ++ MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x400130b1 ++ /* DISP1_DATA21 */ ++ MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x400130b1 ++ /* DISP1_DATA22 */ ++ MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x400130b1 ++ /* DISP1_DATA23 */ ++ MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x400130b1 ++ /* DI1_DISP_CLK */ ++ MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x400130b1 ++ /* SPDIF_IN */ ++ MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x400130b1 ++ /* SPDIF_OUT */ ++ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x400130b1 ++ ++ /* MikroBUS GPIO pin number 10 */ ++ MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x400130b1 ++ >; ++ }; ++ ++ pinctrl_hummingboard2_gpio7_9: hummingboard2-gpio7_9 { ++ fsl,pins = < ++ MX6QDL_PAD_SD4_CMD__GPIO7_IO09 0x80000000 ++ >; ++ }; ++ ++ pinctrl_hummingboard2_hdmi: hummingboard2-hdmi { ++ fsl,pins = < ++ MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 ++ >; ++ }; ++ ++ pinctrl_hummingboard2_i2c1: hummingboard2-i2c1 { ++ fsl,pins = < ++ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 ++ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 ++ >; ++ }; ++ ++ pinctrl_hummingboard2_i2c2: hummingboard2-i2c2 { ++ fsl,pins = < ++ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 ++ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 ++ >; ++ }; ++ ++ pinctrl_hummingboard2_i2c3: hummingboard2-i2c3 { ++ fsl,pins = < ++ MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 ++ MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 ++ >; ++ }; ++ ++ pinctrl_hummingboard2_mipi: hummingboard2_mipi { ++ fsl,pins = < ++ MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x4001b8b1 ++ MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x4001b8b1 ++ MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x130b0 ++ >; ++ }; ++ ++ pinctrl_hummingboard2_pcie_reset: hummingboard2-pcie-reset { ++ fsl,pins = < ++ MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b1 ++ >; ++ }; ++ ++ pinctrl_hummingboard2_pwm1: pwm1grp { ++ fsl,pins = < ++ MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b1 ++ >; ++ }; ++ ++ pinctrl_hummingboard2_sgtl5000: hummingboard2-sgtl5000 { ++ fsl,pins = < ++ MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 ++ MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 ++ MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0 ++ MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 ++ MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0 ++ >; ++ }; ++ ++ pinctrl_hummingboard2_usbh1_vbus: hummingboard2-usbh1-vbus { ++ fsl,pins = ; ++ }; ++ ++ pinctrl_hummingboard2_usbh2_vbus: hummingboard2-usbh2-vbus { ++ fsl,pins = ; ++ }; ++ ++ pinctrl_hummingboard2_usbh3_vbus: hummingboard2-usbh3-vbus { ++ fsl,pins = ; ++ }; ++ ++ pinctrl_hummingboard2_usbotg_id: hummingboard2-usbotg-id { ++ /* ++ * Similar to pinctrl_usbotg_2, but we want it ++ * pulled down for a fixed host connection. ++ */ ++ fsl,pins = ; ++ }; ++ ++ pinctrl_hummingboard2_usbotg_vbus: hummingboard2-usbotg-vbus { ++ fsl,pins = ; ++ }; ++ ++ pinctrl_hummingboard2_usdhc2_pwr: hummingboard2-usdhc2-pwr { ++ fsl,pins = ; ++ }; ++ ++ pinctrl_hummingboard2_usdhc2_aux: hummingboard2-usdhc2-aux { ++ fsl,pins = < ++ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x13071 ++ MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x1b071 ++ >; ++ }; ++ ++ pinctrl_hummingboard2_usdhc2: hummingboard2-usdhc2 { ++ fsl,pins = < ++ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 ++ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 ++ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 ++ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 ++ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 ++ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059 ++ >; ++ }; ++ ++ pinctrl_hummingboard2_usdhc2_100mhz: hummingboard2-usdhc2-100mhz { ++ fsl,pins = < ++ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 ++ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 ++ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 ++ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 ++ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 ++ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x130b9 ++ >; ++ }; ++ ++ pinctrl_hummingboard2_usdhc2_200mhz: hummingboard2-usdhc2-200mhz { ++ fsl,pins = < ++ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9 ++ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9 ++ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 ++ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 ++ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 ++ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x130f9 ++ >; ++ }; ++ ++ pinctrl_hummingboard2_usdhc3: hummingboard2-usdhc3 { ++ fsl,pins = < ++ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 ++ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 ++ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 ++ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 ++ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 ++ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 ++ MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 ++ MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 ++ MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 ++ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 ++ MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059 ++ >; ++ }; ++ pinctrl_hummingboard2_uart3: hummingboard2-uart3 { ++ fsl,pins = < ++ MX6QDL_PAD_EIM_D25__UART3_TX_DATA 0x1b0b1 ++ MX6QDL_PAD_EIM_D24__UART3_RX_DATA 0x40013000 ++ >; ++ }; ++ pinctrl_hummingboard2_ecspi2: hummingboard2-ecspi2grp { ++ fsl,pins = < ++ MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 ++ MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 ++ MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 ++ MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1 /* CS */ ++ >; ++ }; ++ }; ++}; ++ ++&ldb { ++ status = "disabled"; ++ ++ lvds-channel@0 { ++ fsl,data-mapping = "spwg"; ++ fsl,data-width = <18>; ++ crtc = "ipu2-di0"; ++ primary; ++ ++ display-timings { ++ native-mode = <&timing0>; ++ timing0: hsd100pxn1 { ++ clock-frequency = <65000000>; ++ hactive = <1024>; ++ vactive = <768>; ++ hback-porch = <220>; ++ hfront-porch = <40>; ++ vback-porch = <21>; ++ vfront-porch = <7>; ++ hsync-len = <60>; ++ vsync-len = <10>; ++ }; ++ }; ++ }; ++}; ++ ++&mipi_csi { ++ ipu_id = <0>; ++ csi_id = <1>; ++ v_channel = <0>; ++ lanes = <2>; ++ mipi_dphy_clk = <0x14>; ++ status = "okay"; ++}; ++ ++&pcie { ++ pinctrl-names = "default"; ++ pinctrl-0 = < ++ &pinctrl_hummingboard2_pcie_reset ++ >; ++ reset-gpio = <&gpio2 11 0>; ++ status = "okay"; ++ no-msi; ++}; ++ ++&pwm1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_hummingboard2_pwm1>; ++ status = "okay"; ++}; ++ ++&pwm3 { ++ status = "disabled"; ++}; ++ ++&pwm4 { ++ status = "disabled"; ++}; ++ ++&ssi1 { ++ fsl,mode = "i2s-slave"; ++ status = "okay"; ++}; ++ ++&usbh1 { ++ disable-over-current; ++ vbus-supply = <®_usbh1_vbus>; ++ status = "okay"; ++}; ++ ++&usbotg { ++ disable-over-current; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_hummingboard2_usbotg_id>; ++ vbus-supply = <®_usbotg_vbus>; ++ status = "okay"; ++}; ++ ++&usdhc2 { ++ pinctrl-names = "default", "state_100mhz", "state_200mhz"; ++ pinctrl-0 = < ++ &pinctrl_hummingboard2_usdhc2_aux ++ &pinctrl_hummingboard2_usdhc2 ++ >; ++ pinctrl-1 = < ++ &pinctrl_hummingboard2_usdhc2_aux ++ &pinctrl_hummingboard2_usdhc2_100mhz ++ >; ++ pinctrl-2 = < ++ &pinctrl_hummingboard2_usdhc2_aux ++ &pinctrl_hummingboard2_usdhc2_200mhz ++ >; ++ ++ card-external-vcc-supply = <®_usdhc2_vbus>; ++ cd-gpios = <&gpio1 4 0>; ++ status = "okay"; ++}; ++ ++&usdhc3 { ++ pinctrl-names = "default"; ++ pinctrl-0 = < ++ &pinctrl_hummingboard2_usdhc3 ++ >; ++ vmmc-supply = <®_3p3v>; ++ bus-width = <8>; ++ non-removable; ++ status = "okay"; ++}; ++ ++&uart3 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_hummingboard2_uart3>; ++ status = "okay"; ++}; +diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi +index d3499f4..7ead52b 100644 +--- a/arch/arm/boot/dts/imx6qdl.dtsi ++++ b/arch/arm/boot/dts/imx6qdl.dtsi +@@ -11,7 +11,7 @@ + */ + + #include +- ++#include + #include "skeleton.dtsi" + #include + +diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h +new file mode 100644 +index 0000000..4bd9d6e +--- /dev/null ++++ b/include/dt-bindings/clock/imx6qdl-clock.h +@@ -0,0 +1,261 @@ ++/* ++ * Copyright (C) 2015 Freescale Semiconductor, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef __DT_BINDINGS_CLOCK_IMX6QDL_H ++#define __DT_BINDINGS_CLOCK_IMX6QDL_H ++ ++#define IMX6QDL_CLK_DUMMY 0 ++#define IMX6QDL_CLK_CKIL 1 ++#define IMX6QDL_CLK_CKIH 2 ++#define IMX6QDL_CLK_OSC 3 ++#define IMX6QDL_CLK_PLL2_PFD0_352M 4 ++#define IMX6QDL_CLK_PLL2_PFD1_594M 5 ++#define IMX6QDL_CLK_PLL2_PFD2_396M 6 ++#define IMX6QDL_CLK_PLL3_PFD0_720M 7 ++#define IMX6QDL_CLK_PLL3_PFD1_540M 8 ++#define IMX6QDL_CLK_PLL3_PFD2_508M 9 ++#define IMX6QDL_CLK_PLL3_PFD3_454M 10 ++#define IMX6QDL_CLK_PLL2_198M 11 ++#define IMX6QDL_CLK_PLL3_120M 12 ++#define IMX6QDL_CLK_PLL3_80M 13 ++#define IMX6QDL_CLK_PLL3_60M 14 ++#define IMX6QDL_CLK_TWD 15 ++#define IMX6QDL_CLK_STEP 16 ++#define IMX6QDL_CLK_PLL1_SW 17 ++#define IMX6QDL_CLK_PERIPH_PRE 18 ++#define IMX6QDL_CLK_PERIPH2_PRE 19 ++#define IMX6QDL_CLK_PERIPH_CLK2_SEL 20 ++#define IMX6QDL_CLK_PERIPH2_CLK2_SEL 21 ++#define IMX6QDL_CLK_AXI_SEL 22 ++#define IMX6QDL_CLK_ESAI_SEL 23 ++#define IMX6QDL_CLK_ASRC_SEL 24 ++#define IMX6QDL_CLK_SPDIF_SEL 25 ++#define IMX6QDL_CLK_GPU2D_AXI 26 ++#define IMX6QDL_CLK_GPU3D_AXI 27 ++#define IMX6QDL_CLK_GPU2D_CORE_SEL 28 ++#define IMX6QDL_CLK_GPU3D_CORE_SEL 29 ++#define IMX6QDL_CLK_GPU3D_SHADER_SEL 30 ++#define IMX6QDL_CLK_IPU1_SEL 31 ++#define IMX6QDL_CLK_IPU2_SEL 32 ++#define IMX6QDL_CLK_LDB_DI0_SEL 33 ++#define IMX6QDL_CLK_LDB_DI1_SEL 34 ++#define IMX6QDL_CLK_IPU1_DI0_PRE_SEL 35 ++#define IMX6QDL_CLK_IPU1_DI1_PRE_SEL 36 ++#define IMX6QDL_CLK_IPU2_DI0_PRE_SEL 37 ++#define IMX6QDL_CLK_IPU2_DI1_PRE_SEL 38 ++#define IMX6QDL_CLK_IPU1_DI0_SEL 39 ++#define IMX6QDL_CLK_IPU1_DI1_SEL 40 ++#define IMX6QDL_CLK_IPU2_DI0_SEL 41 ++#define IMX6QDL_CLK_IPU2_DI1_SEL 42 ++#define IMX6QDL_CLK_HSI_TX_SEL 43 ++#define IMX6QDL_CLK_PCIE_AXI_SEL 44 ++#define IMX6QDL_CLK_SSI1_SEL 45 ++#define IMX6QDL_CLK_SSI2_SEL 46 ++#define IMX6QDL_CLK_SSI3_SEL 47 ++#define IMX6QDL_CLK_USDHC1_SEL 48 ++#define IMX6QDL_CLK_USDHC2_SEL 49 ++#define IMX6QDL_CLK_USDHC3_SEL 50 ++#define IMX6QDL_CLK_USDHC4_SEL 51 ++#define IMX6QDL_CLK_ENFC_SEL 52 ++#define IMX6QDL_CLK_EMI_SEL 53 ++#define IMX6QDL_CLK_EMI_SLOW_SEL 54 ++#define IMX6QDL_CLK_VDO_AXI_SEL 55 ++#define IMX6QDL_CLK_VPU_AXI_SEL 56 ++#define IMX6QDL_CLK_CKO1_SEL 57 ++#define IMX6QDL_CLK_PERIPH 58 ++#define IMX6QDL_CLK_PERIPH2 59 ++#define IMX6QDL_CLK_PERIPH_CLK2 60 ++#define IMX6QDL_CLK_PERIPH2_CLK2 61 ++#define IMX6QDL_CLK_IPG 62 ++#define IMX6QDL_CLK_IPG_PER 63 ++#define IMX6QDL_CLK_ESAI_PRED 64 ++#define IMX6QDL_CLK_ESAI_PODF 65 ++#define IMX6QDL_CLK_ASRC_PRED 66 ++#define IMX6QDL_CLK_ASRC_PODF 67 ++#define IMX6QDL_CLK_SPDIF_PRED 68 ++#define IMX6QDL_CLK_SPDIF_PODF 69 ++#define IMX6QDL_CLK_CAN_ROOT 70 ++#define IMX6QDL_CLK_ECSPI_ROOT 71 ++#define IMX6QDL_CLK_GPU2D_CORE_PODF 72 ++#define IMX6QDL_CLK_GPU3D_CORE_PODF 73 ++#define IMX6QDL_CLK_GPU3D_SHADER 74 ++#define IMX6QDL_CLK_IPU1_PODF 75 ++#define IMX6QDL_CLK_IPU2_PODF 76 ++#define IMX6QDL_CLK_IPU1_DI0_PRE 79 ++#define IMX6QDL_CLK_IPU1_DI1_PRE 80 ++#define IMX6QDL_CLK_IPU2_DI0_PRE 81 ++#define IMX6QDL_CLK_IPU2_DI1_PRE 82 ++#define IMX6QDL_CLK_HSI_TX_PODF 83 ++#define IMX6QDL_CLK_SSI1_PRED 84 ++#define IMX6QDL_CLK_SSI1_PODF 85 ++#define IMX6QDL_CLK_SSI2_PRED 86 ++#define IMX6QDL_CLK_SSI2_PODF 87 ++#define IMX6QDL_CLK_SSI3_PRED 88 ++#define IMX6QDL_CLK_SSI3_PODF 89 ++#define IMX6QDL_CLK_UART_SERIAL_PODF 90 ++#define IMX6QDL_CLK_USDHC1_PODF 91 ++#define IMX6QDL_CLK_USDHC2_PODF 92 ++#define IMX6QDL_CLK_USDHC3_PODF 93 ++#define IMX6QDL_CLK_USDHC4_PODF 94 ++#define IMX6QDL_CLK_ENFC_PRED 95 ++#define IMX6QDL_CLK_ENFC_PODF 96 ++#define IMX6QDL_CLK_EMI_PODF 97 ++#define IMX6QDL_CLK_EMI_SLOW_PODF 98 ++#define IMX6QDL_CLK_VPU_AXI_PODF 99 ++#define IMX6QDL_CLK_CKO1_PODF 100 ++#define IMX6QDL_CLK_AXI 101 ++#define IMX6QDL_CLK_ARM 104 ++#define IMX6QDL_CLK_AHB 105 ++#define IMX6QDL_CLK_APBH_DMA 106 ++#define IMX6QDL_CLK_ASRC 107 ++#define IMX6QDL_CLK_CAN1_IPG 108 ++#define IMX6QDL_CLK_CAN1_SERIAL 109 ++#define IMX6QDL_CLK_CAN2_IPG 110 ++#define IMX6QDL_CLK_CAN2_SERIAL 111 ++#define IMX6QDL_CLK_ECSPI1 112 ++#define IMX6QDL_CLK_ECSPI2 113 ++#define IMX6QDL_CLK_ECSPI3 114 ++#define IMX6QDL_CLK_ECSPI4 115 ++#define IMX6Q_CLK_ECSPI5 116 ++#define IMX6DL_CLK_I2C4 116 ++#define IMX6QDL_CLK_ENET 117 ++#define IMX6QDL_CLK_ESAI_EXTAL 118 ++#define IMX6QDL_CLK_GPT_IPG 119 ++#define IMX6QDL_CLK_GPT_IPG_PER 120 ++#define IMX6QDL_CLK_GPU2D_CORE 121 ++#define IMX6QDL_CLK_GPU3D_CORE 122 ++#define IMX6QDL_CLK_HDMI_IAHB 123 ++#define IMX6QDL_CLK_HDMI_ISFR 124 ++#define IMX6QDL_CLK_I2C1 125 ++#define IMX6QDL_CLK_I2C2 126 ++#define IMX6QDL_CLK_I2C3 127 ++#define IMX6QDL_CLK_IIM 128 ++#define IMX6QDL_CLK_ENFC 129 ++#define IMX6QDL_CLK_IPU1 130 ++#define IMX6QDL_CLK_IPU1_DI0 131 ++#define IMX6QDL_CLK_IPU1_DI1 132 ++#define IMX6QDL_CLK_IPU2 133 ++#define IMX6QDL_CLK_IPU2_DI0 134 ++#define IMX6QDL_CLK_LDB_DI0 135 ++#define IMX6QDL_CLK_LDB_DI1 136 ++#define IMX6QDL_CLK_IPU2_DI1 137 ++#define IMX6QDL_CLK_HSI_TX 138 ++#define IMX6QDL_CLK_MLB 139 ++#define IMX6QDL_CLK_MMDC_CH0_AXI 140 ++#define IMX6QDL_CLK_MMDC_CH1_AXI 141 ++#define IMX6QDL_CLK_OCRAM 142 ++#define IMX6QDL_CLK_OPENVG_AXI 143 ++#define IMX6QDL_CLK_PCIE_AXI 144 ++#define IMX6QDL_CLK_PWM1 145 ++#define IMX6QDL_CLK_PWM2 146 ++#define IMX6QDL_CLK_PWM3 147 ++#define IMX6QDL_CLK_PWM4 148 ++#define IMX6QDL_CLK_PER1_BCH 149 ++#define IMX6QDL_CLK_GPMI_BCH_APB 150 ++#define IMX6QDL_CLK_GPMI_BCH 151 ++#define IMX6QDL_CLK_GPMI_IO 152 ++#define IMX6QDL_CLK_GPMI_APB 153 ++#define IMX6QDL_CLK_SATA 154 ++#define IMX6QDL_CLK_SDMA 155 ++#define IMX6QDL_CLK_SPBA 156 ++#define IMX6QDL_CLK_SSI1 157 ++#define IMX6QDL_CLK_SSI2 158 ++#define IMX6QDL_CLK_SSI3 159 ++#define IMX6QDL_CLK_UART_IPG 160 ++#define IMX6QDL_CLK_UART_SERIAL 161 ++#define IMX6QDL_CLK_USBOH3 162 ++#define IMX6QDL_CLK_USDHC1 163 ++#define IMX6QDL_CLK_USDHC2 164 ++#define IMX6QDL_CLK_USDHC3 165 ++#define IMX6QDL_CLK_USDHC4 166 ++#define IMX6QDL_CLK_VDO_AXI 167 ++#define IMX6QDL_CLK_VPU_AXI 168 ++#define IMX6QDL_CLK_CKO1 169 ++#define IMX6QDL_CLK_PLL1_SYS 170 ++#define IMX6QDL_CLK_PLL2_BUS 171 ++#define IMX6QDL_CLK_PLL3_USB_OTG 172 ++#define IMX6QDL_CLK_PLL4_AUDIO 173 ++#define IMX6QDL_CLK_PLL5_VIDEO 174 ++#define IMX6QDL_CLK_PLL8_MLB 175 ++#define IMX6QDL_CLK_PLL7_USB_HOST 176 ++#define IMX6QDL_CLK_PLL6_ENET 177 ++#define IMX6QDL_CLK_SSI1_IPG 178 ++#define IMX6QDL_CLK_SSI2_IPG 179 ++#define IMX6QDL_CLK_SSI3_IPG 180 ++#define IMX6QDL_CLK_ROM 181 ++#define IMX6QDL_CLK_USBPHY1 182 ++#define IMX6QDL_CLK_USBPHY2 183 ++#define IMX6QDL_CLK_LDB_DI0_DIV_3_5 184 ++#define IMX6QDL_CLK_LDB_DI1_DIV_3_5 185 ++#define IMX6QDL_CLK_SATA_REF 186 ++#define IMX6QDL_CLK_SATA_REF_100M 187 ++#define IMX6QDL_CLK_PCIE_REF 188 ++#define IMX6QDL_CLK_PCIE_REF_125M 189 ++#define IMX6QDL_CLK_ENET_REF 190 ++#define IMX6QDL_CLK_USBPHY1_GATE 191 ++#define IMX6QDL_CLK_USBPHY2_GATE 192 ++#define IMX6QDL_CLK_PLL4_POST_DIV 193 ++#define IMX6QDL_CLK_PLL5_POST_DIV 194 ++#define IMX6QDL_CLK_PLL5_VIDEO_DIV 195 ++#define IMX6QDL_CLK_EIM_SLOW 196 ++#define IMX6QDL_CLK_SPDIF 197 ++#define IMX6QDL_CLK_CKO2_SEL 198 ++#define IMX6QDL_CLK_CKO2_PODF 199 ++#define IMX6QDL_CLK_CKO2 200 ++#define IMX6QDL_CLK_CKO 201 ++#define IMX6QDL_CLK_VDOA 202 ++#define IMX6QDL_CLK_PLL4_AUDIO_DIV 203 ++#define IMX6QDL_CLK_LVDS1_SEL 204 ++#define IMX6QDL_CLK_LVDS2_SEL 205 ++#define IMX6QDL_CLK_LVDS1_GATE 206 ++#define IMX6QDL_CLK_LVDS2_GATE 207 ++#define IMX6QDL_CLK_ESAI_MEM 208 ++#define IMX6QDL_CLK_LDB_DI0_DIV_7 209 ++#define IMX6QDL_CLK_LDB_DI1_DIV_7 210 ++#define IMX6QDL_CLK_LDB_DI0_DIV_SEL 211 ++#define IMX6QDL_CLK_LDB_DI1_DIV_SEL 212 ++#define IMX6QDL_CLK_VIDEO_27M 213 ++#define IMX6QDL_CLK_DCIC1 214 ++#define IMX6QDL_CLK_DCIC2 215 ++#define IMX6QDL_CLK_GPT_3M 216 ++#define IMX6QDL_CLK_ESAI_IPG 217 ++#define IMX6QDL_CLK_ASRC_IPG 218 ++#define IMX6QDL_CLK_ASRC_MEM 219 ++#define IMX6QDL_CLK_LVDS1_IN 220 ++#define IMX6QDL_CLK_LVDS2_IN 221 ++#define IMX6QDL_CLK_ANACLK1 222 ++#define IMX6QDL_CLK_ANACLK2 223 ++#define IMX6QDL_PLL1_BYPASS_SRC 224 ++#define IMX6QDL_PLL2_BYPASS_SRC 225 ++#define IMX6QDL_PLL3_BYPASS_SRC 226 ++#define IMX6QDL_PLL4_BYPASS_SRC 227 ++#define IMX6QDL_PLL5_BYPASS_SRC 228 ++#define IMX6QDL_PLL6_BYPASS_SRC 229 ++#define IMX6QDL_PLL7_BYPASS_SRC 230 ++#define IMX6QDL_CLK_PLL1 231 ++#define IMX6QDL_CLK_PLL2 232 ++#define IMX6QDL_CLK_PLL3 233 ++#define IMX6QDL_CLK_PLL4 234 ++#define IMX6QDL_CLK_PLL5 235 ++#define IMX6QDL_CLK_PLL6 236 ++#define IMX6QDL_CLK_PLL7 237 ++#define IMX6QDL_PLL1_BYPASS 238 ++#define IMX6QDL_PLL2_BYPASS 239 ++#define IMX6QDL_PLL3_BYPASS 240 ++#define IMX6QDL_PLL4_BYPASS 241 ++#define IMX6QDL_PLL5_BYPASS 242 ++#define IMX6QDL_PLL6_BYPASS 243 ++#define IMX6QDL_PLL7_BYPASS 244 ++#define IMX6QDL_CLK_AXI_ALT_SEL 245 ++#define IMX6QDL_CAAM_MEM 246 ++#define IMX6QDL_CAAM_ACLK 247 ++#define IMX6QDL_CAAM_IPG 248 ++#define IMX6QDL_CLK_SPDIF_GCLK 249 ++#define IMX6QDL_CLK_END 250 ++ ++#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */