From 00ca1863416b48a1dda11752eff1e4f95bd61b70 Mon Sep 17 00:00:00 2001 From: EvilOlaf Date: Fri, 9 Jan 2026 16:16:06 +0000 Subject: [PATCH] actually copy everything and adjust do not commit regex --- .../sunxi-6.18/0000.patching_config.yaml | 2 +- .../archive/sunxi-6.18/overlay_32/Makefile | 100 +++++ .../overlay_32/README.sun4i-a10-overlays | 278 ++++++++++++++ .../overlay_32/README.sun5i-a13-overlays | 172 +++++++++ .../overlay_32/README.sun7i-a20-overlays | 348 ++++++++++++++++++ .../overlay_32/README.sun8i-h3-overlays | 250 +++++++++++++ .../overlay_32/sun4i-a10-fixup.scr-cmd | 124 +++++++ .../overlay_32/sun5i-a13-fixup.scr-cmd | 48 +++ .../overlay_32/sun7i-a20-fixup.scr-cmd | 143 +++++++ .../overlay_32/sun8i-h3-fixup.scr-cmd | 110 ++++++ .../archive/sunxi-6.18/overlay_64/Makefile | 117 ++++++ .../overlay_64/README.sun50i-a64-overlays | 201 ++++++++++ .../overlay_64/README.sun50i-h5-overlays | 250 +++++++++++++ .../overlay_64/sun50i-a64-fixup.scr-cmd | 95 +++++ .../overlay_64/sun50i-h5-fixup.scr-cmd | 110 ++++++ .../overlay_64/sun50i-h6-fixup.scr-cmd | 96 +++++ .../overlay_64/sun50i-h616-fixup.scr-cmd | 110 ++++++ 17 files changed, 2553 insertions(+), 1 deletion(-) create mode 100644 patch/kernel/archive/sunxi-6.18/overlay_32/Makefile create mode 100644 patch/kernel/archive/sunxi-6.18/overlay_32/README.sun4i-a10-overlays create mode 100644 patch/kernel/archive/sunxi-6.18/overlay_32/README.sun5i-a13-overlays create mode 100644 patch/kernel/archive/sunxi-6.18/overlay_32/README.sun7i-a20-overlays create mode 100644 patch/kernel/archive/sunxi-6.18/overlay_32/README.sun8i-h3-overlays create mode 100644 patch/kernel/archive/sunxi-6.18/overlay_32/sun4i-a10-fixup.scr-cmd create mode 100644 patch/kernel/archive/sunxi-6.18/overlay_32/sun5i-a13-fixup.scr-cmd create mode 100644 patch/kernel/archive/sunxi-6.18/overlay_32/sun7i-a20-fixup.scr-cmd create mode 100644 patch/kernel/archive/sunxi-6.18/overlay_32/sun8i-h3-fixup.scr-cmd create mode 100644 patch/kernel/archive/sunxi-6.18/overlay_64/Makefile create mode 100644 patch/kernel/archive/sunxi-6.18/overlay_64/README.sun50i-a64-overlays create mode 100644 patch/kernel/archive/sunxi-6.18/overlay_64/README.sun50i-h5-overlays create mode 100644 patch/kernel/archive/sunxi-6.18/overlay_64/sun50i-a64-fixup.scr-cmd create mode 100644 patch/kernel/archive/sunxi-6.18/overlay_64/sun50i-h5-fixup.scr-cmd create mode 100644 patch/kernel/archive/sunxi-6.18/overlay_64/sun50i-h6-fixup.scr-cmd create mode 100755 patch/kernel/archive/sunxi-6.18/overlay_64/sun50i-h616-fixup.scr-cmd diff --git a/patch/kernel/archive/sunxi-6.18/0000.patching_config.yaml b/patch/kernel/archive/sunxi-6.18/0000.patching_config.yaml index eaf992412f..67c6db63ef 100644 --- a/patch/kernel/archive/sunxi-6.18/0000.patching_config.yaml +++ b/patch/kernel/archive/sunxi-6.18/0000.patching_config.yaml @@ -28,4 +28,4 @@ config: do-not-commit-regexes: # Python-style regexes # ignore DT Makefile patches, we've an auto-patcher now - this does NOT ignore overlay Makefile! - "^arch/([a-zA-Z0-9]+)/boot/dts/([a-zA-Z0-9]+)/Makefile$" - + - "^arch/([a-zA-Z0-9]+)/boot/dts/([a-zA-Z0-9-]+)/overlay/.+$" diff --git a/patch/kernel/archive/sunxi-6.18/overlay_32/Makefile b/patch/kernel/archive/sunxi-6.18/overlay_32/Makefile new file mode 100644 index 0000000000..560f926b70 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.18/overlay_32/Makefile @@ -0,0 +1,100 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_MACH_SUN4I) += \ + sun4i-a10-analog-codec.dtbo \ + sun4i-a10-can.dtbo \ + sun4i-a10-i2c1.dtbo \ + sun4i-a10-i2c2.dtbo \ + sun4i-a10-nand.dtbo \ + sun4i-a10-pps-gpio.dtbo \ + sun4i-a10-pwm.dtbo \ + sun4i-a10-spdif-out.dtbo \ + sun4i-a10-spi-jedec-nor.dtbo \ + sun4i-a10-spi-spidev.dtbo \ + sun4i-a10-uart2.dtbo \ + sun4i-a10-uart3.dtbo \ + sun4i-a10-uart4.dtbo \ + sun4i-a10-uart5.dtbo \ + sun4i-a10-uart6.dtbo \ + sun4i-a10-uart7.dtbo \ + sun4i-a10-w1-gpio.dtbo + +dtb-$(CONFIG_MACH_SUN5I) += \ + sun5i-a13-analog-codec.dtbo \ + sun5i-a13-i2c1.dtbo \ + sun5i-a13-i2c2.dtbo \ + sun5i-a13-nand.dtbo \ + sun5i-a13-pwm.dtbo \ + sun5i-a13-spi0.dtbo \ + sun5i-a13-spi1.dtbo \ + sun5i-a13-spi2.dtbo \ + sun5i-a13-spi-jedec-nor.dtbo \ + sun5i-a13-spi-spidev.dtbo \ + sun5i-a13-uart0.dtbo \ + sun5i-a13-uart1.dtbo \ + sun5i-a13-uart2.dtbo \ + sun5i-a13-uart3.dtbo + +dtb-$(CONFIG_MACH_SUN7I) += \ + sun7i-a20-analog-codec.dtbo \ + sun7i-a20-can.dtbo \ + sun7i-a20-i2c1.dtbo \ + sun7i-a20-i2c2.dtbo \ + sun7i-a20-i2c3.dtbo \ + sun7i-a20-i2c4.dtbo \ + sun7i-a20-mmc2.dtbo \ + sun7i-a20-nand.dtbo \ + sun7i-a20-pps-gpio.dtbo \ + sun7i-a20-pwm.dtbo \ + sun7i-a20-spdif-out.dtbo \ + sun7i-a20-spi-add-cs1.dtbo \ + sun7i-a20-spi-jedec-nor.dtbo \ + sun7i-a20-spi-spidev.dtbo \ + sun7i-a20-uart2.dtbo \ + sun7i-a20-uart3.dtbo \ + sun7i-a20-uart4.dtbo \ + sun7i-a20-uart5.dtbo \ + sun7i-a20-uart6.dtbo \ + sun7i-a20-uart7.dtbo \ + sun7i-a20-w1-gpio.dtbo + +dtb-$(CONFIG_MACH_SUN8I) += \ + sun8i-h3-analog-codec.dtbo \ + sun8i-h3-cir.dtbo \ + sun8i-h3-cpu-clock-1.2GHz-1.3v.dtbo \ + sun8i-h3-cpu-clock-1.368GHz-1.3v.dtbo \ + sun8i-h3-cpu-clock-1.3GHz-1.3v.dtbo \ + sun8i-h3-i2c0.dtbo \ + sun8i-h3-i2c1.dtbo \ + sun8i-h3-i2c2.dtbo \ + sun8i-h3-pps-gpio.dtbo \ + sun8i-h3-pwm.dtbo \ + sun8i-h3-spdif-out.dtbo \ + sun8i-h3-spi-add-cs1.dtbo \ + sun8i-h3-spi-jedec-nor.dtbo \ + sun8i-h3-spi-spidev.dtbo \ + sun8i-h3-uart1.dtbo \ + sun8i-h3-uart2.dtbo \ + sun8i-h3-uart3.dtbo \ + sun8i-h3-usbhost0.dtbo \ + sun8i-h3-usbhost1.dtbo \ + sun8i-h3-usbhost2.dtbo \ + sun8i-h3-usbhost3.dtbo \ + sun8i-h3-w1-gpio.dtbo \ + sun8i-r40-i2c2.dtbo \ + sun8i-r40-i2c3.dtbo \ + sun8i-r40-spi-spidev0.dtbo \ + sun8i-r40-spi-spidev1.dtbo \ + sun8i-r40-uart2.dtbo \ + sun8i-r40-uart4.dtbo \ + sun8i-r40-uart5.dtbo \ + sun8i-r40-uart7.dtbo + +scr-$(CONFIG_MACH_SUN4I) += sun4i-a10-fixup.scr +scr-$(CONFIG_MACH_SUN5I) += sun5i-a13-fixup.scr +scr-$(CONFIG_MACH_SUN7I) += sun7i-a20-fixup.scr +scr-$(CONFIG_MACH_SUN8I) += sun8i-h3-fixup.scr + +dtbotxt-$(CONFIG_MACH_SUN4I) += README.sun4i-a10-overlays +dtbotxt-$(CONFIG_MACH_SUN5I) += README.sun5i-a13-overlays +dtbotxt-$(CONFIG_MACH_SUN7I) += README.sun7i-a20-overlays +dtbotxt-$(CONFIG_MACH_SUN8I) += README.sun8i-h3-overlays diff --git a/patch/kernel/archive/sunxi-6.18/overlay_32/README.sun4i-a10-overlays b/patch/kernel/archive/sunxi-6.18/overlay_32/README.sun4i-a10-overlays new file mode 100644 index 0000000000..b5dc7cab9e --- /dev/null +++ b/patch/kernel/archive/sunxi-6.18/overlay_32/README.sun4i-a10-overlays @@ -0,0 +1,278 @@ +This document describes overlays provided in the kernel packages +For generic Armbian overlays documentation please see +https://docs.armbian.com/User-Guide_Armbian_overlays/ + +### Platform: + +sun4i-a10 (Allwinner A10) + +### Platform details: + +Supported pin banks: PB, PC, PD, PE, PG, PH, PI + +SPI controller 0 have 2 exposed hardware CS, +other SPI controllers have only one hardware CS +Reference: A10 User manual section 17.4.13, A10 datasheet section 5.2 + +I2C bus 0 is used for the AXP209 PMIC + +### Provided overlays: + +- analog-codec +- can +- i2c1 +- i2c2 +- nand +- pps-gpio +- pwm +- spdif-out +- spi0 +- spi1 +- spi2 +- spi-jedec-nor +- spi-spidev +- uart1 +- uart2 +- uart3 +- uart4 +- uart5 +- uart6 +- uart7 +- w1-gpio + +### Overlay details: + +### analog-codec + +Activates SoC analog codec driver that provides Line Out and Mic In +functionality + +## can + +Activates SoC CAN controller + +CAN pins (TX, RX): PH20, PH21 + +### i2c1 + +Activates TWI/I2C bus 1 + +I2C1 pins (SCL, SDA): PB18, PB19 + +### i2c2 + +Activates TWI/I2C bus 2 + +I2C2 pins (SCL, SDA): PB20, PB21 + +### nand + +Activates NAND controller + +This overlay should not be used until mainline MLC NAND support +allows using NAND storage reliably + +### pps-gpio + +Activates pulse-per-second GPIO client + +Parameters: + +param_pps_pin (pin) + Pin PPS source is connected to + Optional + Default: PI15 + +param_pps_falling_edge (bool) + Assert by falling edge + Optional + Default: 0 + When set (to 1), assert is indicated by a falling edge + (instead of by a rising edge) + +### pwm + +Activates hardware PWM controller + +PWM pins (PWM0, PWM1): PB2, PI3 + +Parameters: + +param_pwm_pins (string) + PWM pins activated with this overlay + Optional + Default: both + Supported values: 0, 1, both + If set to 0 only PWM0 can be used, + if set to 1 then only PWM1 can be used, + if set to both (default), both PWM0 and PWM1 can be used + +### spdif-out + +Activates SPDIF/Toslink audio output + +SPDIF pin: PB13 + +### spi0 + +Activates SPI controller 0 to use it with other overlays and sets up the pin multiplexing for it + +SPI 0 pins (MOSI, MISO, SCK, CS0, CS1): PI12, PI13, PI11, PI10, PI14 + +### spi1 + +Activates SPI controller 1 to use it with other overlays and sets up the pin multiplexing for it + +SPI 1 pins (MOSI, MISO, SCK, CS0): PI18, PI19, PI17, PI16 + +### spi2 + +Activates SPI controller 2 to use it with other overlays and sets up the pin multiplexing for it + +SPI 2 pins a (MOSI, MISO, SCK, CS0): PC21, PC22, PC20, PC19 +SPI 2 pins b (MOSI, MISO, SCK, CS0): PB16, PB17, PB15, PB14 + +Parameters: + +param_spi2_bus_pins (char) + SPI bus 2 pinmux variant + Optional + Default: a + Supported values: a, b + Determines what pins SPI bus 2 is exposed on if SPI 2 is used + + +### spi-jedec-nor + +Activates MTD support for JEDEC compatible SPI NOR flash chips on SPI bus +supported by the kernel SPI NOR driver + +SPI 0 pins (MOSI, MISO, SCK, CS0, CS1): PI12, PI13, PI11, PI10, PI14 +SPI 1 pins (MOSI, MISO, SCK, CS0): PI18, PI19, PI17, PI16 +SPI 2 pins a (MOSI, MISO, SCK, CS0): PC21, PC22, PC20, PC19 +SPI 2 pins b (MOSI, MISO, SCK, CS0): PB16, PB17, PB15, PB14 + +Parameters: + +param_spinor_spi_bus (int) + SPI bus to activate SPI NOR flash support on + Required + Supported values: 0, 1, 2 + +param_spinor_max_freq (int) + Maximum SPI frequency + Optional + Default: 1000000 + Range: 3000 - 100000000 + +### spi-spidev + +Activates SPIdev device node (/dev/spidevX.Y) for userspace SPI access, +where X is the bus number and Y is the CS number + +SPI 0 pins (MOSI, MISO, SCK, CS0, CS1): PI12, PI13, PI11, PI10, PI14 +SPI 1 pins (MOSI, MISO, SCK, CS0): PI18, PI19, PI17, PI16 +SPI 2 pins a (MOSI, MISO, SCK, CS0): PC21, PC22, PC20, PC19 +SPI 2 pins b (MOSI, MISO, SCK, CS0): PB16, PB17, PB15, PB14 + +Parameters: + +param_spidev_spi_bus (int) + SPI bus to activate mcp2515 support on + Required + Supported values: 0, 1, 2 + +param_spidev_max_freq (int) + Maximum SPIdev frequency + Optional + Default: 1000000 + Range: 3000 - 100000000 + +### uart2 + +Activates serial port 2 (/dev/ttyS2) + +UART 2 pins (TX, RX, RTS, CTS): PI18, PI19, PI16, PI17 + +Parameters: + +param_uart2_rtscts (bool) + Enable RTS and CTS pins + Optional + Default: 0 + Set to 1 to enable CTS and RTS pins + +### uart3 + +Activates serial port 3 (/dev/ttyS3) + +UART 3 pins a (TX, RX, RTS, CTS): PG6, PG7, PG8, PG9 +UART 3 pins b (TX, RX, RTS, CTS): PH0, PH1, PH2, PH3 + +Parameters: + +param_uart3_pins (char) + Determines what pins UART 3 is exposed on + Optional + Default: a + Supported values: a, b + +param_uart3_rtscts (bool) + Enable RTS and CTS pins + Optional + Default: 0 + Set to 1 to enable CTS and RTS pins + +### uart4 + +Activates serial port 4 (/dev/ttyS4) + +UART 4 pins a (TX, RX): PG10, PG11 +UART 4 pins b (TX, RX): PH4, PH5 + +Parameters: + +param_uart4_pins (char) + Determines what pins UART 4 is exposed on + Optional + Default: a + Supported values: a, b + +### uart 5 + +Activates serial port 5 (/dev/ttyS5) + +UART 5 pins (TX, RX): PH6, PH7 + +### uart 6 + +Activates serial port 6 (/dev/ttyS6) + +UART 6 pins (TX, RX): PI12, PI13 + +### uart 7 + +Activates serial port 7 (/dev/ttyS7) + +UART 7 pins (TX, RX): PI20, PI21 + +### w1-gpio + +Activates 1-Wire GPIO master +Requires an external pull-up resistor on the data pin +or enabling the internal pull-up + +Parameters: + +param_w1_pin (pin) + Data pin for 1-Wire master + Optional + Default: PI15 + +param_w1_pin_int_pullup (bool) + Enable internal pull-up for the data pin + Optional + Default: 0 + Set to 1 to enable the pull-up + This option should not be used with multiple sensors or long wires - + please use external pull-up resistor instead diff --git a/patch/kernel/archive/sunxi-6.18/overlay_32/README.sun5i-a13-overlays b/patch/kernel/archive/sunxi-6.18/overlay_32/README.sun5i-a13-overlays new file mode 100644 index 0000000000..d8759ce7ec --- /dev/null +++ b/patch/kernel/archive/sunxi-6.18/overlay_32/README.sun5i-a13-overlays @@ -0,0 +1,172 @@ +This document describes overlays provided in the kernel packages +For generic Armbian overlays documentation please see +https://docs.armbian.com/User-Guide_Armbian_overlays/ + +### Platform: + +sun5i-a13 (Allwinner A13) + +### Platform details: + +I2C bus 0 is used for the AXP209 PMIC + +### Provided overlays: + +- analog-codec +- i2c1 +- i2c2 +- nand +- pwm +- spi0 +- spi1 +- spi2 +- spi-jedec-nor +- spi-spidev +- uart0 +- uart1 +- uart2 +- uart3 + +### Overlay details: + +### analog-codec + +Activates SoC analog codec driver that provides HP Out and Mic In +functionality + +### i2c1 + +Activates TWI/I2C bus 1 + +I2C1 pins (SCL, SDA): PB15, PB16 + +### i2c2 + +Activates TWI/I2C bus 2 + +I2C2 pins (SCL, SDA): PB17, PB18 + +### nand + +Activates NAND controller + +This overlay should not be used until mainline MLC NAND support +allows using NAND storage reliably + +### pwm + +Activates hardware PWM controller + +PWM pins (PWM0): PB2 + +### spi0 + +Activates SPI controller 0 to use it with other overlays and sets up the pin multiplexing for it + +SPI 0 pins (MOSI, MISO, SCK, CS0): PC0, PC1, PC2, PC3 + +### spi1 + +Activates SPI controller 1 to use it with other overlays and sets up the pin multiplexing for it + +SPI 1 pins (MOSI, MISO, SCK, CS0): PG11, PG12, PG10, PG9 + +### spi2 + +Activates SPI controller 2 to use it with other overlays and sets up the pin multiplexing for it + +SPI 2 pins (MOSI, MISO, SCK, CS0): PE2, PE3, PE1, PE0 + +### spi-jedec-nor + +Activates MTD support for JEDEC compatible SPI NOR flash chips on SPI bus +supported by the kernel SPI NOR driver + +SPI 0 pins (MOSI, MISO, SCK, CS0): PC0, PC1, PC2, PC3 +SPI 1 pins (MOSI, MISO, SCK, CS0): PG11, PG12, PG10, PG9 +SPI 2 pins (MOSI, MISO, SCK, CS0): PE2, PE3, PE1, PE0 + +Parameters: + +param_spinor_spi_bus (int) + SPI bus to activate SPI NOR flash support on + Required + Supported values: 0, 1, 2 + +param_spinor_max_freq (int) + Maximum SPI frequency + Optional + Default: 1000000 + Range: 3000 - 100000000 + +### spi-spidev + +Activates SPIdev device node (/dev/spidevX.Y) for userspace SPI access, +where X is the bus number and Y is the CS number + +SPI 0 pins (MOSI, MISO, SCK, CS0): PC0, PC1, PC2, PC3 +SPI 1 pins (MOSI, MISO, SCK, CS0): PG11, PG12, PG10, PG9 +SPI 2 pins (MOSI, MISO, SCK, CS0): PE2, PE3, PE1, PE0 + +Parameters: + +param_spidev_spi_bus (int) + SPI bus to activate mcp2515 support on + Required + Supported values: 0, 1, 2 + +param_spidev_max_freq (int) + Maximum SPIdev frequency + Optional + Default: 1000000 + Range: 3000 - 100000000 + +### uart 0 + +Activates serial port 0 (/dev/ttyS0) + +UART 0 pins (TX, RX): PF2, PF4 + +### uart 1 + +Activates serial port 1 (/dev/ttyS1) + +UART 1 pins a (TX, RX): PE10, PE11 +UART 1 pins b (TX, RX): PG3, PG4 + +Parameters: + +param_uart1_pins (char) + UART 1 pinmux variant + Optional + Default: a + Supported values: a, b + Determines what pins UART 1 is exposed on if UART 1 is used + +### uart2 + +Activates serial port 2 (/dev/ttyS2) + +UART 2 pins (TX, RX, RTS, CTS): PD2, PD3, PD4, PD5 + +Parameters: + +param_uart2_rtscts (bool) + Enable RTS and CTS pins + Optional + Default: 0 + Set to 1 to enable CTS and RTS pins + +### uart3 + +Activates serial port 3 (/dev/ttyS3) + +UART 3 pins (TX, RX, RTS, CTS): PG9, PG10, PG12, PG11 + +Parameters: + +param_uart3_rtscts (bool) + Enable RTS and CTS pins + Optional + Default: 0 + Set to 1 to enable CTS and RTS pins diff --git a/patch/kernel/archive/sunxi-6.18/overlay_32/README.sun7i-a20-overlays b/patch/kernel/archive/sunxi-6.18/overlay_32/README.sun7i-a20-overlays new file mode 100644 index 0000000000..7983cac7ce --- /dev/null +++ b/patch/kernel/archive/sunxi-6.18/overlay_32/README.sun7i-a20-overlays @@ -0,0 +1,348 @@ +This document describes overlays provided in the kernel packages +For generic Armbian overlays documentation please see +https://docs.armbian.com/User-Guide_Armbian_overlays/ + +### Platform: + +sun7i-a20 (Allwinner A20) + +### Platform details: + +Supported pin banks: PB, PC, PD, PE, PG, PH, PI + +SPI controller 0 have 2 exposed hardware CS, +other SPI controllers have only one hardware CS +Reference: A20 Datasheet sections 6.3.5.1, 1.19.2 + +I2C bus 0 is used for the AXP209 PMIC + +### Provided overlays: + +- analog-codec +- can +- i2c1 +- i2c2 +- i2c3 +- i2c4 +- i2s0 +- i2s1 +- mmc2 +- nand +- pps-gpio +- pwm +- spdif-out +- spi0 +- spi1 +- spi2 +- spi-add-cs1 +- spi-jedec-nor +- spi-spidev +- uart1 +- uart2 +- uart3 +- uart4 +- uart5 +- uart6 +- uart7 +- w1-gpio + +### Overlay details: + +### analog-codec + +Activates SoC analog codec driver that provides Line Out and Mic In +functionality + +## can + +Activates SoC CAN controller + +CAN pins (TX, RX): PH20, PH21 + +### i2c1 + +Activates TWI/I2C bus 1 + +I2C1 pins (SCL, SDA): PB18, PB19 + +### i2c2 + +Activates TWI/I2C bus 2 + +I2C2 pins (SCL, SDA): PB20, PB21 + +### i2c3 + +Activates TWI/I2C bus 3 + +I2C3 pins (SCL, SDA): PI0, PI1 + +### i2c4 + +Activates TWI/I2C bus 4 + +I2C4 pins (SCL, SDA): PI2, PI3 + +### i2s0 + +Activates SoC I2S controller 0 + +I2S0 pins (MCLK, BCLK, LRCK, DO0, DO1, DO2, DO3, DI): PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12 + +### i2s1 + +Activates SoC I2S controller 1 + +I2S1 pins (MCLK, BCLK, LRCK, DO, DI): PA9, PA14, PA15, PA16, PA17 + +### mmc2 + +Activates SD/MMC controller 2. To be used on boards with second SD slot, eMMC +or tSD instead of NAND storage. + +MMC2 pins: PC6, PC7, PC8, PC9, PC10, PC11 + +Parameters: + +param_mmc2_cd_pin (pin) + SD/MMC 2 card detect pin + Optional + Default: PH0 + +param_mmc2_non_removable (bool) + Option for non-removable storage options on MMC 2 controller (eMMC or tSD) + Optional + Default: 0 + Set to 1 to use this option + +### nand + +Activates NAND controller + +This overlay should not be used until mainline MLC NAND support +allows using NAND storage reliably + +### pps-gpio + +Activates pulse-per-second GPIO client + +Parameters: + +param_pps_pin (pin) + Pin PPS source is connected to + Optional + Default: PI15 + +param_pps_falling_edge (bool) + Assert by falling edge + Optional + Default: 0 + When set (to 1), assert is indicated by a falling edge + (instead of by a rising edge) + +### pwm + +Activates hardware PWM controller + +PWM pins (PWM0, PWM1): PB2, PI3 + +Parameters: + +param_pwm_pins (string) + PWM pins activated with this overlay + Optional + Default: both + Supported values: 0, 1, both + If set to 0 only PWM0 can be used, + if set to 1 then only PWM1 can be used, + if set to both (default), both PWM0 and PWM1 can be used + +### spdif-out + +Activates SPDIF/Toslink audio output + +SPDIF pin: PB13 + +### spi0 + +Activates SPI controller 0 to use it with other overlays and sets up the pin multiplexing for it + +SPI 0 pins (MOSI, MISO, SCK, CS0, CS1): PI12, PI13, PI11, PI10, PI14 + +### spi1 + +Activates SPI controller 1 to use it with other overlays and sets up the pin multiplexing for it + +SPI 1 pins (MOSI, MISO, SCK, CS0): PI18, PI19, PI17, PI16 + +### spi2 + +Activates SPI controller 2 to use it with other overlays and sets up the pin multiplexing for it + +SPI 2 pins a (MOSI, MISO, SCK, CS0): PC21, PC22, PC20, PC19 +SPI 2 pins b (MOSI, MISO, SCK, CS0): PB16, PB17, PB15, PB14 + +Parameters: + +param_spi2_bus_pins (char) + SPI bus 2 pinmux variant + Optional + Default: a + Supported values: a, b + Determines what pins SPI bus 2 is exposed on if SPI 2 is used + +### spi-add-cs1 + +Activates SPI chip select 1 on SPI controller 0 +This overlay is required for using chip select 1 with other SPI overlays + +SPI 0 CS1 pin: PI14 + +### spi-jedec-nor + +Activates MTD support for JEDEC compatible SPI NOR flash chips on SPI bus +supported by the kernel SPI NOR driver + +SPI 0 pins (MOSI, MISO, SCK, CS0, CS1): PI12, PI13, PI11, PI10, PI14 +SPI 1 pins (MOSI, MISO, SCK, CS0): PI18, PI19, PI17, PI16 +SPI 2 pins a (MOSI, MISO, SCK, CS0): PC21, PC22, PC20, PC19 +SPI 2 pins b (MOSI, MISO, SCK, CS0): PB16, PB17, PB15, PB14 + +Parameters: + +param_spinor_spi_bus (int) + SPI bus to activate SPI NOR flash support on + Required + Supported values: 0, 1, 2 + +param_spinor_spi_cs (int) + SPI chip select number for SPI NOR connected to SPI bus 0 + Optional + Default: 0 + Supported values: 0, 1 + Using chip select 1 on SPI 0 requires using "spi-add-cs1" overlay + +param_spinor_max_freq (int) + Maximum SPI frequency + Optional + Default: 1000000 + Range: 3000 - 100000000 + +### spi-spidev + +Activates SPIdev device node (/dev/spidevX.Y) for userspace SPI access, +where X is the bus number and Y is the CS number + +SPI 0 pins (MOSI, MISO, SCK, CS0, CS1): PI12, PI13, PI11, PI10, PI14 +SPI 1 pins (MOSI, MISO, SCK, CS0): PI18, PI19, PI17, PI16 +SPI 2 pins a (MOSI, MISO, SCK, CS0): PC21, PC22, PC20, PC19 +SPI 2 pins b (MOSI, MISO, SCK, CS0): PB16, PB17, PB15, PB14 + +Parameters: + +param_spidev_spi_bus (int) + SPI bus to activate mcp2515 support on + Required + Supported values: 0, 1, 2 + +param_spidev_spi_cs (int) + SPI chip select number for SPIdev on SPI bus 0 + Optional + Default: 0 + Supported values: 0, 1 + Using chip select 1 on SPI 0 requires using "spi-add-cs1" overlay + +param_spidev_max_freq (int) + Maximum SPIdev frequency + Optional + Default: 1000000 + Range: 3000 - 100000000 + +### uart2 + +Activates serial port 2 (/dev/ttyS2) + +UART 2 pins (TX, RX, RTS, CTS): PI18, PI19, PI16, PI17 + +Parameters: + +param_uart2_rtscts (bool) + Enable RTS and CTS pins + Optional + Default: 0 + Set to 1 to enable CTS and RTS pins + +### uart3 + +Activates serial port 3 (/dev/ttyS3) + +UART 3 pins a (TX, RX, RTS, CTS): PG6, PG7, PG8, PG9 +UART 3 pins b (TX, RX, RTS, CTS): PH0, PH1, PH2, PH3 + +Parameters: + +param_uart3_pins (char) + Determines what pins UART 3 is exposed on + Optional + Default: a + Supported values: a, b + +param_uart3_rtscts (bool) + Enable RTS and CTS pins + Optional + Default: 0 + Set to 1 to enable CTS and RTS pins + +### uart4 + +Activates serial port 4 (/dev/ttyS4) + +UART 4 pins a (TX, RX): PG10, PG11 +UART 4 pins b (TX, RX): PH4, PH5 + +Parameters: + +param_uart4_pins (char) + Determines what pins UART 4 is exposed on + Optional + Default: a + Supported values: a, b + +### uart 5 + +Activates serial port 5 (/dev/ttyS5) + +UART 5 pins (TX, RX): PH6, PH7 + +### uart 6 + +Activates serial port 6 (/dev/ttyS6) + +UART 6 pins (TX, RX): PI12, PI13 + +### uart 7 + +Activates serial port 7 (/dev/ttyS7) + +UART 7 pins (TX, RX): PI20, PI21 + +### w1-gpio + +Activates 1-Wire GPIO master +Requires an external pull-up resistor on the data pin +or enabling the internal pull-up + +Parameters: + +param_w1_pin (pin) + Data pin for 1-Wire master + Optional + Default: PI15 + +param_w1_pin_int_pullup (bool) + Enable internal pull-up for the data pin + Optional + Default: 0 + Set to 1 to enable the pull-up + This option should not be used with multiple sensors or long wires - + please use external pull-up resistor instead diff --git a/patch/kernel/archive/sunxi-6.18/overlay_32/README.sun8i-h3-overlays b/patch/kernel/archive/sunxi-6.18/overlay_32/README.sun8i-h3-overlays new file mode 100644 index 0000000000..462439ec48 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.18/overlay_32/README.sun8i-h3-overlays @@ -0,0 +1,250 @@ +This document describes overlays provided in the kernel packages +For generic Armbian overlays documentation please see +https://docs.armbian.com/User-Guide_Armbian_overlays/ + +### Platform: + +sun8i-h3 (Allwinner H3) + +### Platform details: + +Supported pin banks: PA, PC, PD, PG + +Both SPI controllers have only one hardware CS pin exposed, +adding fixed software (GPIO) chip selects is possible with a separate overlay + +### Provided overlays: + +- analog-codec +- cir +- i2c0 +- i2c1 +- i2c2 +- pps-gpio +- pwm +- spdif-out +- spi-add-cs1 +- spi-jedec-nor +- spi-spidev +- uart1 +- uart2 +- uart3 +- usbhost0 +- usbhost1 +- usbhost2 +- usbhost3 +- w1-gpio + +### Overlay details: + +### analog-codec + +Activates SoC analog codec driver that provides Line Out and Mic In +functionality + +### cir + +Activates CIR (Infrared remote) receiver + +CIR pin: PL11 + +### i2c0 + +Activates TWI/I2C bus 0 + +I2C0 pins (SCL, SDA): PA11, PA12 + +### i2c1 + +Activates TWI/I2C bus 1 + +I2C1 pins (SCL, SDA): PA18, PA19 + +### i2c2 + +Activates TWI/I2C bus 2 + +I2C2 pins (SCL, SDA): PE12, PE13 + +On most board this bus is wired to Camera (CSI) socket + +### pps-gpio + +Activates pulse-per-second GPIO client + +Parameters: + +param_pps_pin (pin) + Pin PPS source is connected to + Optional + Default: PD14 + +param_pps_falling_edge (bool) + Assert by falling edge + Optional + Default: 0 + When set (to 1), assert is indicated by a falling edge + (instead of by a rising edge) + +### pwm + +Activates hardware PWM controller + +PWM pin: PA5 + +Pin PA5 is used as UART0 RX by default, so if this overlay is activated, +UART0 and kernel console on ttyS0 will be disabled + +### spdif-out + +Activates SPDIF/Toslink audio output + +SPDIF pin: PA17 + +### spi-add-cs1 + +Adds support for using SPI chip select 1 with GPIO for both SPI controllers +Respective GPIO will be claimed only if controller is enabled by another +overlay +This overlay is required for using chip select 1 with other SPI overlays +Due to the u-boot limitations CS1 pin can't be customized by a parameter, but +it can be changed by using an edited copy of this overlay +A total of 4 chip selects can be used with custom overlays (1 HW + 3 GPIO) + +SPI 0 pins (CS1): PA21 +SPI 1 pins (CS1): PA10 + +### spi-jedec-nor + +Activates MTD support for JEDEC compatible SPI NOR flash chips on SPI bus +supported by the kernel SPI NOR driver + +SPI 0 pins (MOSI, MISO, SCK, CS): PC0, PC1, PC2, PC3 +SPI 1 pins (MOSI, MISO, SCK, CS): PA15, PA16, PA14, PA13 + +Parameters: + +param_spinor_spi_bus (int) + SPI bus to activate SPI NOR flash support on + Required + Supported values: 0, 1 + +param_spinor_spi_cs (int) + SPI chip select number + Optional + Default: 0 + Supported values: 0, 1 + Using chip select 1 requires using "spi-add-cs1" overlay + +param_spinor_max_freq (int) + Maximum SPI frequency + Optional + Default: 1000000 + Range: 3000 - 100000000 + +### spi-spidev + +Activates SPIdev device node (/dev/spidevX.Y) for userspace SPI access, +where X is the bus number and Y is the CS number + +SPI 0 pins (MOSI, MISO, SCK, CS): PC0, PC1, PC2, PC3 +SPI 1 pins (MOSI, MISO, SCK, CS): PA15, PA16, PA14, PA13 + +Parameters: + +param_spidev_spi_bus (int) + SPI bus to activate SPIdev support on + Required + Supported values: 0, 1 + +param_spidev_spi_cs (int) + SPI chip select number + Optional + Default: 0 + Supported values: 0, 1 + Using chip select 1 requires using "spi-add-cs1" overlay + +param_spidev_max_freq (int) + Maximum SPIdev frequency + Optional + Default: 1000000 + Range: 3000 - 100000000 + +### uart1 + +Activates serial port 1 (/dev/ttyS1) + +UART 1 pins (TX, RX, RTS, CTS): PG6, PG7, PG8, PG9 + +Parameters: + +param_uart1_rtscts (bool) + Enable RTS and CTS pins + Optional + Default: 0 + Set to 1 to enable + +### uart2 + +Activates serial port 2 (/dev/ttyS2) + +UART 2 pins (TX, RX, RTS, CTS): PA0, PA1, PA2, PA3 + +Parameters: + +param_uart2_rtscts (bool) + Enable RTS and CTS pins + Optional + Default: 0 + Set to 1 to enable CTS and RTS pins + +### uart3 + +Activates serial port 3 (/dev/ttyS3) + +UART 3 pins (TX, RX, RTS, CTS): PA13, PA14, PA15, PA16 + +Parameters: + +param_uart3_rtscts (bool) + Enable RTS and CTS pins + Optional + Default: 0 + Set to 1 to enable CTS and RTS pins + +### usbhost0 + +Activates USB host controller 0 + +### usbhost1 + +Activates USB host controller 1 + +### usbhost2 + +Activates USB host controller 2 + +### usbhost3 + +Activates USB host controller 3 + +### w1-gpio + +Activates 1-Wire GPIO master +Requires an external pull-up resistor on the data pin +or enabling the internal pull-up + +Parameters: + +param_w1_pin (pin) + Data pin for 1-Wire master + Optional + Default: PD14 + +param_w1_pin_int_pullup (bool) + Enable internal pull-up for the data pin + Optional + Default: 0 + Set to 1 to enable the pull-up + This option should not be used with multiple devices, parasite power setup + or long wires - please use external pull-up resistor instead diff --git a/patch/kernel/archive/sunxi-6.18/overlay_32/sun4i-a10-fixup.scr-cmd b/patch/kernel/archive/sunxi-6.18/overlay_32/sun4i-a10-fixup.scr-cmd new file mode 100644 index 0000000000..c5614cb951 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.18/overlay_32/sun4i-a10-fixup.scr-cmd @@ -0,0 +1,124 @@ +# overlays fixup script +# implements (or rather substitutes) overlay arguments functionality +# using u-boot scripting, environment variables and "fdt" command + +# setexpr test_var ${tmp_bank} - A +# works only for hex numbers (A-F) + +setenv decompose_pin 'setexpr tmp_bank sub "P(B|C|D|E|G|H|I)\\d+" "\\1"; +setexpr tmp_pin sub "P\\S(\\d+)" "\\1"; +test "${tmp_bank}" = "B" && setenv tmp_bank 1; +test "${tmp_bank}" = "C" && setenv tmp_bank 2; +test "${tmp_bank}" = "D" && setenv tmp_bank 3; +test "${tmp_bank}" = "E" && setenv tmp_bank 4; +test "${tmp_bank}" = "G" && setenv tmp_bank 6; +test "${tmp_bank}" = "H" && setenv tmp_bank 7; +test "${tmp_bank}" = "I" && setenv tmp_bank 8' + +if test -n "${param_spinor_spi_bus}"; then + test "${param_spinor_spi_bus}" = "0" && setenv tmp_spi_path "spi@1c05000" + test "${param_spinor_spi_bus}" = "1" && setenv tmp_spi_path "spi@1c06000" + test "${param_spinor_spi_bus}" = "2" && setenv tmp_spi_path "spi@1c17000" + fdt set /soc/${tmp_spi_path} status "okay" + fdt set /soc/${tmp_spi_path}/spiflash status "okay" + if test -n "${param_spinor_max_freq}"; then + fdt set /soc/${tmp_spi_path}/spiflash spi-max-frequency "<${param_spinor_max_freq}>" + fi + env delete tmp_spi_path +fi + +if test -n "${param_spidev_spi_bus}"; then + test "${param_spidev_spi_bus}" = "0" && setenv tmp_spi_path "spi@1c05000" + test "${param_spidev_spi_bus}" = "1" && setenv tmp_spi_path "spi@1c06000" + test "${param_spidev_spi_bus}" = "2" && setenv tmp_spi_path "spi@1c17000" + fdt set /soc/${tmp_spi_path} status "okay" + fdt set /soc/${tmp_spi_path}/spidev status "okay" + if test -n "${param_spidev_max_freq}"; then + fdt set /soc/${tmp_spi_path}/spidev spi-max-frequency "<${param_spidev_max_freq}>" + fi + env delete tmp_spi_path +fi + +if test "${param_spi2_bus_pins}" = "b"; then + fdt get value tmp_phandle1 /soc/pinctrl@1c20800/spi2@1 phandle + fdt get value tmp_phandle2 /soc/pinctrl@1c20800/spi2_cs0@1 phandle + fdt set /soc/spi@1c17000 pinctrl-0 "<${tmp_phandle1}>" + fdt set /soc/spi@1c17000 pinctrl-1 "<${tmp_phandle2}>" + env delete tmp_phandle1 tmp_phandle2 +fi + +if test -n "${param_pps_pin}"; then + setenv tmp_bank "${param_pps_pin}" + setenv tmp_pin "${param_pps_pin}" + run decompose_pin + fdt set /soc/pinctrl@1c20800/pps_pins pins "${param_pps_pin}" + fdt get value tmp_phandle /soc/pinctrl@1c20800 phandle + fdt set /pps@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>" + env delete tmp_pin tmp_bank tmp_phandle +fi + +if test "${param_pps_falling_edge}" = "1"; then + fdt set /pps@0 assert-falling-edge +fi + +if test "${param_pwm_pins}" = "0"; then + fdt get value tmp_phandle /soc/pinctrl@1c20800/pwm0@0 + fdt set /soc/pwm@1c20e00 pinctrl-0 "<${tmp_phandle}>" + env delete tmp_phandle +fi + +if test "${param_pwm_pins}" = "1"; then + fdt get value tmp_phandle /soc/pinctrl@1c20800/pwm1@0 + fdt set /soc/pwm@1c20e00 pinctrl-0 "<${tmp_phandle}>" + env delete tmp_phandle +fi + +if test -n "${param_w1_pin}"; then + setenv tmp_bank "${param_w1_pin}" + setenv tmp_pin "${param_w1_pin}" + run decompose_pin + fdt set /soc/pinctrl@1c20800/w1_pins pins "${param_w1_pin}" + fdt get value tmp_phandle /soc/pinctrl@1c20800 phandle + fdt set /onewire@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>" + env delete tmp_pin tmp_bank tmp_phandle +fi + +if test "${param_w1_pin_int_pullup}" = "1"; then + fdt set /soc/pinctrl@1c20800/w1_pins bias-pull-up +fi + +if test "${param_uart2_rtscts}" = "1"; then + fdt get value tmp_phandle /soc/pinctrl@1c20800/uart2@0 phandle + fdt set /soc/serial@1c28800 pinctrl-0 "<${tmp_phandle}>" + env delete tmp_phandle +fi + +if test "${param_uart3_pins}" = "b"; then + if test "${param_uart3_rtscts}" = "1"; then + fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart3_pins_b phandle + fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart3_pins_b_rts_cts phandle + fdt set /soc/serial@1c28c00 pinctrl-names "default" "default" + fdt set /soc/serial@1c28c00 pinctrl-0 "<${tmp_phandle1}>" + fdt set /soc/serial@1c28c00 pinctrl-1 "<${tmp_phandle2}>" + env delete tmp_phandle1 tmp_phandle2 + else + fdt get value tmp_phandle /soc/pinctrl@1c20800/uart3_pins_b phandle + fdt set /soc/serial@1c28c00 pinctrl-0 "<${tmp_phandle}>" + env delete tmp_phandle + fi +else + if test "${param_uart3_rtscts}" = "1"; then + fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart3_pins_a phandle + fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart3_pins_a_rts_cts phandle + fdt set /soc/serial@1c28c00 pinctrl-names "default" "default" + fdt set /soc/serial@1c28c00 pinctrl-0 "<${tmp_phandle1}>" + fdt set /soc/serial@1c28c00 pinctrl-1 "<${tmp_phandle2}>" + env delete tmp_phandle1 tmp_phandle2 + fi +fi + +if test "${param_uart4_pins}" = "b"; then + fdt get value tmp_phandle /soc/pinctrl@1c20800/uart4@1 phandle + fdt set /soc/serial@1c29000 pinctrl-0 "<${tmp_phandle}>" + env delete tmp_phandle +fi diff --git a/patch/kernel/archive/sunxi-6.18/overlay_32/sun5i-a13-fixup.scr-cmd b/patch/kernel/archive/sunxi-6.18/overlay_32/sun5i-a13-fixup.scr-cmd new file mode 100644 index 0000000000..c82590c1ac --- /dev/null +++ b/patch/kernel/archive/sunxi-6.18/overlay_32/sun5i-a13-fixup.scr-cmd @@ -0,0 +1,48 @@ +# overlays fixup script +# implements (or rather substitutes) overlay arguments functionality +# using u-boot scripting, environment variables and "fdt" command + +if test -n "${param_spinor_spi_bus}"; then + test "${param_spinor_spi_bus}" = "0" && setenv tmp_spi_path "spi@1c05000" + test "${param_spinor_spi_bus}" = "1" && setenv tmp_spi_path "spi@1c06000" + test "${param_spinor_spi_bus}" = "2" && setenv tmp_spi_path "spi@1c17000" + fdt set /soc/${tmp_spi_path} status "okay" + fdt set /soc/${tmp_spi_path}/spiflash status "okay" + if test -n "${param_spinor_max_freq}"; then + fdt set /soc/${tmp_spi_path}/spiflash spi-max-frequency "<${param_spinor_max_freq}>" + fi + env delete tmp_spi_path +fi + +if test -n "${param_spidev_spi_bus}"; then + test "${param_spidev_spi_bus}" = "0" && setenv tmp_spi_path "spi@1c05000" + test "${param_spidev_spi_bus}" = "1" && setenv tmp_spi_path "spi@1c06000" + test "${param_spidev_spi_bus}" = "2" && setenv tmp_spi_path "spi@1c17000" + fdt set /soc/${tmp_spi_path} status "okay" + fdt set /soc/${tmp_spi_path}/spidev status "okay" + if test -n "${param_spidev_max_freq}"; then + fdt set /soc/${tmp_spi_path}/spidev spi-max-frequency "<${param_spidev_max_freq}>" + fi + env delete tmp_spi_path +fi + +if test "${param_uart1_pins}" = "b"; then + fdt get value tmp_phandle /soc/pinctrl@1c28400/uart1@1 phandle + fdt set /soc/serial@1c28400 pinctrl-0 "<${tmp_phandle}>" + env delete tmp_phandle +fi + +if test "${param_uart2_rtscts}" = "1"; then + fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart2@0 phandle + fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart2-cts-rts@0 phandle + fdt set /soc/serial@1c28800 pinctrl-0 "<${tmp_phandle1}>, <${tmp_phandle2}>" + env delete tmp_phandle1 tmp_phandle2 +fi + +if test "${param_uart3_rtscts}" = "1"; then + fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart3@0 phandle + fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart3-cts-rts@0 phandle + fdt set /soc/serial@1c28c00 pinctrl-names "default" "default" + fdt set /soc/serial@1c28c00 pinctrl-0 "<${tmp_phandle1}>, <${tmp_phandle2}>" + env delete tmp_phandle1 tmp_phandle2 +fi diff --git a/patch/kernel/archive/sunxi-6.18/overlay_32/sun7i-a20-fixup.scr-cmd b/patch/kernel/archive/sunxi-6.18/overlay_32/sun7i-a20-fixup.scr-cmd new file mode 100644 index 0000000000..b97042a720 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.18/overlay_32/sun7i-a20-fixup.scr-cmd @@ -0,0 +1,143 @@ +# overlays fixup script +# implements (or rather substitutes) overlay arguments functionality +# using u-boot scripting, environment variables and "fdt" command + +# setexpr test_var ${tmp_bank} - A +# works only for hex numbers (A-F) + +setenv decompose_pin 'setexpr tmp_bank sub "P(B|C|D|E|G|H|I)\\d+" "\\1"; +setexpr tmp_pin sub "P\\S(\\d+)" "\\1"; +test "${tmp_bank}" = "B" && setenv tmp_bank 1; +test "${tmp_bank}" = "C" && setenv tmp_bank 2; +test "${tmp_bank}" = "D" && setenv tmp_bank 3; +test "${tmp_bank}" = "E" && setenv tmp_bank 4; +test "${tmp_bank}" = "G" && setenv tmp_bank 6; +test "${tmp_bank}" = "H" && setenv tmp_bank 7; +test "${tmp_bank}" = "I" && setenv tmp_bank 8' + +if test -n "${param_spinor_spi_bus}"; then + test "${param_spinor_spi_bus}" = "0" && setenv tmp_spi_path "spi@1c05000" + test "${param_spinor_spi_bus}" = "1" && setenv tmp_spi_path "spi@1c06000" + test "${param_spinor_spi_bus}" = "2" && setenv tmp_spi_path "spi@1c17000" + fdt set /soc/${tmp_spi_path} status "okay" + fdt set /soc/${tmp_spi_path}/spiflash status "okay" + if test -n "${param_spinor_max_freq}"; then + fdt set /soc/${tmp_spi_path}/spiflash spi-max-frequency "<${param_spinor_max_freq}>" + fi + if test "${param_spinor_spi_bus}" = "0" && test "${param_spinor_spi_cs}" = "1"; then + fdt set /soc/${tmp_spi_path}/spiflash reg "<1>" + fi + env delete tmp_spi_path +fi + +if test -n "${param_spidev_spi_bus}"; then + test "${param_spidev_spi_bus}" = "0" && setenv tmp_spi_path "spi@1c05000" + test "${param_spidev_spi_bus}" = "1" && setenv tmp_spi_path "spi@1c06000" + test "${param_spidev_spi_bus}" = "2" && setenv tmp_spi_path "spi@1c17000" + fdt set /soc/${tmp_spi_path} status "okay" + fdt set /soc/${tmp_spi_path}/spidev status "okay" + if test -n "${param_spidev_max_freq}"; then + fdt set /soc/${tmp_spi_path}/spidev spi-max-frequency "<${param_spidev_max_freq}>" + fi + if test "${param_spidev_spi_bus}" = "0" && test "${param_spidev_spi_cs}" = "1"; then + fdt set /soc/${tmp_spi_path}/spidev reg "<1>" + fi + env delete tmp_spi_path +fi + +if test "${param_spi2_bus_pins}" = "b"; then + fdt get value tmp_phandle1 /soc/pinctrl@1c20800/spi2@1 phandle + fdt get value tmp_phandle2 /soc/pinctrl@1c20800/spi2_cs0@1 phandle + fdt set /soc/spi@1c17000 pinctrl-0 "<${tmp_phandle1}>" + fdt set /soc/spi@1c17000 pinctrl-1 "<${tmp_phandle2}>" + env delete tmp_phandle1 tmp_phandle2 +fi + +if test -n "${param_pps_pin}"; then + setenv tmp_bank "${param_pps_pin}" + setenv tmp_pin "${param_pps_pin}" + run decompose_pin + fdt set /soc/pinctrl@1c20800/pps_pins pins "${param_pps_pin}" + fdt get value tmp_phandle /soc/pinctrl@1c20800 phandle + fdt set /pps@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>" + env delete tmp_pin tmp_bank tmp_phandle +fi + +if test "${param_pps_falling_edge}" = "1"; then + fdt set /pps@0 assert-falling-edge +fi + +if test "${param_pwm_pins}" = "0"; then + fdt get value tmp_phandle /soc/pinctrl@1c20800/pwm0@0 + fdt set /soc/pwm@1c20e00 pinctrl-0 "<${tmp_phandle}>" + env delete tmp_phandle +fi + +if test "${param_pwm_pins}" = "1"; then + fdt get value tmp_phandle /soc/pinctrl@1c20800/pwm1@0 + fdt set /soc/pwm@1c20e00 pinctrl-0 "<${tmp_phandle}>" + env delete tmp_phandle +fi + +if test -n "${param_w1_pin}"; then + setenv tmp_bank "${param_w1_pin}" + setenv tmp_pin "${param_w1_pin}" + run decompose_pin + fdt set /soc/pinctrl@1c20800/w1_pins pins "${param_w1_pin}" + fdt get value tmp_phandle /soc/pinctrl@1c20800 phandle + fdt set /onewire@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>" + env delete tmp_pin tmp_bank tmp_phandle +fi + +if test -n "${param_mmc2_cd_pin}"; then + setenv tmp_bank "${param_mmc2_cd_pin}" + setenv tmp_pin "${param_mmc2_cd_pin}" + run decompose_pin + fdt get value tmp_phandle /soc/pinctrl@1c20800 phandle + fdt set /soc/mmc@1c11000 cd-gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 1>" +fi + +if test "${param_mmc2_non_removable}" = "1"; then + fdt rm /soc/mmc@1c11000 cd-gpios + fdt set /soc/mmc@1c11000 non-removable +fi + +if test "${param_w1_pin_int_pullup}" = "1"; then + fdt set /soc/pinctrl@1c20800/w1_pins bias-pull-up +fi + +if test "${param_uart2_rtscts}" = "1"; then + fdt get value tmp_phandle /soc/pinctrl@1c20800/uart2-pi-pins phandle + fdt set /soc/serial@1c28800 pinctrl-0 "<${tmp_phandle}>" + env delete tmp_phandle +fi + +if test "${param_uart3_pins}" = "b"; then + if test "${param_uart3_rtscts}" = "1"; then + fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart3-ph-pins phandle + fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart3-cts-rts-ph-pins phandle + fdt set /soc/serial@1c28c00 pinctrl-names "default" "default" + fdt set /soc/serial@1c28c00 pinctrl-0 "<${tmp_phandle1}>" + fdt set /soc/serial@1c28c00 pinctrl-1 "<${tmp_phandle2}>" + env delete tmp_phandle1 tmp_phandle2 + else + fdt get value tmp_phandle /soc/pinctrl@1c20800/uart3-ph-pins phandle + fdt set /soc/serial@1c28c00 pinctrl-0 "<${tmp_phandle}>" + env delete tmp_phandle + fi +else + if test "${param_uart3_rtscts}" = "1"; then + fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart3-pg-pins phandle + fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart3-cts-rts-pg-pins phandle + fdt set /soc/serial@1c28c00 pinctrl-names "default" "default" + fdt set /soc/serial@1c28c00 pinctrl-0 "<${tmp_phandle1}>" + fdt set /soc/serial@1c28c00 pinctrl-1 "<${tmp_phandle2}>" + env delete tmp_phandle1 tmp_phandle2 + fi +fi + +if test "${param_uart4_pins}" = "b"; then + fdt get value tmp_phandle /soc/pinctrl@1c20800/uart4-pg-pins phandle + fdt set /soc/serial@1c29000 pinctrl-0 "<${tmp_phandle}>" + env delete tmp_phandle +fi diff --git a/patch/kernel/archive/sunxi-6.18/overlay_32/sun8i-h3-fixup.scr-cmd b/patch/kernel/archive/sunxi-6.18/overlay_32/sun8i-h3-fixup.scr-cmd new file mode 100644 index 0000000000..604fe8bb78 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.18/overlay_32/sun8i-h3-fixup.scr-cmd @@ -0,0 +1,110 @@ +# overlays fixup script +# implements (or rather substitutes) overlay arguments functionality +# using u-boot scripting, environment variables and "fdt" command + +# setexpr test_var ${tmp_bank} - A +# works only for hex numbers (A-F) + +setenv decompose_pin 'setexpr tmp_bank sub "P(A|C|D|G)\\d+" "\\1"; +setexpr tmp_pin sub "P\\S(\\d+)" "\\1"; +test "${tmp_bank}" = "A" && setenv tmp_bank 0; +test "${tmp_bank}" = "C" && setenv tmp_bank 2; +test "${tmp_bank}" = "D" && setenv tmp_bank 3; +test "${tmp_bank}" = "G" && setenv tmp_bank 6' + +if test -n "${param_spinor_spi_bus}"; then + test "${param_spinor_spi_bus}" = "0" && setenv tmp_spi_path "spi@1c68000" + test "${param_spinor_spi_bus}" = "1" && setenv tmp_spi_path "spi@1c69000" + fdt set /soc/${tmp_spi_path} status "okay" + fdt set /soc/${tmp_spi_path}/spiflash status "okay" + if test -n "${param_spinor_max_freq}"; then + fdt set /soc/${tmp_spi_path}/spiflash spi-max-frequency "<${param_spinor_max_freq}>" + fi + if test "${param_spinor_spi_cs}" = "1"; then + fdt set /soc/${tmp_spi_path}/spiflash reg "<1>" + fi + env delete tmp_spi_path +fi + +if test -n "${param_spidev_spi_bus}"; then + test "${param_spidev_spi_bus}" = "0" && setenv tmp_spi_path "spi@1c68000" + test "${param_spidev_spi_bus}" = "1" && setenv tmp_spi_path "spi@1c69000" + fdt set /soc/${tmp_spi_path} status "okay" + fdt set /soc/${tmp_spi_path}/spidev status "okay" + if test -n "${param_spidev_max_freq}"; then + fdt set /soc/${tmp_spi_path}/spidev spi-max-frequency "<${param_spidev_max_freq}>" + fi + if test "${param_spidev_spi_cs}" = "1"; then + fdt set /soc/${tmp_spi_path}/spidev reg "<1>" + fi + env delete tmp_spi_path +fi + +if test -n "${param_pps_pin}"; then + setenv tmp_bank "${param_pps_pin}" + setenv tmp_pin "${param_pps_pin}" + run decompose_pin + fdt set /soc/pinctrl@1c20800/pps_pins pins "${param_pps_pin}" + fdt get value tmp_phandle /soc/pinctrl@1c20800 phandle + fdt set /pps@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>" + env delete tmp_pin tmp_bank tmp_phandle +fi + +if test "${param_pps_falling_edge}" = "1"; then + fdt set /pps@0 assert-falling-edge +fi + +for f in ${overlays}; do + if test "${f}" = "pwm"; then + setenv bootargs_new "" + for arg in ${bootargs}; do + if test "${arg}" = "console=ttyS0,115200"; then + echo "Warning: Disabling ttyS0 console due to enabled PWM overlay" + else + setenv bootargs_new "${bootargs_new} ${arg}" + fi + done + setenv bootargs "${bootargs_new}" + fi +done + +if test -n "${param_w1_pin}"; then + setenv tmp_bank "${param_w1_pin}" + setenv tmp_pin "${param_w1_pin}" + run decompose_pin + fdt set /soc/pinctrl@1c20800/w1_pins pins "${param_w1_pin}" + fdt get value tmp_phandle /soc/pinctrl@1c20800 phandle + fdt set /onewire@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>" + env delete tmp_pin tmp_bank tmp_phandle +fi + +if test "${param_w1_pin_int_pullup}" = "1"; then + fdt set /soc/pinctrl@1c20800/w1_pins bias-pull-up +fi + +if test "${param_uart1_rtscts}" = "1"; then + fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart1-pins phandle + fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart1-rts-cts-pins phandle + fdt set /soc/serial@1c28400 pinctrl-names "default" "default" + fdt set /soc/serial@1c28400 pinctrl-0 "<${tmp_phandle1}>" + fdt set /soc/serial@1c28400 pinctrl-1 "<${tmp_phandle2}>" + env delete tmp_phandle1 tmp_phandle2 +fi + +if test "${param_uart2_rtscts}" = "1"; then + fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart2-pins phandle + fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart2-rts-cts-pins phandle + fdt set /soc/serial@1c28800 pinctrl-names "default" "default" + fdt set /soc/serial@1c28800 pinctrl-0 "<${tmp_phandle1}>" + fdt set /soc/serial@1c28800 pinctrl-1 "<${tmp_phandle2}>" + env delete tmp_phandle1 tmp_phandle2 +fi + +if test "${param_uart3_rtscts}" = "1"; then + fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart3-pins phandle + fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart3-rts-cts-pins phandle + fdt set /soc/serial@1c28c00 pinctrl-names "default" "default" + fdt set /soc/serial@1c28c00 pinctrl-0 "<${tmp_phandle1}>" + fdt set /soc/serial@1c28c00 pinctrl-1 "<${tmp_phandle2}>" + env delete tmp_phandle1 tmp_phandle2 +fi diff --git a/patch/kernel/archive/sunxi-6.18/overlay_64/Makefile b/patch/kernel/archive/sunxi-6.18/overlay_64/Makefile new file mode 100644 index 0000000000..db0d41f60e --- /dev/null +++ b/patch/kernel/archive/sunxi-6.18/overlay_64/Makefile @@ -0,0 +1,117 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_SUNXI) += \ + sun50i-a64-i2c0.dtbo \ + sun50i-a64-i2c1.dtbo \ + sun50i-a64-pine64-7inch-lcd.dtbo \ + sun50i-a64-pps-gpio.dtbo \ + sun50i-a64-spi-add-cs1.dtbo \ + sun50i-a64-spi-jedec-nor.dtbo \ + sun50i-a64-spi-spidev.dtbo \ + sun50i-a64-uart1.dtbo \ + sun50i-a64-uart2.dtbo \ + sun50i-a64-uart3.dtbo \ + sun50i-a64-uart4.dtbo \ + sun50i-a64-w1-gpio.dtbo \ + sun50i-h5-analog-codec.dtbo \ + sun50i-h5-cir.dtbo \ + sun50i-h5-cpu-clock-1.0GHz-1.1v.dtbo \ + sun50i-h5-cpu-clock-1.2GHz-1.3v.dtbo \ + sun50i-h5-cpu-clock-1.3GHz-1.3v.dtbo \ + sun50i-h5-gpio-regulator-1.3v.dtbo \ + sun50i-h5-i2c0.dtbo \ + sun50i-h5-i2c1.dtbo \ + sun50i-h5-i2c2.dtbo \ + sun50i-h5-pps-gpio.dtbo \ + sun50i-h5-pwm.dtbo \ + sun50i-h5-spdif-out.dtbo \ + sun50i-h5-spi-add-cs1.dtbo \ + sun50i-h5-spi-jedec-nor.dtbo \ + sun50i-h5-spi-spidev.dtbo \ + sun50i-h5-uart1.dtbo \ + sun50i-h5-uart2.dtbo \ + sun50i-h5-uart3.dtbo \ + sun50i-h5-usbhost0.dtbo \ + sun50i-h5-usbhost1.dtbo \ + sun50i-h5-usbhost2.dtbo \ + sun50i-h5-usbhost3.dtbo \ + sun50i-h5-w1-gpio.dtbo \ + sun50i-h6-i2c0.dtbo \ + sun50i-h6-i2c1.dtbo \ + sun50i-h6-i2c2.dtbo \ + sun50i-h6-pwm.dtbo \ + sun50i-h6-ruart.dtbo \ + sun50i-h6-spi-add-cs1.dtbo \ + sun50i-h6-spi-jedec-nor.dtbo \ + sun50i-h6-spi-spidev.dtbo \ + sun50i-h6-spi-spidev1.dtbo \ + sun50i-h6-uart1.dtbo \ + sun50i-h6-uart2.dtbo \ + sun50i-h6-uart3.dtbo \ + sun50i-h6-w1-gpio.dtbo \ + sun50i-h616-bananapi-m4-pg-6-7-uart1.dtbo \ + sun50i-h616-bananapi-m4-pg-8-9-rts-cts-uart1.dtbo \ + sun50i-h616-bananapi-m4-pg-15-16-i2c4.dtbo \ + sun50i-h616-bananapi-m4-pg-17-18-i2c3.dtbo \ + sun50i-h616-bananapi-m4-ph-2-3-uart5.dtbo \ + sun50i-h616-bananapi-m4-pi-13-14-uart4.dtbo \ + sun50i-h616-bananapi-m4-pi-15-16-rts-cts-uart4.dtbo \ + sun50i-h616-bananapi-m4-pi-5-6-i2c0.dtbo \ + sun50i-h616-bananapi-m4-pi-7-8-i2c1.dtbo \ + sun50i-h616-bananapi-m4-sdio-wifi-bt.dtbo \ + sun50i-h616-bananapi-m4-spi1-cs0-cs1-spidev.dtbo \ + sun50i-h616-bananapi-m4-spi1-cs0-spidev.dtbo \ + sun50i-h616-bananapi-m4-spi1-cs1-spidev.dtbo \ + sun50i-h616-gpu.dtbo \ + sun50i-h616-i2c0-pi.dtbo \ + sun50i-h616-i2c1-pi.dtbo \ + sun50i-h616-i2c2-pi.dtbo \ + sun50i-h616-i2c2-ph.dtbo \ + sun50i-h616-i2c3-pg.dtbo \ + sun50i-h616-i2c3-ph.dtbo \ + sun50i-h616-i2c4-pg.dtbo \ + sun50i-h616-i2c4-ph.dtbo \ + sun50i-h616-keys.dtbo \ + sun50i-h616-pwm1-ph3.dtbo \ + sun50i-h616-pwm1-pi11.dtbo \ + sun50i-h616-pwm2-ph2.dtbo \ + sun50i-h616-pwm2-pi12.dtbo \ + sun50i-h616-pwm3-ph0.dtbo \ + sun50i-h616-pwm3-pi13.dtbo \ + sun50i-h616-pwm4-ph1.dtbo \ + sun50i-h616-pwm4-pi14.dtbo \ + sun50i-h616-uart2-pg.dtbo \ + sun50i-h616-uart2-pg-rts-cts.dtbo \ + sun50i-h616-uart2-ph.dtbo \ + sun50i-h616-uart2-ph-rts-cts.dtbo \ + sun50i-h616-uart2-pi.dtbo \ + sun50i-h616-uart2-pi-rts-cts.dtbo \ + sun50i-h616-uart3-pi.dtbo \ + sun50i-h616-uart3-pi-rts-cts.dtbo \ + sun50i-h616-uart4-pi.dtbo \ + sun50i-h616-uart4-pi-rts-cts.dtbo \ + sun50i-h616-uart5.dtbo \ + sun50i-h616-spi-spidev.dtbo \ + sun50i-h616-spidev0_0.dtbo \ + sun50i-h616-spidev1_0.dtbo \ + sun50i-h616-spidev1_1.dtbo \ + sun50i-h616-spidev1_2.dtbo \ + sun50i-h616-ir.dtbo \ + sun50i-h616-tft35_spi.dtbo \ + sun50i-h616-mcp2515.dtbo \ + sun50i-h616-ws2812.dtbo \ + sun50i-h616-light.dtbo + +scr-$(CONFIG_ARCH_SUNXI) += \ + sun50i-a64-fixup.scr \ + sun50i-h5-fixup.scr \ + sun50i-h6-fixup.scr \ + sun50i-h616-fixup.scr + +dtbotxt-$(CONFIG_ARCH_SUNXI) += \ + README.sun50i-a64-overlays \ + README.sun50i-h5-overlays + +targets += $(dtb-y) $(scr-y) $(dtbotxt-y) + +always := $(dtb-y) $(scr-y) $(dtbotxt-y) +clean-files := *.dtbo *.scr diff --git a/patch/kernel/archive/sunxi-6.18/overlay_64/README.sun50i-a64-overlays b/patch/kernel/archive/sunxi-6.18/overlay_64/README.sun50i-a64-overlays new file mode 100644 index 0000000000..b684c2e3ab --- /dev/null +++ b/patch/kernel/archive/sunxi-6.18/overlay_64/README.sun50i-a64-overlays @@ -0,0 +1,201 @@ +This document describes overlays provided in the kernel packages +For generic Armbian overlays documentation please see +https://docs.armbian.com/Hardware_Allwinner_overlays/ + +### Platform: + +sun50i-a64 (Allwinner A64) + +### Platform details: + +Supported pin banks: PB, PC, PD, PH + +Both SPI controllers have only one hardware CS pin exposed, +adding fixed software (GPIO) chip selects is possible with a separate overlay + +I2C controller 2 (PE14, PE15) pins are used for non-I2C CSI functions or are not available +on supported boards, so this controller is not supported in provided overlays + +### Provided overlays: + +- i2c0 +- i2c1 +- pine64-7inch-lcd +- pps-gpio +- spi-add-cs1 +- spi-jedec-nor +- spi-spidev +- uart1 +- uart2 +- uart3 +- uart4 +- w1-gpio + +### Overlay details: + +### i2c0 + +Activates TWI/I2C bus 0 + +I2C0 pins (SCL, SDA): PH0, PH1 + +### i2c1 + +Activates TWI/I2C bus 1 + +I2C1 pins (SCL, SDA): PH2, PH3 + +### pine64-7inch-lcd + +Activates the Pine64 7" LCD on pine64/pine64so boards + +### pps-gpio + +Activates pulse-per-second GPIO client + +Parameters: + +param_pps_pin (pin) + Pin PPS source is connected to + Optional + Default: PD4 + +param_pps_falling_edge (bool) + Assert by falling edge + Optional + Default: 0 + When set (to 1), assert is indicated by a falling edge + (instead of by a rising edge) + +### spi-add-cs1 + +Adds support for using SPI chip select 1 with GPIO for both SPI controllers +Respective GPIO will be claimed only if controller is enabled by another overlay +This overlay is required for using chip select 1 with other SPI overlays + +SPI 0 pins (CS1): PB6 +SPI 1 pins (CS1): PD6 + +### spi-jedec-nor + +Activates MTD support for JEDEC compatible SPI NOR flash chips on SPI bus +supported by the kernel SPI NOR driver + +SPI 0 pins (MOSI, MISO, SCK, CS): PC0, PC1, PC2, PC3 +SPI 1 pins (MOSI, MISO, SCK, CS): PD2, PD3, PD1, PD0 + +Parameters: + +param_spinor_spi_bus (int) + SPI bus to activate SPI NOR flash support on + Required + Supported values: 0, 1 + +param_spinor_spi_cs (int) + SPI chip select number + Optional + Default: 0 + Supported values: 0, 1 + Using chip select 1 requires using "spi-add-cs1" overlay + +param_spinor_max_freq (int) + Maximum SPI frequency + Optional + Default: 1000000 + Range: 3000 - 100000000 + +### spi-spidev + +Activates SPIdev device node (/dev/spidevX.Y) for userspace SPI access, +where X is the bus number and Y is the CS number + +SPI 0 pins (MOSI, MISO, SCK, CS): PC0, PC1, PC2, PC3 +SPI 1 pins (MOSI, MISO, SCK, CS): PD2, PD3, PD1, PD0 + +Parameters: + +param_spidev_spi_bus (int) + SPI bus to activate SPIdev support on + Required + Supported values: 0, 1 + +param_spidev_spi_cs (int) + SPI chip select number + Optional + Default: 0 + Supported values: 0, 1 + Using chip select 1 requires using "spi-add-cs1" overlay + +param_spidev_max_freq (int) + Maximum SPIdev frequency + Optional + Default: 1000000 + Range: 3000 - 100000000 + +### uart1 + +Activates serial port 1 (/dev/ttyS1) + +UART 1 pins (TX, RX, RTS, CTS): PG6, PG7, PG8, PG9 + +Parameters: + +param_uart1_rtscts (bool) + Enable RTS and CTS pins + Optional + Default: 0 + Set to 1 to enable + +### uart2 + +Activates serial port 2 (/dev/ttyS2) + +UART 2 pins (TX, RX, RTS, CTS): PB0, PB1, PB2, PB3 + +Parameters: + +param_uart2_rtscts (bool) + Enable RTS and CTS pins + Optional + Default: 0 + Set to 1 to enable CTS and RTS pins + +### uart3 + +Activates serial port 3 (/dev/ttyS3) + +UART 3 pins (TX, RX): PD0, PD1 + +### uart4 + +Activates serial port 4 (/dev/ttyS4) + +UART 4 pins (TX, RX, RTS, CTS): PD2, PD3, PD4, PD5 + +Parameters: + +param_uart2_rtscts (bool) + Enable RTS and CTS pins + Optional + Default: 0 + Set to 1 to enable CTS and RTS pins + +### w1-gpio + +Activates 1-Wire GPIO master +Requires external pull-up resistor on data pin + +Parameters: + +param_w1_pin (pin) + Data pin for 1-Wire master + Optional + Default: PD4 + +param_w1_pin_int_pullup (bool) + Enable internal pull-up for the data pin + Optional + Default: 0 + Set to 1 to enable the pull-up + This option should not be used with multiple devices, parasite power setup + or long wires - please use external pull-up resistor instead diff --git a/patch/kernel/archive/sunxi-6.18/overlay_64/README.sun50i-h5-overlays b/patch/kernel/archive/sunxi-6.18/overlay_64/README.sun50i-h5-overlays new file mode 100644 index 0000000000..4ad72deb82 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.18/overlay_64/README.sun50i-h5-overlays @@ -0,0 +1,250 @@ +This document describes overlays provided in the kernel packages +For generic Armbian overlays documentation please see +https://docs.armbian.com/User-Guide_Armbian_overlays/ + +### Platform: + +sun50i-h5 (Allwinner H5) + +### Platform details: + +Supported pin banks: PA, PC, PD, PG + +Both SPI controllers have only one hardware CS pin exposed, +adding fixed software (GPIO) chip selects is possible with a separate overlay + +### Provided overlays: + +- analog-codec +- cir +- i2c0 +- i2c1 +- i2c2 +- pps-gpio +- pwm +- spdif-out +- spi-add-cs1 +- spi-jedec-nor +- spi-spidev +- uart1 +- uart2 +- uart3 +- usbhost0 +- usbhost1 +- usbhost2 +- usbhost3 +- w1-gpio + +### Overlay details: + +### analog-codec + +Activates SoC analog codec driver that provides Line Out and Mic In +functionality + +### cir + +Activates CIR (Infrared remote) receiver + +CIR pin: PL11 + +### i2c0 + +Activates TWI/I2C bus 0 + +I2C0 pins (SCL, SDA): PA11, PA12 + +### i2c1 + +Activates TWI/I2C bus 1 + +I2C1 pins (SCL, SDA): PA18, PA19 + +### i2c2 + +Activates TWI/I2C bus 2 + +I2C2 pins (SCL, SDA): PE12, PE13 + +On most board this bus is wired to Camera (CSI) socket + +### pps-gpio + +Activates pulse-per-second GPIO client + +Parameters: + +param_pps_pin (pin) + Pin PPS source is connected to + Optional + Default: PD14 + +param_pps_falling_edge (bool) + Assert by falling edge + Optional + Default: 0 + When set (to 1), assert is indicated by a falling edge + (instead of by a rising edge) + +### pwm + +Activates hardware PWM controller + +PWM pin: PA5 + +Pin PA5 is used as UART0 RX by default, so if this overlay is activated, +UART0 and kernel console on ttyS0 will be disabled + +### spdif-out + +Activates SPDIF/Toslink audio output + +SPDIF pin: PA17 + +### spi-add-cs1 + +Adds support for using SPI chip select 1 with GPIO for both SPI controllers +Respective GPIO will be claimed only if controller is enabled by another +overlay +This overlay is required for using chip select 1 with other SPI overlays +Due to the u-boot limitations CS1 pin can't be customized by a parameter, but +it can be changed by using an edited copy of this overlay +A total of 4 chip selects can be used with custom overlays (1 HW + 3 GPIO) + +SPI 0 pins (CS1): PA21 +SPI 1 pins (CS1): PA10 + +### spi-jedec-nor + +Activates MTD support for JEDEC compatible SPI NOR flash chips on SPI bus +supported by the kernel SPI NOR driver + +SPI 0 pins (MOSI, MISO, SCK, CS): PC0, PC1, PC2, PC3 +SPI 1 pins (MOSI, MISO, SCK, CS): PA15, PA16, PA14, PA13 + +Parameters: + +param_spinor_spi_bus (int) + SPI bus to activate SPI NOR flash support on + Required + Supported values: 0, 1 + +param_spinor_spi_cs (int) + SPI chip select number + Optional + Default: 0 + Supported values: 0, 1 + Using chip select 1 requires using "spi-add-cs1" overlay + +param_spinor_max_freq (int) + Maximum SPI frequency + Optional + Default: 1000000 + Range: 3000 - 100000000 + +### spi-spidev + +Activates SPIdev device node (/dev/spidevX.Y) for userspace SPI access, +where X is the bus number and Y is the CS number + +SPI 0 pins (MOSI, MISO, SCK, CS): PC0, PC1, PC2, PC3 +SPI 1 pins (MOSI, MISO, SCK, CS): PA15, PA16, PA14, PA13 + +Parameters: + +param_spidev_spi_bus (int) + SPI bus to activate SPIdev support on + Required + Supported values: 0, 1 + +param_spidev_spi_cs (int) + SPI chip select number + Optional + Default: 0 + Supported values: 0, 1 + Using chip select 1 requires using "spi-add-cs1" overlay + +param_spidev_max_freq (int) + Maximum SPIdev frequency + Optional + Default: 1000000 + Range: 3000 - 100000000 + +### uart1 + +Activates serial port 1 (/dev/ttyS1) + +UART 1 pins (TX, RX, RTS, CTS): PG6, PG7, PG8, PG9 + +Parameters: + +param_uart1_rtscts (bool) + Enable RTS and CTS pins + Optional + Default: 0 + Set to 1 to enable + +### uart2 + +Activates serial port 2 (/dev/ttyS2) + +UART 2 pins (TX, RX, RTS, CTS): PA0, PA1, PA2, PA3 + +Parameters: + +param_uart2_rtscts (bool) + Enable RTS and CTS pins + Optional + Default: 0 + Set to 1 to enable CTS and RTS pins + +### uart3 + +Activates serial port 3 (/dev/ttyS3) + +UART 3 pins (TX, RX, RTS, CTS): PA13, PA14, PA15, PA16 + +Parameters: + +param_uart3_rtscts (bool) + Enable RTS and CTS pins + Optional + Default: 0 + Set to 1 to enable CTS and RTS pins + +### usbhost0 + +Activates USB host controller 0 + +### usbhost1 + +Activates USB host controller 1 + +### usbhost2 + +Activates USB host controller 2 + +### usbhost3 + +Activates USB host controller 3 + +### w1-gpio + +Activates 1-Wire GPIO master +Requires an external pull-up resistor on the data pin +or enabling the internal pull-up + +Parameters: + +param_w1_pin (pin) + Data pin for 1-Wire master + Optional + Default: PD14 + +param_w1_pin_int_pullup (bool) + Enable internal pull-up for the data pin + Optional + Default: 0 + Set to 1 to enable the pull-up + This option should not be used with multiple devices, parasite power setup + or long wires - please use external pull-up resistor instead diff --git a/patch/kernel/archive/sunxi-6.18/overlay_64/sun50i-a64-fixup.scr-cmd b/patch/kernel/archive/sunxi-6.18/overlay_64/sun50i-a64-fixup.scr-cmd new file mode 100644 index 0000000000..9b34c05ecf --- /dev/null +++ b/patch/kernel/archive/sunxi-6.18/overlay_64/sun50i-a64-fixup.scr-cmd @@ -0,0 +1,95 @@ +# overlays fixup script +# implements (or rather substitutes) overlay arguments functionality +# using u-boot scripting, environment variables and "fdt" command + +# setexpr test_var ${tmp_bank} - A +# works only for hex numbers (A-F) + +setenv decompose_pin 'setexpr tmp_bank sub "P(B|C|D|H)\\d+" "\\1"; +setexpr tmp_pin sub "P\\S(\\d+)" "\\1"; +test "${tmp_bank}" = "B" && setenv tmp_bank 1; +test "${tmp_bank}" = "C" && setenv tmp_bank 2; +test "${tmp_bank}" = "D" && setenv tmp_bank 3; +test "${tmp_bank}" = "H" && setenv tmp_bank 7' + +if test -n "${param_spinor_spi_bus}"; then + test "${param_spinor_spi_bus}" = "0" && setenv tmp_spi_path "spi@1c68000" + test "${param_spinor_spi_bus}" = "1" && setenv tmp_spi_path "spi@1c69000" + fdt set /soc/${tmp_spi_path} status "okay" + fdt set /soc/${tmp_spi_path}/spiflash@0 status "okay" + if test -n "${param_spinor_max_freq}"; then + fdt set /soc/${tmp_spi_path}/spiflash@0 spi-max-frequency "<${param_spinor_max_freq}>" + fi + if test "${param_spinor_spi_cs}" = "1"; then + fdt set /soc/${tmp_spi_path}/spiflash@0 reg "<1>"; + fi + env delete tmp_spi_path +fi + +if test -n "${param_spidev_spi_bus}"; then + test "${param_spidev_spi_bus}" = "0" && setenv tmp_spi_path "spi@1c68000" + test "${param_spidev_spi_bus}" = "1" && setenv tmp_spi_path "spi@1c69000" + fdt set /soc/${tmp_spi_path} status "okay" + fdt set /soc/${tmp_spi_path}/spidev status "okay" + if test -n "${param_spidev_max_freq}"; then + fdt set /soc/${tmp_spi_path}/spidev spi-max-frequency "<${param_spidev_max_freq}>" + fi + if test "${param_spidev_spi_cs}" = "1"; then + fdt set /soc/${tmp_spi_path}/spidev reg "<1>"; + fi +fi + +if test -n "${param_pps_pin}"; then + setenv tmp_bank "${param_pps_pin}" + setenv tmp_pin "${param_pps_pin}" + run decompose_pin + fdt set /soc/pinctrl@1c20800/pps_pins pins "${param_pps_pin}" + fdt get value tmp_phandle /soc/pinctrl@1c20800 phandle + fdt set /pps@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>" + env delete tmp_pin tmp_bank tmp_phandle +fi + +if test "${param_pps_falling_edge}" = "1"; then + fdt set /pps@0 assert-falling-edge +fi + +if test -n "${param_w1_pin}"; then + setenv tmp_bank "${param_w1_pin}" + setenv tmp_pin "${param_w1_pin}" + run decompose_pin + fdt set /soc/pinctrl@1c20800/w1_pins pins "${param_w1_pin}" + fdt get value tmp_phandle /soc/pinctrl@1c20800 phandle + fdt set /onewire@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>" + env delete tmp_pin tmp_bank tmp_phandle +fi + +if test "${param_w1_pin_int_pullup}" = "1"; then + fdt set /soc/pinctrl@1c20800/w1_pins bias-pull-up +fi + +if test "${param_uart1_rtscts}" = "1"; then + fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart1-pins phandle + fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart1-rts-cts-pins phandle + fdt set /soc/serial@1c28400 pinctrl-names "default" "default" + fdt set /soc/serial@1c28400 pinctrl-0 "<${tmp_phandle1}>" + fdt set /soc/serial@1c28400 pinctrl-1 "<${tmp_phandle2}>" + env delete tmp_phandle1 tmp_phandle2 +fi + +if test "${param_uart2_rtscts}" = "1"; then + fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart2-pins phandle + fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart2-rts-cts-pins phandle + fdt set /soc/serial@1c28800 pinctrl-names "default" "default" + fdt set /soc/serial@1c28800 pinctrl-0 "<${tmp_phandle1}>" + fdt set /soc/serial@1c28800 pinctrl-1 "<${tmp_phandle2}>" + env delete tmp_phandle1 tmp_phandle2 +fi + +if test "${param_uart4_rtscts}" = "1"; then + fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart4-pins phandle + fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart4-rts-cts-pins phandle + fdt set /soc/serial@1c29000 pinctrl-names "default" "default" + fdt set /soc/serial@1c29000 pinctrl-0 "<${tmp_phandle1}>" + fdt set /soc/serial@1c29000 pinctrl-1 "<${tmp_phandle2}>" + env delete tmp_phandle1 tmp_phandle2 +fi diff --git a/patch/kernel/archive/sunxi-6.18/overlay_64/sun50i-h5-fixup.scr-cmd b/patch/kernel/archive/sunxi-6.18/overlay_64/sun50i-h5-fixup.scr-cmd new file mode 100644 index 0000000000..7abb64d84a --- /dev/null +++ b/patch/kernel/archive/sunxi-6.18/overlay_64/sun50i-h5-fixup.scr-cmd @@ -0,0 +1,110 @@ +# overlays fixup script +# implements (or rather substitutes) overlay arguments functionality +# using u-boot scripting, environment variables and "fdt" command + +# setexpr test_var ${tmp_bank} - A +# works only for hex numbers (A-F) + +setenv decompose_pin 'setexpr tmp_bank sub "P(A|C|D|G)\\d+" "\\1"; +setexpr tmp_pin sub "P\\S(\\d+)" "\\1"; +test "${tmp_bank}" = "A" && setenv tmp_bank 0; +test "${tmp_bank}" = "C" && setenv tmp_bank 2; +test "${tmp_bank}" = "D" && setenv tmp_bank 3; +test "${tmp_bank}" = "G" && setenv tmp_bank 6' + +if test -n "${param_spinor_spi_bus}"; then + test "${param_spinor_spi_bus}" = "0" && setenv tmp_spi_path "spi@1c68000" + test "${param_spinor_spi_bus}" = "1" && setenv tmp_spi_path "spi@1c69000" + fdt set /soc/${tmp_spi_path} status "okay" + fdt set /soc/${tmp_spi_path}/spiflash@0 status "okay" + if test -n "${param_spinor_max_freq}"; then + fdt set /soc/${tmp_spi_path}/spiflash@0 spi-max-frequency "<${param_spinor_max_freq}>" + fi + if test "${param_spinor_spi_cs}" = "1"; then + fdt set /soc/${tmp_spi_path}/spiflash@0 reg "<1>" + fi + env delete tmp_spi_path +fi + +if test -n "${param_spidev_spi_bus}"; then + test "${param_spidev_spi_bus}" = "0" && setenv tmp_spi_path "spi@1c68000" + test "${param_spidev_spi_bus}" = "1" && setenv tmp_spi_path "spi@1c69000" + fdt set /soc/${tmp_spi_path} status "okay" + fdt set /soc/${tmp_spi_path}/spidev status "okay" + if test -n "${param_spidev_max_freq}"; then + fdt set /soc/${tmp_spi_path}/spidev spi-max-frequency "<${param_spidev_max_freq}>" + fi + if test "${param_spidev_spi_cs}" = "1"; then + fdt set /soc/${tmp_spi_path}/spidev reg "<1>" + fi + env delete tmp_spi_path +fi + +if test -n "${param_pps_pin}"; then + setenv tmp_bank "${param_pps_pin}" + setenv tmp_pin "${param_pps_pin}" + run decompose_pin + fdt set /soc/pinctrl@1c20800/pps_pins pins "${param_pps_pin}" + fdt get value tmp_phandle /soc/pinctrl@1c20800 phandle + fdt set /pps@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>" + env delete tmp_pin tmp_bank tmp_phandle +fi + +if test "${param_pps_falling_edge}" = "1"; then + fdt set /pps@0 assert-falling-edge +fi + +for f in ${overlays}; do + if test "${f}" = "pwm"; then + setenv bootargs_new "" + for arg in ${bootargs}; do + if test "${arg}" = "console=ttyS0,115200"; then + echo "Warning: Disabling ttyS0 console due to enabled PWM overlay" + else + setenv bootargs_new "${bootargs_new} ${arg}" + fi + done + setenv bootargs "${bootargs_new}" + fi +done + +if test -n "${param_w1_pin}"; then + setenv tmp_bank "${param_w1_pin}" + setenv tmp_pin "${param_w1_pin}" + run decompose_pin + fdt set /soc/pinctrl@1c20800/w1_pins pins "${param_w1_pin}" + fdt get value tmp_phandle /soc/pinctrl@1c20800 phandle + fdt set /onewire@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>" + env delete tmp_pin tmp_bank tmp_phandle +fi + +if test "${param_w1_pin_int_pullup}" = "1"; then + fdt set /soc/pinctrl@1c20800/w1_pins bias-pull-up +fi + +if test "${param_uart1_rtscts}" = "1"; then + fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart1-pins phandle + fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart1-rts-cts-pins phandle + fdt set /soc/serial@1c28400 pinctrl-names "default" "default" + fdt set /soc/serial@1c28400 pinctrl-0 "<${tmp_phandle1}>" + fdt set /soc/serial@1c28400 pinctrl-1 "<${tmp_phandle2}>" + env delete tmp_phandle1 tmp_phandle2 +fi + +if test "${param_uart2_rtscts}" = "1"; then + fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart2-pins phandle + fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart2-rts-cts-pins phandle + fdt set /soc/serial@1c28800 pinctrl-names "default" "default" + fdt set /soc/serial@1c28800 pinctrl-0 "<${tmp_phandle1}>" + fdt set /soc/serial@1c28800 pinctrl-1 "<${tmp_phandle2}>" + env delete tmp_phandle1 tmp_phandle2 +fi + +if test "${param_uart3_rtscts}" = "1"; then + fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart3-pins phandle + fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart3-rts-cts-pins phandle + fdt set /soc/serial@1c28c00 pinctrl-names "default" "default" + fdt set /soc/serial@1c28c00 pinctrl-0 "<${tmp_phandle1}>" + fdt set /soc/serial@1c28c00 pinctrl-1 "<${tmp_phandle2}>" + env delete tmp_phandle1 tmp_phandle2 +fi diff --git a/patch/kernel/archive/sunxi-6.18/overlay_64/sun50i-h6-fixup.scr-cmd b/patch/kernel/archive/sunxi-6.18/overlay_64/sun50i-h6-fixup.scr-cmd new file mode 100644 index 0000000000..f757db7aa4 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.18/overlay_64/sun50i-h6-fixup.scr-cmd @@ -0,0 +1,96 @@ +# overlays fixup script +# implements (or rather substitutes) overlay arguments functionality +# using u-boot scripting, environment variables and "fdt" command + +# setexpr test_var ${tmp_bank} - A +# works only for hex numbers (A-F) + +setenv decompose_pin 'setexpr tmp_bank sub "P(A|C|D|G)\\d+" "\\1"; +setexpr tmp_pin sub "P\\S(\\d+)" "\\1"; +test "${tmp_bank}" = "A" && setenv tmp_bank 0; +test "${tmp_bank}" = "C" && setenv tmp_bank 2; +test "${tmp_bank}" = "D" && setenv tmp_bank 3; +test "${tmp_bank}" = "G" && setenv tmp_bank 6' + +if test -n "${param_spinor_spi_bus}"; then + test "${param_spinor_spi_bus}" = "0" && setenv tmp_spi_path "spi@5010000" + test "${param_spinor_spi_bus}" = "1" && setenv tmp_spi_path "spi@5011000" + fdt set /soc/${tmp_spi_path} status "okay" + fdt set /soc/${tmp_spi_path}/spiflash@0 status "okay" + if test -n "${param_spinor_max_freq}"; then + fdt set /soc/${tmp_spi_path}/spiflash@0 spi-max-frequency "<${param_spinor_max_freq}>" + fi + if test "${param_spinor_spi_cs}" = "1"; then + fdt set /soc/${tmp_spi_path}/spiflash@0 reg "<1>" + fi + env delete tmp_spi_path +fi + +if test -n "${param_spidev_spi_bus}"; then + test "${param_spidev_spi_bus}" = "0" && setenv tmp_spi_path "spi@5010000" + test "${param_spidev_spi_bus}" = "1" && setenv tmp_spi_path "spi@5011000" + fdt set /soc/${tmp_spi_path} status "okay" + fdt set /soc/${tmp_spi_path}/spidev status "okay" + if test -n "${param_spidev_max_freq}"; then + fdt set /soc/${tmp_spi_path}/spidev spi-max-frequency "<${param_spidev_max_freq}>" + fi + if test "${param_spidev_spi_cs}" = "1"; then + fdt set /soc/${tmp_spi_path}/spidev reg "<1>" + fi + env delete tmp_spi_path +fi + +if test -n "${param_pps_pin}"; then + setenv tmp_bank "${param_pps_pin}" + setenv tmp_pin "${param_pps_pin}" + run decompose_pin + fdt set /soc/pinctrl@300b000/pps_pins pins "${param_pps_pin}" + fdt get value tmp_phandle /soc/pinctrl@300b000 phandle + fdt set /pps@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>" + env delete tmp_pin tmp_bank tmp_phandle +fi + +if test "${param_pps_falling_edge}" = "1"; then + fdt set /pps@0 assert-falling-edge +fi + +if test -n "${param_w1_pin}"; then + setenv tmp_bank "${param_w1_pin}" + setenv tmp_pin "${param_w1_pin}" + run decompose_pin + fdt set /soc/pinctrl@300b000/w1_pins pins "${param_w1_pin}" + fdt get value tmp_phandle /soc/pinctrl@300b000 phandle + fdt set /onewire@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>" + env delete tmp_pin tmp_bank tmp_phandle +fi + +if test "${param_w1_pin_int_pullup}" = "1"; then + fdt set /soc/pinctrl@300b000/w1_pins bias-pull-up +fi + +if test "${param_uart1_rtscts}" = "1"; then + fdt get value tmp_phandle1 /soc/pinctrl@300b000/uart1-pins phandle + fdt get value tmp_phandle2 /soc/pinctrl@300b000/uart1-rts-cts-pins phandle + fdt set /soc/serial@5000400 pinctrl-names "default" "default" + fdt set /soc/serial@5000400 pinctrl-0 "<${tmp_phandle1}>" + fdt set /soc/serial@5000400 pinctrl-1 "<${tmp_phandle2}>" + env delete tmp_phandle1 tmp_phandle2 +fi + +if test "${param_uart2_rtscts}" = "1"; then + fdt get value tmp_phandle1 /soc/pinctrl@300b000/uart2-pins phandle + fdt get value tmp_phandle2 /soc/pinctrl@300b000/uart2-rts-cts-pins phandle + fdt set /soc/serial@5000800 pinctrl-names "default" "default" + fdt set /soc/serial@5000800 pinctrl-0 "<${tmp_phandle1}>" + fdt set /soc/serial@5000800 pinctrl-1 "<${tmp_phandle2}>" + env delete tmp_phandle1 tmp_phandle2 +fi + +if test "${param_uart3_rtscts}" = "1"; then + fdt get value tmp_phandle1 /soc/pinctrl@300b000/uart3-pins phandle + fdt get value tmp_phandle2 /soc/pinctrl@300b000/uart3-rts-cts-pins phandle + fdt set /soc/serial@5000c00 pinctrl-names "default" "default" + fdt set /soc/serial@5000c00 pinctrl-0 "<${tmp_phandle1}>" + fdt set /soc/serial@5000c00 pinctrl-1 "<${tmp_phandle2}>" + env delete tmp_phandle1 tmp_phandle2 +fi diff --git a/patch/kernel/archive/sunxi-6.18/overlay_64/sun50i-h616-fixup.scr-cmd b/patch/kernel/archive/sunxi-6.18/overlay_64/sun50i-h616-fixup.scr-cmd new file mode 100755 index 0000000000..ebe12d7e74 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.18/overlay_64/sun50i-h616-fixup.scr-cmd @@ -0,0 +1,110 @@ +# overlays fixup script +# implements (or rather substitutes) overlay arguments functionality +# using u-boot scripting, environment variables and "fdt" command + +# setexpr test_var ${tmp_bank} - A +# works only for hex numbers (A-F) + +setenv decompose_pin 'setexpr tmp_bank sub "P(C|G|H|I)\\d+" "\\1"; +setexpr tmp_pin sub "P\\S(\\d+)" "\\1"; +test "${tmp_bank}" = "C" && setenv tmp_bank 2; +test "${tmp_bank}" = "G" && setenv tmp_bank 6; +test "${tmp_bank}" = "H" && setenv tmp_bank 7; +test "${tmp_bank}" = "I" && setenv tmp_bank 8' + +if test -n "${param_spinor_spi_bus}"; then + test "${param_spinor_spi_bus}" = "0" && setenv tmp_spi_path "spi@5010000" + test "${param_spinor_spi_bus}" = "1" && setenv tmp_spi_path "spi@5011000" + fdt set /soc/${tmp_spi_path} status "okay" + fdt set /soc/${tmp_spi_path}/spiflash@0 status "okay" + if test -n "${param_spinor_max_freq}"; then + fdt set /soc/${tmp_spi_path}/spiflash@0 spi-max-frequency "<${param_spinor_max_freq}>" + fi + if test "${param_spinor_spi_cs}" = "1"; then + fdt set /soc/${tmp_spi_path}/spiflash@0 reg "<1>" + fi + env delete tmp_spi_path +fi + +if test -n "${param_spidev_spi_bus}"; then + test "${param_spidev_spi_bus}" = "0" && setenv tmp_spi_path "spi@5010000" + test "${param_spidev_spi_bus}" = "1" && setenv tmp_spi_path "spi@5011000" + fdt set /soc/${tmp_spi_path} status "okay" + fdt set /soc/${tmp_spi_path}/spidev status "okay" + if test -n "${param_spidev_max_freq}"; then + fdt set /soc/${tmp_spi_path}/spidev spi-max-frequency "<${param_spidev_max_freq}>" + fi + if test "${param_spidev_spi_cs}" = "1"; then + fdt set /soc/${tmp_spi_path}/spidev reg "<1>" + fi + env delete tmp_spi_path +fi + +if test -n "${param_pps_pin}"; then + setenv tmp_bank "${param_pps_pin}" + setenv tmp_pin "${param_pps_pin}" + run decompose_pin + fdt set /soc/pinctrl@300b000/pps_pins pins "${param_pps_pin}" + fdt get value tmp_phandle /soc/pinctrl@300b000 phandle + fdt set /pps@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>" + env delete tmp_pin tmp_bank tmp_phandle +fi + +if test "${param_pps_falling_edge}" = "1"; then + fdt set /pps@0 assert-falling-edge +fi + +for f in ${overlays}; do + if test "${f}" = "pwm34"; then + setenv bootargs_new "" + for arg in ${bootargs}; do + if test "${arg}" = "console=ttyS0,115200"; then + echo "Warning: Disabling ttyS0 console due to enabled PWM3 and PWM4 overlay" + else + setenv bootargs_new "${bootargs_new} ${arg}" + fi + done + setenv bootargs "${bootargs_new}" + fi +done + +if test -n "${param_w1_pin}"; then + setenv tmp_bank "${param_w1_pin}" + setenv tmp_pin "${param_w1_pin}" + run decompose_pin + fdt set /soc/pinctrl@300b000/w1_pins pins "${param_w1_pin}" + fdt get value tmp_phandle /soc/pinctrl@300b000 phandle + fdt set /onewire@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>" + env delete tmp_pin tmp_bank tmp_phandle +fi + +if test "${param_w1_pin_int_pullup}" = "1"; then + fdt set /soc/pinctrl@300b000/w1_pins bias-pull-up +fi + +if test "${param_uart1_rtscts}" = "1"; then + fdt get value tmp_phandle1 /soc/pinctrl@300b000/uart1-pins phandle + fdt get value tmp_phandle2 /soc/pinctrl@300b000/uart1-rts-cts-pins phandle + fdt set /soc/serial@5000400 pinctrl-names "default" "default" + fdt set /soc/serial@5000400 pinctrl-0 "<${tmp_phandle1}>" + fdt set /soc/serial@5000400 pinctrl-1 "<${tmp_phandle2}>" + env delete tmp_phandle1 tmp_phandle2 +fi + +if test "${param_uart2_rtscts}" = "1"; then + fdt get value tmp_phandle1 /soc/pinctrl@300b000/uart2-pins phandle + fdt get value tmp_phandle2 /soc/pinctrl@300b000/uart2-rts-cts-pins phandle + fdt set /soc/serial@5000800 pinctrl-names "default" "default" + fdt set /soc/serial@5000800 pinctrl-0 "<${tmp_phandle1}>" + fdt set /soc/serial@5000800 pinctrl-1 "<${tmp_phandle2}>" + env delete tmp_phandle1 tmp_phandle2 +fi + +if test "${param_uart3_rtscts}" = "1"; then + fdt get value tmp_phandle1 /soc/pinctrl@300b000/uart3-pins phandle + fdt get value tmp_phandle2 /soc/pinctrl@300b000/uart3-rts-cts-pins phandle + fdt set /soc/serial@5000c00 pinctrl-names "default" "default" + fdt set /soc/serial@5000c00 pinctrl-0 "<${tmp_phandle1}>" + fdt set /soc/serial@5000c00 pinctrl-1 "<${tmp_phandle2}>" + env delete tmp_phandle1 tmp_phandle2 +fi